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ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Product Specification PS009007-1202 Z86L82/85/88 28-Pin Low-Voltage IR Microcontrollers
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28-Pin Low-Voltage IR Microcontrollers PS009007-1202 iii Table of Contents
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 iv
28-Pin Low-Voltage IR Microcontrollers PS009007-1202
Features
Table 1 shows some of the features of the Z86L82/85/88 microcontrollers.
- Low power consumption—40 mW (typical)
- Three standby modes – STOP—2 /g109A (typical) – HALT—0.8 mA (typical) – Low voltage
- Special architecture to automate both generation and reception of complex pulses or signals: – One programmable 8-bit counter/timer with two capture registers and two load registers – One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair – Programmable input glitch filter for pulse reception
- Five priority interrupts – Three external – Two assigned to counter/timers
- Low voltage protection
- Programmable watch-dog/power-on reset circuits
- Two independent comparators with programmable interrupt polarity
- Mask-selectable pull-up transistor on Ports 0, 2, and 3
Table 1. Z86L82/85/88 Features
28-Pin Low-Voltage IR Microcontrollers PS009007-1202
- Programmable mask options: – Oscillator selection: RC oscillator versus crystal or other clock source – Oscillator operational mode: normal high-frequency operation enabled versus 32-KHz operation enabled – Port 0: 0–3 pull-ups – Port 0: 4–7 pull-ups – Port 2: 0–7 pull-ups – Port 3: pull-ups – Port 0: 0–3 Mouse Mode: Normal Mode (.5VDD input threshold) versus Mouse Mode (.4VDD input threshold) The mask option pull-up transistor has a typical equivalent resistance of 200 K/g87/g32±50% at VCC=3 V and 450 K/g87/g32±50% at VCC=2 V. General Description The Z86L82/85/88 are ROM-based members of the Z8 MCU single-chip family of infrared (IR) controllers, featuring 237 bytes of general-purpose RAM and 4/8/16 KB of ROM, respectively. ZiLOG’s CMOS microcontrollers offer fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. The Z86L8X architecture is based on ZiLOG's 8-bit microcontroller core featuring an Expanded Register File to allow access to register-mapped peripherals, I/O cir- cuits, and powerful counter/timer circuitry. The Z8 offers a flexible I/O scheme, an efficient register and address-space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery- operated hand-held applications. Three basic address spaces are available to support a wide range of configura- tions: program memory, register file, and Expanded Register File. The register file consists of 256 bytes of RAM. It includes 4 I/O port registers, 16 control and status registers, and 236 general-purpose registers. [Register FEh (SPH) can be used as a general-purpose register.] The Expanded Register File consists of two addi- tional register groups (F and D). The Z86L8X offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages (see Figure 9 on page 18). Note:
Figure 2. Functional Block Diagram
grated circuit (SOIC) is shown in Figure 3. The pins are identified in Table 3. Figure 3. 28-Pin DIP/SOIC Pin Assignment Table 3. 28-Pin DIP and SOIC Pin Identification 19 P00 Input/Output Port 0 is nibble programmable.
20 P01 Input/Output Port 0–3 can be configured as a
21 P02 Input/Output mouse/trackball input.
23 P03 Input/Output
4 P04 Input/Output
5 P05 Input/Output
6 P06 Input/Output
7 P07 Input/Output
24 P20 Input/Output Port 2 pins are individually
25 P21 Input/Output configurable as input or output.
26 P22 Input/Output
27 P23 Input/Output
28 P24 Input/Output
1 P25 Input/Output
2 P26 Input/Output
3 P27 Input/Output
18 Pref1 Input Analog ref input; connect to V
Table 4 lists the absolute maximum ratings for the Z86L82/85/88 microcontrollers. ing conditions for an extended period might affect device reliability.
11 P31 Input IRQ2/modulator input
12 P32 Input IRQ0
13 P33 Input IRQ1
14 P34 Output T8 output
15 P35 Output T16 output
17 P36 Output T8/T16 output
16 P37 Output
10 XTAL1 Input Crystal, oscillator clock
9 XTAL2 Output Crystal, oscillator clock
22 V SS Ground
Table 4. Absolute Maximum Ratings † See “Ordering Information” on page 69. Table 3. 28-Pin DIP and SOIC Pin Identification (Continued)
Figure 4. Test Load Diagram Table 5 lists the capacitance for the Z86L82/85/88 microcontrollers. Table 5. Capacitance
Table 6 lists the direct current (DC) characteristics. Table 6. DC Characteristics
3.6 V 7 V I IN <250 /g109A
3.6 V 25 mV
3.6 V –1 1 /g109AV IN = 0 V, VCC
2.0 V 250
3.6 V 850 /g109A at 32 kHz 2, 3, 8
8.0 MHz
3.6 V 5 mA Same as above 2, 3
2.0 V 2 mA Clock Divide-by-16
3.6 V 4 mA Same as above 2, 3
3.6 V 10 /g109A Same as above 4, 6, 9
2.0 V 500 /g109AV IN = 0 V, VCC
3.6 V 800 /g109A Same as above 4, 6, 9
3.6 V 5 20 ms
- All outputs excluding P00, P01, P36, and P37
- All outputs unloaded, inputs at rail
- Same as note 2 except inputs at V
- The VBO is measured at room temperature and typically is 1.6 V. VBO increases as the temperature decreases.
- 32-kHz clock driver input
- WDT, Comparators, Low Voltage Detection, and ADC (if applicable) are disabled. The IC might draw more
current if any of the above peripherals is enabled. Table 6. DC Characteristics (Continued)
gram is shown in Figure 5 and described in Table 7. Figure 5. Timing Diagram
Table 7. AC Characteristics
3.6 V 121 DC ns 1
2 TrC,TfC Clock Input Rise and
2.0 V 25 ns 1
3.6 V 25 ns 1
3.6 V 37 ns 1
4 TwTinL Timer Input
2.0 V 100 ns 1
3.6 V 70 ns 1
5 TwTinH Timer Input High
2.0 V 3TpC 1
5.5 V 3TpC 1
3.6 V 8TpC 1
7 TrTin,TfTin Timer Input Rise and
3.6 V 100 ns 1
2.0 V 100 ns 1, 2
3.6 V 70 ns 1, 2
2.0 V 5TpC 1, 3
3.6 V 5TpC 1, 3
9 TwIH Interrupt Request
2.0 V 5TpC 1, 2
3.6 V 5TpC 1, 2
10 Twsm Stop-Mode Recovery
2.0 V 12 ns
3.6 V 12 ns
11 Tost Oscillator
2.0 V 5TpC 4
3.6 V 5TpC 4
12 Twdt Watch-Dog Timer
2.0 V 20 ms 5 0, 0
2.0 V 20 ms 5 0, 1
2.0 V 40 ms 5 1, 0
3.6 V 15 ms 5
3.6 V 60 ms 5
- Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
- Interrupt request through Port 3 (P33–P31)
- Interrupt request through Port 3 (P30)
- For internal RC oscillator
Table 7. AC Characteristics (Continued)
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC net- work to the on-chip oscillator input. An external single-phase clock to the on-chip oscillator input is also an option. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant crystal, ceramic resonant, LC, or RC net- work to the on-chip oscillator output. Port 0 (P07–P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open drain controlled by bit D2 in the PCON register. If one or both nibbles are required for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. A mask option is available to program 0.4 V DD CMOS trip inputs on P00–P03. This option allows direct interface to mouse/trackball IR sensors. An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. See Figure 6. Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. Note:
Figure 6. Port 0 Configuration
0.4 VCC
8 bits of Port 2 configured as inputs. Figure 7. Port 2 Configuration
Figure 8. Port 3 Configuration
the Port 3 input register, which then generates IRQ1. inputs must be placed into digital mode. PCON register. See Figure 9. Table 8. Pin Assignments
Figure 9. Port 3 Counter/Timer Output Configuration
consumer and battery-operated applications. vectors that correspond to the five available interrupts. The Z86L8X device has 237 bytes of RAM that make up the register file. Figure 10. Program Memory Map (16K ROM)
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 16 banks with 16 registers per bank. These register groups are known as the Expanded Register File (ERF). Bits 7–4 of register RP select the working register group. Bits 3–0 of register RP select the expanded register file bank. An expanded register bank is also referred to as an expanded register group (see Figure 11). The upper nibble of the register pointer (Figure 12 on page 22) selects which working register group is accessed of 16 bytes in the register file, out of the possi- ble 256. The lower nibble selects the expanded register file bank and, in the case of the Z86L8X family, banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register file (bank 0) to be addressed, but any other value from 1h to Fh exchanges the lower 16 registers to an expanded register bank. For example, for the Z86L8X (see Figure 11): R253 RP = 00h R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0Dh R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved The counter/timers are mapped into ERF group D. Access is easily performed using the following: LD RP, #0Dh ; Select ERF D for access to bank D ; (working register group 0) LD R0,#xx ; load CTRL0 LD 1, #xx ; load CTRL1 LD R1, 2 ; CTRL2 /g174CTRL1 LD RP, #0Dh ; Select ERF D for access to bank D ; (working register group 0) LD RP, #7Dh ; Select expanded register bank D ; working register group 7 of bank 0 ; for access. LD 71h, 2 ; CTRL2 /g174register 71h LD R1, 2 ; CTRL2/g174register 71h Note:
Figure 11. Expanded Register File Architecture † Not reset with a Stop-Mode Recovery, except Bit 0.
Figure 14. T8 and T16 Common Control Functions—(0D) 1H: Read/Write
1 T16_OUT is 1 Initially
transmit mode from demodulation mode. disabling the counter/timers.
Figure 15. T16 Control Register—(0D) 2H: Read/Write Except Where Noted
Figure 17. Stop-Mode Recovery Register 2—(0F) 0DH: D2–D4, D6 Write Only causes a Stop-Mode Recovery.
Figure 18. Watch-Dog Timer Register—(0F) 0FH: Write Only Figure 19. Port Configuration Register (PCON)—(0F) 0H: Write Only
0 P34, P37, Standard Output*
1 P34, P37, Comparator Output
Figure 22. Port 0 and 1 Mode Register (F8h: Write Only)
Figure 30. Register Pointer
Table 9 describes the expanded register group D. the input signal is 0HI16(D)09h. Table 9. Expanded Register Group D
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 HI16(D)09h This register (Table 12) holds the captured data from the output of the 16-bit Counter/Timer16. This register also holds the MS-Byte of the data. L016(D)08h This register (Table 13) holds the captured data from the output of the 16-bit Counter/Timer16. This register also holds the LS-Byte of the data. TC16H(D)07h Table 14 describes the Counter/Timer2 MS-Byte Hold Register. Table 11.L08(D)0Ah Field Bit Position Description T8_Capture_L0 76543210R W Captured Data No Effect Table 12.HI16(D)09h Field Bit Position Description T16_Capture_HI 76543210R W Captured Data No Effect Table 13.L016(D)08h Field Bit Position Description T16_Capture_LO 76543210R W Captured Data No Effect Table 14.TC16H(D)07h Field Bit Position Description T16_Data_HI 76543210R/W Data
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 TC16L(D)06h Table 15 describes the Counter/Timer2 LS-Byte Hold Register. TC8H(D)05h Table 16 describes the Counter/Timer8 High Hold Register. TC8L(D)04h Table 17 describes the Counter/Timer8 Low Hold Register. Table 15.TC16L(D)06h Field Bit Position Description T16_Data_LO 76543210R/W Data Table 16.TC8H(D)05h Field Bit Position Description T8_Level_HI 76543210R/W Data Table 17.TC8L(D)04h Field Bit Position Description T8_Level_LO 76543210R/W Data
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 CTR0 Counter/Timer8 Control Register Table 18 describes the CTR0 (D)00 Counter/Timer8 Control Register. T8 Enable This field enables T8 when set (written) to 1. Single/Modulo-N When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Time-Out This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 must be written to this location. Table 18.CTR0 (D)00 Counter/Timer8 Control Register Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Single/Modulo-N Modulo-N Single Pass W No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T8 _Clock ---43---R/W 0 0 0 1 1 0 1 1 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_MASK -----2--R/W 0 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34 Note: * Indicates the value upon Power-On Reset.
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Writing a 1 is the only way to reset the Terminal Count status condition. Therefore, you must reset this bit before using/enabling the counter/timers. The first clock of T8 might not exhibit complete clock width and can occur anytime when enabled. Care must be taken when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (demodulation mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. For example, when the status of bit 5 is 1, a timer reset condition occurs. T8 Clock This bit defines the frequency of the input signal to T8. Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a time-out. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. Caution: Note:
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Common Control Register to Counter/Timer T8 and T16 This register controls the functions in common with the T8 and T16. See Table 19. Table 19.CTR1(D)01h Register Field Bit Position Value Description Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 T8/T16_Logic/Edge _Detect --54----R/W Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit_Submode/Glitch_Filter ----32--R/W Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter
4 SCLK Cycle
8 SCLK Cycle
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Mode If it is 0, the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. P36_Out/Demodulator_Input In transmit mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In demodulation mode, this bit defines whether the input signal to the counter/tim- ers is from P20 or P31. T8/T16_Logic/Edge_Detect In transmit mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In demodulation mode, this field defines which edge needs to be detected by the edge detector. Transmit_Submode/Glitch_Filter In transmit mode, this field defines whether T8 and T16 are in the “Ping-Pong” mode or in independent normal operation mode. Setting this field to “Normal R/W R W Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Initial_T16_Out/Falling_Edge R/W R W Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0 Note: *Default upon Power-On Reset Table 19.CTR1(D)01h Register (Continued) Field Bit Position Value Description
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Operation Mode” terminates the “Ping-Pong Mode” operation. When this field is set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In demodulation mode, this field defines the width of the glitch that needs to be fil- tered out. Initial_T8_Out/Rising_Edge In transmit mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This measure ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 must be written to this location. Initial_T16 Out/Falling_Edge In transmit mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This measure ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 must be written to this location. Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. Note:
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 CTR2 Counter/Timer16 Control Register Table 20 describes the contents of the CTR2 register. T16_Enable This field enables T16 when set to 1. Single/Modulo-N In transmit mode, when this bit is set to 0, the counter reloads the initial value when the terminal count is reached. When this bit is set to 1, the counter stops when the terminal count is reached. Table 20.CTR2 (D)02h: Counter/Timer16 Control Register Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Single/Modulo-N Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge Time_Out --5----- R W No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T16 _Clock ---43--- R/W 00 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W 0 Disable Data Capture Int. Enable Data Capture Int. Enable Time-Out Int. P35 as Port Output T16 Output on P35 Note: * Indicates the value upon Power-On Reset.
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 In demodulation mode, when this bit is set to 0, T16 captures and reloads on detection of all the edges. When this bit is set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see “T16 Demodula- tion Mode” on page 51. Time_Out This bit is set when T16 times out (terminal count reached). To reset this bit, a 1 must be written to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. Counter_INT_Mask This bit is set to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. Counter/Timer Functional Blocks The following are the counter/timer functional blocks:
- Input circuit
- Eight-bit counter/timer circuits (page 44)
- Sixteen-bit counter/timer circuits (page 50)
- Output circuit (page 54) Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5– D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 31).
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0. When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter (see Figure 33). In Single-Pass Mode (CTR0 D6), T8 counts down to 0 and stops, T8_OUT toggles, and the time-out status bit (CTR0 D5) is set. A time-out interrupt can be generated if it is enabled (CTR0 D1). See Figure 34. In Modulo-N Mode, upon reaching the terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5), and generates an interrupt if enabled (CTR0 D1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 35.
Figure 33. Transmit Mode Flowchart
T8 continues counting from FFh (see Figure 36 and Figure 37). Figure 36. Demodulation Mode Count Capture Flowchart
Figure 37. Demodulation Mode Flowchart
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A time-out of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 and then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both, depending on CTR1 D5, D4) but continues to ignore subsequent edges. This T16 mode is generally used to measure mark times, the length of active car- rier signal bursts. When T16 reaches 0, it continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt time-out can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode (see Figure 41) is only valid in transmit mode. T8 and T16 must be programmed in Single-Pass Mode (CTR0 D6, CTR2 D6), and Ping-Pong Mode must be programmed in CTR1 D3 and D2. You can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the termi- nal count, it stops, T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1. Enabling Ping-Pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and then reset the status flags before instituting this operation. Note:
Figure 41. Ping-Pong Mode counter/timers reach the terminal count.
Figure 43. Interrupt Block Diagram
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 When more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is granted. As a result, all subsequent interrupt are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All Z86L8X interrupts are vectored through locations in the pro- gram memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommo- date polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require ser- vice. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered; all are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 22. Clock The Z86L8X on-chip oscillator has a high-gain, parallel-resonant amplifier for con- nection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input; XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The Z86LXX on-chip oscillator can be driven with a low-cost RC network or other suit- able external clock source. Table 22.IRQ Register * IRQ Interrupt Edge D7 D6 IRQ2 (P31) IRQ0 (P32)
00 F F
01 F R
10 R F
Notes: F = Falling Edge R = Rising Edge *In stop mode, the comparators are turned off.
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC, and LC oscillators). HALT HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/ timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 /g109A or less. STOP Mode is terminated only by a reset (such as WDT time-out), POR, SMR, or external reset. This termination causes the processor to restart the application program at address 000CH. To enter STOP (or HALT) mode, you need to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To execute this action, you must execute a NOP (op code = FFH) immediately before the appropriate sleep instruc- tion. For example: FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode
expanded register 2 at Bank F, location 00, as shown in Figure 45. Figure 45. Port Configuration Register (PCON)—Write Only pull, and a 0 sets the output to open-drain. Mode Recovery (Figure 46). All bits are write only except bit 7, which is read only.
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 SCLK/TCLK Divide-by-16 Select (D0) D0 of the SMR controls a Divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal pro- cessor execution (SCLK control) and/or HALT Mode (where TCLK sources inter- rupt logic). After Stop-Mode Recovery, this bit is set to a 0. Stop-Mode Recovery Source (D2, D3, and D4) These three bits of the SMR specify the wake-up source of the STOP recovery (Figure 48 and Table 23 on page 63).
Figure 48. Stop-Mode Recovery Source
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Any Port 2 bit defined as an output drives the corresponding input to the default state to allow the remaining inputs to control the AND/OR function. Refer to “Stop-Mode Recovery Register 2 (SMR2)” on page 64 for other recover sources. Stop-Mode Recovery Delay Select (D5) This bit, if low, disables the 5-ms RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the “fast” wake up is selected, the Stop- Mode Recovery source must be kept active for at least 5TpC. Stop-Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86L8X from STOP Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is set to 0 when the device is reset other than Stop-Mode Recovery (SMR). Table 23.Stop-Mode Recovery Source SMR:432 Operation D4 D3 D2 Description of Action 0 0 0 POR and/or external reset recovery 00 1 R e s e r v e d 0 1 0 P31 transition 0 1 1 P32 transition 1 0 0 P33 transition 1 0 1 P27 transition 1 1 0 Logical NOR of P20 through P23 1 1 1 Logical NOR of P20 through P27 Note:
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Watch-Dog Timer Mode Register (WDTMR) The WDT is a retriggerable, one-shot timer that resets the Z8 if it reaches its ter- minal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is selected with bit 4 of the WDT register. Bits 0 and 1 con- trol a tap circuit that determines the minimum time-out period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during STOP. Bits 5 through 7 are reserved (Figure 50). This register is accessible only during the first 61 processor cycles (122 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recov- ery (Figure 50). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0FH. The WDTMR is organized as shown in Figure 50. Table 24.SMR2(F)0Dh: Stop-Mode Recovery Register 2 Field Bit Position Value Description Low High Reserved --5----- 0 Reserved (Must be 0) Source ---432-- W0 0 0 * 001 010 011 100 101 110 111 A. POR Only B. NAND of P23–P20 C. NAND or P27–P20 D. NOR of P33–P31 E. NAND of P33–P31 F. NOR of P33–P31, P00, P07 G. NAND of P33–P31, P00, P07 H. NAND of P33–P31, P22–P20 Reserved Notes: *Indicates the value upon Power-On Reset Port pins configured as outputs are ignored as a SMR recovery source.
Figure 50. Watch-Dog Timer Mode Register—Write Only This bit selects the WDT time period. It is configured as indicated in Table 25. cates active during HALT. The default is 1. The default on reset is 10 ms.
configuration of this bit is 0, which selects the RC oscillator. See Figure 51. Figure 51. Resets and WDT
5 Clock
18 Clock Reset
18 Clock Reset timers upon a Low-to-High input translation.
28-Pin Low-Voltage IR Microcontrollers PS009007-1202 Mask Selectable Options There are seven Mask Selectable Options to choose from based on ROM code requirements. These are listed in Table 26. Table 26.Mask Selectable Options RC/Other RC/XTAL 32 kHz XTAL On/Off Port 0: 0–3 pull-ups On/Off Port 0: 4–7 pull-ups On/Off Port 2: 2–7 pull-ups On/Off Port 3: pull-ups On/Off Port 0: 0–3 Mouse Mode 0.4 V DD Trip On/Off
Figure 53. 28-Pin DIP Package Diagram
Figure 54. 28-Pin SSOP Package Diagram
8.0 MHz 28-Pin DIP
For the die form, please contact ZiLOG.
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