Z86L88 ZILOG | Alldatasheet
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P RELIMINARY P RODUCT S PECIFICATION Z86L88/81/86/87/89/73 IR/L OW OLTAGE M ICROCONTROLLER
FEATURES
n Low Power Consumption - 40 mW (Typical) n Three Standby Modes – STOP – HALT – Low Voltage n Special Architecture to Automate Both Generation and Reception of Complex Pulses or Signals: – One Programmable 8-Bit Counter/Timer with Two Capture Registers – One Programmable 16-Bit Counter/Timer with One 16-Bit Capture Register – Programmable Input Glitch Filter for Pulse Reception n Five Priority Interrupts – Three External – Two Assigned to Counter/Timers n Low Voltage Detection and Standby Mode n Programmable Watch-Dog/Power-On Reset Circuits n Two Independent Comparators with Programmable Interrupt Polarity n On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC (Mask Option), or External Clock Drive n Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3 – All Eight Port 2 Bits at One Time or Not – Pull-Ups Automatically Disabled Upon Selecting Individual Pins as Outputs. n Maskable Mouse/Trackball Interface on P00 Through P03. n 32 kHz Oscillator Mask Option GENERAL DESCRIPTION The Z86LXX family of IR (Infrared) CCP (Consumer Con- troller Processor) Controllers are ROM/ROMless-based members of the Z8 single-chip microcontroller family with 256 bytes of internal RAM. The differentiating factor be- tween these devices is the availability of ROM, and pack- age options. For the 40 and 44-pin devices the use of ex- ternal memory enables these Z8 microcontrollers to be used where code flexibility is required. Zilog’s CMOS mi- crocontrollers offers fast executing, efficient use of memo- ry, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and in- ternal key-scan pull-up resistors. The Z86LXX product line offers easy hardware/software system expansion cost-ef- fective and low power consumption. The Z86LXX architecture is based on Zilog's 8-bit micro- controller core with an Expanded Register File to allow ac- cess to register mapped peripherals, I/O circuits, and pow- erful counter/timer circuitry. The CCP offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many Device ROM (KB) RAM* (Bytes) I/O Lines Voltage Range Z86L88 16 237 23 2.0V to 3.9V Z86L81 24 237 23 2.0V to 3.9V Z86L86 32 237 23 2.0V to 3.9V Z86L87 16 236 31 2.0V to 3.9V Z86L89 24 236 31 2.0V to 3.9V Z86L73 32 236 31 2.0V to 3.9V Note: *General-Purpose
operated hand-held applications. ter File, Expanded Register File, and External Memory. arate reference voltages (Figure 2). Figure 1. Counter/Timers Diagram
Figure 2. Functional Block Diagram
Figure 7. 44-Pin QFP
Table 1. Pin Identification 26 40 23 P00 Input/Output Port 0 is Nibble Programmable. 34 5 32 P03 Input/Output ROM Address Bus. 6 18 1 P05 Input/Output mouse/trackball input. 28 42 25 P10 Input/Output Port 1 is byte programmable. 8 20 3 P14 Input/Output Address/Data Bus. 36 7 34 P21 Input/Output configurable as input or output.
Table 2. Pin Identification
19 P00 Input/Output Port 0 is Nibble Programmable
20 P01 Input/Output Port 0 can be configured as
21 P02 Input/Output A15-A8 external program
23 P03 Input/Output ROM Address Bus.
4 P04 Input/Output
5 P05 Input/Output Port 0 can be configured as a
6 P06 Input/Output
7 P07 Input/Output
24 P20 Input/Output Port 2 pins are individually
25 P21 Input/Output configurable as input or output.
26 P22 Input/Output
27 P23 Input/Output
28 P24 Input/Output
1 P25 Input/Output
2 P26 Input/Output
3 P27 Input/Output
18 Pref1 Input Analog Ref Input
11 P31 Input IRQ2/Modulator input
12 P32 Input IRQ0
13 P33 Input IRQ1
14 P34 Output T8 output
15 P35 Output T16 output
17 P36 Output T8/T16 output
16 P37 Output
10 XTAL1 Input Crystal, Oscillator Clock
9 XTAL2 Output Crystal, Oscillator Clock
may affect device reliability. conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 8). = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
- Voltage on all pins with respect to GND.
Figure 8. Test Load Diagram
IR/Low-Voltage Microcontroller P R E L I M I N A R Y DS96LV00800 DC CHARACTERISTICS Preliminary T A = 0 C to +70 C Typ @ Sym Parameter V CC Min Max 25 °C Units Conditions Notes Max Input Voltage 2.0V 3.9V V V IIN <250 mA IIN <250 mA VCH Clock Input High Voltage 2.0V 3.9V
0.8 VCC
VCC + 0.3 VCC + 0.3 V V Driven by External Clock Generator Driven by External Clock Generator V CL Clock Input Low Voltage 2.0V 3.9V VSS – 0.3 VSS – 0.3
0.2 VCC
V V Driven by External Clock Generator Driven by External Clock Generator V IH Input High Voltage2.0V 3.9V
0.7 VCC
VCC + 0.3 VCC + 0.3 0.5VCC 0.5VCC V V VIL Input Low Voltage 2.0V 3.9V VSS – 0.3 VSS – 0.3 0.5VCC 0.5VCC V V VOH1 Output High Voltage 2.0V 3.9V VCC – 0.4 VCC – 0.4 1.7 3.7 V V IOH = –0.5 mA IOH = –0.5 mA VOH2 Output High Voltage (P36, P37,P00, P01) 2.0V 3.9V V CC - 0.8 VCC - 0.8 V V IOH = –7 mA IOH = –7 mA VOL1 Output Low Voltage 2.0V 3.9V 0.4 0.4 0.1 0.2 V V IOL = 1.0 mA IOL = 4.0 mA VOL2* Output Low Voltage 2.0V 3.9V 0.8 0.8 0.5 0.3 V V IOL = 5.0 mA IOL = 7.0 mA VOL2 Output Low Voltage(P36, P37,P00,P01) 2.0V 3.9V 0.8 0.8 0.3 0.2 V V I OL = 10 mA IOL = 10 mA VRH Reset Input High Voltage 2.0V 3.9V 1.5 2.0 V V VRl Reset Input Low Voltage 2.0V 3.9V VSS – 0.3 VSS – 0.3 0.5 0.9 V V VOFFSET Comparator Input Offset Voltage 2.0V 3.9V mV mV IIL Input Leakage 2.0V 3.9V < 1 < 1 mA mA VIN = OV, VCC VIN = OV, VCC IOL Output Leakage 2.0V 3.9V < 1 < 1 mA mA VIN = OV, VCC VIN = OV, VCC IIR Reset Input Pull- Up Current 2.0V 3.9V –230 –400 -90 –220 mA mA VIN = OV VIN = OV‘ ICC Supply Current 2.0V 3.9V mA mA @ 8.0 MHz @ 8.0 MHz 1,2 1,2 2.0V 3.9V 250 850 100 500 mA mA @ 32 kHz @ 32 kHz 1,2,7 1,2,7
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 11 TA = 0°C to +70°C Typ @ Sym Parameter VCC Min Max 25 °C Units Conditions Notes ICC1 Standby Current (WDT Off) 2.0V 3.9V mA mA HALT Mode VIN = OV, VCC @
8.0 MHz
V IN = OV, VCC @ 8.0 MHz 1,2 1,2 2.0V 3.9V 0.8 2.5 mA mA Clock Divide-by- 16 @ 8.0 MHz Clock Divide-by- 16 @ 8.0 MHz 1,2 1,2 I CC2 Standby Current 2.0V 3.9V mA mA STOP Mode VIN = OV, VCC WDT is not Running STOP Mode V IN = OV, VCC WDT is not Running 3,5 3,5 2.0V 3.9V 500 800 310 600 mA mA STOP Mode V IN = OV, VCC WDT is Running 3,5 TPOR Power-On Reset 2.0V 3.9V ms ms Vram Static RAM Data Retention Voltage Vram 0.8 0.5 V 6 VLV (Vbo) VCC Low Voltage Protection 2.15 1.7 V 8 MHz max Ext. CLK Freq. Notes: ICC1 Crystal/Resonator External Clock Drive Typ 3.0 mA 0.3 mA Max Unit mA mA Frequency
- All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF 3. Same as note [4] except inputs at V CC . 4. The VLV increases as the temperature decreases. 5. Oscillator stopped. 6. Oscillator stops when VCC falls below Vlv limit 7. 32 kHz clock driver input. * All Outputs excluding P00, P01, P36, and P37.
12 P R E L I M I N A R Y DS96LV00800
Figure 9. External I/O or Memory Read/Write Timing
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 13 AC CHARACTERISTICS Preliminary External I/O or Memory Read and Write Timing Table TA = 0°C to +70°C 8.0MHz No Symbol Parameter VCC Min Max Units Notes
1 TdA(AS) Address Valid to
/AS Rising Delay 2.0V 3.9V ns ns
2 TdAS(A) /AS Rising to Address
2.0V 3.9V ns ns
3 TdAS(DR) /AS Rising to Read
2.0V 3.9V 400 400 ns ns 1,2 4 TwAS /AS Low Width 2.0V 3.9V ns ns
5 Td Address Float to
/DS Falling 2.0V 3.9V ns ns 6 TwDSR /DS (Read) Low Width 2.0V 3.9V 300 300 ns ns 1,2 7 TwDSW /DS (Write) Low Width 2.0V 3.9V 165 165 ns ns 1,2
8 TdDSR(DR) /DS Falling to Read
2.0V 3.9V 260 260 ns ns 1,2
9 ThDR(DS) Read Data to /DS Rising
2.0V 3.9V ns ns
10 TdDS(A) /DS Rising to Address
2.0V 3.9V ns ns
11 TdDS(AS) /DS Rising to /AS
2.0V 3.9V ns ns
12 TdR/W(AS) R//W Valid to /AS
2.0V 3.9V ns ns
13 TdDS(R/W) /DS Rising to
2.0V 3.9V ns ns
14 TdDW(DSW) Write Data Valid to /DS
Falling (Write) Delay 2.0V 3.9V ns ns
15 TdDS(DW) /DS Rising to Write
2.0V 3.9V ns ns
16 TdA(DR) Address Valid to Read
2.0V 3.9V 475 475 ns ns 1,2
17 TdAS(DS) /AS Rising to
/DS Falling Delay 2.0V 3.9V 100 100 ns ns
18 TdDM(AS) /DM Valid to /AS
2.0V 3.9V ns ns
19 TdDS(DM) /DS Rise to
/DM Valid Delay 2.0V 3.9V ns ns
20 ThDS(A) /DS Rise to Address
2.0V 3.9V ns Notes: 1. When using extended memory timing add 2 TpC. 2. Timing numbers given are for minimum TpC. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
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Figure 10. Additional Timing
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 15 AC CHARACTERISTICS Preliminary Additional Timing Table TA = 0°C to +70°C 8.0MHz No Sym Parameter VCC Min Max Units Notes 1 TpC Input Clock Period 2.0V 3.9V 121 121 DC DC ns ns
2 TrC,TfC Clock Input Rise
2.0V 3.9V ns ns 3 TwC Input Clock Width 2.0V 3.9V ns ns
4 TwTinL Timer Input
2.0V 3.9V 100 ns ns
5 TwTinH Timer Input
2.0V 3.9V 3TpC 3TpC
6 TpTin Timer Input
2.0V 3.9V 8TpC 8TpC
7 TrTin,TfTin Timer Input Rise
2.0V 3.9V 100 100 ns ns 8A TwIL Interrupt Request Low Time 2.0V 3.9V 100 ns ns 1,2 1,2 8B TwIL Interrupt Request Low Time 2.0V 3.9V 5TpC 5TpC 1,3 1,3
9 TwIH Interrupt Request
2.0V 3.9V 5TpC 5TpC 1,2 1,2
10 Twsm Stop-Mode Recovery
2.0V 3.9V 2.0V 3.9V
5 TpC
11 Tost Oscillator
2.0V 3.9V 5TpC 5TpC
12 Twdt Watch-Dog Timer
Delay Time (5 ms) (10 ms) (20 ms) (80 ms) 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 225 150 300 1200 320 ms ms ms ms ms ms ms ms Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. Interrupt request through Port 3 (P30). 4. SMR – D5 = 0
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Figure 11. Port Input Handshake Timing Figure 12. Port Output Handshake Timing
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 17 AC CHARACTERISTICS Preliminary Handshake Timing Table TA = 0°C to +70°C Data No Sym Parameter VCC Min Max Direction 1 TsDI(DAV) Data In Setup Time 2.0V 3.9V IN IN 2 ThDI(DAV) Data In Hold Time 2.0V 3.9V IN IN 3 TwDAV Data Available Width 2.0V 3.9V 155 110 IN IN
4 TdDAVI(RDY) DAV Falling to RDY
2.0V 3.9V 160 115 IN IN
5 TdDAVId(RDY) DAV Rising to RDY
2.0V 3.9V 120 IN IN
6 TdRDYO(DAV) RDY Rising to DAV
2.0V 3.9V IN IN
7 TdDO(DAV) Data Out to DAV
2.0V 3.9V OUT OUT
8 TdDAV0(RDY) DAV Falling to RDY
2.0V 3.9V OUT OUT
9 TdRDY0(DAV) RDY Falling to DAV
2.0V 3.9V 160 115 OUT OUT 10 TwRDY RDY Width 2.0V 3.9V 110 OUT OUT
11 TdRDY0d(DAV) RDY Rising to DAV
2.0V 3.9V 110 OUT OUT
IR/Low-Voltage Microcontroller
18 P R E L I M I N A R Y DS96LV00800
/DS (Output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (Output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Un- der program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write. XTAL1 Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network or an external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output. R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory. R//RL (input). This pin, when connected to GND, disables the internal ROM and forces the device to function as a ROMless Z8. (Note that, when left unconnected or pulled high to V CC , the part functions normally as a Z8 ROM ver- sion.) Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS compatible port. These eight I/O lines are configured un- der software control as a nibble I/O port, or as an address port for interfacing external memory. The output drivers are push-pull. Port 0 can be placed under handshake con- trol. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0. Hand- shake signal function is dictated by the I/O direction of the Port 0 upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble. For external memory references, Port 0 can provide ad- dress bits A11-A8 (lower nibble) or A15-A8 (lower and up- per nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nib- bles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware re- set, Port 0 is configured as an input port. Port 0 is set in the high-impedance mode (if selected as an address output) along with Port 1 and the control signals /AS, /DS, and R//W through P3M bits D4 and D3(Figure 13). A ROM mask option is available to program 0.4 V DD CMOS trip inputs on P00-P03. This allows direct interface to mouse/trackball IR sensors. An optional 200 kOhms pull-up is available as a mask op- tion on all Port 0 bits with nibble select. Note: Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode.
Figure 13. Port 0 Configuration inputs in a mouse or trackball application.
0.4 VDD
20 P R E L I M I N A R Y DS96LV00800
® -compatible memory interface. Read/Write (R//W) and Data Memory (/DM) control lines. quired, Port 0 outputs the additional lines. Figure 14. Port 1 Configuration
of Port 2 configured as inputs with open-drain outputs. Figure 15. Port 2 Configuration
22 P R E L I M I N A R Y DS96LV00800
P33 are standard CMOS inputs; outputs are push-pull. and P32 with reference to the voltage on Pref1 and P33. are available on P31 through P36. ming bits D5-D4 of CTR1, bit 0 of CTR0 and bit 0 of CTR2. buffer whether or not analog mode is enabled). source, these inputs must be placed into digital mode. Table 3. Pin Assignments
Figure 16. Port 3 Configuration
0 Normal Control
24 P R E L I M I N A R Y DS96LV00800
After the POR time, /RESET is a Schmitt-triggered input. the duration of the external reset, whichever is longer. Figure 17. Port 3 Configuration
Figure 18. Port 3 Counter Timer Output Configuration
26 P R E L I M I N A R Y DS96LV00800
battery operated applications. ecuted (provided proper A/D port mode register settings). 000Ch and data memory fetches begin at address 0000h. which make up the Register file. tion references data (/DM active Low) memory. Figure 19. Program Memory Map(32K ROM) Figure 20. External Memory Map
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 27 Expanded Register File. The register file has been ex- panded to allow for additional system control registers, and for mapping of additional peripheral devices into the register address area. The Z8 register address space R0 through R15 has been implemented as 16 banks of 16 reg- isters per bank. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of register RP se- lect the working register group. Bits 3-0 of register RP se- lect the expanded register file bank. Note that expanded register bank is also referred to as expanded register group (Figure 21). The upper nibble of the register pointer (Figure 23) selects which working register group of 16 bytes in the register file, out of the possible 256, will be accessed. The lower nibble selects the expanded register file bank and, in the case of the Z86LXX family, banks 0, F, and D are implemented. A 0h in the lower nibble will allow the normal register file (bank 0) to be addressed, but any other value from 1h to Fh will exchange the lower 16 registers to an expanded register bank. For example: Z86L73: (See Figure 21) R253 RP = 00h R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0Dh R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved The counter/timers are mapped into ERF group D. Access is easily done using the following example: LD RP, #0Dh Select ERF D for access to bank D ( work- ing register group 0) LD R0,#xx load CTRL0 LD 1, #xx load CTRL1 LD R1, 2 CTRL2 fi CTRL1 LD RP, #7Dh Select expanded register bank D and working register group 7 of bank 0 for access . LD 71h, 2 CTRL2 fi register 71h LD R1, 2 CTRL2 fi register 71h
28 P R E L I M I N A R Y DS96LV00800
Figure 21. Expanded Register File Architecture † Will not be reset with a Stop-Mode Recovery , except Bit 0.
0 UUUUUU
IR/Low-Voltage Microcontroller
30 P R E L I M I N A R Y DS96LV00800
HI16(D)%09: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the MS- Byte of the data. L016(D)%08: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the LS- Byte of the data. TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register. TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register. TC8H(D)%05: Counter/Timer8 High Hold Register. TC8L(D)%04: Counter/Timer8 Low Hold Register. Field Bit Position Description T16_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position Description T16_Capture_L O 76543210 R W Captured Data No Effect Field Bit Position Description T16_Data_HI 76543210 R/W Data Field Bit Position Description T16_Data_LO76543210 R/W Data Field Bit Position Description T8_Level_HI 76543210 R/W Data Field Bit Position Description T8_Level_LO 76543210 R/W Data
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 31 CTR0 (D)00: Counter/Timer8 Control Register. CTR0: Counter/Timer8 Control Register Description T8 Enable. This field enables T8 when set (written) to 1. Single/Modulo-N. When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Time-Out. This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to this lo- cation. This is the only way to reset this status condi- tion, therefore, care should be taken to reset this bit prior to using/enabling the counter/timers. Note: Care must be taken when utilizing the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers will be ORed or ANDed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a timer reset condition will occur. T8 Clock. Defines the frequency of the input signal to T8. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask. Set this bit to allow interrupt when T8 has a time out. P34_Out. This bit defines whether P34 is used as a normal output pin or the T8 output. Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass W No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T8 _Clock ---43--- R/W 0 0 0 1 1 0 1 1 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_MASK -----2-- R/W 0 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34 Note: * Indicates the value upon Power-On Reset.
IR/Low-Voltage Microcontroller
32 P R E L I M I N A R Y DS96LV00800
CTR1(D)%01: Controls the functions in common with the T8 and T16. Field Bit Position Value Description Demodulation Mode P36_Out/Demodulator _Input Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 T8/T16_Logic/ Edge _Detect --54---- R/W Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit_Submode/ Glitch_Filter ----32-- R/W Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter
4 SCLK Cycle
8 SCLK Cycle
16 SCLK Cycle
Initial_T8_Out/ Rising Edge R/W R W Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Initial_T16_Out/ Falling_Edge R/W R W Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0 Note: *Default upon Power-On Reset
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 33 CTR1 Register Description Mode. If it is 0, the Counter/Timers are in the transmit mode, otherwise they are in the demodulation mode. P36_Out/Demodulator_Input. In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/Timers is from P20 or P31. T8/T16_Logic/Edge _Detect. In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter. In Transmit Mode, this field defines whether T8 and T16 are in the "Ping-Pong" mode or in independent normal operation mode. Setting this field to "Normal Operation Mode" terminates the "Ping- Pong Mode" operation. When set to 10, T16 is immediate- ly forced to a 0; a setting of 11 will force T16 to output a 1. In Demodulation Mode, this field defines the width of the glitch that should be filtered out. Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the out- put of T8 is set to 1 when it starts to count. When The counter is not enabled and this bit is set to 1 or 0, T8_OUT will be set to the opposite state of this bit. This insures that when the clock is enabled a transition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). When the counter is not enabled and this bit is set, T16_OUT will be set to the opposite state of this bit. This insures that when the clock is enabled a transition oc- curs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Note: Modifying CTR1, (D1 or D0) while the counters are enabled will cause un-predictable output from T8/16_OUT.
IR/Low-Voltage Microcontroller
34 P R E L I M I N A R Y DS96LV00800
CTR2 (D)%02: Counter/Timer16 Control Register. CTR2 Description T16_Enable. This field enables T16 when set to 1. Single/Modulo-N. In Transmit Mode, when set to 0, the counter reloads the initial value when terminal count is reached. When set to 1, the counter stops when the termi- nal count is reached. In Demodulation Mode, when set to 0 , T16 captures and reloads on detection of all the edges; when set to 1, T16 captures and detects on the first edge, but ignores the sub- sequent edges. For details, see the description of T16 De- modulation Mode. Time_Out. This bit is set when T16 times out (terminal count reached). In order to reset it, a 1 should be written to this location. T16_Clock. Defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into LO16 and HI16. Counter_INT_Mask. Set this bit to allow interrupt when T16 times out. P35_Out. This bit defines whether P35 is used as a normal output pin or T16 output. Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge Time_Out --5----- R W No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T16 _Clock ---43--- R/W 00 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W 0 Disable Data Capture Int. Enable Data Capture Int. Enable Time-Out Int. P35 as Port Output T16 Output on P35 Note: * Indicates the value upon Power-On Reset.
IR/Low-Voltage Microcontroller DS96LV00800 P R E L I M I N A R Y 35 SMR2(F)%0D: Stop-Mode Recovery Register 2. Field Bit Position Value Description Low High Reserved --5----- 0 Reserved (Must be 0) Source ---432-- W 000* 001 010 011 100 101 110 111 A. POR Only B. NAND of P23-P20 C. NAND or P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F . NOR of P33-P31, P00,P07 G. NAND of P33-P31,P00,P07 H. NAND of P33-P31,P22-P20 Notes: * Indicates the value upon Power-On Reset Port pins configured as outputs are ignored as a SMR recovery source.
36 P R E L I M I N A R Y DS96LV00800
Figure 24. Glitch Filter Circuitry Figure 25. 8-Bit Counter/Timer Circuits
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Figure 28. Demodulation Mode Count Capture Flowchart
Figure 29. Transmit Mode Flowchart
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Figure 30. Demodulation Mode Flowchart
programming CTR1 D3, D2 to a 10 or 11. and T16_OUT is switched to its initial value (CTR1 D0). Figure 31. 16-Bit Counter/Timer Circuits
42 P R E L I M I N A R Y DS96LV00800
HI16 and LO16, reloads and begins counting. with %FFFF and starts again. the length of time between bursts of carrier signal(marks). the length of an active carrier signal bursts. time-out can be generated if enabled (CTR2 D1). Figure 32. T16_OUT in Single-Pass Mode Figure 33. T16_OUT in Modulo-N Mode
reset the status flags prior to instituting this operation. abling either T8 (CTR0 D7) or T16 (CTR2 D7). counter/timers reach the terminal count. Figure 34. Ping-Pong Mode
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Figure 35. Output Circuit
Figure 36. Interrupt Block Diagram
46 P R E L I M I N A R Y DS96LV00800
gram memory vector location reserved for that interrupt. of the interrupt requests need service. can poll to identify the state of the pin. er suitable external clock source. (Rf) and a serial resistor (Rd) are required. See Figure 37. greater than or equal to 22 pF) from each pin to ground. pacitor from XTAL1 to ground (Figure 37). Table 5. Interrupt Types, Sources, and Vectors Table 6. IRQ Register
00 F F
01 F R
10 R F
P33) can be used to generate IRQ1 (falling edge triggered).
- Power Fail to Power OK status including Waking up
- Stop-Mode Recovery (if D5 of SMR = 1).
rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. Figure 37. Oscillator Configuration
48 P R E L I M I N A R Y DS96LV00800
Figure 38. Port Configuration Register (PCON)
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Figure 39. Stop-Mode Recovery Register Figure 40. SCLK Circuit
0 OFF
0 Low
1 High
0 POR
1 Stop Recovery
Figure 41. Stop-Mode Recovery Source
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logic). After Stop-Mode Recovery, this bit is set to a 0. STOP recovery (Figure 41 and Table 7). ister for other recover sources. needs to be kept active for at least 5TpC. specified events will cause a Stop-Mode Recovery. (P23-P21) form the NAND equation. Table 7. Stop-Mode Recovery Source
Figure 42. Stop-Mode Recovery Register 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
0 Low*
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the Zero (Z), Sign (S), and Overflow (V) flags. Figure 43. Watch-Dog Timer Mode Register
0 On-Board RC
1 XT AL
WDT Time Select (D0, D1). Selects the WDT time period. It is configured as shown in Table 8. active during HALT. The default is 1. ration of this bit is 0, which selects the RC oscillator. Table 8. WDT Time Select The default on reset is 10 ms. Figure 44. Resets and WDT
18 Clock RESET
5 Clock
18 Clock Reset timers upon a Low to High input translation.
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function normally (Figure 45). Figure 45. Typical Z86LXX Low Voltage vs
Figure 46. TC8 Control Register
0 P34 as Port Output*
1 Timer8 Output
0 Disable T8 Time Out Interrupt
1 Enable T8 Time Out Interrupt
0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt
00 SCLK on T8
01 SCLK/2 on T8
10 SCLK/4 on T8
0 Modulo-N
1 Single Pass
IR/Low-Voltage Microcontroller
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CTR1 (0D) 1H
0 T16_OUT is 0 Initially
1 T16_OUT is 1 Initially
R R W W
0 No Falling Edge Detection
1 Falling Edge Detection
0 No Effect
1 Reset Flag to 0
0 T8_OUT is 0 Initially
1 T8_OUT is 1 Initially
0 No Rising Edge Detection
1 Rising Edge Detection
1 0 T16_OUT = 0 1 1 T16_OUT = 1 Transmit Mode/T8/T16 Logic 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved
0 P36 as Port Output *
1 P36 as T8/T16_OUT
0 Transmit Mode *
1 Demodulation Mode
R R W W Transmit Mode Demodulation Mode 0 0 AND 0 1 OR 1 0 NOR 1 1 NAND Demodulation Mode Transmit Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
Transmit/Demodulation Modes Note: Care must be taken in differentiating Transmit Mode from Demodulation Mode. Depending on which of these two modes is operating, the CTR1 bit will have different functions. Note: Changing from one mode to another cannot be done without disabling the counter/timers. *Default setting after Reset
Figure 48. T16 Control Register
0 P35 is Port Output*
1 P35 is TC16 Output
0 Disable T16 Time-Out Interrupt
1 Enable T16 Time-Out Interrupt
0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt
0 Modulo-N for T16
1 Single Pass for T16
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
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Figure 49. Stop-Mode Recovery Register
1 Stop Recovery * *
Figure 50. Stop-Mode Recovery Register 2
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Figure 51. Watch-Dog Timer Register Figure 52. Port Configuration Register (PCON)
Figure 53. Port 2 Mode Register Figure 54. Port 3 Mode Register
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
0 Port 2 Open Drain*
1 Port 2 Push-pull
0 P32 = Input
1 P32 = /DA V0/RDY0
0 P31 = Input (TIN)
1 P31 = /DA V2/RDY2
00 P33 = Input
01 P33 = Input
10 P34 = /DM
Figure 55. Port 0 and 1 Mode Register Figure 56. Interrupt Priority Registers
00 Output
01 Input*
0 External
1 Internal*
00 Byte Output
01 Reserved
10 AD7-AD0
0 Normal*
1 Extended
- Default Setting After Reset.
Note: Only P00 and P07 are Available on Z86L71.
000 Reserved
001 C>A>B
010 A>B>C
011 A>C>B
100 B>C>A
101 C>B>A
110 B>A>C
111 Reserved
0 IRQ1>IRQ4
1 IRQ4>IRQ1
0 IRQ2>IRQ0
1 IRQ0>IRQ2
0 IRQ5>IRQ3
1 IRQ3>IRQ5
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Figure 57. Interrupt Request Register Figure 58. Interrupt Mask Register Figure 59. Flag Register
1 Enables IRQ4-IRQ0
0 Master Interrupt Disable*
1 Master Interrupt Enable
Figure 60. Register Pointer Figure 61. Stack Pointer High Figure 62. Stack Pointer Low
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Figure 65. 40-Pin DIP Package Diagram Figure 66. 44-Pin PLCC Package Diagram
Figure 67. 44-Pin QFP Package Diagram
IR/Low-Voltage Microcontroller
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ORDERING INFORMATION
28-Pin SIOC 44-Pin PLCC 44-Pin QFP Z86L8808SSC Z86L8708VSC Z86L8708FSC Z86L8108SSC Z86L8908VSC Z86L8908FSC Z86L8608SSC Z86L7308VSC Z86L7308FSC For fast results, contact your local Zilog sales office for as- sistance in ordering the part desired. Codes Package P = Plastic DIP F = Plastic Quad Flat Pack V = Plastic Chip Carrier S = SOIC (Small Outline Integrated Circuit) Temperature S = 0°C to +70°C Speed 8 = 8.0 MHz Environmental C = Plastic Standard Example: Z 86LXX 08 P S C Environmental Flow T emperature Package Speed Product Number Zilog Prefix is a Z86LXX, 8 MHz, DIP, 0°C to +70°C, Plastic Standard Flow