Z86L70 ZILOG | Alldatasheet
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P RELIMINARY P RODUCT S PECIFICATION Z86L70/71/75/C71 IR/L OW OLTAGE M ICROCONTROLLER
FEATURES
n Two Standby Modes (Typical) – STOP - 2 m A – HALT - 0.8 mA n Special Architecture to Automate Both Generation and Reception of Complex Pulses or Signals: – One Programmable 8-Bit Counter/Timer with Two Capture Registers – One Programmable 16-Bit Counter/Timer with One Capture Register – Programmable Input Glitch Filter for Pulse Reception n Five Priority Interrupts n Low Voltage Detection and Protection n Programmable Watch-Dog/Power-On Reset Circuits n Two Independent Comparators with Programmable Interrupt Polarity n On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC (mask option), or External Clock Drive n Mask Selectable 200 KOhm Pull-Ups on Ports 0, 2, 3 GENERAL DESCRIPTION The Z86L7X family of IR (Infrared)/Low-Voltage Microcon- trollers are ROM/ROMless-based members of the Z8 MCU single-chip family with 237/125 bytes of internal RAM. The differentiating factor between these devices is the availability of RAM, ROM and package options. Offer- ing the 3V versions (Z86LXX) with the Z86C71 gives opti- mum performance in both the low and high voltage ranges. Zilog's CMOS Low-Voltage Microcontrollers offer fast exe- cution, efficient use of memory, sophisticated interrupts, in- put/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up resis- tors. The Z86L7X product line offers easy hardware/soft- ware system expansion with cost-effective and low power consumption. The Z86L7X architecture is based on Zilog's 8-bit micro- controller core with an Expanded Register File to allow ac- cess to register mapped peripherals, I/O circuits, and pow- erful counter/timer circuitry. The Z8 Ò MCU offers a flexible I/O scheme, an efficient register and address space struc- ture, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery operated hand-held applications. There are three basic address spaces available to support a wide range of configurations: Program Memory, Register File, and Expanded Register File. The register file is com- posed of 256/144 bytes of RAM. It includes four I/O port registers, 15 control and status registers and the rest are General-Purpose registers. The Expanded Register File consists of two additional register groups (F and D). Exter- nal Memory is not available on 18 and 20-pin versions. Part ROM (KB) RAM* (Bytes) I/O Voltage Ranges Z86L70 2 125 14 2.0V to 3.9V Z86L71 8 237 16 2.0V to 3.9V Z86L75 4 237 14 2.0V to 3.9V Z86C71 8 237 16 4.5V to 5.5V Note: *General-Purpose
Figure 1. Counter/Timer Block Diagram
Figure 2. Functional Block Diagram
may affect device reliability. conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 5). = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
- Voltage on all pins with respect to GND.
Figure 5. Test Load Diagram
IR/Low-Voltage Microcontroller Zilog 1-6 P R E L I M I N A R Y DS97LVO0500 DC CHARACTERISTICS (Z86L70/71/75 LOW VOLTAGE SPECIFICATIONS) Preliminary T A = 0 C to +70 C Typ @ Sym Parameter V CC Min Max 25 C Units Conditions Notes Max Input Voltage 2.0V 3.9V V V I IN <250 m A I IN <250 m A V CH Clock Input High Voltage 2.0V 3.9V 0.8 V CC 0.8 V CC V CC + 0.3 V CC + 0.3 V V Driven by External Clock Generator Driven by External Clock Generator V CL Clock Input Low Voltage 2.0V 3.9V V SS – 0.3 V SS – 0.3 0.2 V CC 0.2 V CC V V Driven by External Clock Generator Driven by External Clock Generator V IH Input High Voltage 2.0V 3.9V 0.7 V CC 0.7 V CC V CC + 0.3 V CC + 0.3 0.5V CC 0.5V CC V V V IL Input Low Voltage 2.0V 3.9V V SS – 0.3 V SS – 0.3 0.2 V CC 0.2 V CC 0.5VCC 0.5VCC V V VOH1 Output High Voltage 2.0V 3.9V VCC – 0.4 VCC – 0.4 1.7 3.7 V V IOH = –0.5 mA IOH = –0.5 mA VOH2 Output High Voltage (P36, P37,P00, P01) 2.0V 3.9V V CC - 0.8 VCC - 0.8 V V IOH = –7 mA IOH = –7 mA VOL1 Output Low Voltage 2.0V 3.9V 0.4 0.4 0.1 0.2 V V IOL = 1.0 mA IOL = 4.0 mA VOL2* Output Low Voltage 2.0V 3.9V 0.8 0.8 0.5 0.3 V V IOL = 5.0 mA IOL = 7.0 mA VOL2 Output Low Voltage(P36, P37,P00,P01) 2.0V 3.9V 0.8 0.8 0.3 0.2 V V I OL = 10 mA IOL = 10 mA VRH Reset Input High Voltage 2.0V 3.9V
0.8 VCC
1.5 2.0 V V VRl Reset Input Low Voltage 2.0V 3.9V VSS – 0.3 VSS – 0.3
0.2 VCC
0.5 0.9 V V VOFFSET Comparator Input Offset Voltage 2.0V 3.9V mV mV IIL Input Leakage 2.0V 3.9V < 1 < 1 mA mA VIN = OV, VCC VIN = OV, VCC IOL Output Leakage 2.0V 3.9V < 1 < 1 mA mA VIN = OV, VCC VIN = OV, VCC IIR Reset Input Pull- Up Current 2.0V 3.9V –230 –400 -50 –90 mA mA VIN = OV VIN = OV ICC Supply Current 2.0V 3.9V 2.0V 3.9V 250 850 100 500 mA mA mA mA @ 8.0 MHz @ 8.0 MHz @ 32 kHz @ 32 kHz 1,2 1,2 1,2,8
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-7 TA = 0°C to +70°C Typ @ Sym Parameter VCC Min Max 25 °C Units Conditions Notes ICC1 Standby Current (WDT Off) 2.0V 3.9V mA mA HALT Mode VIN = OV, VCC @
8.0 MHz
V IN = OV, VCC @ 8.0 MHz 1,2 1,2 2.0V 3.9V 0.8 2.5 mA mA Clock Divide-by- 16 @ 8.0 MHz Clock Divide-by- 16 @ 8.0 MHz 1,2 1,2 I CC2 Standby Current 2.0V 3.9V 2.0V 3.9V 500 800 310 600 mA mA mA mA STOP Mode V IN = OV, VCC WDT is not Running STOP Mode V IN = OV, VCC WDT is not Running STOP Mode V IN = OV, VCC WDT is Running 3,5 3,5 3,5 VICR Input Common Mode Voltage Range 2.0V 3.9V VCC - 1.0V VCC - 1.0V V V TPOR Power-On Reset 2.0V 3.9V ms ms VRAM Static RAM Data Retention Voltage Vram 0.8 0.5 V 6 VLV VCC Low Voltage Protection 2.15 1.7 V 8 MHz max Ext. CLK Freq. Notes: ICC1 Crystal/Resonator External Clock Drive Typ 3.0 mA 0.3 mA Max Unit mA mA Frequency
- All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF 3. Same as note [4] except inputs at V CC . 4. The VLV increases as the temperature decreases. 5. Oscillator stopped 6. Oscillator stops when VCC falls below VLV limit. 7. 32 kHz clock driver input. 8. For analog comparator, inputs when analog comparators are enabled. * All Outputs excluding P00, P01, P36, and P37.
IR/Low-Voltage Microcontroller Zilog 1-8 P R E L I M I N A R Y DS97LVO0500 DC CHARACTERISTICS (Z86C71 SPECIFICATIONS) Preliminary TA = 0°C to +70°C Typ @ Sym Parameter VCC Min Max 25 °C Units Conditions Notes Max Input Voltage 4.5V 5.5V V V IIN 250 mA IIN 250 mA VCH Clock Input High Voltage 4.5V 5.5V
0.9 VCC
VCC + 0.3 VCC + 0.3 V Driven by External Clock Generator V CL Clock Input Low Voltage 4.5V 5.5V VSS – 0.3 VSS –0.3 V IH Input High Voltage 4.5V 5.5V
0.7 VCC
VCC + 0.3 VCC + 0.3 0.5VCC 0.5VCC V Driven by External Clock Generator V IL Input Low Voltage 4.5V 5.5V VSS – 0.3 VSS – 0.3 0.5VCC 0.5VCC V VOH1 Output High Voltage 4.5V 5.5V VCC – 0.4 VCC – 0.4 4.4 5.4 VI OH = –0.5 mA IOH = –0.5 mA VOH2 Output High Voltage (P36, P37) 4.5V 5.5V V CC – 0.8 VCC – 0.8 V V IOH = –7 mA IOH = –7 mA VOL1 Output Low Voltage 4.5V 5.5V 0.4 0.4 0.1 0.2 V V IOL = 1.0 mA IOL = 4.0 mA VOL2* Output Low Voltage 4.5V 3.9 V 0.8 0.8 0.3 0.4 V V IOL = 5.0 mA IOL = 7.0 mA VOL2 Output Low Voltage (P00, P01, P36,P37) 4.5V 5.5V 0.8 0.8 0.3 0.2 VI OL = 10 mA VRH Reset Input High Voltage 4.5V 5.5V 2.5 3.0 V V VRl Reset Input Low Voltage 4.5V 5.5V VSS – 0.3 VSS – 0.3 0.5 0.9 VOFFSET Comparator Input Offset Voltage 4.5V 5.5V mV mV I IL Input Leakage 4.5V 5.5V mA mA VIN = OV, VCC VIN = OV, VCC IOL Output Leakage 4.5V 5.5V mA mA VIN = OV, VCC VIN = OV, VCC IIR Reset Input Current 4.5V 5.5V -500 -800 mA mA ICC Supply Current 4.5V 5.5V mA mA @8.0 MHz @8.0 MHz 1,2 1.2 WDT Off 4.5V 5.5V 1000 1250 mA mA @ 32 kHz @ 32 kHz 1,2,8 1,2,8
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-9 TA = 0°C to +70°C Typ @ Sym Parameter VCC Min Max 25 °C Units Conditions Notes ICC1 Standby Current (WDT Off) 4.5V 5.5V mA mA HALT Mode VIN = OV, VCC @ V IN = OV, VCC @ 8.0 MHz 1,2 1,2 4.5V 5.5V 1.0 3.0 mA mA Clock Divide-by- 16 @ 8.0 MHz Clock Divide-by- 16 @ 8.0 MHz 1,2 1,2 I CC2 Standby Current 4.5V 5.5V mA mA STOP Mode VIN = OV, VCC WDT is not Running STOP Mode V IN = OV, VCC WDT is not Running 3,5 3,5 4.5V 5.5V 500 800 310 600 mA mA STOP Mode V IN = OV, VCC WDT is Running 3,5 VICR Input Common Mode Voltage Range 2.0V 3.9V VCC - 1.0V VCC - 1.0V V V TPOR Power-On Reset 4.5V 5.5V 5.0 4.0 8.0 6.0 ms ms VRAM Static RAM Data Retention Voltage VRAM 0.8 0.5 V 6 VLV VCC Low Voltage Protection 2.15 1.7 V 8 MHz max Ext. CLK Freq. Notes: ICC1 Crystal/Resonator External Clock Drive Typ 3.5 mA 0.8 mA Max Unit mA mA Frequency
- All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF 3. Same as note [4] except inputs at V CC . 4. The VLV increases as the temperature decreases. 5. Oscillator stopped 6. Oscillator stops when VCC falls below VLV limit. 7. 32 kHz clock driver input 8. For analog comparator, inputs when analog comparators are enabled. * All Outputs excluding P00, P01, P36, and P37.
Figure 6. External I/O or Memory Read/Write Timing
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-11 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table TA = 0°C to +70°C No Symbol Parameter VCC Min Max Units Notes
1 TdA(AS) Address Valid to /AS
2.0V 3.9V ns ns
2 TdAS(A) /AS Rising to Address
2.0V 3.9V ns ns
3 TdAS(DR) /AS Rising to Read
2.0V 3.9V 400 400 ns ns 1,2 4 TwAS /AS Low Width 2.0V 3.9V ns ns
5 Td Address Float to /DS
2.0V 3.9V ns ns 6 TwDSR /DS (Read) Low Width 2.0V 3.9V 300 300 ns ns 1,2 7 TwDSW /DS (Write) Low Width 2.0V 3.9V 165 165 ns ns 1,2
8 TdDSR(DR) /DS Falling to Read
2.0V 3.9V 260 260 ns ns 1,2
9 ThDR(DS) Read Data to
/DS Rising Hold Time 2.0V 3.9V ns ns
10 TdDS(A) /DS Rising to Address
2.0V 3.9V ns ns 11 TdDS(AS) /DS Rising to /AS 2.0V 3.9V ns ns
12 TdR/W(AS) R//W Valid to /AS
2.0V 3.9V ns ns
13 TdDS(R/W) /DS Rising to
2.0V 3.9V ns ns
14 TdDW(DSW) Write Data Valid to
/DS Falling (Write) Delay 2.0V 3.9V ns ns
15 TdDS(DW) /DS Rising to Write
2.0V 3.9V ns ns
16 TdA(DR) Address Valid to Read
2.0V 3.9V 475 475 ns ns 1,2
17 TdAS(DS) /AS Rising to /DS
2.0V 3.9V 100 100 ns ns
18 TdM(AS) /DM Valid to /AS
2.0V 3.9V ns ns
19 TdDS(DM) /DS Rise to /DM Valid
2.0V 3.9V ns ns
20 ThDS(A) /DS Rise to Address
2.0V 3.9V ns ns Notes: 1. When using extended memory timing add 2 TpC. 2. Timing numbers given are for minimum TpC. Standard Test Load All timing references use 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0.
Figure 7. Additional Timing
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-13 AC CHARACTERISTICS Additional Timing Table TA = 0°C to +70°C No Symbol Parameter VCC Min Max Units Notes 1 TpC Input Clock Period 2.0V 3.9V 121 121 DC DC ns ns
2 TrC, TfC Clock Input Rise and
2.0V 3.9V ns ns 3 TwC Input Clock Width 2.0V 3.9V ns ns
4 TwTinL Timer Input Low
2.0V 3.9V 100 ns ns
5 TwTinH Timer Input High
2.0V 3.9V 3TpC 3TpC 6 TpTin Timer Input Period 2.0V 3.9V 8TpC 8TpC 7 TrTin, TfTin Timer Input Rise 2.0V 3.9V 100 100 ns ns 8A TwIL Interrupt Request Low Time 2.0V 3.9V 100 ns ns 1,2 1,2 8B TwIL Int. Request Low Time 4.5V 5.5V 5TpC 5TpC 1,3 1,3
9 TwIH Interrupt Request
4.5V 5.5V 5TpC 5TpC 1,2 1,2
10 Twsm Stop-Mode
2.0V 3.9V 2.0V 5TpC 5TpC ns ns
11 Tost Oscillator Start-up
2.0V 3.9V 5TpC 5TpC
12 Twdt Watch-Dog Timer
(5 ms) 2.0V 3.9V ms ms D0=0, 5 D1=0, 5 10 ms 2.0V 3.9V 150 ms ms D0=1, 5 D1=0, 5 20 ms 2.0V 3.9V 300 ms ms D0=1, 5 D1=0, 5 80 ms 2.0V 3.9V 225 1200 320 ms ms D0=1, 5 D1=0, 5 Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. Interrupt request through Port 3 (P30). 4. SMR - D5 = 0 5. Reg. WDTMR 6. Reg. SMR - D5 = 0 7. Reg. SMR - D5 = 1
network to the on-chip oscillator output. Figure 8. Port 0 Configuration
ured as inputs with open-drain outputs. Figure 9. Port 2 Configuration
put/Output, Interrupt, and output from the counter/timers. capability (controlled by P3M, D0). circuit is through P31 or P20 (see CTR1 description). nal interrupt request signals (IRQ2-IRQ0). ming bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2. Table 2. Pin Assignments Figure 10. Port 3 Configuration
0 Normal Control
Figure 12. Port 3 Configuration
- Stop-Mode Recovery Source
8 KB of internal program memory, with the remainder be-
Figure 13. Program Memory Map
IR/Low-Voltage Microcontroller Zilog 1-20 P R E L I M I N A R Y DS97LVO0500 Expanded Register File. The register file has been ex- panded to allow for additional system control registers, and for mapping of additional peripheral devices into the register address area. The Z8 register address space R0 through R15 has been implemented as 16 banks of 16 reg- isters per bank. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of register RP se- lect the working register group. Bits 3-0 of register RP se- lect the expanded register file bank. Note that expanded register bank is also referred to as expanded register group (Figure14). The upper nibble of the register pointer (Figure 23) selects which working register group of 16 bytes in the register file, out of the possible 256, will be accessed. The lower nibble selects the expanded register file bank and, in the case of the Z86LXX family, banks 0, F, and D are implemented. A 0h in the lower nibble will allow the normal register file (bank 0) to be addressed, but any other value from 1H to FH will exchange the lower 16 registers to an expanded register bank. For example: Z86L70: (See Figure 16) R253 RP = 00H R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0DH R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved The counter/timers are mapped into ERF group D. Access is easily done using the following example: LD RP, #0DH Select ERF D for access to bank D ( work- ing register group 0) LD R0,#xx load CTRL0 LD 1, #xx load CTRL1 LD R1, 2 CTRL2 fi CTRL1 LD RP, #7DH Select expanded register bank D and working register group 7 of bank 0 for access . LD 71H, 2 CTRL2 fi register 71H LD R1, 2 CTRL2 fi register 71H
Figure 14. Expanded Register File Architecture † Will not be reset with a Stop-Mode Recovery , except Bit 0.
0 UUUUUU
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-23 Counter/Timer Register Description HI8(D)%0B: Holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 1. L08(D)%0A: Holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 0. HI16(D)%09: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the MS- Byte of the data. L016(D)%08: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the LS- Byte of the data. TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register. TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register. TC8H(D)%05: Counter/Timer8 High Hold Register. TC8L(D)%04: Counter/Timer8 Low Hold Register. Expanded Register Group D (D)%0C Reserved (D)%0B HI8 (D)%0A LO8 (D)%09 HI16 (D)%08 LO16 (D)%07 TC16H (D)%06 TC16L (D)%05 TC8H (D)%04 TC8L (D)%03 Reserved (D)%02 CTR2 (D)%01 CTR1 (D)%00 CTR0 Field Bit Position Description T8_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position Description T16_Capture_LO 76543210 R W Captured Data No Effect Field Bit Position Description T16_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position Description T16_Capture_LO 76543210 R W Captured Data No Effect Field Bit Position Description T16_Data_HI 76543210 R W Data Field Bit Position Description T16_Data_LO 76543210 R/W Data Field Bit Position Description T8_Level_HI 76543210 R/W Data Field Bit Position Description T8_Level_LO 76543210 R/W Data
IR/Low-Voltage Microcontroller Zilog 1-24 P R E L I M I N A R Y DS97LVO0500 CTR0 (D)00: Counter/Timer8 Control Register. CTR0: Counter/Timer8 Control Register Description T8 Enable. This field enables T8 when set (written) to 1. Single/Modulo-N. When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Time-Out. This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to this lo- cation. This is the only way to reset this status condition, therefore, care should be taken to reset this bit prior to us- ing/enabling the counter/timers. Note: Care must be taken when utilizing the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers will be ORed or ANDed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a reset condition will occur. T8 Clock. Defines the frequency of the input signal to T8. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask. Set this bit to allow interrupt when T8 has a time out. P34_Out. This bit defines whether P34 is used as a normal output pin or the T8 output. Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass Time_Out --5----- R 0 No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T8_Clock ---43--- R/W 0 0 0 1 1 0 1 1 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W 0 Disabled Data Capture Int. Enable Data Capture Int. Disable Data Capture Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-25 CTR1 (D)01: Controls the functions in common with the T8 and T16 Field Bit Position Value Description Transmit Mode Demodulation Mode P36_Out/ Demodulator_Input T ransmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 T8/T16_Logic/ Edge _Detect --54---- R/W T ransmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit_Submode/Glitch_ Filter ----32-- R/W T ransmit Mode Normal Operation Ping-Pong Mode T16_Out=0 T16_Out=1 Demodulation Mode No Filter
4 SCLK Cycle
8 SCLK Cycle
16 SCLK Cycle
Initial_T8_Out/ Rising_Edge R/W R W T ransmit Mode T8_OUT is 1 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Initial_T16_Out/ Falling _Edge R/W R W T ransmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0
IR/Low-Voltage Microcontroller Zilog 1-26 P R E L I M I N A R Y DS97LVO0500 CTR1 Register Description Mode. If it is 0, the Counter/Timers are in the transmit mode, otherwise they are in the demodulation mode. P36_Out/Demodulator_Input. In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/Timers is from P20 or P31. T8/T16_Logic/Edge _Detect. In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter. In Transmit Mode, this field defines whether T8 and T16 are in the "Ping-Pong" mode or in independent normal operation mode. Setting this field to "Normal Operation Mode" terminates the "Ping- Pong Mode" operation. When set to 10, T16 is immediately forced to a 0. When set to 11, T16 is immediately forced to a 1. In Demodulation Mode, this field defines the width of the glitch that should be filtered out. Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the out- put of T8 is set to 1 when it starts to count. When this bit is set to 1 or 0, T8_OUT will be set to the opposite state of this bit. This insures that when the clock is enabled a tran- sition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). When this bit is set, T16_OUT will be set to the opposite state of this bit. This insures that when the clock is enabled a transition occurs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Note: Modifying CTR1, (D1 or D0) while the counters are enabled will cause un-predictable output from T8/16_OUT.
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-27 CTR2 (D)%02: Counter/Timer16 Control Register. CTR2 Description T16_Enable. This field enables T16 when set to 1. Single/Modulo-N. In Transmit Mode, when set to 0, the counter reloads the initial value when terminal count is reached. When set to 1, the counter stops when the termi- nal count is reached. In Demodulation Mode, when set to 0 , T16 captures and reloads on detection of all the edges; when set to 1, T16 captures and detects on the first edge, but ignores the sub- sequent edges. For details, see the description of T16 De- modulation Mode. Time_Out. This bit is set when T16 times out (terminal count reached). In order to reset it, a 1 should be written to this location. T16_Clock. Defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into LO16 and HI16. Counter_INT_Mask. Set this bit to allow interrupt when T16 times out. P35_Out. This bit defines whether P35 is used as a normal output pin or T16 output. Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge Time_Out --5----- R0 No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T16 _Clock ---43---R/W 00 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2--R/W 0 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P35 as Port Output T16 Output on P35 Note: * Indicates the value upon Power-On Reset
IR/Low-Voltage Microcontroller Zilog 1-28 P R E L I M I N A R Y DS97LVO0500 SMR2(F)%0D: Stop-Mode Recovery Register 2. Field Bit Position Value Description Low High Reserved --5----- 0 Reserved (Must be 0) Source ---432--W 000* 001 010 011 100 101 110 111 A. POR Only B. NAND of P23-P20 C. NAND or P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F . NOR of P33-P31, P00,P07 G. NAND of P33-P31,P00,P07 H. NAND of P33-P31,P22-P20 Note: * Indicates the value upon Power-On Reset.
Figure 21. Demodulation Mode Count Capture Flowchart
Figure 22. Transmit Mode Flowchart
Figure 23. Demodulation Mode Flowchart
programming CTR1 D3, D2 to a 10 or 11. and T16_OUT is switched to its initial value (CTR1 D0). Figure 24. 16-Bit Counter/Timer Circuits
reset the status flags prior to instituting this operation. abling either T8 (CTR0 D7) or T16 (CTR2 D7). counter/timers reach the terminal count. Figure 27. Ping-Pong Mode
Change Transmit Mode to Normal Mode (CTR1 D2, D3). Figure 28. T8_OUT and T16_OUT in Ping-Pong Mode
Figure 29. Output Circuit
Figure 30. Interrupt Block Diagram
gram memory vector location reserved for that interrupt. of the interrupt requests need service. ware can poll to identify the state of the pin. or other suitable external clock source. greater than or equal to 22 pF) from each pin to ground. pacitor from XTAL1 to ground (Figure 8). Table 3. Interrupt Types, Sources, and Vectors Table 4. IRQ Register
00 F F
01 F R
10 R F
- Power Fail to Power OK status.
- Stop-Mode Recovery (if D5 of SMR = 1).
Figure 31. Oscillator Configuration
rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. Figure 32. Port Configuration Register (PCON)
0 P34,Standard Output*
1 P34,Comparator Output
to its standard I/O configuration. ter, specify the source of the Stop-Mode Recovery signal. Bit D0 determines if SCLK/TCLK are divided by 16 or not. Figure 33. Stop-Mode Recovery Register
0 OFF
0 Low
0 POR
1 Stop Recovery * *
Figure 34. Stop-Mode Recovery Source
logic). After Stop-Mode Recovery, this bit is set to a 0. STOP recovery (Figure 36 and Table 5). lines are configured as analog input. ister for other recover sources. needs to be kept active for at least 5TpC. specified events will cause a Stop-Mode Recovery. Figure 35. SCLK Circuit Table 5. Stop-Mode Recovery Source
Figure 36. Stop-Mode Recovery Register 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
0 Low*
1 High
the Zero (Z), Sign (S), and Overflow (V) flags. Figure 37. Watch-Dog Timer Mode Register
0 On-Chip RC
1 XT AL
WDT Time Select (D0, D1). Selects the WDT time period. It is configured as shown in Table 6. active during HALT. The default is 1. ration of this bit is 0, which selects the RC oscillator. Table 6. WDT Time Select
- The default on reset is 10 ms.
Figure 38. Resets and WDT
18 Clock RESET
5 Clock
18 Clock Reset timers upon a Low to High input transition.
when port pins are configured as outputs. Figure 39. Typical Z86L7X Low Voltage vs
Figure 40. TC8 Control Register
0 P34 as Port Output
1 Timer8 Output
0 Disable T8 Time Out Interrupt
1 Enable T8 Time Out Interrupt
0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt
00 SCLK on T8
01 SCLK/2 on T8
10 SCLK/4 on T8
0 Modulo-N
1 Single Pass
Figure 41. T8 and T16 Common Control Functions
0 T16_OUT is 0 Initially
1 T16_OUT is 1 Initially
0 No Falling Edge Detection
1 Falling Edge Detection
0 No Effect
1 Reset Flag to 0
0 T8_OUT is 0 Initially
1 T8_OUT is 1 Initially
0 No Rising Edge Detection
1 Rising Edge Detection
0 P36 as Port Output *
1 P36 as T8/T16_OUT
0 Transmit Mode *
1 Demodulation Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
Transmit Mode from Demodulation Mode. disabling the counter/timers.
Figure 42. T16 Control Register
0 P35 is Port Output
1 P35 is TC16 Output
0 Disable T16 Time-Out Interrupt
1 Enable T16 Time-Out Interrupt
0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt
0 Modulo-N for T16
1 Single Pass for T16
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
Figure 43. Stop-Mode Recovery Register
1 Stop Recovery**
Figure 44. Stop-Mode Recovery Register 2
Figure 45. Watch-Dog Timer Mode Register Figure 46. Port Configuration Register (PCON)
Figure 47. Port 3 Mode Register Figure 48. Port 0 and 1 Mode Register
0 Port 2 Open Drain*
1 Port 2 Push-pull
0 P32 = Input
1 P32 = /DA V0/RDY0
0 P31 = Input (TIN)
1 P31 = /DA V2/RDY2
00 P33 = Input
01 P33 = Input
10 P34 = /DM
Note: D0 affects P34, P35 as well as Port 2.
00 Output
01 Input*
0 External
1 Internal*
0 Normal*
1 Extended
- Default Setting After Reset.
Note: Only P00 and P07 are Available on Z86L71. Figure 49. Port 2 Mode Register Figure 50. Interrupt Priority Register
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
000 Reserved
001 C>A>B
010 A>B>C
011 A>C>B
100 B>C>A
101 C>B>A
110 B>A>C
111 Reserved
0 IRQ1>IRQ4
1 IRQ4>IRQ1
0 IRQ2>IRQ0
1 IRQ0>IRQ2
0 IRQ5>IRQ3
1 IRQ3>IRQ5
Figure 51. Interrupt Request Register Figure 52. Interrupt Mask Register Figure 53. Flag Register
1 Enables IRQ4-IRQ0
0 Master Interrupt Disable*
1 Master Interrupt Enable
Figure 54. Register Pointer Figure 55. Stack Pointer High Figure 56. Stack Pointer Low
Zilog IR/Low-Voltage Microcontroller DS97LVO0500 P R E L I M I N A R Y 1-61
ORDERING INFORMATION
16.0 MHz
P = Plastic DIP S = SOIC (Small Outline Chip Carrier) Temperature Standard = 0 °C to +70 °C Environmental C = Plastic Standard © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com Example: Z 86L71 08 P S C Environmental Flow T emperature Package Speed Product Number Zilog Prefix is a Z86L71, 8 MHz, DIP, 0°C to +70°C, Plastic Standard Flow