Z86C02 ZILOG | Alldatasheet
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P RELIMINARY P RODUCT S PECIFICATION Z86C02/E02/L02 C OST E FFECTIVE , 512-B YTE ROM CMOS Z8 M ICROCONTROLLERS
FEATURES
n 18-Pin DIP and SOIC Packages n C to 70 C Standard Temperature –40 C to 105 C Extended Temperature (Z86C02/E02 only) n 3.0V to 5.5V Operating Range (Z86C02) 4.5V to 5.5V Operating Range (Z86E02) 2.0V to 3.9V Operating Range (Z86L02) n
14 Input / Output Lines
n Five Vectored, Prioritized Interrupts from Five Different Sources n Two On-Board Comparators n Software Enabled Watch-Dog Timer (WDT) n Programmable Interrupt Polarity n Two Standby Modes: STOP and HALT n Low-Voltage Protection n ROM Mask/OTP Options: – Low-Noise (Z86C02/E02 only) – ROM Protect – Auto Latch – Permanent Watch-Dog Timer (WDT) – RC Oscillator (Z86C02/L02 Only) – 32 KHz Operation (Z86C02/L02 Only) n One Programmable 8-Bit Counter/Timer with a 6-Bit Programmable Prescaler n Power-On Reset (POR) Timer n On-Chip Oscillator that Accepts RC, Crystal, Ceramic Resonator, LC, or External Clock Drive (C02/L02 only) n On-Chip Oscillator that Accepts RC or External Clock Drive (Z86E02 SL1903 only) n On-Chip Oscillator that Accepts Crystal, Ceramic Resonator, LC, or External Clock Drive (Z86E02 only) n Clock-Free WDT Reset n Low-Power Consumption (50mw) n Fast Instruction Pointer (1.5 m s @ 8 MHz) n Fourteen Digital Inputs at CMOS Levels; Schmitt-Triggered GENERAL DESCRIPTION Zilog's Z86C02/E02/L02 microcontrollers (MCUs) are members of the Z8 single-chip MCU family, which offer easy software/hardware system expansion. For applications demanding powerful I/O capabilities, the MCU's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. One on-chip counter/timer, with a large number of user-se- lectable modes, off-load the system of administering real- time tasks such as counting/timing and I/O data communi- Device ROM (KB) RAM* (Bytes) Speed (MHz) Auto Latch Permanent WDT Z86C02 512 61 8 Optional Optional Z86E02 512 61 8 Optional Optional Z86L02 512 61 8 Optional Optional Note: *General-Purpose
Figure 1. Z86C02/E02/L02 Functional Block Diagram
Figure 2. EPROM Programming Mode Block Diagram
3 Bits
Figure 3. 18-Pin Standard Mode Configuration Table 1. 18-Pin Standard Mode Identification
6 XTAL2 Crystal Oscillator
7 XTAL1 Crystal Oscillator
8 P31 Port 3, Pin 1, AN1 Input
9 P32 Port 3, Pin 2, AN2 Input
10 P33 Port 3, Pin 3, REF Input
14 GND Ground
Figure 4. 18-Pin EPROM Mode Configuration Table 2. 18-Pin EPROM Mode Identification
5 Vcc Power Supply
6 NC No Connection
9 EPM EPROM Program
10 VPP Program Voltage Input
11 Clear Clear Clock Input
12 Clock Address Input
Figure 5. 18-Pin SOIC Configuration Table 3. 18-Pin SOIC Pin Identification
operational sections of these specifications is not implied. extended period may affect device reliability.
- This applies to all pins except where otherwise noted.
- Maximum current into pin must be
- This excludes Pin 6 and Pin 7.
- Device pin is not at an output Low state.
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Figure 6. Test Load Diagram
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers Zilog
6 P R E L I M I N A R Y DS96DZ80301
DC ELECTRICAL CHARACTERISTICS Z86C02 TA = 40°C to +105°C TA = 0°C to +70°C Typical Sym. Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 3.0V 0.8 V CC VCC +0.3 1.7 V Driven by External Clock Generator 5.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator VCL Clock Input Low Voltage 3.0V V SS –0.3 0.2 V CC 0.8 V Driven by External Clock Generator 5.5V V SS –0.3 0.2 V CC 1.7 V Driven by External Clock Generator VIH Input High Voltage 3.0V 0.7 V CC VCC +0.3 1.8 V [1] 5.5V 0.7 V CC VCC +0.3 2.8 V [1] VIL Input Low Voltage 3.0V V SS –0.3 0.2 V CC 0.8 V [1] 5.5V V SS –0.3 0.2 V CC 1.5 V [1] VOH Output High Voltage 3.0V V CC –0.4 3.0 V I OH = –2.0 mA [5] 5.5V V CC –0.4 4.8 V I OH = –2.0 mA [5] 3.0V V CC –0.4 3.0 V Low Noise @ IOH = –0.5 mA 5.5V V CC –0.4 4.8 V Low Noise @ IOH = –0.5 mA VOL1 Output Low Voltage 3.0V 0.8 0.2 V I OL = +4.0 mA [5] 5.5V 0.4 0.1 V I OL = +4.0 mA [5] 3.0V 0.8 0.2 V Low Noise @ IOL = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA VOL2 Output Low Voltage 3.0V 1.0 0.8 V I OL = +12 mA [5] 5.5V 0.8 0.3 V I OL = +12 mA [5] VOFFSET Comparator Input Offset Voltage 3.0V 25 10 mV 5.5V 25 10 mV VLV VCC Low Voltage Auto Reset V 2.2 2.8 2.6 V [9] 2.0 3.0 2.6 V [10] I IL Input Leakage (Input Bias Current of Comparator) 3.0V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC IOL Output Leakage 3.0V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC VVICR Comparator Input Common Mode Voltage Range V SS –0.3 V CC –1.0 V [9] VSS –0.3 V CC –1.5 V [10]
Zilog Cost Effective, 512-Byte ROM CMOS Z8 ® Microcontrollers DS96DZ80301 P R E L I M I N A R Y 7 DC CHARACTERISTICS Z86C02 TA = 40°C to+105°C TA = 0°C to +70°C Typical Sym. Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes ICC Supply Current 3.0V 3.5 1.5 mA @ 2 MHz [5,6,7] 5.5V 11.0 4.4 mA @ 8 MHz [5,6,7] I CC1 Standby Current (Halt Mode) 3.0V 2.5 0.7 mA @ 2 MHz [5,6,7] I CC Supply Current (Low Noise Mode) 3.0V 3.5 1.5 mA @ 1 MHz [5,6,7] 5.5V 11.0 4.4 mA @ 4 MHz [5,6,7] I CC1 Standby Current (Low Noise Halt Mode) I CC2 Standby Current (Stop Mode) 3.0V 10 1.0 mA [6,7,8,9] IALL Auto Latch Low Current 3.0V 12 3.0 mA 0V < V IN < VCC 5.5V 32 16 mA 0V < V IN < VCC IALH Auto Latch High Current 3.0V –8 -1.5 mA 0V < V IN < VCC 5.5V –16 -8.0 mA 0V < V IN < VCC Notes: 1. ort 0, 2, and 3 only. 2. V SS = 0V = GND. 3. The device operates down to VLV The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. 5. Standard mode (not Low EMI mode). 6. Inputs at VCC or VSS , outputs unloaded. 7. Halt mode and Low EMI mode. 8. WDT not running. 9. T A= 0˚C to 70˚C. 10. TA= 40˚C to 105˚C.
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers Zilog
8 P R E L I M I N A R Y DS96DZ80301
TA = 0°C to +70°C Typical Sym. Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 2.0V 0.9 V CC VCC +0.3 V Driven by External Clock Generator 3.9V 0.9 V CC VCC +0.3 V Driven by External Clock Generator VCL Clock Input Low Voltage 2.0V V SS –0.3 0.1 V CC V Driven by External Clock Generator 3.9V V SS –0.3 0.1 V CC V Driven by External Clock Generator VIH Input High Voltage 2.0V 0.9 V CC VCC +0.3 V [1] 3.9V 0.9 V CC VCC +0.3 V [1] VIL Input Low Voltage 2.0V V SS –0.3 0.1 V CC V [1] 3.9V V SS –0.3 0.1 V CC V [1] VOH Output High Voltage 2.0V V CC –0.4 3.0 V I OH = – 500 mA [5] 3.9V V CC –0.4 3.0 V I OH = –500 mA [5] VOL1 Output Low Voltage 2.0V 0.8 0.2 V I OL = +1.0 mA [5] 3.9V 0.4 0.1 V I OL = +1.0 mA [5] VOL2 Output Low Voltage 2.0V 1.0 0.8 V I OL = + 3.0 mA [5] 3.9V 0.8 0.3 V I OL = + 3.0 mA [5] VOFFSET Comparator Input Offset Voltage 2.0V 25 10 mV 3.9V 25 10 mV VLV VCC Low Voltage Auto Reset 1.4 2.15 V IIL Input Leakage (Input Bias Current of Comparator) 2.0V –1.0 1.0 mAV IN = 0V, VCC 3.9V –1.0 1.0 mAV IN = 0V, VCC IOL Output Leakage 2.0V –1.0 1.0 mA VIN = 0V, VCC 3.9V –1.0 1.0 mAV IN = 0V, VCC VVICR Comparator Input Common Mode Voltage Range V SS –0.3 V CC –1.0 V
Zilog Cost Effective, 512-Byte ROM CMOS Z8 ® Microcontrollers DS96DZ80301 P R E L I M I N A R Y 9 TA = 0°C to +70°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes ICC Supply Current 2.0V 3.3 mA @ 2 MHz [5,6] 3.9V 6.8 mA @ 2 MHz [5,6] 2.0V 6.0 mA @ 8 MHz [5,6] 3.9V 9.0 mA @ 8 MHz [5,6] I CC1 Standby Current (Halt Mode) 2.0V 2.3 mA @ 2 MHz [5,6,7] I CC2 Standby Current (Stop Mode) 2.0V 10 1.0 mA [6,7] 3.9V 10 1.0 mA [6,7] IALL Auto Latch Low Current 2.0V 12 3.0 mA 0V < V IN < VCC 3.9V 32 16 mA 0V < V IN < VCC IALH Auto Latch High Current 2.0V –8 -1.5 mA 0V < V IN < VCC 3.9V –16 -8.0 mA Notes: 1. Port 0, 2, and 3 only 2. V SS = 0V = GND.The device operates down to VLV. The minimum operational VCC is determined by the value of the voltage VLV at the ambient temperature. 4. Standard Mode (not Low EMI mode). 5. Inputs at VCC or VSS , outputs are unloaded. 6. WDT is not running.
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers Zilog
10 P R E L I M I N A R Y DS96DZ80301
TA = –40°C to +105°C TA = 0°C to +70°C Typical Sym. Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 4.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator 5.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V V SS –0.3 0.2 V CC 1.7 V Driven by External Clock Generator 5.5V V SS– 0.3 0.2 V CC 1.7 V Driven by External Clock Generator VIH Input High Voltage 4.5V 0.7 V CC VCC +0.3 2.8 V 5.5V 0.7 V CC VCC +0.3 2.8 V VIL Input Low Voltage 4.5V V SS –0.3 0.2 V CC 1.5 V 5.5V V SS –0.3 0.2 V CC 1.5 V VOH Output High Voltage 4.5V V CC –0.4 4.8 V I OH = –2.0 mA [5] 5.5V V CC –0.4 4.8 V I OH = –2.0 mA [5] 4.5V V CC –0.4 4.8 V Low Noise @ IOH = –0.5 mA5.5V V CC –0.4 4.8 V VOL1 Output Low Voltage 4.5V 0.4 0.1 V I OL = +4.0 mA [5] 5.5V 0.4 0.1 V I OL = +4.0 mA [5] 4.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA VOL2 Output Low Voltage 4.5V 1.0 0.8 V I OL = +12 mA [5] 5.5V 1.0 0.8 V I OL = +12 mA [5] VOFFSET Comparator Input Offset Voltage 4.5V 25 10 mV 5.5V 25 10 mV VLV VCC Low Voltage Auto Reset 2.6 3.3 3.0 V [9] 2.2 3.6 3.0 V [10] IIL Input Leakage (Input Bias Current of Comparator) 4.5V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC IOL Output Leakage 4.5V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC VVICR Comparator Input Common Mode Voltage Range V SS –0.3 V CC –1.0 V [9] VSS –0.3 V CC –1.5 V [10]
Zilog Cost Effective, 512-Byte ROM CMOS Z8 ® Microcontrollers DS96DZ80301 P R E L I M I N A R Y 11 TA = –40°C to +105°C TA = 0°C to +70°C Typical Sym. Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes ICC Supply Current 4.5V 9.0 3.8 mA @ 2 MHz [5,6] 5.5V 9.0 3.8 mA @ 2 MHz [5,6] 4.5V 15.0 4.4 mA @ 8 MHz [5,6] 5.5V 15.0 4.4 mA @ 1 MHz [5,6] I CC1 Standby Current (HALT mode) 4.5V 4.0 2.5 mA @ 2 MHz [5,6] 5.5V 4.0 2.5 mA @ 2 MHz [5,6] 4.5V 5.0 3.0 mA @ 4 MHz [5,6] 5.5V 5.0 3.0 mA @ 4 MHz [5,6] I CC Supply Current (Low Noise Mode) 4.5V 11.0 4.0 mA @ 2 MHz [6] 5.5V 11.0 4.0 mA @ 2 MHz [6] 4.5V 15.0 4.4 mA @ 4 MHz [6] 5.5V 15.0 4.4 mA @ 4 MHz [6] I CC1 Standby Current (Low Noise Halt Mode) I CC2 Standby Current (Stop Mode) 4.5V 10 1.0 mA [6,7,9] 5.5V 20 1.0 mA 6,7,10] IALL Auto Latch Low Current 4.5V 32 16 mA 0V <V IN<VCC 5.5V 32 16 mA 0V <V IN<VCC ALH Auto Latch High 4.5V –16 -8.0 mA 0V <V IN<VCC 5.5V –16 –8.0 mA 0V <V IN<VCC Notes: 1. Port 0, 2, and 3 only. 2. V SS = 0V = GND. 3. The device operates down to VLV of the specified frequency for VLV. The minimum operational VCC is determined by the value of the voltage VLV at the ambient temperature. 4. The VLV increases as the temperature decreases. 6. Standard mode (not Low EMI mode). 7. Inputs at VCC or VSS , outputs unloaded. 8. WDT not running. 9. Halt mode and Low EMI mode. 10. TA= 0˚C to 70˚C.TA= –40˚C to 105˚C.
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Figure 7. AC Electrical Timing Diagram
Zilog Cost Effective, 512-Byte ROM CMOS Z8 ® Microcontrollers DS96DZ80301 P R E L I M I N A R Y 13 AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) TA = –40°C to +105°C TA = 0°C to +70°C
8 MHz
No. Symbol Parameter VCC Min Max Units Notes 1 TpC Input Clock Period 2.0V 125 DC ns [1] 5.5V 125 DC ns [1] 2 TrC,TfC Clock Input Rise and Fall Times 2.0V 25 ns [1] 5.5V 25 ns [1] 3 TwC Input Clock Width 2.0V 62 ns [1] 5.5V 62 ns [1] 4 TwTinL Timer Input Low Width 2.0V 70 ns [1] 5.5V 70 ns [1] 5 TwTinH Timer Input High Width 2.0V 5TpC [1] 5.5V 5TpC [1] 6 TpTin Timer Input Period 2.0V 8TpC [1] 5.5V 8TpC [1]
7 TrTin,
Timer Input Rise and Fall Time 2.0V 100 ns [1] 5.5V 100 ns [1] 8 TwIL Int. Request Input Low Time 2.0V 70 ns [1,2,3] 5.5V 70 ns [1,2,3] 9 TwIH Int. Request Input High Time 3.0V 5TpC [1,2,3] 5.5V 5TpC [1,2,3] 10 Twdt Watch-Dog Timer Delay Time Before Time-Out 2.0V 25 ms 3.0V 10 ms 5.5V 5 ms
11 Tpor Power-On Reset Time
2.0V 70 250 ms [4] 3.0V 50 150 ms [4] 5.5V 10 70 ms [4] 2.0V 8 76 ms [5] 3.0V 4 38 ms [5] 5.5V 2 18 ms [5] Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. IRQ 0,1,2 only. 4. Z86E02 only. 5. Z86C02/L02 only.
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers Zilog
14 P R E L I M I N A R Y DS96DZ80301
AC ELECTRICAL CHARACTERISTICS Low Noise Mode (Z86C02/E02 Only) TA = –40°C to +105°C TA = 0°C to +70°C
1 MHz 4 MHz
No. Symbol Parameter VCC Min Max Min Max Units Notes 1 TPC Input Clock Period 3.0V 1000 DC 250 DC ns [1] 5.5V 1000 DC 250 DC ns [1] 2T r C TfC Clock Input Rise and Fall Times 3.0V 25 25 ns [1] 5.5V 25 25 ns [1] 3 TwC Input Clock Width 3.0V 500 125 ns [1] 5.5V 500 125 ns [1] 4. TwTinL Timer Input Low Width 3.0V 70 70 ns [1] 5.5V 70 70 ns [1] 5 TwTinH Timer Input High Width 3.0V 2.5TpC 2.5TpC [1] 5.5V 2.5TpC 2.5TpC [1] 6 TpTin Timer Input Period 3.0V 4TpC 4TpC [1] 5.5V 4TpC 4TpC [1] Timer Input Rise and Fall Time 3.0V 100 100 ns [1] 5.5V 100 100 ns [1] 8 TwIL Int. Request Input Low Time 3.0V 70 70 ns [1,2,3] 5.5V 70 70 ns [1,2,3] 9 TwIH Int. Request Input High Time 3.0V 2.5TpC 2.5TpC [1,2,3] 5.5V 2.5TpC 2.5TpC [1,2,3] 10 Tpor Power-On Reset Time 3.0V 50 150 50 150 ms [4] 5.5V 10 70 10 70 ms [4] 2.0V 8 76 8 76 ms [5] 3.0V 4 38 4 38 ms [5] 5.5V 2 18 2 18 ms [5] 11 Twdt Watch-Dog Timer Delay 3.0V 10 10 ms 5.5V 5 5 ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. IRQ 0,1,2 only. 4. Z86E02 only. 5. Z86C02/L02 only.
Zilog Cost Effective, 512-Byte ROM CMOS Z8 ® Microcontrollers DS96DZ80301 P R E L I M I N A R Y 15 LOW NOISE VERSION Low EMI Emission The Z8 can be programmed to operate in a Low EMI emis- sion mode by means of a mask ROM bit option (Z86C02) or OTP bit option (Z86E02). Use of this feature results in: n All pre-driver slew rates reduced to 10 ns typical. n Internal SCLK/TCLK operation limited to a maximum of 4 MHz - 250 ns cycle time. n Output drivers have resistances of 200 ohms (typical). n Oscillator divide-by-two circuitry eliminated. The Low EMI mode is mask-programmable to be selected by the customer at the time the ROM Code is submitted (for Z86C02 only). PRECAUTION Stack pointer register (SPL) at FFHex and general purpose register at FEHex are set to 00Hex after reset. PIN FUNCTIONS OTP Programming Mode D7-D0 Data Bus. Data can be read from, or written to the EPROM through this data bus. VCC Power Supply. It is 5V during EPROM Read Mode and 6.4V during the other modes (Program, Program Ver- ify, etc.). /CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. /OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input. This pin must toggle for each data output read. EPM EPROM Program Mode. This pin controls the differ- ent EPROM Program Modes by applying different voltages. V PP Program Voltage. This pin supplies the program volt- age. Clear Clear (active High). This pin resets the internal ad- dress counter at the High Level. Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle. /PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above V CC occur on the XTAL1 pin. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP , /CE, /EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following: n Using a clamping diode to VCC. n Adding a capacitor to the affected pin.
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reduces excessive supply current flow in the input buffer. Figure 8. Port 0 Configuration
directional, Schmitt-triggered CMOS compatible I/O port. ther push-pull or open-drain (Figure 9). Figure 9. Port 2 Configuration
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Schmitt-trigger inputs or analog inputs. serve as a reference voltage to the comparators. tios are 90 dB and 60 dB, respectively. output, or on the falling edge of Comparator 1's output. (P33) for use as IRQ1 and/or P33 input. Figure 10. Port 3 Configuration
Figure 11. Internal Reset Configuration
18 CLK
Table 4. Control Register
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program memory are reserved for the interrupt vectors. Figure 12. Program Memory Map Figure 13. Register File
eral-purpose registers. It is set to 00Hex after any reset. register. But is set to 00Hex after any reset. quest IRQ5 (T1) is generated. tinue counting (Modulo-N Continuous Mode). input for the internal clock. Figure 14. Register Pointer the active working-register group.
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five interrupt requests (Table 5). that particular interrupt request. determine which of the interrupt requests needs service. supported on the Z86CCP00ZEM emulator. Figure 15. Counter/Timers Block Diagram Table 5. Interrupt Types, Sources, and Vectors
8 MHz max, with a series resistance (RS) of less than or
to reduce Ground noise injection. Figure 16. Interrupt Block Diagram Figure 17. Oscillator Configuration
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers Zilog
24 P R E L I M I N A R Y DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued) HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timer and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac- tive. The device is recovered by interrupts, either external- ly or internally generated. An interrupt request must be ex- ecuted (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 mA. The STOP mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP mode. Program exe- cution begins at location 000C(Hex). However, when P27 is used to release the STOP mode, the I/O port mode reg- isters are not reconfigured to their default power-on condi- tions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an un- known state. To use the P27 release approach with STOP mode, use the following instruction: In order to enter STOP or HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, i.e.: Watch-Dog Timer (WDT). The Watch-Dog Timer is en- abled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT in- struction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time opcode 5FH is execut- ed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every T WDT ; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of T POR , plus 18 XTAL clock cycles.The WDT does not run in stop mode, unless the permanent WDT enable option is select- ed. The WDT does not run in halt mode unless WDH in- struction is executed or permanent WDT enable option is selected. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT mode. A WDH instruction executed without executing WDT (5FH) has no effect. Note: Opcode WDH and permanently enabled WDT is not directly supported by the Z86CCP00ZEM. Auto Reset Voltage (V LV). The Z8 has an auto-reset built- in. The auto-reset circuit resets the Z8 when it detects the V CC below VLV. Figure 18 shows the Auto Reset Voltage versus temperature. LD P2M, #1XXX XXXXB NOP STOP Notes: X = Dependent on user’s application. Stop-Mode Recovery pin P27 is not edge triggered. FF NOP ; clear the pipeline 6F STOP ; enter STOP mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT mode
n All drivers slew rates are reduced to 10 ns (typical). maximum of 4 MHz - 250 ns cycle time. n Output drivers have resistances of 200 ohms (typical). n Oscillator divide-by-two circuitry is eliminated. lected, the instructions LDC and LDCI are supported. permanently disable EPROM and Factory Test mode. lected will globally disable all Auto Latches. resistor (R) and a capacitor (C) as a clock source. not be stopped in HALT or STOP Mode. PP , and P02 functions as /PGM. both a diode and a 100 pF capacitor. Figure 18. Typical Auto Reset Voltage (VLV) vs. Temperature
26 P R E L I M I N A R Y DS96DZ80301
shows the timing of programming waveforms. of the Z86E02 programming algorithm. Table 6. EPROM Programming Table VIH=As per specific Z8 DC specification. VIL=As per specific Z8 DC specification. X=Not used, but must be set to VH , VIH, or VIL level. NU=Not used, but must be set to either VIH or VIL level. IPP during programming = 40 mA maximum. ICC during programming, verify, or read = 40 mA maximum.
- VCC has a tolerance of –0.25V.
Table 7. Z86E02 Timing of Programming Waveforms
1 Address Setup Time 2 ms
2 Data Setup Time 2 ms
5 Chip Enable Setup Time 2 ms
7 Data Hold Time 2 ms
9 Data Access Time 188 4000 ns
10 Data Output Float Time 100 ns
12 EPM Setup Time 2 ms
14 Address to /OE Setup Time 2 ms
15 Option Program Pulse Width 150 ms
Figure 19. Z86E02 Address Counter Waveform
0 Min
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Figure 20. Z86E02 Programming Waveform (EPROM Read)
Figure 21. Z86E02 Programming Waveform (Program and Verify)
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Figure 22. Z86E02 Programming Options Waveform (ROM Protect and Low Noise Program)
Figure 23. Z86E02 Programming Options Waveform (Auto Latch Disable,
32 P R E L I M I N A R Y DS96DZ80301
Figure 24. Z86E02 Programming Algorithm
Figure 25. Timer Mode Register (F1H : Read/Write) Figure 26. Counter Timer 1 Register (f2H :Read/Write) Figure 27. Prescaler! Register (F3H : Write Only) Figure 28. Port 2 Mode Register (F6H : Write Only)
0 Disable T Count
1 Enable T Count
0 No Function
1 Load T1
1 Enable T Count1
00 External Clock Input
01 Gate Input
10 Trigger Input
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 29. Port 3 Mode Register (F7H : Write Only) Figure 30. Port 0 and 1 Mode Register Figure 31. Interrupt Priority Register
0 Port 2 Open-Drain
1 Port 2 Push-pull
0 Digital Mode
1 Analog Mode
000 Reserved
001 C > A > B
010 A > B > C
100 B > C > A
101 C > B > A
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
34 P R E L I M I N A R Y DS96DZ80301
Figure 32. Interrupt Request Register Figure 33. Interrupt Mask Register (FBH : Read/Write) Figure 34. Flag Register (FCH : Read/Write)
1 Enables IRQ5-IRQ0
1 Enables Interrupts
Figure 35. Register Pointer FDH : Read/Write) Figure 36. Stack Pointer (FFH : Read/Write)
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers Zilog
36 P R E L I M I N A R Y DS96DZ80301
ORDERING INFORMATION
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. CODES Preferred Package P = Plastic DIP Longer Lead Time S = SOIC Preferred Temperature S = 0°C to +70°C E = –40°C to +105°C Speed 08 = 8 MHz Environmental C = Plastic Standard Standard Temperature 18-Pin DIP 18-Pin SOIC Z86E0208PSC Z86E0208SSC Z86L0208PSC Z86L0208SSC Z86C0208PSC Z86C0208SSC Z86E0208PSC1903 Z86E0208SSC1903 Extended Temperature 18-Pin DIP 18-Pin SOIC Z86E0208PEC Z86E0208SEC Z86L0208PEC Z86L0208SEC Z86C0208PEC Z86C0208SEC Z86E0208PEC1903 Z86E0208SEC1903 Examp le: Z 86E08 08 P S C is a Z86E08, 08 MHz, DIP , 0° to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
Zilog Cost Effective, 512-Byte ROM CMOS Z8 ® Microcontrollers DS96DZ80301 P R E L I M I N A R Y 37 © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com