Z86E30 ZILOG | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 66
Technical content
P RELIMINARY P RODUCT S PECIFICATION Z86E30/E31/E40 4K OTP M ICROCONTROLLER
FEATURES
n Standard Temperature (V CC = 3.5V to 5.5V) n Extended Temperature (V CC = 4.5V to 5.5V) n Available Packages: 28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only) 28-Pin DIP Window (Z86E30/31 only) 40-Pin DIP OTP/Window (Z86E40 only) 44-Pin PLCC/QFP OTP (Z86E40 only) 44-Pin PLCC Window (Z86E40 only) n Software Enabled Watch-Dog Timer (WDT) n Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2 n 24/32 Input/Output Lines n Auto Latches n Auto Power-On Reset (POR) n Programmable OTP Options: RC Oscillator EPROM Protect Auto Latch Disable Permanently Enabled WDT Crystal Oscillator Feedback Resistor Disable RAM Protect n Low-Power Consumption: 60 mW n Fast Instruction Pointer: 0.75 m s n Two Standby Modes: STOP and HALT n Digital Inputs CMOS Levels, Schmitt-Triggered n Software Programmable Low EMI Mode n Two Programmable 8-Bit Counter/Timers Each with a 6-Bit Programmable Prescaler n Six Vectored, Priority Interrupts from Six Different Sources n Two Comparators n On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive GENERAL DESCRIPTION The Z86E30/E31/E40 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip MCU family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI op- tions, and easy hardware/software system expansion ca- pability. Four basic address spaces support a wide range of mem- ory configurations. The designer has access to three addi- tional control registers that allow easy access to register mapped peripheral and I/O circuits. For applications demanding powerful I/O capabilities, the Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and par- Device ROM (KB) RAM* (Bytes) I/O Lines Speed (MHz) Z86E30 4 237 24 16 Z86E31 2 125 24 16 Z86E40 4 236 32 16 Note: *General-Purpose
for interfacing external memory. Figure 1. Z86E30/E31/E40 Functional Block Diagram
Figure 2. EPROM Programming Block Diagram
Figure 3. 40-Pin DIP Pin Configuration* Table 1. 40-Pin DIP Pin Identification
1 R//W Read/Write Output
10 P07 Port 0, Pin 7 In/Output
14 XTAL2 Crystal Oscillator Output
15 XTAL1 Crystal Oscillator Input
19 P34 Port 3, Pin 4 Output
22 P35 Port 3, Pin 5 Output
23 P37 Port 3, Pin 7 Output
24 P36 Port 3, Pin 6 Output
25 P30 Port 3, Pin 0 Input
30 P02 Port 0, Pin 2 In/Output
31 GND Ground
34 P03 Port 0, Pin 3 In/Output
and Cerdip Window Lid style packages.
Figure 4. 44-Pin PLCC Pin Configuration Table 2. 44-Pin PLCC Pin Identification
5 P03 Port 0, Pin 3 In/Output
12 NC No Connection
13 R//W Read/Write Output
22 P07 Port 0, Pin 7 In/Output
27 XTAL2 Crystal OscillatorOutput
28 XTAL1 Crystal OscillatorInput
32 P34 Port 3, Pin 4 Output
34 R//RL ROM/ROMless
36 P35 Port 3, Pin 5 Output
37 P37 Port 3, Pin 7 Output
38 P36 Port 3, Pin 6 Output
39 P30 Port 3, Pin 0 Input
44 P02 Port 0, Pin 2 In/Output
Figure 5. 44-Pin QFP Pin Configuration Table 3. 44-Pin QFP Pin Identification
5 P07 Port 0, Pin 7 In/Output
10 XTAL2 Crystal Oscillator Output
11 XTAL1 Crystal Oscillator Input
15 P34 Port 3, Pin 4 Output
17 R//RL ROM/ROMless select Input
19 P35 Port 3, Pin 5 Output
20 P37 Port 3, Pin 7 Output
21 P36 Port 3, Pin 6 Output
22 P30 Port 3, Pin 0 Input
27 P02 Port 0, Pin 2 In/Output
32 P03 Port 0, Pin 3 In/Output
39 NC No Connection
40 R//W Read/Write Output
44 P04 Port 0, Pin 4 In/Output
Figure 6. 40-Pin DIP Pin Configuration* Table 4. 40-Pin DIP Package Pin Identification
1 NC No Connection
10 A7 Address 7 Input
19 A8 Address 8 Input
22 A9 Address 9 Input
23 A11 Address 11 Input
24 A10 Address 10 Input
30 A2 Address 2 Input
34 A3 Address 3 Input
40 NC No Connection
Figure 7. 44-Pin PLCC Pin Configuration Table 5. 44-Pin PLCC Pin Configuration
5 A3 Address 3 Input
22 A7 Address 7 Input
32 A8 Address 8 Input
36 A9 Address 9 Input
37 A11 Address 11 Input
38 A10 Address 10 Input
44 A2 Address 2 Input
Figure 8. 44-Pin QFP Pin Configuration Table 6. 44-Pin QFP Pin Identification
5 A7 Address 7 Input
15 A8 Address 8 Input
19 A9 Address 9 Input
20 A11 Address 11 Input
21 A10 Address 10 Input
27 A2 Address 2 Input
32 A3 Address 3 Input
44 A4 Address 4 Input
Figure 9. Standard Mode Table 7. 28-Pin DIP/SOIC/PLCC
9 XTAL2 Crystal Oscillator Output
10 XTAL1 Crystal Oscillator Input
16 P37 Port 3, Pin 7 Output
17 P36 Port 3, Pin 6 Output
18 P30 Port 3, Pin 0 Input
23 P03 Port 0, Pin 3 In/Output
Cerdip Window Lid style packages. Figure 10. EPROM Programming Mode Figure 11. Standard Mode
Figure 12. EPROM Programming Mode Table 8. 28-Pin EPROM
9 NC No connection
16 A11 Address 11 Input
17 A10 Address 10 Input
23 A3 Address 3 Input
Cerdip Window Lid style packages.
12 P R E L I M I N A R Y DS97Z8X0500
tended period may affect device reliability.
- This applies to all pins except XTAL pins and where otherwise noted.
- There is no input protection diode from pin to V
- Device pin is not at an output Low state.
Figure 13. Test Load Diagram
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 13 CAPACITANCE TA = 25°C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. DC ELECTRICAL CHARACTERISTICS Parameter Min Max Input capacitance 0 12 pF Output capacitance 0 12 pF I/O capacitance 0 12 pF T A = 0 °C to +70 °C Sym Parameter VCC Note [3] Min Max Typical @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 3.5V 5.5V
0.7 VCC
VCC +0.3 VCC +0.3 1.8 2.5 V V Driven by External Clock Generator VCL Clock Input Low Voltage 3.5V 4.5V GND-0.3 GND-0.3
0.2 VCC
0.9 1.5 V V Driven by External Clock Generator VIH Input High Voltage 3.5V 5.5V VCC +0.3 VCC +0.3 2.5 2.5 V V VIL Input Low Voltage 3.5V 5.5V GND-0.3 GND-0.3 1.5 1.5 V V VOH Output High Voltage Low EMI Mode 3.5V 5.5V VCC –0.4 VCC -0.4 3.3 4.8 V V IOH = – 0.5 mA VOH1 Output High Voltage 3.5V 5.5V VCC –0.4 VCC –0.4 3.3 4.8 V V IOH = -2.0 mA IOH = -2.0 mA VOL Output Low Voltage Low EMI Mode 3.5V 4.5V 0.4 0.4 0.2 0.2 V V IOL = 1.0 mA IOL = 1.0 mA VOL1 Output Low Voltage 3.5V 4.5V 0.4 0.4 0.1 0.1 V V IOL = + 4.0 mA IOL = + 4.0 mA VOL2 Output Low Voltage 3.5V 4.5V 1.2 1.2 0.5 0.5 V V IOL = + 12 mA IOL = + 12 mA VRH Reset Input High Voltage 3.5V 5.5V .8 VCC .8 VCC VCC VCC 1.7 2.1 V V VRL Reset Input Low Voltage 3.5V 5.5V GND –0.3 GND –0.3 1.3 1.7 V V VOLR Reset Output Low Voltage 3.5V 5.5V 0.6 0.6 0.3 0.2 V V IOL = 1.0 mA IOL = 1.0 mA VOFFSET Comparator Input Offset Voltage 3.5V 4.5V mV mV VICR Input Common Mode Voltage Range 3.5V 5.5V VCC -1.0V VCC -1.0V V V IIL Input Leakage 3.5V 4.5V 0.032 0.032 mA mA VIN = 0V, VCC VIN = 0V, VCC IOL Output Leakage 3.5V 4.5V 0.032 0.032 mA mA VIN = 0V, VCC VIN = 0V, VCC IIR Reset Input Current 3.5V 4.5V –20 –20 –130 –180 –65 –112 mA mA
Z8 4K OTP Microcontroller Zilog
14 P R E L I M I N A R Y DS97Z8X0500
ICC Supply Current 3.5V 5.5V mA mA @ 16 MHz @ 16 MHz 4,5 4,5 ICC1 Standby Current Halt Mode 3.5V 5.5V 3.7 3.7 mA mA VIN = 0V, VCC @ 16 MHz 4,5 4,5 3.5V 5.5V 7.0 7.0 2.9 2.9 mA mA Clock Divide by 16 @ 16 MHz 4,5 4,5 ICC2 Standby Current Stop Mode 3.5V 5.5V 3.5V 5.5V 800 800 600 600 mA mA mA mA V IN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 6,11 6,11 6,11,14 6,11,14 I ALL Auto Latch Low Current 3.5V 5.5V 0.7 1.4 2.4 4.7 mA mA 0V <VIN<V CC 0V <VIN<V CC IALH Auto Latch High Current 3.5V 5.5V –0.6 –1.8 –3.8 mA mA 0V<V IN<V CC 0V<V IN<V CC TPOR Power On Reset 3.5V 5.5V 3.0 2.0 ms ms VLV Auto Reset Voltage 2.3 3.1 2.9 V 1,7 Notes: 1. Device does not function down to the Auto Reset voltage 2. GND=0V 3. The V CC voltage specification of 5.5V guarantees 5.0V – 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1= CL2 = 22 pF 6. Same as note [4] except inputs at V CC 7. Max. temperature is 70°C 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating 12. Typicals are at V CC = 5.0V and VCC = 3.5V 13. Z86C40 only 14. WDT running TA = 0 °C to +70 °C Sym Parameter VCC Note [3] Min Max Typical @ 25 °C Units Conditions Notes
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 15 TA =–40 °C to +105 °C Sym Parameter VCC Note [3] Min Max Typical @ 25 °C Units Conditions Notes VCH Clock Input High Voltage 4.5V 5.5V VCC +0.3 VCC +0.3 2.5 2.5 V V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V 5.5V GND-0.3 GND-0.3 1.5 1.5 V V Driven by External Clock Generator VIH Input High Voltage 4.5V 5.5V VCC +0.3 VCC +0.3 2.5 2.5 V V VIL Input Low Voltage 4.5V 5.5V GND-0.3 GND-0.3 1.5 1.5 V V VOH Output High Voltage Low EMI Mode 4.5V 5.5V V CC –0.4 VCC –0.4 4.8 4.8 V V IOH = – 0.5 mA IOH = – 0.5 mA VOH1 Output High Voltage 4.5V 4.5V VCC –0.4 VCC –0.4 4.8 4.8 V V IOH = -2.0 mA IOH = -2.0 mA VOL Output Low Voltage Low EMI Mode 4.5V 5.5V 0.4 0.4 0.2 0.2 V V IOL = 1.0 mA IOL = 1.0 mA VOL1 Output Low Voltage 4.5V 5.5V 0.4 0.4 0.1 0.1 V V IOL = + 4.0 mA IOL = +4.0 mA VOL2 Output Low Voltage 4.5V 5.5V 1.2 1.2 0.5 0.5 V V IOL = + 12 mA IOL = + 12 mA VRH Reset Input High Voltage 3.5V 5.5V .8 VCC .8 VCC VCC VCC 1.7 2.1 V V VOLR Reset Output Low Voltage 3.5V 5.5V 0.6 0.6 0.3 0.2 V V IOL = 1.0 mA IOL = 1.0 mA VOFFSET Comparator Input Offset Voltage 4.5V 5.5V mV mV VICR Input Common Mode Voltage Range 4.5V 5.5V V CC -1.5V VCC -1.5V V V IIL Input Leakage 4.5V 5.5V mA mA VIN = 0V, VCC VIN = 0V, VCC IOL Output Leakage 4.5V 5.5V mA mA VIN = 0V, VCC VIN = 0V, VCC IIR Reset Input Current 4.5V 5.5V –18 –18 –180 –180 –112 –112 mA mA ICC Supply Current 4.5V 5.5V mA mA @ 16 MHz @ 16 MHz 4,5 4,5 ICC1 Standby Current Halt Mode 4.5V 5.5V 3.7 3.7 mA mA VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz 4,5 4,5 ICC2 Standby Current (Stop Mode) 4.5V 5.5V mA mA VIN = 0V, VCC VIN = 0V, VCC 6,11,14 6,11,14 IALL Auto Latch Low Current 4.5V 5.5V 1.4 1.4 4.7 4.7 mA mA 0V < VIN < VCC 0V < VIN < VCC
Z8 4K OTP Microcontroller Zilog
16 P R E L I M I N A R Y DS97Z8X0500
4.5V 5.5V –1.0 –1.0 –10 –10 –3.8 –3.8 mA mA 0V < VIN < VCC 0V < VIN < VCC TPOR Power On Reset 4.5V 5.5V 2.0 2.0 mS mS VLV Auto Reset Voltage 2.0 3.3 2.9 V 1 1. Device does not function down to the Auto Reset voltage 2. GND=0V 3. The V CC voltage spec. of 5.5V guarantees 5.0V +/- – 0.5V 4. All outputs unloaded, I/O pins floating, inputs at rail 5. CL1= CL2 = 22 pF 6. Same as note [4] except inputs at V CC 7. Max. temperature is 70°C 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating 12. Typicals are at V CC = 5.0V 13. Z86C40 only 14. WDT is not running TA =–40 °C to +105 °C Sym Parameter VCC Note [3] Min Max Typical @ 25 °C Units Conditions Notes
Figure 14. External I/O or Memory Read/Write Timing
Z8 4K OTP Microcontroller Zilog
18 P R E L I M I N A R Y DS97Z8X0500
TA = 0°C to 70°C
16 MHz
Note [3] VCC Min Max Units Notes
1 TdA(AS) Address Valid to /AS Rise
3.5V 5.5V ns ns
2 TdAS(A) /AS Rise to Address Float
3.5V 5.5V ns ns
3 TdAS(DR) /AS Rise to Read Data
Req’d Valid 3.5V 5.5V 180 180 ns ns 1,2 4 TwAS /AS Low Width 3.5V 5.5V ns ns 5 TdAS(DS) Address Float to /DS Fall 3.5V 5.5V ns ns 6 TwDSR /DS (Read) Low Width 3.5V 5.5V 135 135 ns ns 1,2 7 TwDSW /DS (Write) Low Width 3.5V 5.5V ns ns 1,2
8 TdDSR(DR) /DS Fall to Read Data Req’d
3.5V 5.5V ns ns 1,2
9 ThDR(DS) Read Data to /DS Rise Hold
3.5V 5.5V ns ns
10 TdDS(A) /DS Rise to Address Active
3.5V 5.5V ns ns 11 TdDS(AS) /DS Rise to /AS Fall Delay 3.5V 5.5V ns ns
12 TdR/W(AS) R//W Valid to /AS Rise
3.5V 5.5V ns ns 13 TdDS(R/W) /DS Rise to R//W Not Valid 3.5V 5.5V ns ns
14 TdDW(DSW) Write Data Valid to /DS Fall
(Write) Delay 3.5V 5.5V ns ns
15 TdDS(DW) /DS Rise to Write Data Not
3.5V 5.5V ns ns
16 TdA(DR) Address Valid to Read Data
Req’d Valid 3.5V 5.5V 230 230 ns ns 1,2 17 TdAS(DS) /AS Rise to /DS Fall Delay 3.5V 5.5V ns ns 18 TdDM(AS) /DM Valid to /AS Fall Delay 3.5V 5.5V ns ns
20 ThDS(AS) /DS Valid to Address Valid
3.5V 5.5V ns ns Notes: 1. When using extended memory timing add 2 TpC 2. Timing numbers given are for minimum TpC 3. The V CC voltage specification of 5.5V guarantees 5.0V +/- –0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0 For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 19 TA = -40°C to 105°C Note [3] VCC Min Max Units Notes 4.5V 5.5V ns ns 4.5V 5.5V ns ns Req’d Valid 4.5V 5.5V 180 180 ns ns 1,2 4 TwAS /AS Low Width 4.5V 5.5V ns ns 5 TdAS(DS) Address Float to /DS Fall 4.5V 5.5V ns ns 6 TwDSR /DS (Read) Low Width 4.5V 5.5V 135 135 ns ns 1,2 7 TwDSW /DS (Write) Low Width 4.5V 5.5V ns ns 1,2 4.5V 5.5V ns ns 1,2 4.5V 5.5V ns ns 4.5V 5.5V ns ns 11 TdDS(AS) /DS Rise to /AS Fall Delay 4.5V 5.5V ns ns 4.5V 5.5V ns ns 13 TdDS(R/W) /DS Rise to R//W Not Valid 4.5V 5.5V ns ns (Write) Delay 4.5V 5.5V ns ns 4.5V 5.5V ns ns Req’d Valid 4.5V 5.5V 230 230 ns ns 1,2 17 TdAS(DS) /AS Rise to /DS Fall Delay 4.5V 5.5V ns ns 18 TdDM(AS) /DM Valid to /AS Fall Delay 4.5V 5.5V ns ns 4.5V 5.5V ns ns Notes: 1. When using extended memory timing add 2 TpC 2. Timing numbers given are for minimum TpC 3. The V CC voltage specification of 5.5V guarantees 5.0V +/- 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0 For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0
20 P R E L I M I N A R Y DS97Z8X0500
Figure 15. Additional Timing Diagram
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 21 Additional Timing Table (Divide-By-One Mode) TA = 0 °C to +70 °C T A = -40 °C to +105 °C
4 MHz 4 MHz
Note [6] Min Max Min Max Units Notes 1 TpC Input Clock Period 3.5V 5.5V 250 250 DC DC 250 250 DC DC ns ns 1,7,8 1,7,8
2 TrC,TfC Clock Input Rise &
3.5V 5.5V ns ns 1,7,8 1,7,8 3 TwC Input Clock Width 3.5V 5.5V 100 100 100 100 ns ns 1,7,8 1,7,8
4 TwTinL Timer Input Low
3.5V 5.5V 100 100 ns ns 1,7,8 1,7,8
5 TwTinH Timer Input High
3.5V 5.5V 5TpC 5TpC 5TpC 5TpC 1,7,8 1,7,8 6 TpTin Timer Input Period 3.5V 5.5V 8TpC 8TpC 8TpC 8TpC 1,7,8 1,7,8
7 TrTin, TfTin Timer Input Rise
& Fall Timer 3.5V 5.5V 100 100 100 100 ns ns 1,7,8 1,7,8 8A TwIL Int. Request Low Time 3.5V 5.5V 100 100 ns ns 1,2,7,8 1,2,7,8 8B TwIL Int. Request Low Time 3.5V 5.5V 5TpC 5TpC 5TpC 5TpC 1,3,7,8 1,3,7,8 9 TwIH Int. Request Input High Time 3.5V 5.5V 5TpC 5TpC 5TpC 5TpC 1,2,7,8 1,2,7,8
10 Twsm STOP Mode
3.5V 5.5V ns ns 4,8 4,8
11 Tost Oscillator Startup
3.5V 5.5V 5TpC 5TpC 5TpC 4,8,9 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WDTMR. 6. The V CC voltage specification of 5.5V guarantees 5.0V –+/- 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver.
22 P R E L I M I N A R Y DS97Z8X0500
Figure 16. Input Handshake Timing Figure 17. Output Handshake Timing
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 23 Additional Timing Table TA = -40 °C to +105 °C Note [6] Min Max Units Conditions Notes 1 TpC Input Clock Period 3.5V 5.5V 62.5 62.5 DC DC ns ns 1,7,8 1,7,8 3.5V 5.5V ns ns 1,7,8 1,7,8 3 TwC Input Clock Width 3.5V 5.5V ns ns 1,7,8 1,7,8 3.5V 5.5V ns ns 1,7,8 1,7,8 3.5V 5.5V 5TpC 5TpC 1,7,8 1,7,8 6 TpTin Timer Input Period 3.5V 5.5V 8TpC 8TpC [1,7,8 1,7,8 & Fall Timer 3.5V 5.5V 100 100 ns ns 1,7,8 1,7,8 8A TwIL Int. Request Low Time 3.5V 5.5V ns ns 1,2,7,8 1,2,7,8 8B TwIL Int. Request Low Time 3.5V 5.5V 5TpC 5TpC 1,3,7,8 1,3,7,8 9 TwIH Int. Request Input High Time 3.5V 5.5V 5TpC 1,2,7,8 3.5V 5.5V ns ns 4,8 4,8 3.5V 5.5V 5TpC 5TpC 4,8 4,8
12 Twdt Watch-Dog Timer
3.5V 5.5V ms ms D0 = 0 D1 = 0 5,11 5,11 3.5V 5.5V ms ms D0 = 1 D1 = 0 5,11 5,11 3.5V 5.5V ms ms D0 = 0 D1 = 1 5,11 5,11 3.5V 5.5V 160 ms ms D0 = 1 D1 = 1 5,11 5,11 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0 2. Interrupt request via Port 3 (P31-P33) 3. Interrupt request via Port 3 (P30) 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Reg. WDTMR 7. SMR D1 = 0 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 10. Standard Mode (not Low EMI output ports) 11. Using internal RC
Z8 4K OTP Microcontroller Zilog
24 P R E L I M I N A R Y DS97Z8X0500
D7-D0 Data Bus. The data can be read from or written to external memory through the data bus. A11-A0 Address Bus. During programming, the EPROM address is written to the address bus. VCC Power Supply. This pin must supply 5V during the EPROM read mode and 6V during other modes. /CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. /OE Output Enable (active Low). This pin drives the direc- tion of the Data Bus. When this pin is Low, the Data Bus is output, when High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the differ- ent EPROM Program Mode by applying different voltages. V PP Program Voltage. This pin supplies the program volt- age. /PGM Program Mode (active Low). When this pin is Low, the data is programmed to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above V CC occur on pins XTAL1 and /RESET. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP , /CE, /EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following: n Using a clamping diode to VCC n Adding a capacitor to the affected pin Standard Mode XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC net- work, or external single-phase clock to the on-chip oscilla- tor input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator output. R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory (Z86E40 only). /RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished either through Power-On, Watch-Dog Timer reset, STOP-Mode Recovery, or exter- nal reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drain in order to avoid damage from a pos- sible conflict during reset conditions. Pull-up is provided in- ternally. After the POR time, /RESET is a Schmitt-trig- gered input. To avoid asynchronous and noisy reset problems, the Z86E40 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the re- set is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. Dur- ing the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-10 TpC cycles after /RESET is released. For Power-On Reset, the reset output time is 5 ms. The Z86E40 does not reset WDTMR, SMR, P2M, and P3M registers on a STOP-Mode Recovery operation. /ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when left unconnected or pulled High to V CC , the device func- tions normally as a Z8 ROM version). Note: When using in ROM Mode in High EMI (noisy) envi- ronment, the ROMless pins should be connected directly to V CC .
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 25 Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines can be config- ured under software control as a nibble I/O port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Ei- ther nibble output that can be globally programmed as push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 0 can be placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as handshake control lines. The handshake direction is determined by the configura- tion (input or output) assigned to Port 0's upper nibble. The lower nibble must have the same direction as the upper nibble. For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib- ble) depending on the required address space. If the ad- dress range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. In ROMless mode, after a hardware reset, Port 0 is configured as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine can include re- configuration to eliminate this extended timing mode. In ROM mode, Port 0 is defined as input after reset. Port 0 can be set in the High-Impedance Mode if selected as an address output state, along with Port 1 and the con- trol signals /AS, /DS, and R//W (Figure 18).
26 P R E L I M I N A R Y DS97Z8X0500
Figure 18. Port 0 Configuration
Figure 19. Port 1 Configuration (Z86E40 Only)
28 P R E L I M I N A R Y DS97Z8X0500
I/O port, Port 2 can be placed under handshake control. Figure 20. Port 2 Configuration
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 29 Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible port with four fixed inputs (P33-P30) and four fixed outputs (P37-P34). These eight lines can be configured by soft- ware for interrupt and handshake control functions. Port 3, Pin 0 is Schmitt- triggered. P31, P32 and P33 are standard CMOS inputs with single trip point (no Auto Latches) and P34, P35, P36 and P37 are push-pull output lines. Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by setting the D1 of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit D0 to 1 state. For the interrupt function, P30 and P33 are falling edge triggered interrupt inputs. P31 and P32 can be programmed as falling, rising or both edges triggered interrupt inputs (Figure 21). Access to Counter/Timer 1 is made through P31 (T IN) and P36 (TOUT ). Handshake lines for Port 0, Port 1, and Port 2 are also available on Port 3 (Table 9). Note: P33-P30 differs from the Z86C30/C31/C40 in that there is no clamping diode to VCC due to the EPROM high- voltage circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM mode.
30 P R E L I M I N A R Y DS97Z8X0500
Figure 21. Port 3 Configuration
is the reference voltage of the comparators. driven. Whether this level is 0 or 1, cannot be determined. are no Auto Latches on P31, P32, and P33. operate in a low EMI Emission Mode in the PCON register. n The pre-drivers slew rate reduced to 10 ns typical. Table 9. Port 3 Pin Assignments
32 P R E L I M I N A R Y DS97Z8X0500
with increased design flexibility.
- STOP-Mode Recovery Source
specification before the TPOR expires. program memory are reserved for the interrupt vectors. is only available on the 44-pin devices. Figure 22. Program Memory Map
can read Internal Program Memory. between data and program memory space (Figure 23). tion references data (/DM active Low) memory. Figure 23. Data Memory Map
34 P R E L I M I N A R Y DS97Z8X0500
groups are known as the Expanded Register File (ERF). is reserved for future expansion. Figure 24. Register Pointer Register
Figure 25. Register Pointer the active working-register group.
36 P R E L I M I N A R Y DS97Z8X0500
Figure 26. Expanded Register File Architecture ** Will not be reset with a STOP Mode Recovery, except Bit D0.
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 37 General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the V CC voltage-specified operating range. The register R254 is general-purpose on Z86E30/E31. R254 and R255 are set to 00H after any reset or STOP-Mode re- covery. RAM Protect. The upper portion of the RAM's address spaces 80H to EFH (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the user can activate this feature from the internal EPROM. D6 of the IMR control register (R251) is used to turn off/on the RAM protect by loading a 0 or 1, respectively. A 1 in D6 indicates RAM Protect enabled. RAM Protect is not available on the Z86E31. Stack. The Z86E40 external data memory or the internal register file can be used for the stack. The 16-bit Stack Pointer (R254-R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 4096 to 65535 in ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack on the Z86E30/E31/E40 that resides within the 236 general-pur- pose registers (R4-R239). SPH (R254) can be used as a general-purpose register when using internal stack only. R254 and R255 are set to 00H after any reset or STOP- Mode Recovery. Counter/Timers. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by in- ternal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 27). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
Z8 4K OTP Microcontroller Zilog
38 P R E L I M I N A R Y DS97Z8X0500
continue counting (modulo-n continuous mode). Figure 27. Counter/Timer Block Diagram
40 P R E L I M I N A R Y DS97Z8X0500
Figure 28. Interrupt Block Diagram Table 10. Interrupt Types, Sources, and Vectors
routine for that particular interrupt request. determine which of the interrupt requests need service. may poll to identify the state of the pin. uration is shown in Table 11. lator option can be selected in the programming mode. ting capacitor from XTAL1 to Ground (Figure 29). Table 11. IRQ Register Configuration
10 R F
Figure 29. Oscillator Configuration
Z8 4K OTP Microcontroller Zilog
42 P R E L I M I N A R Y DS97Z8X0500
Power-On Reset (POR). A timer circuit clocked by a ded- icated on-board RC oscillator is used for the Power-On Re- set (POR) timer function. The POR timer allows V CC and the oscillator circuit to stabilize before instruction execu- tion begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power fail to Power OK status 2. STOP-Mode Recovery (if D5 of SMR=0) 3. WDT time-out The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines whether the POR timer is by- passed after STOP-Mode Recovery (typical for an external clock and RC/LC oscillators with fast start up times). HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated. An in- terrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program con- tinues from the instruction after the HALT. In order to enter STOP or HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. To do this, the user must execute a NOP (opcode=FFH) immediately before the appropriate sleep instruction, that is: STOP. This instruction turns off the internal clock and ex- ternal crystal oscillation and reduces the standby current to 10 microamperes or less. STOP mode is terminated by one of the following resets: either by WDT time-out, POR, a STOP-Mode Recovery Source, which is defined by the SMR register or external reset. This causes the processor to restart the application program at address 000CH. Port Configuration Register (PCON). The PCON regis- ter configures the ports individually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1, 2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00 (Figure 30). FF NOP ; clear the pipeline 6F STOP ; enter STOP ;mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT mode
mode and must be set D4 = 1. Figure 30. Port Configuration Register (PCON)
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
0 Low EMI
1 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
0 Port 1 Open Drain
1 Port 1 Push-pull Active*
0 Port 1 Low EMI
1 Port 1 Standard*
44 P R E L I M I N A R Y DS97Z8X0500
SMR register specify the STOP-Mode Recovery Source. Figure 31. STOP-Mode Recovery Register
0 OFF
000 POR and/or External Reset
001 P30
010 P31
100 P33
101 P27
0 Low
1 High
0 POR
1 Stop Recovery
- Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
0 SCLK/TCLK =XT AL/2*
1 SCLK/TCLK =XT AL
SMR controls a divide-by-16 prescaler of SCLK/TCLK. counter/timers and interrupt logic). (SMR) = 1). The default setting is zero. register bits D0, D1 must be set to zero. level will be read by the SMR circuitry.. Figure 32. STOP-Mode Recovery Source
46 P R E L I M I N A R Y DS97Z8X0500
recovery. The default value is 0. ister then SMR Register. Bits D2, D3, and D4 must be 0. ro), S (Sign), and V (Overflow) flags. ables the WDT in HALT mode. The default value is 1. clock source is the internal RC oscillator. bit is 0, which selects the RC oscillator. WDT will not run in STOP mode. Table 12. STOP-Mode Recovery Source Table 13. Time-out Period of WDT *The default setting is 10 ms.
panded Register Group at address location 0FH. Figure 33. Watch-Dog Timer Mode Register
0 On-Board RC
1 XT AL
48 P R E L I M I N A R Y DS97Z8X0500
the minimum Power-On Reset time-out (TPOR ). Figure 34. Resets and WDT
18 Clock RESET
4 Clock
Figure 35. Typical Z86E40 VLV Voltage vs Temperature
50 P R E L I M I N A R Y DS97Z8X0500
shows the adaptation from the 2764A to Z86E30/E31. ROM look-up table can be used with this feature. erations, once the mode is latched.
7 Unused
6 Unused
4 Permanent WDT
3 Auto Latch Disable
2 RC Oscillator Option
1 RAM Protect
0 ROM Protect
Table 14. EPROM Programming Table VIH = As per specific Z8 DC specification. VIL= As per specific Z8 DC specification. X=Not used, but must be set to VH , VIH, or VIL level. NU = Not used, but must be set to either VIH or VIL level. IPP during programming = 40 mA maximum. ICC during programming, verify, or read = 40 mA maximum. *VCC has a tolerance of –0.25V. but VCC = 5.0 V is acceptable.
Table 15. EPROM Programming Timing
1 Address Setup Time 2 msm
2 Data Setup Time 2 ms
5 Chip Enable Setup Time 2 ms
7 Data Hold Time 2 ms
9 Data Access Time 200 ns
10 Data Output Float Time 100 ns
11 Overprogram Pulse
12 EPM Setup Time 2 ms
14 Address to /OE Setup Time 2 msm
16 Address to /OE Low 125 ns
52 P R E L I M I N A R Y DS97Z8X0500
Figure 36. EPROM Read Mode Timing Diagram
Figure 37. Timing Diagram of EPROM Program and Verify Modes
54 P R E L I M I N A R Y DS97Z8X0500
Figure 38. Z86E40 Z8 OTP Programming Adapter
6 P05
14 GND
28 VCC
1 VPP
2764 Pins
1 KOhm R2
11 VCC
12.5 Volt
10 KOhm
1 KOhm
Figure 39. Z86E30/E31 Programming Adaptor Circuitry
5 P05
56 P R E L I M I N A R Y DS97Z8X0500
Figure 40. Z86E40 Programming Algorithm But Vcc = 5.0V is acceptable.
Figure 41. Port Configuration Register Figure 42. STOP-Mode Recovery Register
0 Port 0 Open-Drain
0 P34, P37 Standard*
0 Port 1 Open-Drain
1 Port 1 Push-Pull Active*†
1 Port 1 Standard*†
000 POR Only and/or External Reset*
1 ON*
0 Low*
0 POR*
- Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery. Figure 43. Watch-Dog Timer Mode Register Figure 44. STOP-Mode Recovery Register 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
58 P R E L I M I N A R Y DS97Z8X0500
Figure 45. Reserved Figure 46. Timer Mode Register Figure 47. Counter/Timer 1 Register
0 Disable T0 Count*
1 Enable T0 Count
0 No Function*
1 Load T0
1 Load T1
0 Disable T1 Count*
1 Enable T1 Count
00 External Clock Input*
01 Gate Input
10 Trigger Input
00 Not Used*
01 T0 Out
10 T1 Out
Figure 48. Prescaler 1 Register Figure 49. Counter/Timer 0 Register Figure 50. Prescaler 0 Register
0 T1 Single Pass*
1 T1 Modulo N
1 T1 Internal
0 T1 External Timing Input
0 T1 Single Pass
Figure 51. Port 2 Mode Register Figure 52. Port 3 Mode Register
0 Defines Bit as Output
1 Defines Bit as Input*
0 Port 2 Open-Drain
1 Port 2 Push-pull Active
0 P32 = Input
1 P32 = /DA V0/RDY0
00 P33 = Input
01 P33 = Input
10 P34 = /DM
0 P31 = Input (TIN)
1 P31 = /DA V2/RDY2
0 P30 = Input
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
Figure 53. Port 0 and 1 Mode Register Figure 54. Interrupt Priority Register
00 Output
01 Input
0 External
1 Internal
00 Byte Output†
01 Byte Input
10 AD7 - AD0
0 Normal
1 Extended
000 Reserved
001 C > A > B
010 A > B > C
100 B > C > A
101 C > B > A
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
60 P R E L I M I N A R Y DS97Z8X0500
Figure 55. Interrupt Request Register Figure 56. Interrupt Mask Register Figure 57. Flag Register
1 Enables RAM Protect †
1 Enables IRQ5-IRQ0
1 Enables Interrupts
Figure 58. Register Pointer Figure 59. Stack Pointer High Figure 60. Stack Pointer Low
62 P R E L I M I N A R Y DS97Z8X0500
Figure 63. 44-Pin QFP Package Diagram Figure 64. 40-Pin Cerdip Window Lid Package Diagram
64 P R E L I M I N A R Y DS97Z8X0500
Figure 67. 18-Pin SOIC Package Diagram
Zilog Z8 4K OTP Microcontroller DS97Z8X0500 P R E L I M I N A R Y 65
ORDERING INFORMATION
Z86E40 (16 MHz) For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package P = Plastic DIP V = Plastic Chip Carrier F = Plastic Quad Flat Pack K = Cerdip Window Lid Temperature S = 0 °C to +70 °C E = -40 °C to +105 °C Speed 16 = 16 MHz Environmental C= Plastic Standard E = Hermetic Standard 40-Pin DIP 44-Pin PLCC 44-Pin QFP 40-Pin Cerdip Window Lid Z86E4016PSC Z86E4016VSC Z86E4016FSC Z86E4016ESE Z86E4016PEC Z86E4016VEC Z86E4016FEC Z86E4016ESE Z86E30 (16 MHz) 28-Pin DIP 28-Pin Cerdip Window Lid Z86E3016PSC Z86E3016ESE Z96E3016PEC Z86E3016SSC Z86E3016SEC Z86E31 (16 MHz) 28-Pin DIP 28-Pin Cerdip Window Lid Z86E3116PSC Z86E3116SSC Example: Z 86E40 16 P S C Environmental Flow T emperature Package Speed Product Number Zilog Prefix is a Z86E40, 16 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Z8 4K OTP Microcontroller Zilog
66 P R E L I M I N A R Y DS97Z8X0500
© 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com