Z86C28 ZILOG | Alldatasheet
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——— ps PRELIMINARY PRODUCT SPECIFICATION CMOS 8-BiT Low-Cost 4K-ROM MICROCONTROLLERS
FEATURES
Part ROM RAM* Speed Auto Permanent ™ Clock-Free WOT Reset Number (KB) (Bytes) (MHz) Latch — WDT Power-On Reset (POR) Timer Z86C28 4 237 12 Optional Optional Z86E28 4t (237 12 Optional Optional m Options: Note: * General-Purpose ~ RAM Protect t+ One Time Programmable EPROM in DIP only. - ROM Protect j - Auto Latch @ = 18-Pin DIP and SOIC Packages (Z86C28) — Permanent Watch-Dog Timer (WDT) ™ 18-Pin DIP Packages (Z86E28) - RC Oscillator - 32 kHz Operation ™ 3.0V to 5.5V Operating Range (Z86C28) - 3.5V to 5.5V (Z86E28 Std. Temp.) @ On-Chip Oscillator that Accepts RC, Crystal, ; - 4.5V to 5.5V (286E28 Ext. Temp.) Ceramic Resonance, LC, or External Clock Drive ™ Available Temperature Ranges m Low-Power Consumption (50 mw) - E=-40°C to +105°C (Extended Temperature) m Fast Instruction Pointer - $=0°C to +70°C (Standard Temperature) (1.0 ps @ 12 MHz) @ = 14 Input/Output Lines @ Fourteen Digital Inputs at CMOS Levels; Schmitt-Triggered m Six Vectored, Prioritized Interrupts from Six Different Sources ™ Software Enabled Watch-Dog Timer @ Two On-Board Comparators @ Programmable Interrupt Polarity m@ Two Programmable 8-Bit Counter/Timers, ™@ Two Standby Modes: STOP and HALT Each with 6-Bit Programmable Prescaler m@ Low-Voltage Protection GENERAL DESCRIPTION Zilog’s Z86C28/E28 are members of the Z8® MCU family — Two on-chip counter/timers, with a large number of user and offer easy software/hardware system expansion. selectable modes, off-load the system of administering ; . real-time tasks such as counting/timing and I/O data com- For applications demanding powerful I/O capabilities, the — munications. Additionally, two on-board comparators pro- 286C28/E28's dedicated input and output lines are cess analog signals with a common reference voltage (Fig- grouped into three ports, and are configurable under soft- ure 1). ware control to provide timing, status signals, or parallel VO. CP97Z8X5100 PRELIMINARY 1
Figure 1. Z286C28/E28 Functional Block Diagram
2 PRELIMINARY CP97Z8X5100
Figure 2. 18-Pin DIP/SOIC
5 Vee Power Supply
6 XTAL2 Crystal Oscillator Clock Output
7 XTAL1 Crystal Oscillator Clock Input
8 P31 Port 3, Pin 1, AN1 Input
9 P32 Port 3, Pin 2, AN2 Input
10 P33 Port 3, Pin 3, REF Input
14 GND Ground
- This applies to all pins except XTAL pins and where otherwise noted.
- There is no input protection diode from pin to Vpp.
- Device pin is not at an output Low state.
tended period may affect device reliability. Figure 3. Test Load Diagram
4 PRELIMINARY CP97Z8X5100
Zilog CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers CAPACITANCE Ta = 25°C, Voc = GND = OV, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Min Max Input capacitance 0 12 pF Output capacitance 0 12 pF (/O capacitance 0 12 pF DC ELECTRICAL CHARACTERISTICS Taz 0°C to +70 °C Voc Typical Sym Parameter Note [3] Min Max @25°C Units Conditions Notes Vou Clock Input High Voltage 3.5V 0.7Veg = Vect0.3 1.8 V__ Driven by 5.5V 0.7 Vog Voc+0.3 2.5 V External Clock Generator Vo Clock Input Low Voltage 3.5V GND-0.3 0.2 Voc 0.9 V__ Driven by 5.5V GND-0.3 0.2 Veg 1.6 V External Clock Generator Vin Input High Voltage 3.5V 0.7 Voc Voc+0.3 2.5 Vv 55V 0.7Voo Voc 40.3 2.5 Vv Vit Input Low Voltage 3.5V GND-0.3 0.2 Voc 1.5 Vv 55V GND-0.3 0.2Veo 15 7 Vou Output High Voltage 3.5V Voc-0.4 3.3 Vi lon =- 0.5 mA Low EMI Mode 55V Vig -0.4 48 OV Vout Output High Voltage 3.5V Vec-0.4 3.3 Vi lon =-2.0 mA 5.5V Voc-0.4 48 Vi loy =-2.0 mA Vou Output Low Voltage 3.5V 0.4 0.2 Vi Ig, = +1.0 mA Low EMI Mode 5.5V 0.4 0.2 Vi lop = +1.0 mA Vou Output Low Voltage 3.5V 0.4 0.1 Vi Iop =+4.0 mA 8 Voie Output Low Voltage 3.5V 1.2 0.5 Vo Igp=+10mA 8 5.5V 1.2 0.5 Vi Ig =+10mA 8 Vorrset Comparator Input 3.5V 25 10 mV Offset Voltage 5.5V 25 10 mv Vicr Input Common Mode 3.5V ) Voc -1.0V Vv 10 Voltage Range 5.5V 0 Voc -1.0V Vv 10 lit Input Leakage 3.5V -1 2 0.032 HA Vin =0V, Voc 5.5V = 2 0.032 HA Vy = OV, Veg lot Output Leakage 3.5V = 2 0.082 pA Vin=OV, Voc 5.5V 1 2 0.032 HA Vin = OV, Veg loc Supply Current 3.5V 15 5 mA @ 12 MHz 45 5.5V 20 15 mA @ 12 MHz 4,5 loct Standby Current 3.5V 4 2 mA Vin=OV, Voc 4,5 Halt Mode 5.5V 6 4 mA @12MHz 45 3.5V 3 1.5 mA Clock Divide by 45 5.5V 5 3 mA 16 @ 12 MHz 45 ee CP97Z8X5100 PRELIMINARY 5
CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers Zilog SSS DC ELECTRICAL CHARACTERISTICS (Continued) Ty= 0 °C to +70 °C Voc Typical Sym Parameter Note [3] Min Max @25°C Units Conditions Notes loce Standby Current 3.5V 10 2 HA Vin = OV, Voc 6,11 Stop Mode 5.5V 10 3 BA Vin = OV, Voo 6,11 3.5V 15 7 WA Vina OVVeg 1113 5.5V 30 10 pA Vin = OV, Veg 611,13 TALL. Auto Latch 3.5V 0.7 8 2.4 HA OV <Vin<Voc 9 Low Current 5.5V 1.4 15 47 pA ov <Vin<Voo 9 TaLH Auto Latch 3.5V 0.6 5 1.8 vA 0V<Vin<Voc 9 High Current 5.5V -1 -8 -3.8 BA 0V<Vin<Vog 9 Tpor Power On Reset 3.5V 3.0 24 7 ms 5.5V 2.0 13 4 ms Viv Auto Reset Voltage 2.3 3.0 2.8 Vv 1,7 Notes: 1. Device does function down to the Auto Reset voltage. 2. GND=0V 3. The Vcc voltage specification of 5.5V guarantees 5.0V + 0.5V and the Vcc voltage specification of 3.5V guarantees only 3.5V. 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CLi= CL2 = 22 pF 6. Same as note [4] except inputs at Voc, 7. Max. temperature is 70°C. 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are at Voc = 5.0V and Veg = 3.5V 13. WDT running
6 PRELIMINARY CP97Z8X5100
Zilog CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers ——$— Ta=-40 °C to +105 °C Voc Typical Sym Parameter Note [3] Min Max @ 25°C Units Conditions Notes Vou Clock Input High 45V 0.7Vocg — Vgct0.3 2.5 V__ Driven by External Voltage 5.5V 0.7Vog Voct0.3 2.5 V_ Clock Generator Vo Clock Input Low 45V GND03 0.2Voo 1.5 V__ Driven by External Voltage 5.5V GND-0.3 0.2Vgo 1.5 V__ Clock Generator Vin InputHigh Voltage 4.5V 0.7Vgg Voct03 25 V 55V 0.7Vo¢ Voc 0.3 2.5 Vv Vit Input Low Voltage 45V GND-03 0.2Voo 1.5 Vv 55V GND03 02 Voc 1.5 Vv Vor Output High 45V Voc-0.4 48 V_Ioq=—-0.5mA 8 Voltage Low EMI 5.5V Voc-0.4 48 Vs logy =-0.5 mA 8 Mode Vox: Output High Voltage 4.5V Voco-0.4 48 V Ioy=-2.0mA 8 5.5V V¢o-0.4 4.8 Voy =-2.0 mA 8 Voi Output Low Voltage 4.5V 0.4 0.2 Vig, =+1.0 mA Low EMI Mode 5.5V 0.4 0.2 Vv lo, = +1.0 mA Vou Output Low Voltage 4.5V 0.4 0.1 Vo lop =+4.0 mA 8 Vote Output Low Voltage 4.5V 1.2 0.5 Vi Iop=+12mA 8 5.5V 1.2 0.5 Vo Igp=+12mA 8 Vorrser Comparator Input 4.5V 25 10 mV Offset Voltage 5.5V 25 10 mV Vicr Input Common 4.5V ) Voc-1.5V Vv 10 Mode Voltage 5.5V ) Voo-1.5V Vv 10 Range Iie Input Leakage 4.5V 1 2 <1 vA Vin =OV, Voc 5.5V +1 2 <1 pA Vin=OV, Voc lo. Output Leakage 4.5V -1 2 <1 HA Vin = OV, Veg 5.5V 4 2 <1 BA Vin = OV, Voo lec Supply Current 4.5V 20 15 mA @ 12 MHz 4,5 5.5V 20 15 mA @ 12MHz 4,5 CP97Z8X5100 PRELIMINARY 7
CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers Zilog Ta=-40 °C to +105 °C Voc Typical Sym Parameter Note [3] Min Max @ 25°C Units Conditions Notes Ico: StandbyCurrent =«s 45V0—~C<C*“‘“‘“S;SSOCON:CO#2 UMA Vy=OV,Vogq 45 Halt Mode @ 12 MHz 5.5V 6 4 MA Vin = OV, Voc 45 @ 12 MHz loce Standby Current 4.5V 10 2 WA Vin =OV, Voc 6,11 (Stop Mode) 5.5V 10 3 BA Vix = OV, Voc 6,11 4.5V 40 10 WA Vin =OV,Vog 11,13 5.5V 40 10 pA Vin = OV, Veo 611,13 TALL Auto Latch Low 4.5V 1.4 20 47 pA OV<Vin<Voo 9 Current 5.5V 1.4 20 47 BA OV<Vin<Voc 9 latH Auto Latch High 45V =1.0 10 38 pA 0V<Vin<Voo 9 Current 5.5V -1.0 -10 3.8 pA OV< Vin<Voo 9 Teor Power On Reset 4.5V 2.0 14 4 ms 5.5V 2.0 14 4 ms Viv Auto Reset Voltage 2.0 3.3 2.8 Vv 1 1. Device does function down to the Auto Reset voltage. 2. GND=0V 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1=CL2 = 22 pF 6. Same as note [4] except inputs at Voc. 7. Maximum temperature is 70°C 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are at Voc = 5.0V 13. WDT is not running.
8 PRELIMINARY CP97Z8X5100
Figure 4. Additional Timing Diagram
CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers Zilog Pa a aaah eins) Additional Timing Table (Divide-By-One Mode) Ta = 0°C to +70°C
4 MHz 6 MHz
No Symbol Parameter Note [6] Min Max Min Max Units Notes 1 Tpc Input Clock Period 3.5V 250 DC 166 DC ns 1,7,8 5.5V 250 Dc 166 DC ns 1,7,8 2 = TrC,TfC Clock Input Rise & 3.5V 25 25 ns 1,7,8 Fall Times 5.5V 25 25 ns 1,7,8 3 TwC Input Clock Width 3.5V 100 100 ns 1,7,8 5.5V 100 100 ns 1,7,8 4° TTinl Timer Input Low 3.5V 100 100 ns 1,7,8 Width 5.5V 70 70 ns 1,7,8 5 TwTinH Timer Input High 3.5V 5TpC 5TpC 1,7,8 Width 5.5V 5TpC 5TpC 1,7,8 6 = TpTin Timer Input Period 3.5V 8TpC 8TpC 1,7,8 5.5V 8TpC 8TpC 1,7,8 7 — TrTin, TfTin Timer Input Rise 3.5V 100 100 ns 1,7,8 & Fall Timer 5.5V 100 100 ns 1,7,8 8A TwIL Int. Request Low 3.5V 100 100 ns 1,2,7,8 Time 5.5V 70 70 ns 1,2,7,8 8B OTwIL Int. Request Low 3.5V 5TpC 5TpC 1,3,7,8 Time 5.5V 5TpC 5TpC 1,3,7,8 9 TwIH Int. Request Input 3.5V 5TpC 5TpC 1,2,7,8 High Time 5.5V 5TpC 5TpC 1,2,7,8 10 Twsm STOP Mode 3.5V 12 12 ns 48 Recovery Width 5.5V 12 12 ns 48 Spec 11 ‘Tost Oscillator Startup 3.5V 5TpC 5TpC 4,8,9 Time 5.5V 5TpC 5TpC 48,9 Notes: 1. Timing Reference uses 0.7 Veg for a logic 1 and 0.2 Veg for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WOTMR. 6. The Vgc voltage specification of 5.5V guarantees 5.0V +0.5V and the Vcc voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 =0. 8. Maximum frequency for internal system clock is 4 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver.
10 PRELIMINARY CP97Z8X5100
Zilog CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers RE Additional Timing Table (Divide-By-One Mode) Ta =~-40 °C to +105 °C No Symbol Parameter Note [6] Min Max Min Max Units Notes 1 Tpc Input Clock Period § —4.5V 250 [pfe} 166 DC ns 1,7,8 5.5V 250 DC 166 oc ns 1,7,8 2 TrC,TfC Clock Input Rise & 4.5V 25 25 ns 1,7,8 Fall Times 5.5V 25 25 ns 1,7,8 3 Tw Input Clock Width 4.5V 100 100 ns 1,7,8 5.5V 100 100 ns 1,7,8 4 9 Twink Timer Input Low 4.5V 100 100 ns 1,7,8 Width 5.5V 70 70 ns 1,7,8 5 TwTinH Timer Input High 4.5V 5TpC 5TpC 1,7,8 Width 5.5V 5TpC 5TpC 1,7,8 6 = TpTin Timer Input Period 4.5V 8TpC 8TpC 1,7,8 5.5V 8TpC 8TpC 1,7,8 7 — TrTin, TfTin Timer Input Rise 4.5V 100 100 ns 1,7,8 & Fall Timer 5.5V 100 100 ns 1,7,8 8A TwiL int. Request Low 4.5V 100 100 ns 1,2,7,8 Time 5.5V 70 70 ns 1,2,7,8 8B TwiL Int. Request Low 4.5V 5TpC 5TpC 1,3,7,8 Time 5.5V 5TpC 5TpC 1,3,7,8 9 TWH Int. Request Input 4.5V 5TpC 5TpC 1,2,7,8 High Time 5.5V 5TpC 5TpC 1,2,7,8 10 Twsm STOP Mode 4.5V 12 12 ns 48 Recovery Width 5.5V 12 12 ns 48 Spec 11 Tost Oscillator Startup 4.5V 5TpC 5TpC 4,8,9 Time 5.5V 5TpC 5TpC 4,8,9 Notes: 1. Timing Reference uses 0.7 Vgc for a logic 1 and 0.2 Vog for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WOTMR. 6. The Vcc voltage specification of 5.5V guarantees 5.0V +0.5V and the Voc voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 =0. 8. Maximum frequency for internal system clock is 4 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver. CP97Z8X5100 PRELIMINARY 1
CMOS 8-Bit Low-Cost 4K-ROM Microcontrollers Zilog Pte hia ahh) Additional Timing Table (Divide by Two Mode) Ty = 0 °C to +70 °C
12 MHz 4 MHz
No = Symbol Parameter Note [6] Min Max Min Max Units Conditions Notes 1 TpCc Input Clock Period 3.5V 62.5 DC 250 DC ns 1,7,8 5.5V 62.5 DC 250 DC ns 1,7,8 2 TrC,TIC = Clock Input Rise& = 3.5V 15 25 ns 1,7,8 Fall Times 5.5V 15 25 ns 1,7,8 3 TwC Input Clock Width 3.5V 31 31 ns 1,7,8 5.5V 31 31 ns 1,7,8 4 TwTink Timer Input Low 3.5V 70 70 ns 1,7,8 Width 5.5V 70 70 ns 1,7,8 5 TwTinH Timer Input High 3.5V 5TpC 5TpC 1,7,8 Width 5.5V 5TpC 5TpC 1,7,8 6 TpTin Timer Input Period 3.5V 8TpC 8TpC 1,7,8 5.5V 8TpC 8TpC 1,7,8 7 TrTin, TfTin Timer Input Rise 3.5V 100 100 ns 1,7,8 & Fall Timer 5.5V 100 100 ns 1,7,8 8A Twi Int. Request Low 3.5V 70 70 ns 1,2,7,8 Time 5.5V 70 70 ns 1,2,7,8 8B Twi Int. Request Low 3.5V 5TpC 5TpC 1,3,7,8 Time 5.5V 5TpC 5TpC 1,3,7,8 9 TwiH Int. Request Input 3.5V 5TpC 5TpC 1,2,7,8 High Time 5.5V 5TpC 5TpC 1,2,7,8 10 Twsm STOP Mode 3.5V 12 12 ns 48 Recovery Width 5.5V 12 12 ns 48 Spec 1 Tost Oscillator Startup 3.5V 5TpC 5TpC 48 Time 5.5V 5TpC 5TpC 48 12 Twdt Watch-Dog Timer 3.5V 10 10 ms DO=0 5,11 Delay Time Before 5.5V 5 5 ms D1=0 5,11 Timeout 3.5V 20 20 ms DO=1 5,11 5.5V 10 10 ms D1 =0 5,11 3.5V 40 40 ms DO=0 5,11 5.5V 20 20 ms Di=1 5,11 3.5V 160 160 ms DO=1 5,11 5.5V 80 80 ms D1i=1 5,11 Notes: 1. Timing Reference uses 0.7 Vcc for a logic 1 and 0.2 Vg for a logic 0. 2. Interrupt request via Port 3 (P31-P33) 3. Interrupt request via Port 3 (P30) 4, SMR-D5 = 1, POR STOP Mode Delay is on 5. Reg. WOTMR: 6. The Voc voltage specification of 5.5V guarantees 5.0V +0.5V and the Vcc voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 =0 8. Maximum frequency for internal system clock is 2 MHz when using Low EMI OSC PCON Bit D7 = 0. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 10. Standard Mode (not Low EMI output ports) 11. Using internal RC
12 PRELIMINARY CP97Z8X5100
Zilog Preliminary Product Specification CP97Z8X5100 a eS Pre-Characterization Product: The product represented by this CPS is newly introduced _ either by Zilog or its customers in the course of further and Zilog has not completed the full characterization ofthe application and characterization work. In addition, Zilog product. The CPS states what Zilog knows about this cautions that delivery may be uncertain at times, due to Product at this time, but additional features or non- _ start-up yield issues. conformance with some aspects of the CPS may be found, © 1997 by Zilog, Inc. All rights reserved. No part of this Zilog’s products are not authorized for use as critical document may be copied or reproduced in any form or by — components in life support devices or systems unless a any means without the prior written consent of Zilog, Inc. __ specific written agreement pertaining to such intended use The information in this document is subject to change _ is executed between the customer and Zilog prior to use. without notice. Devices sold by Zilog, Inc. are covered by Life support devices or systems are those which are warranty and patent indemnification provisions appearing _intended for surgical implantation into the body, or which in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. _ sustains life whose failure to perform, when properly used makes no warranty, express, statutory, implied or by in accordance with instructions for use provided in the description, regarding the information set forth herein or labeling, can be reasonably expected to result in regarding the freedom of the described devices from significant injury to the user. intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. 210 East Hacienda Ave. Zilog, Inc. shall not be responsible for any errors that may | Campbell, CA 95008-6600 appear in this document. Zilog, Inc. makes no commitment — Telephone (408) 370-8000 to update or keep current the information contained in this | FAX 408 370-8056 document. Internet: http://www.zilog.com Soo