Z86E15 ZILOG | Alldatasheet
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yp» PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION CMOS Z8?® 8-Bit OTP KEYBOARD CONTROLLER
FEATURES
ROM RAM* 10 Speed @ A Programmable 8-Bit Counter/Timer, with 6-Bit Device (KB) (Bytes) Lines (Mhz) Programmable Prescaler Z86E15 4 188 32 5 ™@ Power-On-Reset (POR) Timer, Hardware Watch-Dog Note: “General-Purpose Timer (WDT) m@ 4.5V to 5.5V Operating Range @ Digital Inputs CMOS Levels with Internal Pull-Up Resistors m 0°C to +70°C rating Temperature Rani Operating P 9° ™ Four Direct Connect LED Drive Ports m@ Low-Power Consumption: 60 mW @ 5 MHz @ = On-Chip RC Oscillator @ Five Vectored, Priority Interrupts from Five Different Sources @ Low System EMI Emission GENERAL DESCRIPTION The Z86E15 microcontroller (MCU) is amember of the sin- To unburden the program from coping with real-time prob- gle-chip Z8° MCU family with 4 KB of EPROM and 188 _ lems such as counting/timing, the Z86E15 offers an on- bytes of general-purpose RAM. chip counter/timer with a large number of user-selectable modes. The Z86E15 is a pin-compatible, One-Time-Programma- ble (OTP) version of the Z86K15 Keyboard Controller. Five different internal or external interrupt sources are . maskable and prioritized in which a vectored address is Zilog’s CMOS-microcontroller offers fast execution, effi- provided for efficient interrupt subroutine handling and cient use of memory, sophisticated interrupts, input/output —_ multitasking functions. bit manipulation capabilities. The Z86E15 achieves low EMI by means of several modi- fications in the output drivers and clock circuitry of the de- vice. DS97KEY1501 PRELIMINARY 1
Figure 1. Z86E15 Functional Block Diagram
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*Pin 5 and 6 used for testing Ground during normal operation. When Pin 5 is connected to V,.. Pin 6 is CLK OUT. When Pin 5 is connected to GND, Pin 6 outputs nothing. These pins must be tied to ground in application. Figure 2. 40-Pin DIP Configuration Table 1. 40-Pin DIP Pin Identification
1 GND Ground
12 Voe Power Supply Input
29 Veo Power Supply
30 GND Ground
31 AGND Analog Ground
32 RCIN RCIN Input
When Pin 43 is connected to V,.., Pin 44 is CLKOUT. When Pin 43 is connected to GND. Pin 44 outputs nothing. Figure 3. 44-Pin PLCC Pin Assignments Table 2. 44-Pin PLCC Pin Assignments
12 GND Ground
13 Voc Power Supply
29 NC Not Connected
30 P17 Port 1, Pin 7 Output
31 Veo Power Supply
32 GND Ground
33 AGND Analog Ground
34 NC Not Connected
35 RCIN RCIN Input
39 NC Not Connected
40 P37 Port 3, Pin 7 Output
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Pins 43 and 44 are used for testing ground during normal operation. When Pin 45 is connected to V,.., Pin 46 is CLKOUT. When Pin 45 is connected to GND. Pin 46 outputs nothing. Figure 4. 44-Pin QFP Pin Assignments Table 3. 44-Pin QFP Pin Identification
1 NC Not Connected
6 GND Ground
7 Veo Supply Voltage
23 NC Not Connected
24 P17 Port 1, Pin7 Output
25 Voe Supply Voltage
26 GND Ground
27 AGND Analog Ground
28 NC Not Connected
29 RCIN RCIN Input
33 NC Not Connected
34 P37 Port 3, Pin 7 Output
Note: * Voltage on all pins with respect to GND. may affect device reliability. Figure 5. Test Load Diagram T, = 25°C; V,, = GND = OV; f = 1.0 MHz; unmeasured pins returned to GND.
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Zilog CMOS Z8® 8-Bit OTP Keyboard Controller a atic relat hithchsihalchhchidal DC CHARACTERISTICS Veg = 5.0V + 10% @ 0°C to +70°C Sym Parameter Min Max Typ* Unit Condition Vo, Clock Input High Voltage 0.7V., Vag+03V 25 WV Drivenby External Clock Generator Vo Clock Input Low Voltage GND -0.3 0.2 Veg 1.5 V__ Driven by External Clock Generator Vw Input High Voltage 0.7 Veg Vogt 0.3 25 Vv Vi Input Low Voltage GND -0.3 0.2 Veg 1.5 Vv Vo, Output High Voltage Vo¢ 0.4 47 V_ \\g4 =—2.0 mA (Port 2 out. in P/P Mode) Vo, Output High Voltage Vee 71.0 V_— Ig4=—-2.0 pA (Port 0 and Port 1) Vo, Output Low Voltage 4 Volg=4mA Vo, Output Low Voltage 8 V_ Iy=4 mA (see note 1 below.) lon Output Low 10 20 MA V4= Vo, 2.2 V (See note 1, 2 below.) loo Vee Supply Current 12 6 mA @5.0 MHz lees HALTt Mode Current 2 mA @5.0 MHz loco. + STOP Mode Current 10 pA R, Pull Up Resistor 6.76 14.04 10.4 Kohm Port 20-25 and Port 30-33 R, Pull Up Resistor (P26-P27) 1.8 3 2.4 Kohm (PO & P1) 200 500 Kohm Notes: * Typical @ 25°C 1. Ports P37-P34. These may be used for LEDs or as general-purpose outputs requiring high sink current. DS97KEY1501 PRELIMINARY 7
CMOS Z8@® 8-Bit OTP Keyboard Controller Zilog AC ELECTRICAL CHARACTERISTICS T, = 0°C to 70°C Veo 5 MHz No Symbol Parameter Note[4] Min Max Units Notes 1 Tpc Input Clock Period 5.0V 200 250 ns 1 2 TrC,TfC Clock Input Rise & Fall Times 5.0V 25 ns 1 3 TwC Input Clock Width 5.0V 37 ns 1 4 TwTinL — Timer Input Low Width 5.0V 70 ns 1 5 TwTinH Timer Input High Width 5.0V 2.5TpC 1 6 TpTin Timer Input Period 5.0V 4TpC 1 7 TrTin, Timer Input Rise & Fall Timer 5.0V 100 ns 8A TIL Int. Request Low Time 5.0V 70 ns 1,2 8B Twit Int. Request Low Time 5.0V 3TpC 1,3 9 TwiH Int. Request Input High Time 5.0V 3TpC 1,2 10 Twsm Stop Mode Recovery Width Spec 5.0V 5TpC ns 1 Tost Oscillator Start-up Time 5.0V 5TpC 12 Twat Watch-Dog Timer Delay Time 5.0V 53 ms 13 Toon Power--On Reset 5.0V 106 130 ms Notes: 2. Interrupt request through Port 3 (P31-P33). 3. Interrupt request through Port 3 (P30).
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Figure 6. Additional Timing
and the power supply to form the precision RC oscillator. open-drain output (Figure 7). at the frequency of the RC oscillator (Test only). Figure 7. Port 0 Configuration
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open-drain output port (Figure 8). Figure 8. Port 1 Configuration
Port with 4-bit input, 4-bit programmable I/O (Figure 9). have 2.4K (+25%) pull-up resistors.
4 Input
Figure 9. Port 2 Configuration
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four-fixed input (P33-P30) and four-fixed output (P37-P34) external interrupt request signals (IRQO-IRQ3). V/O port. Port 3 inputs have 10.4 Kohm pull-up resistors. Outputs are capable of directly driving LED. Figure 10. Port 3 Configuration
Figure 11. Program Memory Map oe Note:* Will not be reset with a STOP Mode Recovery. Figure 12. Register Pointer Register
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REGISTER POINTER 28 STANDARD CONTROL REGISTERS. Figure 14. Register File Architecture
caler drives its counter, which decrements the value (1 to —_ disturbing its value or count mode. Figure 15. Counter/Timers Block Diagram
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Watch-Dog Timer. The Watch-Dog Timer (WDT) is acti- power-up of the Z86E15 (the default upon power-up is 0). sets the Z8 if it reaches its terminal count. The WDT is driv- automatically reset to 0 when read. register FAH) determines whether a hot start or cold start is 1, and a 1 indicates active during HALT.
- Reset Delay = POR 147 ms +10% at 4 MHz.
Figure 18. WDT Turn-On Timing After Reset
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0 OFF*
0 PORMOT*
- Stop-Mode Recovery * On RESET 9 RO Timeout
HALT. HALT turns off the internal CPU clock, but not the , , . IRQO, IRQ1, IRQ2, and IRQ3 remain active. The Z86E15 . The STOP Mode is terminated by a reset only or external . program at address 000C (HEX) or the active external in- or host data line will recover Z86E15 from STOP Mode. Figure 20. Stop-Mode Recovery Source
1 Defines Bit as INPUT
Figure 21. Timer Mode Register Figure 24 wre Wate Only) Figure 22. (F4,: Read/Write) Figure 25. (F7,,: Write Only) Figure 23. (F5,: Write Only) 0 =1RQ1 >IRO4 Figure 26. Interrupt Priority Register
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0 OFF" Decimal Adjust Flag
1 Stop Recovery Zero Flag
Figure 29. Flag Register Figure 27. Interrupt Request Register 8 (FC,;: ReadWrit)
1 Enables (RQ0-IRQ4 4
1 Enables Interrupts 6 inter
Figure 28. Interrupt Mask Register Figure 30. (FD,,: Read/Write) Figure 31. (FF,,: Read/Write)
CMOS Z8® 8-Bit OTP Keyboard Controller Zilog prelates) PROGRAMMING Signals Required for E15 EPROM P21 (PGMb-Program Mode) a ‘i . 1 This regular pin on the Z86E15 allows the EPROM to be The TEST1 pin will be used as a high voltage pin. The high i . . voltage from this pin will be used to program the EPROM. signal Vans tone He signal is wae dates wil be one tpnowe need to be at high voltage ‘n order for any grammed into the location that is addressed by the internal operation to be done. When this pin is at high counter that generates the address for the EPROM. voltage, then an internal signal V,,, is generated from the ° high voltage detect circuitry and the signal being active will poo (epadr_clk) and P23 (epadr_rst) be used to multiplex the remaining pins that are required in The aadross is generated or an internal address counter all the EPROM operations. which is clocked through the signal epadr_clk. Each clock TEST! (Vpp) increments the counter by one. The counter can be reset This pin is designated a high voltage pin on the Z86E15. ° wore by one onan eo Both epadr_clk and All EPROM operations will require a high voltage on this padr_t ignals. pin. The V,, supplies the high voltage for the programming 1 i ive high signal. of the EPROM. The epadr_rst signal is an active high signal. Note: The pins listed below are based on the condition Data to the EPROM ; ; ; that the V,, is in high voltage. The data to the EPROM are multiplexed with the pins as shown below in Figure 32: (Data <7.0>) P33 (Mode Latch) The Z86E15 utilizes this pin when high will be used to latch the mode. This condition will only happen when the V,,,, is active. ™ Data pin P32 (Oeb-Output Enable) Dt pee This regular pin controls the direction of the data bus. The D3 P37 signal generated goes into the EPROM as the precharge D4 P27 signal. Be p26 When this signal is low, the data is output from the 7 P24 EPROM. When the signal is high, data is input to the EPROM. Figure 32. Data Pin Assignments When the signal is high, the EPROM is precharged. When the signal is low, the EPROM is evaluated. Option Bit Programming P31 (EPMH) _— oa In order to program the option bits, the Mode 3 should be This regular pin is used to read the option bits when the seg. This can be done as follows: EPROM is protected. : ope . oo ™ The V,, pin is set to high voltage (device pin TEST1 is When the signal is high, during POR, the option bits can be driven to high voltage). read from the EPROM. @ = The epadr_rst signal is driven high for one cycle to reset P30 (Volt_Clamp) : 7 the address counter (device pin P23). This regular pin used the signal to disable the voltage clamp circuit. ™ Three clocks are given on the epadr_clk pin (P22), . | we which will advance the counter to the count of 3. When the signal is low, the voltage clamp circuit is en- abled. When the signal is high, the voltage clamp circuitis ™ The Mode Latch signal (P33) is driven high for one cycle disabled and margin testing can be done. to latch in the data into the Mode Register. P20 (CEb) ™ The address counter is again reset and the required This regular pin on the Z86E15 is the chip enable signal for data is programmed into location 0, which will program the EPROM. This signal will be input to the EPROM when the 8 locations of the option bits. In the Z86E15, bits 0, Vpph is high. This is an active low signal. 1 and 2 will be used as there are only 3 option bits for this device.
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3 B r a
Figure 35. 44-Pin QFP Package Diagram
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Zilog CMOS Z8®@ 8-Bit OTP Keyboard Controller
ORDERING INFORMATION
5 MHz 5 MHz 5 MHz
40-Pin DIP 44-Pin PLCC 44-Pin QFP Z86E1505PSC Z86E1505VSC Z86E1505FSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Package Environmental P = Plastic DIP C = Plastic Standard V = Plastic Leaded Chip Carrier F = Quad Flat Pack Temperature Speed $ =0°C to +70°C 05 = 5 MHz Example: Z 86E1505P S C is a Z86E15, 05 MHz, DIP, 0° to +70°C, Plastic Standard Flow L Environmental Flow Temperature Package Speed Product Number Zilog Prefix DS97KEY1501 PRELIMINARY 25
Zilog Preliminary Product Specification DS97KEY1501 Development Projects: Customer is cautioned that while reasonable efforts willbe | and delays. No production release is authorized or employed to meet performance objectives and milestone — committed until the Customer and Zilog have agreed upon dates, development is subject to unanticipated problems a Customer Procurement Specification for this project. Pre-Characterization Product: The product represented by this CPS is newly introduced _ either by Zilog or its customers in the course of further and Zilog has not completed the full characterization of the application and characterization work. In addition, Zilog product. The CPS states what Zilog knows about this cautions that delivery may be uncertain at times, due to product at this time, but additional features or non- _ start-up yield issues. conformance with some aspects of the CPS may be found, Low Margin: Customer is advised that this product does not meet Zilog liability stated on the front and back of the Zilog's internal guardbanded test policies for the | acknowledgement, Zilog makes no claim as to quality and specification requested and is supplied on an exception __ reliability under the CPS. The product remains subject to basis. Customer is cautioned that delivery may be standard warranty for replacement due to defects in uncertain and that, in addition to all other limitations on —_ materials and workmanship. © 1997 by Zilog, Inc. All rights reserved. No part of this Zilog’s products are not authorized for use as critical document may be copied or reproduced in any form or by components in life support devices or systems unless a any means without the prior written consent of Zilog, Inc. specific written agreement pertaining to such intended use The information in this document is subject to change __ is executed between the customer and Zilog prior to use. without notice. Devices sold by Zilog, Inc. are covered by —_Life support devices or systems are those which are warranty and patent indemnification provisions appearing _intended for surgical implantation into the body, or which in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. sustains life whose failure to perform, when properly used makes no warranty, express, statutory, implied or by in accordance with instructions for use provided in the description, regarding the information set forth herein or labeling, can be reasonably expected to result in regarding the freedom of the described devices from __ significant injury to the user. intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. 210 East Hacienda Ave. Zilog, Inc. shall not be responsible for any errors that may | Campbell, CA 95008-6600 appear in this document. Zilog, Inc. makes no commitment — Telephone (408) 370-8000 to update or keep current the information contained in this | FAX 408 370-8056 document. Internet: http://www.zilog.com ee