Z86E0816PSG

Z86E3016PSG ZILOG | Alldatasheet

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San Jose, CA 95126 T elephone: 408.558.8500 F ax: 408.558.8300 www .ZiLOG.com Z8 F amily of Microcontrollers Z8 CPU User Manual UM001602-0904

Z8 Family of Microcontrollers User Manual UM001602-0904 ii This publication is subject to replacement by a later edition. T o determine whether a later edition e xists, or to request copies of publications, contact ZiLOG W orld wide Headquarters San Jose, CA 95126 T elephone: 408.558.8500 F ax: 408.558.8300 www .ZiLOG.com Document Disclaimer ZiLOG is a re gistered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which the y are associated. 2004 by ZiLOG, Inc. All rights reserv ed. Information in this publication concerning the de vices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NO T ASSUME LIABILITY FOR OR PR O VIDE A REPRESENT A TION OF A CCURA CY OF THE INFORMA TION, DEVICES, OR T ECHN OLOGY DESCRIBED IN THIS DOCUMENT . ZiLOG ALSO DOES NO T ASSUME LIABILITY FOR INTELLECTU AL PR OPER TY INFRINGEMENT RELA TED IN ANY MANNER T O USE OF INFORMA TION, DEVICES, OR T ECHN OLOGY DESCRIBED HEREIN OR O THER WISE. De vices sold by ZiLOG, Inc. are co v ered by w arranty and limitation of liability pro visions appearing in the ZiLOG, Inc. T erms and Conditions of Sale. ZiLOG, Inc. mak es no w arranty of merchantability or fi tness for an y purpose Except with the e xpress written appro v al of ZiLOG, use of information, de vices, or technology as critical components of life support systems is not authorized. No licenses are con v e yed, implicitly or otherwise, by this document under an y intellectual property rights.

Revision History

T able refl ects a change to this document from its pre vi ous re vision. T o see more detail, click the appropriate link in the table. T able 1. Revision History of this Document Date Revision Level Section

Description

Page # Sept. 004 Formatted to current publication standards All

Z8 Family of Microcontrollers User Manual

v T able of Contents i L ist of Figures xi List of Tables xvii Z8 CPU Product Overvie w Key F eatures Product Development Support

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UM001602-0904 Table of Contents vii

Z8 Family of Microcontrollers User Manual Table of Contents UM001602-0904 viii

UM001602-0904 Table of Contents ix

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Table 2. ZiLOG General-Purpose Microcontroller Product Family . 4 Table 13. Sample Control and Peripheral Register Reset Values Table 14. Expanded Register File Bank 0 Reset Values at RESET . 51 Table 15. Sample Expanded Register File Bank C Reset Values . . . 51 Table 16. Sample Expanded Register File Bank F Reset Values . . . 52

UM001602-0904 Z8 CPU Product Overview Z8 CPU Product Overview The ZiLOG Z8 microcontroller (MCU) product line continues to expand with new product introductions. ZiLOG MCU products are targeted for cost-sensitive, high-volume applications including consumer, automotive, security, and HVAC. It includes ROM-based products geared for high- volume production (where software is stable) and one-time programma- ble (OTP) equivalents for prototyping as well as volume production where time to market or code flexibility is critical (see Table 1 on page 4). A variety of packaging options are available including plastic DIP, SOIC, PLCC, and QFP. A generalized Z8 CPU® block diagram is shown in Figure 1. The same on-chip peripherals are used across the MCU product line with the pri- mary differences being the amount of ROM/RAM, number of I/O lines present, and packaging/temperature ranges available. This allows code written for one MCU device to be easily ported to another family mem- ber. Key Features General-Purpose Register File. Every RAM register acts like an accu- mulator, speeding instruction execution and maximizing coding effi- ciency. Working register groups allow fast context switching. Flexible I/O. I/O byte, nibble, and/or bit programmable as inputs or out- puts. Outputs are software programmable as open-drain or push–pull on a port basis. Inputs are Schmitt-triggered with autolatches to hold unused inputs at a known voltage state. Analog Inputs. Three input pins are software programmable as digital or analog inputs. When in analog mode, two comparator inputs are provided with a common reference input. These inputs are ideal for a variety of common functions, including threshold level detection, analog-to-digital

Z8 Family of Microcontrollers User Manual Z8 CPU Product Overview UM001602-0904 conversion, and short circuit detection. Each analog input provides a unique maskable interrupt input. Timer/Counter. The Timer/Counter (T/C) consists of a programmable 6- bit prescaler and 8-bit downcounter, with maskable interrupt upon end-of- count. Software controls T/C load/start/stop, countdown read (at any time on the fly), and maskable end-of-count interrupt. Special functions avail- able include TIN (external counter input, external gate input, or external trigger input) and TOUT (external access to timer output or the internal system clock.) These special functions allow accurate hardware input pulse measurement and output waveform generation. Interrupts. There are six vectored interrupt sources with software-pro- grammable enable and priority for each of the six sources. Watch–Dog Timer. An internal Watch–Dog Timer (WDT) circuit is included as a fail-safe mechanism so that if software strays outside the bounds of normal operation, the WDT will time-out and reset the MCU. To maximize circuit robustness and reliability, the default WDT clock source is an internal RC circuit (isolated from the device clock source). Auto Reset/Low-Voltage Protection. All family devices have internal Power-On Reset. ROM devices add low-voltage protection. Low-voltage protection ensures the MCU is in a known state at all times (in active RUN mode or RESET) without external hardware (or a device reset pin). Low-EMI Operation. Mode is programmable via software or as a mask option. This new option provides for reduced radiated emission via clock and output drive circuit changes. Low-Power. CMOS with two standby modes; STOP and HALT. Full Z8 Instruction Set. Forty-eight basic instructions, supported by six addressing modes with the ability to operate on bits, nibbles, bytes, and words.

Figure 1. Z8 CPU Block Diagram

EPROM programmers, and software simulators. Table 1. ZiLOG General-Purpose Microcontroller Product Family

UM001602-0904 Z8 CPU Product Overview The Z86CCP01ZEM kit comes with:

• Z8 CCP Evaluation Board
• Z8 CCP Power Cable
• ZiLOG Developer’s Studio (ZDS) CD-ROM , Including Windows- Based GUI Host Software
• 1999 ZiLOG Technical Library
• Z8 CCP User Manual A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also available and provides an RS-232 cable and power cable along with the 28- and 40- pin ZIF sockets and 28- and 40- pin target connector cables required to emu- late/program 28/40 pin devices.

Z8 Family of Microcontrollers User Manual Z8 CPU Product Overview UM001602-0904

• The Z8® Standard Register File contains addresses for peripheral, control, all general-purpose, and all I/O port registers. This is the default register file specification.
• The Z8® Expanded Register File (ERF) contains addresses for con- trol and data registers for additional peripherals/features.
• Z8 external program memory contains addresses for all memory loca- tions having executable code and/or data.
• Z8 external data memory contains addresses for all memory locations that hold data only, whether internal or external. Z8 CPU Standard Register File The Z8® Standard Register File totals up to 256 consecutive bytes (Regis- ters). The register file consists of 4 I/O ports (00h–03h), 236 General- Purpose Registers (04h–EFh), and 16 control registers (F0h–FFh). Table 2 shows the layout of the register file, including register names, locations, and identifiers.

Table 2. Z8 Standard Register File

03 P3 Port 3

02 P2 Port 2

01 P1 Port 1

00 P0 Port 0

Table 2. Z8 Standard Register File (Continued)

Z8 Family of Microcontrollers User Manual Address Space UM001602-0904 When instructions are executed, registers are read when defined as sources and written when defined as destinations. All General-Purpose Registers function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. General-Purpose Registers General-Purpose Registers (GPR) are undefined after the device is pow- ered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. It will not keep its last state from a VLV reset if VCC drops below 1.8v. Registers in Bank E0-EF may only be accessed through the working regis- ter and indirect addressing modes. Direct access cannot be used because the 4-bit working register address mode already uses the format [E | dst], where dst represents the working register number from 0h to Fh. RAM Protect The upper portion of the register file address space 80h to EFh (excluding the control registers) may be protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the cus- tomer when the ROM code is submitted. After the mask option is selected, the user activates this feature from the internal ROM code to turn off/on the RAM Protect by loading either a 0 or 1 into the IMR regis- ter, bit D6. A 1 in D6 enables RAM Protect. Only devices that use regis- ters 80h to EFh offer this feature. Working Register Groups Z8 instructions can access 8-bit registers and register pairs (16-bit words) using either 4-bit or 8-bit address fields. 8-bit address fields refer to the actual address of the register. For example, Register 58h is accessed by calling upon its 8-bit binary equivalent, 01011000 (58h). With 4-bit addressing, the register file is logically divided into 16 Work- ing Register Groups of 16 registers each, as shown in Table 3. These 16 Note:

current Working Register Group. Table 3. Working Register Groups

Figure 4. Working Register Addressing Examples Table 3. Working Register Groups (Continued)

• Registers F3h and F5h–F9h are write-only registers. If an attempt is made to read these registers, FFh is returned. Reading any write-only register will return FFh. *Note: The full register file is shown. Please refer to the selected device product specification for actual file size.

Figure 5. Register Pointer the active working-register group.

Z8 Family of Microcontrollers User Manual Address Space UM001602-0904

• When register FDh (Register Pointer) is read, the least significant four bits (lower nibble) will indicate the current Expanded Register File Bank. (Example: 0000 indicates the Standard Register File, while 1010 indicates Expanded Register File Bank A.)
• When Ports 0 and 1 are defined as address outputs, registers 00h and 01h will return 1s in each address bit location when read.
• Writing to bits that are defined as timer output, serial output, or hand- shake output will have no effect.
• The Z8® CPU instruction DJNZ uses any general-purpose working register as a counter.
• Logical instructions such as OR and AND require that the current contents of the operand be read. They therefore will not function properly on write-only registers.
• The WDTMR register must be written within the first 60 internal sys- tem clocks (SCLK) of operation after a reset. Z8 Expanded Register File The standard register file of the Z8® CPU has been expanded to form 16 Expanded Register File (ERF) Banks, as shown in Figure 6. Each ERF Bank consists of up to 256 registers (the same amount as in the Standard Register File) that can then be divided into 16 Working Register Groups. This expansion allows for access to additional feature/peripheral control and data registers.

Figure 6. Expanded Register File Architecture

implemented. All are reserved for future use. locations of the Z8® Standard Register File. 0 is implemented in ERF Bank C. Access to the ERF is accomplished through the Register Pointer (FDh). Figure 7. Register Pointer Example

register file assigned to it. Table 4. ERF Bank Address 0001b 1 Expanded Register File Bank 1. 0010b 2 Expanded Register File Bank 2. 0011b 3 Expanded Register File Bank 3.. 0101b 5 Expanded Register File Bank 5.. 0111b 7 Expanded Register File Bank 7.. 1001b 9 Expanded Register File Bank 9.. 1011b B Expanded Register File Bank B. 1100b C Expanded Register File Bank C. 1101b D Expanded Register File Bank D.. 1111b F Expanded Register File Bank F. *Note: the Z8® Standard Register File is equivalent to Expanded Register File Bank 0.

registers. Table 5 shows an example. Table 5. Register Pointer Access Example R253 RP = 00h ;ERF Bank 0, Working Reg. Group 0. If R253 RP = 0Fh ;ERF Bank F, Working Reg. Group 0.

Bank 0 when these registers are required for use. ;ERF Bank F, Working Reg. Group F. Table 5. Register Pointer Access Example (Continued)

Table 6. ERF Bank C Access Example ;register group 0 for access. Table 7. Z8 Expanded Register File Bank Layout

• Interrupt Priority Register (IPR)
• Interrupt Mask Register (IMR)
• Interrupt Request Register (IRQ)
• Program Control Flags (FLAGS)
• Register Pointer (RP)
• Stack Pointer High-Byte (SPH)
• Stack Pointer Low-Byte (SPL) 4h Not implemented (reserved) 3h Not implemented (reserved) 2h Not implemented (reserved) 1h Not implemented (reserved) 0h Z8 Ports 0, 1, 2, 3, and General-Purpose Registers 04h to EFh, and control registers F0h to FFh.

Z8 Family of Microcontrollers User Manual Address Space UM001602-0904 The Z8® CPU uses a 16-bit Program Counter (PC) to determine the sequence of current program instructions. The PC is not an addressable register. Peripheral registers are used to transfer data, configure the operating mode, and control the operation of the on-chip peripherals. Any instruc- tion that references the register file can access the peripheral registers. The peripheral registers are:

• Serial I/O (SIO)
• Timer Mode (TMR)
• Timer/Counter 0 (T0)
• T0 Prescaler (PRE0)
• Timer/Counter 1 (T1)
• T1 Prescaler (PRE1)
• Port 0–1 Mode (P01M)
• Port 2 Mode (P2M)
• Port 3 Mode (P3M) In addition, the four port registers (P0–P3) are considered to be peripheral registers. Expanded Z8 Registers The expanded Z8 control registers govern the operation of additional fea- tures or peripherals. Any instruction which references the register file can access these registers. The ERF contains the control registers for WDT, Port Control, Serial Peripheral Interface (SPI), and the SMR functions. Figure 6 on page 15 shows the layout of the Register Banks in the ERF. Register Bank C in the ERF consists of the registers for the SPI. Table 8 shows the registers within ERF Bank C, Working Register Group 0.

Table 8. Expanded Register File Register Bank C

9 Reserved R9

8 Reserved R8

7 Reserved R7

6 Reserved R6

5 Reserved R5

4 Reserved R4

3 Reserved R3

2 SPI Control (SCON) R2

1 SPI Tx/Rx Data (Roxburgh) R1

0 SPI Compare (SCOMP) R0

Table 9. Expanded Register File Bank 0

9 General-Purpose Register R9

8 General-Purpose Register R8

7 General-Purpose Register R7

6 General-Purpose Register R6

5 General-Purpose Register R5

4 General-Purpose Register R4

3 Port 3 R3

2 Port 2 R2

1 Port 1 R1

0 Port 0 R0

Table 10. Expanded Register File Bank F

2 Reserved R2

1 Reserved R1

0 PCON R0

Z8 Family of Microcontrollers User Manual Address Space UM001602-0904 The functions and applications of the control and peripheral registers are described in subsequent sections of this manual. Program Memory The first 12 bytes of program memory are reserved for the interrupt vec- tors, as shown in Figure 8. These locations contain six 16-bit vectors that correspond to the six available interrupts. Address 12 up to the maximum ROM address consists of on-chip mask-programmable ROM. See the product data sheet for the exact program, data, register memory size, and address range available. At addresses outside the internal ROM, the Z8® CPU executes external program memory fetches through Port 0 and Port 1 in Address/Data mode for devices with Port 0 and Port 1 featured. Oth- erwise, the program counter will continue to execute NOPs up to address FFFFh, roll over to 0000h, and continue to fetch executable code (see Figure 8). The internal program memory is one-time programmable (OTP) or mask programmable dependent on the specific device. A ROM protect feature prevents dumping of the ROM contents by inhibiting execution of the LDC, LDCI, LDE, and LDEI instructions to program memory in all modes. ROM look-up tables cannot be used with this feature. The ROM Protect option is mask-programmable, to be selected by the customer when the ROM code is submitted. For the OTP ROM, the ROM Protect option is an OTP programming option.

Figure 8. Z8 Program Memor y Map

Z8 Family of Microcontrollers User Manual Address Space UM001602-0904 gram memory the Z8® CPU offers multiplexed address/data lines (AD7– AD0) on Port 1 and address lines (A15–A8) on Port 0. This feature only applies to devices that offer Port 0 and Port 1. The maximum external address is FFFF. This memory interface is supported by the control lines AS (Address Strobe), DS (Data Strobe), and R/W (Read/Write). The ori- gin of the external program memory starts after the last address of the internal ROM. Figure 9 shows an example of external program memory for the Z8® CPU. External Data Memory The Z8® CPU, in some cases, can address up to 60 KB of external data memory beginning at location 4096. External data memory (DM) can be included with, or separated from, the external program memory space. DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space. The state of the DM signal is controlled by the type of instruction being exe- cuted. An LDC opcode references program memory (DM inactive) , and an LDE instruction references data memory (DM active Low) . The user must configure Port 3 Mode Register (P3M) bits D3 and D4 for this mode.

memory addressing options available, see the device product specification. Figure 9. External Memory Map

be used for the stack when the internal stack is selected. FEh and LSB in FFh; see Figure 10. CALL instructions and interrupts, as well as a data stack. During a CALL instruction, the contents of the PC are saved on the stack. instruction restores them Figure 11. Figure 10. Stack Pointer

must prevent this occurrence or unpredictable operation will result. Figure 11. Stack Operations

Z8 Family of Microcontrollers User Manual Address Space UM001602-0904

clock circuitry. The oscillator’s input is XTAL1 and its output is XTAL2. or an external clock source. ity of options and output drive characteristics. Mode Recovery Register in Expanded Register File Bank F, Register 0Bh. Figure 12. Z8® CPU Clock Circuit

specification for availability of this feature/register. Figure 13. Stop-Mode Recovery Register (Write-Only Except D7,

0 OFF **

= SCLK ÷ TCLK = X TAL * Default setting after RESET.

In some cases, the CPU of fers softw are control of the oscillator to select lo w EMI dri v e or standard dri v The selection is done by program ming bit D7 of the Port Confi guration (PCON) re gister ( see Figure The PCON re gister is located in Expanded Re gister File Bank F , Re gister 00h Figure 14. External Cloc k Cir cuit OSC External Clock D1 (SMR) ÷16 D0 (SMR)

XTAL clock frequency to the internal system clock (SCLK). ture, and low impedances (not disturbed by stray affects). R1 is a resistive component placed from output to input of the amplifier. and to provide the start-up transition. Figure 15. Port Configuration Register (Write-Only)

0 Low EMI

1 Standard

small phase shift. It will also provide some attenuation of overtones. C1 and C2 can affect the start-up time if they increase dramatically in size. reaches a point where it does not start up any more. possible without resulting in overtone operation. close as possible to the oscillator pins of the Z8® CPU . Figure 16. Pierce Oscillator with Internal Feedback Circuit

Z8 Family of Microcontrollers User Manual Clock UM001602-0904 data lines, system ground) to reduce cross talk and noise injection. This is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit and by placing a Z8® CPU device VSS ground ring around the traces/components. The ground side of the oscillator lead caps should be connected to a single trace to the Z8® CPU’s VSS (GND) pin. It should not be shared with any other system ground trace or components except at the Z8® CPU’s VSS pin. This is to prevent differential system ground noise injection into the oscillator (see Figure 17). Indications of an Unreliable Design Start-up time and output level are two major indicators that are used in working designs to determine their reliability over full lot and tempera- ture variations. These two indicators are described below. Start-Up Time. If start-up time is excessive, or varies widely from unit to unit, there is probably a gain problem. C1/C2 must be reduced; the ampli- fier gain is not adequate at frequency, or crystal resistance is too large. Output Level. The signal at the amplifier output should swing from ground to VCC. This indicates there is adequate gain in the amplifier. As the oscillator starts up, the signal amplitude grows until clipping occurs, at which point the loop gain is effectively reduced to unity and constant oscillation is achieved. A signal of less than 2.5 volts peak-to-peak is an indication that low gain may be a problem. Either C1 or C2 should be made smaller or a low-resistance crystal should be used. Circuit Board Design Rules The following circuit board design rules are suggested:

• To prevent induced noise the crystal and load capacitors should be physically located as close to the Z8® CPU as possible.

• Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry and the internal system clock output should be separated as much as possible.
• VCC power lines should be separated from the clock oscillator input circuitry.
• Resistivity between XTAL1 or XTAL2 and the other pins should be greater than 10 MΩ.

characteristics listed in Table 11 to ensure proper oscillator operation. Figure 17. Circuit Board Design Rules

dependent on the manufacturer’s crystal specifications. Table 11. Crystal/Resonator Characteristics Figure 18. Crystal/Ceramic Resonator Oscillator

In Figures 18 through 20, ZiLOG recommends that the user connect the load capacitor ground trace directly to the VSS (GND) pin of the Z8® CPU to ensure that no system noise is injected into the Z8® clock. This trace should not be shared with any other components except at the VSS pin of the Z8® CPU. In some cases, the Z8® CPU’s XTAL1 pin also functions as one of the EPROM high-voltage mode programming pins or as a special factory test pin. In this case, applying 2 V above VCC on the XTAL1 pin will cause the device to enter one of these modes. Because this pin accepts high volt- ages to enter these respective modes, the standard input protection diode to VCC is not on XTAL1. ZiLOG recommends that in applications where the Z8® CPU is exposed to much system noise, a diode from XTAL1 to VCC be used to prevent accidental enabling of these modes. This diode will not affect the crystal/ceramic resonator operation. Please note that a parallel resonant crystal or resonator data sheet will specify a load capacitor value that is the series combination of C1 and C2, including all parasitics (PCB and holder). LC Oscillator The Z8® CPU oscillator can use a LC network to generate a XTAL clock (see Figure 19). The frequency stays stable over VCC and temperature. The oscillation fre- quency is determined by the equation. where L is the total inductance including parasitics and CT is the total series capacitance including the parasitics. Simple series capacitance is calculated using the following equation: Frequency = 1 2 π (LCT)1/2

Z8 Family of Microcontrollers User Manual Clock UM001602-0904 Sample calculation of capacitance C1 and C2 for 5.83 MHz frequency and inductance value of 27 µH. RC Oscillator In some cases, the Z8® CPU features an RC oscillator option. Please refer to the specific product specification for availability. The RC oscillator requires a resistor across XTAL1 and XTAL2. An additional load capaci- tor is required from the XTAL1 input to VSS pin (see Figure 21). 1 = 1 + 1 CT C1 C2 If C1 = C2 1 = 2 CT = C1 C1 = 2CT 5.83 (106) = 1 CT = 27.6 pF Thus C1 = 55.2 pF and C2 = 55.2 pF.

Figure 21. RC Clock

Z8 Family of Microcontrollers User Manual Clock UM001602-0904

This section describes the Z8® CPU reset conditions, reset timing, and register initialization procedures. Reset is generated by Power-On Reset (POR), Reset Pin, Watch–Dog Timer (WDT), and Stop-Mode Recovery. A system reset overrides all other operating conditions and puts the Z8® CPU into a known state. To initialize the chip’s internal logic, the RESET input must be held Low for at least 21 SCP or 5 XTAL clock cycles. The control register and ports are reset to their default conditions after a POR, a reset from the RESET pin, or Watch–Dog Timer time-out while in RUN mode and HALT mode. The control registers and ports are not reset to their default conditions after Stop- Mode Recovery and WDT time-out while in STOP mode. While RESET pin is Low, AS is output at the internal clock rate, DS is forced Low, and R/W remains High. The program counter is loaded with 000Ch. I/O ports and control registers are configured to their default reset state. Resetting the Z8® CPU does not affect the contents of the general-pur- pose registers. Reset Pin, Internal POR Operation In some cases, the Z8® CPU hardware RESET pin initializes the control and peripheral registers, as shown in Tables 12 through 15. Specific reset values are shown by 1 or 0, while bits whose states are unknown are indi- cated by the letter U. Tables 12 through 15 show the reset conditions for the Z8 CPU. The register file reset state is device dependent. Please refer to the selected device product specifications for register availability and reset state. Note:

Table 12. Sample Control and Peripheral Register Reset Values (ERF Bank 0) F1 Timer Mode 0 0 0 0 0 0 0 0 Counter/Timers stopped. F5 T0 Prescaler U U U U U U U 0 Single-pass count mode. FA Interrupt Request 0 0 0 0 0 0 0 0 All Interrupts Cleared. FB Interrupt Mask 0 U U U U U U U Interrupts Disabled.

the on-board clock oscillator to stabilize. Figure 23. Example of External Power-On Reset Circuit

Table 13. Expanded Register File Bank 0 Reset Values at RESET

00 Port 0 U U U U U U U U Input mode, output set to

01 Port 1 U U U U U U U U Input mode, output set to

02 Port 2 U U U U U U U U Input mode, output set to

03 Port 3 1 1 1 1 U U U U Standard digital input and

Table 14. Sample Expanded Register File Bank C Reset Values

00 SPI Compare

01 Receive Buffer

02 SPI Control

Table 15. Sample Expanded Register File Bank F Reset Values

00 Port Configuration

Figure 24. Example of Z8 Reset with RESET Pin, WDT, SMR, and POR

256 TpC 256 512 1024 4096

4 Clock

Figure 25. Example of Z8 Reset with WDT , SMR, and POR

18 Clock RESET

UM001602-0904 Watch–Dog Timer Watch–Dog Timer The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8® CPU if it reaches its terminal count. When operating in the RUN or HALT modes, a WDT reset is functionally equivalent to a hardware POR reset. The WDT is initially enabled by executing the WDT instruc- tion and refreshed on subsequent executions of the WDT instruction. The WDT cannot be disabled after it has been initially enabled. Permanently enabled WDTs are always enabled and the WDT instruction is used to refresh it. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The POR clock source is selected with bit 4 of the Watch–Dog Timer Mode register (WDTMR). In some cases, a Z8 that offers the WDT but does not have a WDTMR register, has a fixed WDT time-out and uses the on board RC oscillator as the only clock source. Please refer to specific product specifications for selectabil- ity of time-out, WDT during HALT and STOP modes, source of WDT clock, and availability of the permanently-on WDT option. Execution of the WDT instruction affects the Z (zero), S (sign), and V (overflow) flags.

register’s control bits are described on the next two pages. Figure 26. Example of Z8 W atch–Dog Timer Mode Register (Write-

0 OFF

1 ON *

0 On-Board RC *

1 XTAL

obtained. The default value of D1 and D0 are 0 and 1, respectively. to their default reset conditions. using any of the other STOP mode sources. Table 16. Time-Out Period of the WDT for exact WDTMR time out select options available.

1. The default on reset is, D0 = 1 and D1 = 0.

Z8 Family of Microcontrollers User Manual Watch–Dog Timer UM001602-0904 Clock Source for WDT. The D4 bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the internal RC oscillator. Bits 5, 6, and 7. These bits are reserved. VCC Voltage Comparator. An on-board voltage comparator checks that VCC is at the required level to insure correct operation of the device. Reset is globally driven if VCC is below the specified voltage. This feature is available in select ROM Z8 devices. See the device product specification for feature availability and operating range. Power-On-Reset A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function, TPOR. This POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three condi- tions:

• Power fail to Power OK status (cold start)
• Stop-Mode Recovery (if bit 5 of SMR = 1)
• WDT time-out The POR time is specified as TPOR. On Z8 devices that feature a Stop- Mode Recovery register (SMR), bit 5 selects whether the POR timer is used after Stop-Mode Recovery or by-passed. If bit D5 = 1 then the POR timer is used. If bit 5 = 0 then the POR timer is by-passed. In this case, the Stop-Mode Recovery source must be held in the recovery state for 5 TPC or 5 crystal clocks to pass the reset signal internally. This option is used

specification for timing details. will be reset to a 0 to indicate POR. Figure 27. Example of Z8 with Simple SMR and POR

18 CLK

Z8 Family of Microcontrollers User Manual Watch–Dog Timer UM001602-0904

The Z8® CPU features up to 32 lines dedicated to input and output. These lines are grouped into four 8-bit ports known as Port 0, Port 1, Port 2, and Port 3. Port 0 is nibble programmable as input, output, or address. Port 1 is byte configurable as input, output, or address/data. Port 2 is bit pro- grammable as either inputs or outputs, with or without handshake and SPI. Port 3 can be programmed to provide timing, serial and parallel input/output, or comparator input/output. All ports have push–pull CMOS outputs. In addition, the push–pull out- puts of Port 2 can be turned off for open-drain operation. Mode Registers Each port has an associated Mode Register that determines the port’s functions and allows dynamic change in port functions during program execution. Port and Mode Registers are mapped into the Standard Regis- ter File as shown in Figure 28.

Figure 28. I/O Ports and Mode Registers

and can then be read. This mechanism allows the user to initialize the out- puts prior to driving their loads (see Figure 29). Because port inputs are asynchronous to the Z8® CPU internal clock, a READ operation could occur during an input transition. In this case, the logic level might be uncertain (somewhere between a logic 1 and 0). To eliminate this meta-stable condition, the Z8® CPU latches the input data two clock periods prior to the execution of the current instruction. The input register uses these two clock periods to stabilize to a legitimate logic level before the instruction reads the data. The following sections describe the generic function of the Z8® CPU ports. Any additional features of the ports such as SPI, C/T, and Stop- Mode Recovery are covered in their own section. Port 0 This section deals with only the I/O operation of Port 0. The port's exter- nal memory interface operation is covered later in this manual. Figure 29 shows a block diagram of Port 0. This diagram also applies to Ports 1 and Note:

Figure 29. Ports 0, 1, 2 Generic Block Diagram

Port 0 can be an 8-bit, bidirectional, CMOS or TTL compatible I/O port. These eight I/O lines can be configured under software control as a nibble I/O port (P03–P00 input/output and P07–P04 input/output), or as an address port for interfacing external memory. The input buffers can be Schmitt-triggered, level shifted, or a single-trip point buffer and can be nibble programmed. Either nibble output can be globally programmed as push–pull or open-drain. Low EMI output buffers in some cases can be globally programmed by the software as an OTP program option or as a ROM mask option. In such cases, the Z8® MCU features autolatches that are hardwired to the inputs. Please refer to the specific Z8 MCU product specification for the exact input/output buffer features that are available (see Figures 30 and 31).

Figure 30. Port 0 Configuration with Open-Drain Capability,

stored in the port's output register. The port is read by specifying P0 as the source register of an instruction. When an output nibble is read, data on the external pins is returned. Figure 31. Port 0 Configuration with TTL Level Shifter

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904 under handshake control return data latched into the input register via the input strobe. The Port 0–1 Mode resistor bits D1–D0 and D7–D6 are used to configure Port 0 nibbles. The lower nibble (P00–P03) can be defined as inputs by setting bits D1 to 0 and D0 to 1, or as outputs by setting both D1 and D0 to 0. Likewise, the upper nibble (P04–P07) can be defined as inputs by setting bits D7 to 0 and D6 to 1, or as outputs by setting both D6 and D7 to 0 (see Figure 32). Handshake Operation When used as an I/0 port, Port 0 can be placed under handshake control by programming the Port 3 Mode register bit D2 to 1. In this configura- tion, handshake control lines are DAV0 (P32) and RDY0 (P35) when Port 0 is an input port, or RDY0 (P32) and DAV0 (P35) when Port 0 is an out- put port (see Figure 33). Handshake direction is determined by the configuration (input or output) assigned to the Port 0 upper nibble, P04–P07. The lower nibble must have the same I/0 configuration as the upper nibble to be under handshake con- trol. Figure 30 illustrates the Port 0 upper and lower nibbles and the asso- ciated handshake lines of Port 3. Port 1 This section deals only with the I/0 operation. The port's external memory interface operation is discussed later in this manual. Figure 29 shows a block diagram of Port 1. General I/O Mode Port 1 can be an 8-bit, bidirectional, CMOS or TTL compatible port with multiplexed address (A7–A0) and data (D7–D0) ports. These eight I/O lines can be byte programmed as inputs or outputs or can be configured under software control as an Address/Data port for interfacing to external

exact input/output buffer-type features available (Figures 32 and 33). Figure 32. Port 0 I/O Operation Figure 33. Port 0 Handshake Operation

0 P32 = Input

1 P32 = DAV0/RDY0

Figure 34. Port 1 Configuration with Open-Drain Capability,

Figure 35. Port 1 Configuration with TTL Level Shifter

The port is read by specifying P1 as the source register of an instruction. mal loading conditions, this is equivalent to reading the output register. Figure 36. Port 1 I/O Operation

is an output port. See Figures 37 and 39.

1. Each of its lines can be independently programmed as input or output

to 0 configures an output line. Figure 37. Handshake Operation

00 P33 = Input P34 = Output

01 P33 = Input P34 = DM

10 P33 = Input P34 = DM

11 P33 = DAV1/RDY1 P34 = RDY1/DAV1

Port 2 can be an 8-bit, bidirectional, CMOS- or TTL- compatible I/O port. level-shifted, or a single trip point buffer and may contain autolatches. Figure 38. Port 2 I/O Mode Configuration

Figure 39. Port 2 Configuration with Open-Drain Capability,

Figure 40. Port 2 Configuration with TTL Level Shifter

Figure 41. Port 2 Configuration with Open-Drain Capability,

0 SOI D0 Enable

1 P27 OUT

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904 Read/Write Operations Port 2 is accessed as General-Purpose Register P2 (02h). Port 2 is written by specifying P2 as an instruction’s destination register. Writing to Port 2 causes data to be stored in the output register of Port 2, and reflected externally on any bit configured as an output. Port 2 is read by specifying P2 as the source register of an instruction. When an output bit is read, data on the external pin is returned. Under normal loading conditions, this is equivalent to reading the output register. However, if a bit of Port 2 is defined as an open-drain output, the data returned is the value forced on the output pin by the external system. This may not be the same as the data in the output register. Reading input bits of Port 2 also returns data on the external pins. However, inputs under handshake control return data latched into the input register via the input strobe. Handshake Operation Port 2 can be placed under handshake control by programming bit 6 in the Port 3 Mode Register (see Figure 42). In this configuration, Port 3 lines P31 and P36 are used as the handshake control lines DAV2 and RDY2 for input handshake, or RDY2 and DAV2 for output handshake. Handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2. Only those bits with the same configuration as P27 will be under handshake control. Figure 43 illustrates the bit lines of Port 2 and the associated handshake lines of Port 3.

Figure 42. Port 2 Handshake Configuration Figure 43. Port 2 Handshaking

1 P31 = DAV2/RDY2 P36 = RDY2/DAV2

0 P31 = Input (TIN) P36 = Output (TOUT)

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904 Port 3 General Port I/O Port 3 differs structurally from Port 0, 1, and 2. Port 3 lines are fixed as four inputs (P33–P30) and four outputs (P37–P34) Port 3 does not have an input and output register for each bit. Instead, all of the input lines have one input register, and all of the output lines have an output register. Port 3 can be a CMOS- or TTL- compatible I/O port. Under software control, the lines can be configured as special control lines for handshake, com- parator inputs, SPI control, external memory status, or I/O lines for the on-board serial and timer facilities. Figure 44 is a generic block diagram of Port 3. The inputs can be Schmitt-triggered, level-shifted, or single-trip point buffered. In some cases, the Z8® MCU may have autolatches hardwired on certain Port 3 inputs and Low-EMI capabilities on the outputs. Please refer to specific product specifications for exact input/output buffer type features. Please refer to the section on counter/timers, Stop-Mode Recov- ery, serial I/O, comparators, and interrupts for more information on the relationships of Port 3 to that feature.

Figure 44. Port 3 Block Diagram

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904

Figure 45. Port 3 Configuration with Comparator, Autolatch,

Figure 46. Port 3 Configuration with Comparator

0 P34, P37 Standard Output

1 P34, P37 Comparator Output D0

Figure 47. Port 3 Configuration with SPI and Comparator

0 P34, P35 Standard Output

1 P34, P35 Comparator Output D0

Port 3 outputs cannot be written to if they are used for special functions. When writing to Port 3, data is stored in the output register. Port 3 is read by specifying P3 as the source register of an instruction. pins and in the output register. Figure 48. Port 3 Configuration with TTL Level Shifter and

in detail in their corresponding sections in this manual. less of the configuration specified in the Port 3 Mode Register. Figure 49. Port 3 Mode Register Configuration

0 P31, P32 Digital Mode 1 P31, P32 Analog Mode

0 P32 = Input P35 = Output

0 Port 2 Open-Drain

1 Port 2 Push–Pull

01 P33 = Input P34 = D M

0 P31 = Input P36 = Output

0 P30 = Input P37 = Output

1 P30 = Serial In P37 = Serial Out

0 Party ON

1 Party OFF

Table 17. Port 3 Line Functions

cates when the receiver is ready to accept another data transfer. and can be overwritten by the Z8® CPU during the handshake sequence. Table 17. Port 3 Line Functions (Continued)

To avoid losing data, the software must not overwrite the port until the corresponding interrupt request indicates that the external device has latched the data. The software can always read Port 3 output and input handshake lines, but cannot write to the output handshake line. The following is the recommended setup sequence when configuring a Port for handshake operation for the first time after a reset:

• Load P01M or P2M to configure the port for input/output
• Load P3 to set the Output Handshake bit to a logic 1
• Load P3M to select HANDSHAKE mode for the port Once a data transfer begins, the configuration of the handshake lines should not be changed until the handshake is completed. Figures 50 and 51 show detailed operation for the handshake sequence.

Figure 50. Z8 Input Handshake Port 3 output is High, indicating that the I/O device is ready to accept data. State 3. the Z8® CPU forces the Ready (RDY) output Low, signaling to the I/O device that the data has been latched. State 4. The I/O device returns the DAV line High in response to RDY going Low. into the port input register and generates an interrupt request. DAV is High. This returns the interface to its initial state.

• In the Strobed Input mode, data can be latched in the Port input regis- ter using the DAV input. The data transfer rate must allow enough time for the software to read the Port before strobing in the next char- acter. The RDY output is ignored.
• In the Strobed Output Mode, the RDY input should be tied to the DAV output.

Figure 51. Z8 Output Handshake RDY input is High indicating that the I/O device is ready to accept data. forces DAV Low if and only if RDY is High. State 4. The DAV output from the Z8® CPU is driven High in response to RDY going Low. State 5. The DAV goes High, the I/O device is free to raise RDY High thus returning the interface to its initial state.

shown in Figures 54 through 56. Port 2 is configured for input operation on all bits and is set for open-drain (see Figure 55). If push-pull outputs are required for Port 2 outputs, remember to configure them using P3M. Please note that a WDT time-out from Stop-Mode Recovery does not do a full reset. Certain registers that are not reset after Stop-Mode Recovery will not be reset. For the condition of the Ports after Stop-Mode Recovery, please refer to specific device product specifications. In some cases, an Z8® MCU fea- tures the P01M, P2M, and P3M control register set back to the default condition after reset while others do not. All special I/O functions of Port 3 are inactive, with P33–P30 set as inputs and P37–P34 set as outputs (see Figure 56). Because the types and amounts of I/O vary greatly among the Z8® CPU family devices, the user is advised to review the selected device's product specifications for the register default state after reset.

Figure 54. Port 0/1 Reset

Figure 55. Port 2 Reset

Select Z8 devices include two independent on-chip analog comparators. Figure 56. Port 3 Mode Reset

1 P32 = DAV0/RDY0 P35 = RDY0/DAV0

1 P32 = DAV2/RDY2 P36 = RDY2/DAV2

0 Parity OFF

1 Parity ON

falling, or both edge triggered interrupts (IRQ register bits 6 and bit 7). generate interrupts in digital mode. source. The analog comparator is disabled in STOP mode. enced to P33, when in analog mode. Figure 57. Port 3 Input Analog Selection

Figure 58. Port 3 Comparator Output Selection

Figure 59. Port Configuration of Comparator Inputs on P31,

Example of enabling analog comparator mode. Example of enabling analog comparator output. Figure 60. Port 3 Configuration

After enabling the Analog Comparator mode, P33 becomes a common reference input for both comparators. The P33 (Ref) is hard wired to the reference inputs to both comparators and cannot be separated. P31 and P32 are always connected to the positive inputs to the comparators. P31 is the positive input to comparator AN1 while P32 is the positive input to comparator AN2. The outputs to comparators AN1 and AN2 are AN1-out and AN2-out, respectively. The comparator output reflects the relationship between the positive input to the reference input. Example If the voltage on AN1 is higher than the voltage on Ref then AN1-out will be at a high state. If voltage on AN2 is lower than the voltage on Ref then AN2-out will be at a Low state. In this example, when the Port 3 register is read, Bits D1 = 1 and D2 = 0. If the comparator outputs are enabled to come out on P34 and P37, then P34 = 1 and P37 = 0. Please note that the previous data stored in P34 and P37 is not disturbed. Once the comparator outputs are de-selected the stored values in the P34 and P37 register bits will be reflected on these pins again. LD RP, #%0Fh ;Sets register pointer to ;working register group 0 ;and Expanded Register ;File Bank F. LD R0, #XXXX XXX1b ;Enables comparator ;outputs using PCON ;Register programming .

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904 104 Interrupts In the example from Section 5.8.3, P32 (AN2) will generate an interrupt based on the result of the comparison being low and the Interrupt Request Register (IRQ FAh) having bits D7 = 0 and D6 = 0. If IRQ D7 = 1 and D6 = 0 then both P31 and P32 would generate interrupts. Comparator Definitions VICR The usable voltage range for both positive inputs and the reference input is called the common mode voltage range (VICR). The comparator is not guaranteed to work if the inputs are outside of the VICR range. VOFFSET The absolute value of the voltage between the positive input and the refer- ence input required to make the comparator output voltage switch is the input offset voltage (VOFFSET). If AN1 is 3.000V and Ref is 3.001V when the comparator output switches states then the Voffset = 1mV. IIO For CMOS voltage comparator inputs, the input offset current (IIO) is the leakage current of the CMOS input gate. Run Mode P33 is not available as an interrupt input during analog mode. P31 and P32 are valid interrupt inputs in conjunction with P33 (Ref) when in ana- log mode. P31 can still be used as TIN when analog mode is selected. If comparator outputs are required to be outputted on the Port 3 outputs, please refer to specific products specification for priority of mixing when other special features are sharing those same Port 3 pins.

and is disconnected from the interrupt sensing circuits. gramming the Port 3 Mode Register (P3M) bit D0 = 0. which Port 0 and Port 1 can be configured to provide open-drain outputs. Figure 61. Port 2 Configuration

Register 00h. See Figure 62. (D1 = 1). The default value is 1. (D2 = 1). The default value is 1. Figure 62. Port Configuration Register (Write-Only)

0 Port 1 Open Drain 1 Port 1 Push–pull Active *

0 P34, P37 Standard Output*

1 P34, P37 Comparator Output

0 Port 0 Open Drain 1 Port 0 Push–pull Active *

0 Port 0 Low EMI 1 Port 0 Standard *

0 Port 1 Low EMI 1 Port 1 Standard *

0 Port 2 Low EMI 1 Port 2 Standard *

0 Low EMI 1 Standard *

0 Port 3 Low EMI 1 Port 3 Standard *

Some Z8® MCUs can be programmed to operate in a Low EMI Emission Mode using the Port configuration register (PCON). The PCON register allows the oscillator and all I/O ports to be programmed in the Low-EMI Mode independently. Other Z8® MCUs may offer a ROM Mask or OTP programming option to configure the Z8® MCU ports and oscillator glo- bally to a Low-EMI mode (where the XTAL frequency is set equal to the internal system clock frequency. Use of the Low EMI feature results in:

• The output pre-drivers slew rate reduced to 10 ns (typical)
• Low EMI output drivers have resistance of 200 Ω (typical)
• Low EMI Oscillator
• All output drivers are approximately 25 percent of the standard drive
• Internal SCLK ÷ TCLK = XTAL operation limited to a maximum of

4 MHz–250 ns cycle time, when Low EMI Oscillator is selected and

system clock (SCLK = XTAL, SMR Reg. Bit D1 = 1) For Z8® MCUs having the PCON register feature, the following bits con- trol the Low EMI options. Low EMI Port 0. Port 0, D3 can be configured as a Low EMI Port by resetting this bit (D3 = 0) or configured as a Standard Port by setting this bit (D3 = 1). The default value is 1. Low EMI Port 1. Port 1, D4 can be configured as a Low EMI Port by resetting this bit (D4 = 0) or configured as a Standard Port by setting this bit (D4 = 1). The default value is 1. Low EMI Port 2. Port 2, D5 can be configured as a Low EMI Port by resetting this bit (D5 = 0) or configured as a Standard Port by setting this bit (D5 = 1). The default value is 1.

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904 108 Low EMI Port 3. Port 3, D6 can be configured as a Low EMI Port by resetting this bit (D6 = 0) or configured as a Standard Port by setting this bit (D6 = 1). The default value is 1. Low EMI OSC. This D7 bit of the PCON Register controls the Low EMI oscillator. A 1 in this location configures the oscillator with standard drive, while a 0 configures the oscillator with low noise drive. The Low- EMI mode will reduce the drive of the oscillator (OSC). The default value is 1. XTAL ÷ 2 mode is not affected by this bit. The maximum external clock frequency is 4 MHz when running in the Low EMI oscillator mode. Please refer to the selected device product specification for availability of the Low EMI feature and programming options. Input Protection All CMOS ROM Z8® MCUs have I/O pins with diode input protection. There is a diode from the I/O pad to VCC and to VSS. See Figure 63.

schematic of the CMOS Z8 I/O circuit is shown in Figure 65. Figure 64. O TP Diode Input Protection

Figure 65. Simplified CMOS Z8 I/O Circuit

Z8 Family of Microcontrollers User Manual I/O Ports UM001602-0904 112 ing, the state of the autolatch will be at either supply, but which state is unpredictable. There are four operating conditions which will activate the autolatches. The first, which occurs when the input pin is physically disconnected from any source, is the most obvious. The second occurs when the input is connected to the output of a device with tri-state capability. The autolatch will also activate when the input voltage at the pin is not within 200 microvolts or so of either supply rail. In this case, the circuit will draw current, which is not significant compared to the ICC operating current of the device, but will increase ICC2 STOP mode current of the device dramatically. The fourth condition occurs when the I/O bit is configured as an output. Referring to the output section of Figure 65, there are two ways of tri-stat- ing the port pin. The first is by configuring the port as an input, which dis- ables the OE signal turning both transistors off. The second can be achieved in output mode by writing a 1 to the output port, then activating the open drain mode. Both transistors are again off, and the port bit is in a high impedance state. The autolatches then pull the input section toward VDD. Autolatch Model The autolatch’s equivalent circuit is shown in Figure 66. When the input is high, the circuit consists of a resistance Rp from VDD (the P-channel transistor in its ON state) and a much greater resistance Rh to GND. Cur- rent IAO flows from VDD to the output. When the input is low, the circuit may be modeled as a resistance Rp from GND (the N-channel transistor in the ON state) and a much greater resistance Rh to VDD. Current IAO now flows from the input to ground. The autolatch is characterized with respect to IAO, so the equivalent resistance Rp is calculated according to RP = (VDD–VIN)/IAO. The worst case equivalent resistance Rp (min) may be calculated at the worst case input voltage, VI = VIH (min).

operation, the inputs should be within 200 mV of the supply rails. Figure 66. Autolatch Equivalent Circuit

current IAO and a resistor Rp, whose value is VDD/IAO. Figure 67. Effect of Pulldown Resistors on Autolatches

UM001602-0904 Counters and Timers 115 Counters and Timers The Z8® CPU provides up to two 8-bit counter/timers, T0 and T1, each driven by its own 6-bit prescaler, PRE0 and PRE1 (see Figure 68). Both counter/timers are independent of the processor instruction sequence, that relieves software from time-critical operations such as interval timing or event counting. Some MCUs offer clock scaling using the SMR register. See the device product specification for clock available options. The fol- lowing description is typical. Each counter/timer operates in either Single-Pass or Continuous mode. At the end-of-count, counting either stops or the initial value is reloaded and counting continues. Under software control, new values are loaded imme- diately or when the end-of-count is reached. Software also controls the counting mode, how a counter/timer is started or stopped, and its use of I/ O lines. Both the counter and prescaler registers can be altered while the counter/timer is running.

and the 8-bit counter/timer form a synchronous 16-bit divide chain. Counter/timer 1 can also be driven by a external input (TIN) using P31. Figure 68. Counter/Timer Block Diagram

UM001602-0904 Counters and Timers 117 treat the counter/timers as general-purpose registers, and eliminates the requirement for special instructions. Prescalers and Counter/Timers The prescalers, PRE0 (F5h) and PRE1 (F3h), each consist of an 8-bit reg- ister and a 6-bit down-counter as shown in Figure 68. The prescaler regis- ters are write-only registers. Reading the prescalers returns the value FFh. Figures 70 and 71 show the prescaler registers. The six most significant bits (D2–D7) of PRE0 or PRE1 hold the prescal- ers count modulo, a value from 1 to 64 decimal. The prescaler registers also contain control bits that specify T0 and T1 counting modes. These bits also indicate whether the clock source for T1 is internal or external. These control bits will be discussed in detail throughout this chapter. The counter/timer registers, T0 (F4h) and T1 (F2h), each consist of an 8- bit down-counter, a write-only register that holds the initial count value, and a read-only register that holds the current count value (Figure 68). The initial value can range from 1 to 256 decimal (01h,02h,..,00h). Figure 72 illustrates the counter/timer registers.

counter/timer is associated with a Load bit and an Enable Count bit. actually functions as a software re-trigger. The counter timers remain at rest as long as the Enable Count bits are 0. Figure 73. Timer Mode Register

machine state after the operand is fetched (see Figure 74). Figure 74. Starting The Count

count, an interrupt request is generated (IRQ4 for T0, IRQ5 for T1). Figure 75. Counting Modes

UM001602-0904 Counters and Timers 123 Single-pass counting mode, while a 1 written to this bit configures the counter for Continuous mode. The Counter/Timer can be stopped at any time by setting the Enable Count bit to 0, and restarted by setting it back to 1. The Counter/Timer will continue its count value at the time it was stopped. The current value in the Counter/Timer can be read at any time without affecting the count- ing operation. The prescaler registers are write-only and cannot be read. New initial values can be written to the prescaler or the Counter/Timer registers at any time. These values will be transferred to their respective down counters on the next load operation. If the Counter/Timer mode is continuous, the next load occurs on the timer clock following an end-of- count. New initial values should be written before the load operation, because the prescalers always effectively operate in Continuous count mode. The time interval (i) until end-of-count, is given by the equation: i = t x p x v in which t = four times the internal clock period. The internal clock frequency defaults to the external clock source (XTAL, ceramic resonator, and others) divided by 2. Some Z8 microcontrollers allow this divisor to be changed via the Stop-Mode Recovery register. See the product data sheet for available clock divisor options. t is equal to eight divided-by-XTAL frequency of the external clock source for T1 (external clock mode only). p = the prescaler value (1–63) for T0 and T1. The minimum prescaler count of 1 is achieved by loading 000001xx. The maximum prescaler count of 63 is achieved by loading 111111xx. v = the Counter/Timer value (1–256) Note:

The prescaler and counter/timer are true divide-by-n counters. trolled by one of the counter/timers (T0 or T1) or the internal clock. Figure 76. Timer Mode Register (TOUT Operation)

to 0, freeing P36 to be a data output line.

• Configures T0 to drive the TOUT pin (P36)
• Sets the P36 TOUT pin to a logic 1 level
• Loads the initial PRE0 and T0 levels into their respective counters and starts the counter after the M2T2 machine state after the operand is fetched At end-of-count, the interrupt request line (IRQ4 or IRQ5), clocks a tog- gle flip-flop. The output of this flip-flop drives the TOUT line, P36. In all cases, when the selected counter/timer reaches its end-of-count, TOUT toggles to its opposite state (see Figure 78). If, for example, the counter/

Figure 77. Port 3 Mode Register (TOUT Operation)

0 P31 = Input (TIN) P36 = Output (TOUT )

tial values after each end-of-count. then directly output on P36 (see Figure 79). put by reading the port register. Figure 78. T0 and T1 Output Through TOUT

• External Clock Input
• Gated Internal Clock
• Triggered Internal Clock
• Retriggerable Internal Clock The TIN mode is restricted for use with timer 1 only. To enable the TIN mode selected (via TMR bits 4- 5), bit 1 of PRE1 must be set to 0. The counter/timer clock source must be configured for external by setting the PRE1 Register bit 2 to 1. The Timer Mode Register bit 5 and bit 4 can then be used to select the appropriate TIN operation.

Figure 79. Internal Clock Output Through TOUT

regardless of the selected TIN mode or the enabled/disabled state of T1. High-to-Low transition on TIN (see Figure 82). Figure 82. External Clock Input Mode

generated if T1 reaches its end-of-count. Figure 83. Gated Clock Input Mode

Figure 84. Triggered Clock Mode

TOUT can be used to cascade T0 and T1 as a single unit (see Figure 85). High-to-Low transition that causes T1 to count. tion and should be disabled. Figure 85. Cascaded Counter/Timers

Figure 88. Prescaler 0 Reset

Figure 89. Timer Mode Register Reset

Z8 Family of Microcontrollers User Manual Counters and Timers UM001602-0904 136

7 in the Interrupt Mask Register, with a Disable Interrupt (DI) instruction. and Interrupt Priority logic. Figure 90. Interrupt Control Registers

The Z8® family supports both vectored and polled interrupt handling. Figure 91. Interrupt Block Diagram

Figure 92 is a block diagram for interrupt sources IRQ0, IRQ1, and IRQ2. Table 18. Interrupt Types, Sources, and Vectors

six priority orders between the three groups. Bits 6 and 7 are reserved. Figure 95. Interrupt Request Timing

Figure 96. Interrupt Priority Register Table 19. Interrupt Priority

1 IRQ4 IRQ1

1 IRQ0 IRQ2

000 Reserved

001 C > A > B

010 A > B > C

011 A > C > B

100 B > C > A

101 C > B > A

110 B > A > C

111 Reserved

1 IRQ3 IRQ5

Table 20. Interrupt Group Priority Table 19. Interrupt Priority (Continued)

cution of an Interrupt Return (IRET) instruction.

• Immediately after a hardware reset
• Immediately after executing an interrupt service routine and before IMR bit 7 has been set by any instruction

Figure 97. Interrupt Mask Register

The RAM Protect option is selected at ROM mask submission time or at EPROM program time. If not selected or not an available option, this bit is reserved and must be 0. Interrupt Request Register Initialization The Interrupt Request Register (IRQ), shown in Figure 98, is a read/write register that stores the interrupt requests for both vectored and polled interrupts. When an interrupt is made on any of the six, the corresponding bit position in the register is set to 1. Bit 0 to bit 5 are assigned to interrupt requests IRQ0 to IRQ5, respectively. Whenever Power-On Reset (POR) is executed, the IRQ resister is reset to 00h and disabled. Before the IRQ register will accept requests, it must be enabled by executing an ENABLE INTERRUPTS (EI) instruction. Setting the Global Interrupt Enable bit in the Interrupt Mask Register (IMR, bit 7) will not enable the IRQ. Execution of the EI instruction is required (see Figure 99). For polled processing, IRQ must still be initialized by an EI instruction. To properly initialize the IRQ register, the following code is provided. IRQ is always cleared to 00h and is read only until the first EI instruction, which enables the IRQ to be read/write. CLR IMR // Make sure vectored interrupts are disabled. EI // Enable IRQ register, otherwise read only. // Not required if interrupts were previously enabled. DI // Disable interrupt heading. Note:

bits, the configuration options are as show in Table 21. Figure 98. Interrupt Request Register

(assumes IPR and IMR have been previously initialized). Table 21. IRQ Register Configuration* *Note: F = Falling Edge; R = Rising Edge. Figure 99. IRQ Reset Functional Logic Diagram

Z8 Family of Microcontrollers User Manual Interrupts UM001602-0904 150 IRQ Software Interrupt Generation IRQ can be used to generate software interrupts by specifying IRQ as the destination of any instruction referencing the Z8® Standard Register File. These Software Interrupts (SWI) are controlled in the same manner as hardware generated requests (in other words, the IPR and the IMR control the priority and enabling of each SWI level). To generate a SWI, the appropriate request bit in the IRQ is set as follows: ORIRQ, #NUMBER where the immediate data, NUMBER, has a 1 in the bit position corre- sponding to the appropriate level of the SWI. For example, if an SWI is required on IRQ5, NUMBER would have a 1 in bit 5: OR IRQ, #00100000b With this instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and there are no higher priority pending requests, control is transferred to the service routine pointed to by the IRQ5 vector. Vectored Processing Each Z8 interrupt level has its own vector. When an interrupt occurs, con- trol passes to the service routine pointed to by the interrupt’s vector loca- tion in program memory. The sequence of events for vectored interrupts is as follows:

• PUSH PC Low byte on stack
• PUSH PC High byte on stack
• PUSH FLAGS on stack
• Fetch High byte of vector
• Fetch Low byte of vector

• Branch to service routine specified by vector Figures 100 and 101 show the vectored interrupt operation.

Figure 100. Effects of an Interrupt on the Stack

Figure 101. Interrupt Vectoring

gram + 2TPC (internal synchronization time). Figure 102. Z8 Interrupt Acknowledge Timing

Z8 Family of Microcontrollers User Manual Interrupts UM001602-0904 154 Nesting of Vectored Interrupts Nesting of vectored interrupts allows higher priority requests to interrupt a lower priority request. To initiate vectored interrupt nesting, do the fol- lowing during the interrupt service routine:

• Push the old IMR on the stack
• Load IMR with a new mask to disable lower priority interrupts
• Execute EI instruction
• Proceed with interrupt processing
• After processing is complete, execute DI instruction
• Restore the IMR to its original value by returning the previous mask from the stack
• Execute IRET Depending on the application, some simplification of the above procedure may be possible. Polled Processing Polled interrupt processing is supported by masking off the IRQ to be polled. This is accomplished by clearing the corresponding bits in the IMR. To enable any interrupt, first the interrupt mechanism must be engaged with an EI instruction. If only polled interrupts are to be serviced, exe- cute: EI ;Enable interrupt mechanism DI ;Disable vectored interrupts. To initiate polled processing, check the bits of interest in the IRQ using the Test Under Mask (TM) instruction. If the bit is set, call or branch to

the service routine. The service routine services the request, resets its Request Bit in the IRQ, and branches or returns back to the main pro- gram. An example of a polling routine is as follows: In this example, if IRQ2 is being polled, MASKA will be 00000100b and MASKB will be 11111011b. Reset Conditions Upon reset, all bits in IPR are undefined. In IMR, bit 7 is 0 and bits 0–6 are undefined. The IRQ register is reset and held in that state until an enable interrupt (EI) instruction is executed. TM IRQ, #MASKA ;Test for request JR Z, NEXT ;If no request go to NEXT CALL SERVICE ;If request is there, then ;service it NEXT: SERVICE: ;Process Request AND IRQ, #MASKB ;Clear Request Bit RET ;Return to next

Z8 Family of Microcontrollers User Manual Interrupts UM001602-0904 156

UM001602-0904 Power-Down Modes 157 Power-Down Modes In addition to the standard RUN mode, the Z8® CPU supports two Power- Down modes to minimize device current consumption. The two modes supported are HALT and STOP. Halt Mode Operation HALT mode suspends instruction execution and turns off the internal CPU clock. The on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the Counter/Timer(s) and inter- rupt logic. To enter HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the applica- tion program must execute a NOP instruction (opcode = FFh) immedi- ately before the HALT instruction (opcode 7Fh), that is: FF NOP ;clear the instruction pipeline 7F HALT ;enter HALT mode HALT mode is exited by interrupts, either externally or internally gener- ated. Upon completion of the interrupt service routine, the user program continues from the instruction after HALT. HALT mode may also be exited via a POR/RESET activation or a Watch– Dog Timer (WDT) time-out. (See the product data sheet for WDT avail- ability). In this case, program execution will restart at the reset restart address 000Ch. To further reduce power consumption in HALT mode, some Z8 family devices allow dynamic internal clock scaling. Clock scaling may be accomplished on the fly by reprogramming bit 0 and/or bit1 of the Stop- Mode Recovery register (SMR). See Figure 103 on page 160.

Z8 Family of Microcontrollers User Manual Power-Down Modes UM001602-0904 158 Internal clock scaling directly affects Counter/Timer operation—adjust- ment of the prescaler and downcounter values may be required. To deter- mine the actual HALT mode current (ICC1) value for the various optional modes available, see the related Z8 device’s product specification. Stop Mode Operation STOP mode provides the lowest possible device standby current. This instruction turns off the on-chip oscillator and internal system clock. To enter STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the applica- tion program must execute a NOP instruction (opcode = FFh) immedi- ately before the STOP instruction (opcode = 6Fh), that is, FF NOP ;clear the instruction pipeline 6F STOP ;enter STOP mode STOP mode is exited by any one of the following resets: Power-On Reset activation, WDT time out (if available), or a Stop-Mode Recovery source. Upon reset generation, the processor will always restart the application program at address 000Ch. POR/RESET activation is present on all Z8 devices and is implemented as a reset pin and/or an on-chip power on reset circuit. Some Z8 devices allow for the on-chip WDT to run in STOP mode. If so activated, the WDT time-out will generate a reset some fixed time period after entering STOP mode. Stop-Mode Recovery by the WDT will increase STOP mode standby cur- rent (ICC2). This is due to the WDT clock and divider circuitry that is now enabled and running to support this recovery mode. See the product data sheet for actual ICC2 values. Note:

UM001602-0904 Power-Down Modes 159 All Z8 devices provide some form of dedicated Stop-Mode Recovery (SMR) circuitry. Two SMR methods are implemented—a single fixed input pin or a flexible, programmable set of inputs. The selected Z8 device product specification should be reviewed to determine the SMR options available for use. For devices that support SPI, the slave mode compare feature also serves as a SMR source. In the simple case, a low level applied to input pin P27 will trigger a SMR. To use this mode, pin P27 (I/O Port 2, bit 7) must be configured as an input before STOP mode is entered. The low level on P27 must meet a minimum pulse width TWSM. (See the product data sheet) to trigger the device reset mode). Some Z8 devices provide multiple SMR input sources. The appropriate SMR source is selected via the SMR Register. Use of specialized SMR modes (P2.7 input or SMR register based) or the WDT time-out (only when in STOP mode) provide a unique reset opera- tion. Some control registers are initialized differently for a SMR/WDT triggered POR than a standard reset operation. See the product specifica- tion (register file map) for exact details. To determine the actual STOP mode current (ICC2) value for the optional SMR modes available, see the selected Z8 device’s product data sheet. STOP mode current (ICC2) will be minimized when:

• VCC is at the low end of the devices operating range
• WDT is off in STOP mode
• Output current sourcing is minimized
• All inputs (digital and analog) are at the low or high rail voltages

whether a low level or a high level is required from the recovery source. the Expanded Register File at address 0Bh. Figure 103. Stop-Mode Recovery Register (Write-Only Except Bit D7,

000 POR Only and/or External Reset

001 P30

010 P31

011 P32

100 P33

101 P27

110 P2 NOR 0–3

111 P2 NOR 0–7

1 ON*

0 POR*

1 Stop Recovery

0 Low*

1 High

• Default setting after RESET.

counter/timers and interrupt logic). Table 22. Stop-Mode Recovery Source 0 0 0 POR and/or external reset recovery. 0 1 0 P31 transition (not in Analog Mode). 0 1 1 P32 transition (not in Analog Mode). 1 0 0 P33 transition (not in Analog Mode).

source is kept active for at least 5 TpC. 1 1 0 Logical NOR of P20 through P23. 1 1 1 Logical NOR of P20 through P27.

operation must be selected prior to entering STOP mode. Figure 104. Stop-Mode Recovery Source

Z8 Family of Microcontrollers User Manual Power-Down Modes UM001602-0904 164

Figure 105. UAR T Block Diagram

Parity Bit). Odd parity generation and detection is supported. eliminating the requirement for special instructions. of-count signal of T0 no longer generates Interrupt Request IRQ4. each for the receiver and the transmitter) that clock the data stream. Table 23. UART Register Map

times the bit rate in order to synchronize on the incoming data. should therefore be set to CONTINUOUS mode (D0 = 1). Figure 106. Port 3 Mode Register and Bit-Rate Generation Figure 107. Bit Rate Divide Chain

0 P30 Input and P37 = Output

1 P30 Serial In and P37 = Serial Out

tinuous Mode, the value of PRE0 becomes 9Dh (see Figure 108). not intended to be exhaustive. Table 24. Bit Rates

Z8 Family of Microcontrollers User Manual Serial Input/Output UM001602-0904 170 UART Receiver Operation The receiver consists of a receiver buffer (SIO Register [F0h]), a serial-in, parallel-out shift register, parity checking, and data synchronizing logic. The receiver block diagram is shown as part of Figure 105 on page 165. Receiver Shift Register After a hardware reset or after a character has been received, the Receiver Shift Register is initialized to all 1s and the shift clock is stopped. Serial data, input through Port 3 bit 0, is synchronized to the internal clock by two D-type flip-flops before being input to the Shift Register and the start bit detection circuitry. The start bit detection circuitry monitors the incoming data stream, look- ing for a start bit (a High-to-Low input transition). When a start bit is detected, the shift clock logic is enabled. The T0 input is divided-by-16 and, when the count equals eight, the divider outputs a shift clock. This clock shifts the start bit into the Receiver Shift Register at the center of the bit time. Before the shift actually occurs, the input is rechecked to ensure that the start bit is valid. If the detected start bit is false, the receiver is reset and the process of looking for a start bit is repeated. If the start bit is valid, the data is shifted into the Shift Register every sixteen counts until a full character is assembled (see Figure 110).

bit in the Interrupt Request Register must be reset by software. Figure 110. Receiver Timing

testing P30 results in a 0 being read. bit D7 is set to 0. Figure 111 shows these data formats. ware must calculate the received data’s parity. Figure 111. Receiver Data Formats

gram is shown as part of Figure 105 on page 165. to accept another character. Figure 112. Port 3 Mode Register Parity

Z8 Family of Microcontrollers User Manual Serial Input/Output UM001602-0904 174 Overwrites The user is not protected from overwriting the transmitter, so it is up to the software to respond to IRQ4 appropriately. If polling is used, the IRQ4 bit in the Interrupt Request Register must be reset. Parity The data format supported by the transmitter has a start bit, eight data bits, and at least two stop bits. If parity is on, bit 7 of the data transmitted will be replaced by an odd parity bit. Figure 113 shows the transmitter data formats. Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If even parity is required, PARITY mode should be disabled (P3M bit 7 reset to 0), and software must modify the data to include even parity. Because the transmitter can be overwritten, the user is able to generate a break signal. This is done by writing null characters to the transmitter buffer (SIO Register [F0h]) at a rate that does not allow the stop bits to be output. Each time the SIO Register is loaded, the divide-by-16 counter is resynchronized and a new start bit is output followed by data.

of the Expanded Register File at address 02. Figure 115. P3M Register Reset

0 Port 2 Pull-Ups Open-Drain

1 Port 2 Pull-Ups Active

0 Parity ON

1 Parity OFF

enables the compare feature of the SPI, with the default being disabled. nals that a receive character is available in the RxBUF Register. Table 25. SPI Pin Configuration

Figure 116. SPI Control Register

00 TCLK/2

01 TCLK/4

10 TCLK/8

11 TCLK/16

0 SPI DO Port Enable

1 Do Port to I/O

0 Disable *

1 Enable

0 Enable

1 Disable *

0 Trans/Fall

1 Trans/Rise

0 Reset

1 Overrun

0 TCLK

1 Timer 0 Output

0 Slave

1 Master

Timer0 output for the SPI clock, and a 0 uses TCLK for clocking the SPI. 1 puts the SPI into Master mode and a 0 puts the SPI into Slave mode. Figure 117. In slave mode, data transfer starts when the slave select (SS) through the DI pin, which has the same address as the RxBUF Register. in all system modes: STOP, HALT, and RUN.

Z8 Family of Microcontrollers User Manual Serial Input/Output UM001602-0904 180 and interrupt is generated. Before data is transferred via the D0 pin, the SPI Enable bit in the SCON Register must be enabled. SPI Compare When the SPI Compare Enable bit, D3 of the SCON Register is set to 1, the SPI Compare feature is enabled. The compare feature is only valid for slave mode. A compare transaction begins when the (SS) line goes active. Data is received as if it were a normal transaction, but there is no data transmitted to avoid bus contention with other slave devices. When the compare byte is received, IRQ3 is not generated. Instead, the data is com- pared with the contents of the SCOMP Register. If the data does not match, DO remains inactive and the slave ignores all data until the (SS) signal is reset. If the data received matches the data in the SCOMP regis- ter, then a SMR signal is generated. DO is activated if it is not tri-stated by D2 in the SCON Register, and data is received the same as any other SPI slave transaction. Slaves’ not comparing remain in their current mode, whereas slaves’ comparing wake from a STOP mode by means of an SMR SPI Clock The SPI clock maybe driven by three sources: Timer0, a division of the internal system clock, or the external master when in slave mode. Bit D6 of the SCON Register controls what source drives the SPI clock. A 0 in bit D6 of the SCON Register determines the division of the internal system clock if this is used as the SPI clock source. Divide by 2, 4, 8, or 16 is chosen as the scaler.

Figure 117. SPI System Configuration

used to log any RxCharOverrun (see Figures 118 and 119). Figure 118. SPI Timing

Figure 119. SPI Logic

Figure 120. SPI Data In/Out Configuration

Figure 121. SPI Clock/SPI Slave Select Output Configuration

Z8 Family of Microcontrollers User Manual Serial Input/Output UM001602-0904 186

specifications for availability of these features. Write Signal. Figure 122 shows the Z8® CPU external interface pins. Figure 122. Z8® CPU External Interface Pins

Z8 Family of Microcontrollers User Manual External Interface UM001602-0904 188 Pin Descriptions The following sections briefly describe the pins associated with the Z8® CPU external memory interface. Address Strobe (output, active Low). Address Strobe (AS) is pulsed Low once at the beginning of each machine cycle. The rising edge of AS indicates the address, Read/Write (R/W), and data memory (DM) signals are valid for program or data memory transfers. In some cases, the Z8® CPU address strobe is pulsed low regardless of accessing external or internal memory. Please refer to specific product specifications for AS operation. Data Strobe (Output, Active Low). Data Strobe (DS) provides the tim- ing for data movement to or from the Address/Data bus for each external memory transfer. During a Write Cycle, data out is valid at the leading edge of the DS. During a Read Cycle, data in must be valid prior to the trailing edge of the DS. Read/Write (Output). Read/Write (R/W) determines the direction of data transfer for memory transactions. R/W is Low when writing to pro- gram or data memory, and High for all other transactions. Data Memory (Output). Data memory (DM) provides a signal to sepa- rate external program memory from external data memory. It is a pro- grammable function on pin P34. Data memory is active low for external data memory accesses and high for external program memory accesses. High Address Lines A15–A8. A15–A8 provide the High Address lines for the memory interface. The Port 0–1 mode registers must have bits D7 and D1 set equal to 1 to configure Port 0 as A15–A8. Outputs can be CMOS- or TTL-compatible. Please refer to product specifications for actual type. See Figure 123. Address/Data Lines AD7–AD0. AD7–AD0 is a multiplexed Address/ Data memory interface. The lower eight Address lines (A7–A0) are multi- plexed with Data lines (D7–D0). Port 0–1 mode registers must have bits

UM001602-0904 External Interface 189 D4 set equal to 1 and D3 set equal to 0 to configure Port 1 as AD7–AD0. Inputs and outputs are TTL-compatible. See Figure 123. Reset. RESET (input, active Low) initializes the Z8® CPU. When RESET is deactivated, program execution begins from program location 000Ch. If held Low, RESET acts as a register file protect during power- down and power-up sequences. To avoid asynchronous and noisy reset problems, the Z8® CPU is equipped with a reset filter of four external clocks (4TPC). If the external RESET signal is less than 4TPC in duration, no reset will occur. On the fifth clock after the RESET is detected, an internal reset signal is latched and held for an internal register count of 18 or more external clocks, or for the duration of the external RESET, which- ever is longer. Please refer to specific product specifications for length of reset delay time. Crystal1, Crystal2 (Oscillator Input and Output). These pins connect a parallel-resonant crystal, ceramic resonator, LC, RC network, or exter- nal single-phase clock to the on-chip oscillator input. Please refer to the device product specifications for information on availability of RC oscil- lator features. External Addressing Configuration The minimum bus configuration uses Port 1 as a multiplexed address/data port (AD7–AD0), allowing access to 256 bytes of external memory. In this configuration, the eight low-order bits (A0–A7) are multiplexed with the data (D7–D0). Port 0 can be programmed to provide either four additional address lines (A11–A8), which increases the addressable memory to 4 KB, or eight additional address lines (A15–A8), which increases the addressable exter- nal memory up to 64 KB. It is required to add a NOP after configuring Port 0/Port 1 for external addressing before jumping to external memory execution.

0, the stack is in external data memory (see Figure 124). indeterminate program flow. After a RESET, the internal stack is selected. Figure 123. External Address Configuration

FEh to be displayed on Port 0. and bit 3 in the Port 3 Mode Register (F7h) to 10 or 01 (see Figure 125). Figure 124. Z8 Stack Selection

Figure 125. Port 3 Data Memory Operation

Figure 126. External Instruction Fetch or Memory Read Cycle before the execution cycle of the current instruction.

Figure 127. External Memory Write Cycle

UM001602-0904 External Interface 195 outputs (A15–A8) remain stable throughout the machine cycle, regardless of the addressing mode. Data Strobe The Z8® CPU uses DS to time the actual data transfer. For Write opera- tions (R/W = Low), a Low on DS indicates that valid data is on the AD7– AD0 lines. For Read operations (R/W = High), the bus is placed in a high- impedance state before driving DS Low, so the addressed device can put its data on the bus. The Z8® CPU samples this data prior to raising DS High. Extended Bus Timing Some products can accommodate slow memory access time by automati- cally inserting an additional software controlled state time (Tx). This stretches the DS timing by two clock periods. Figures 128 and 129 illus- trate extended external memory Read and Write cycles.

Figure 128. Extended External Instruction Fetch or Memory Read Cycle before the execution of the current instruction.

to 1 (see Figure 130). After a RESET, this bit is set to 0. Figure 129. Extended External Memory Write Cycle

memory as part of their execution, the pipe must be flushed. Figures 131 and 132 assume the XTAL ÷ 2 clock mode is selected. Figure 130. Extended Bus Timing

Figure 131. Instruction Cycle Timing (1-Byte Instructions)

Figure 132. Instruction Cycle Timing (2- and 3-Byte Instructions) the execution cycle of the current instruction.

• Load
• Bit Manipulation
• Arithmetic
• Block Transfer
• Logical
• Rotate and Shift
• Program Control
• CPU Control The following summary shows the instructions belonging to each group and the number of operands required for each. The source operand is src, the destination operand is dst, and a condition code is cc.

Table 26. Load Instructions

Table 27. Arithmetic Instructions Table 28. Logical Instructions Table 29. Program Control Instructions

Table 30. Bit Manipulation Instructions Table 31. Block Transfer Instructions Table 29. Program Control Instructions (Continued)

Table 32. Rotate and Shift Instructions Table 33. CPU Control Instructions

Z8 Family of Microcontrollers User Manual Instruction Set UM001602-0904 206 Carry Flag The Carry Flag (C) is set to 1 whenever the result of an arithmetic opera- tion generates a carry or a borrow the high order bit 7. Otherwise, the Carry Flag is cleared to 0. Following Rotate and Shift instructions, the Carry Flag contains the last value shifted out of the specified register. An instruction can set, reset, or complement the Carry Flag. IRET may change the value of the Carry Flag when the Flag Register, saved in the Stack, is restored. Zero Flag For arithmetic and logical operations, the Zero Flag (Z) is set to 1 if the result is zero. Otherwise, the Zero Flag is cleared to 0. If the result of testing bits in a register is 00h, the Zero Flag is set to 1. Otherwise the Zero Flag is cleared to 0. If the result of a Rotate or Shift operation is 00h, the Zero Flag is set to 1. Otherwise, the Zero Flag is cleared to 0. IRET changes the value of the Zero Flag when the Flag Register saved in the Stack is restored. The WDT Instruction sets the Zero Flag to a 1. Sign Flag The Sign Flag (S) stores the value of the most significant bit of a result following an arithmetic, logical, Rotate, or Shift operation. When performing arithmetic operations on signed numbers, binary two’s- complement notation is used to represent and process information. A pos- itive number is identified by a 0 in the most significant bit position (bit 7); therefore, the Sign Flag is also 0. A negative number is identified by a 1 in the most significant bit position (bit 7); therefore, the Sign Flag is also 1.

UM001602-0904 Instruction Set 207 IRET changes the value of the Sign Flag when the Flag Register saved in the Stack is restored. Overflow Flag For signed arithmetic, Rotate, and Shift operations, the Overflow Flag (V) is set to 1 when the result is greater than the maximum possible number (> 127) or less than the minimum possible number (< –128) that can be represented in two’s-complement form. The Overflow Flag is set to 0 if no overflow occurs. Following logical operations the Overflow Flag is set to 0. IRET changes the value of the Overflow Flag when the Flag Register saved in the Stack is restored. Decimal Adjust Flag The Decimal Adjust Flag (D) is used for BCD arithmetic. Because the algorithm for correcting BCD operations is different for addition and sub- traction, this flag specifies what type of instruction was last executed so that the subsequent Decimal Adjust (DA) operation can function properly. Normally, the Decimal Adjust Flag cannot be used as a test condition. After a subtraction, the Decimal Adjust Flag is set to 1. Following an addition it is cleared to 0. IRET changes the value of the Decimal Adjust Flag when the Flag Regis- ter saved in the Stack is restored. Half Carry Flag The Half Carry Flag (H) is set to 1 whenever an addition generates a carry bit 3 (Overflow) or a subtraction generates a borrow bit 3. The Half Carry Flag is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. As in the case of the Decimal Adjust Flag, the user does not nor- mally access this flag.

saved in the Stack is restored. 7 of the conditional instructions.

1. Notation for the flags and how they are affected are as follows:

Table 34. Z8 Flag Definitions Table 35. Flag Settings Definitions

0 Cleared to 0

1 Set to 1

Table 36. Condition Codes

1111 F NC No Carry C = 0

1110 E NZ Non-Zero Z = 0

1101 D PL Plus S = 0

1100 C NOV No Overflow V = 0

1110 E NE Not Equal Z = 0

1010 A GT Greater Than (Z OR (S XOR V)) = 0

1111 F UGE Unsigned Greater Than

1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0) = 1

ter, operands and status flags are represented by a notational shorthand. Table 37. Notational Shorthand

Additional symbols used are listed in Table 38. Table 38. Additional Symbols

stored in the destination location. refers to bit 7 of the destination operand. coding or who intend to implement their own assembler.

range available. The register file size varies by device type. Table 39. Summary of Z8 Instruction Set

Table 40. Summary of Z8® Address Modes

Figure 134. Op Code Map Note: Blank areas are reserved.

Table 41. Process Manipulation Functions

Table 41. Process Manipulation Functions (Continued)

UM001602-0904 Instruction Description 225 Add ADD dst, src Instruction Format Operation dst ← dst + src The source operand is added to the destination operand. Two’s comple- ment addition is performed. The sum is stored in the destination operand. The contents of the source operand are not affected. Cycles OPC (Hex) Address Mode dst src OPC dst src 6 02 r r 6 03 r lr OPC src dst 10 04 R R 10 05 R IR OPC dst src 10 06 R IM 10 07 IR IM Flags Description C Set if there is a carry from the most significant bit of the result; cleared otherwise. Z Set if the result is zero; cleared otherwise. S Set if the result is negative; cleared otherwise. V Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D Always cleared. H Set if there is a carry from the most significant bit of the low order four bits of the result; cleared otherwise.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 226 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R3 contains 16h and Working Register R11 contains 20h, the statement: ADD R3, R11 Op Code: 02 3B leaves the value 36h in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared. Example If Working Register R16 contains 16h, Working Register R10 contains 20h, and Register 20h contains 11h, the statement: ADD R16, @R10 Op Code: 03 FA leaves the value 27h in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared. Example If Register 34h contains 2Eh and Register 12h contains 1Bh, the state- ment: ADD 34h, 12h Op Code: 04 12 34 leaves the value 49h in Register 34h. The H Flag is set, and the C, Z, S, V, and D flags are cleared. E src or E dst Note:

UM001602-0904 Instruction Description 227 Example If Register 4Bh contains 82h, Working Register R3 contains 10h, and Register 10h contains 01h, the statement: ADD 3Eh, @R3 Op Code: 05 E3 4B leaves the value 83h in Register 4Bh. The S Flag is set, and the C, Z, V, D, and H flags are cleared. Example If Register 6Ch contains 2Ah, the statement: ADD 6Ch, #03h Op Code: 06 6C 03 leaves the value 2Dh in Register 6Ch. The C, Z, S, V, D, and H Flags are all cleared. Example If Register D4h contains 5Fh and Register 5Fh contains 4Ch, the state- ment: ADD @D4h, #02h Op Code: 07 D4 02 leaves the value 4Eh in Register 5Fh. The C, Z, S, V, D, and H Flags are all cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 228 Add With Carry Syntax ADC dst, src Instruction Format Operation dst ← dst + src + C The source operand, along with the setting of the Carry (C) Flag, is added to the destination operand. Two’s complement addition is performed. The sum is stored in the destination operand. The contents of the source oper- and are not affected. In multiple precision arithmetic, this instruction per- mits the carry from the addition of low order operands to be carried into the addition of high order operands. Cycles OPC (Hex) Address Mode dst src OPC dst src 6 02 r r 6 03 r lr OPC src dst 10 04 R R 10 05 R IR OPC dst src 10 06 R IM 10 07 IR IM

UM001602-0904 Instruction Description 229 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R3 contains 16h, the C Flag is set to 1, and Working Register R11 contains 20h, the statement: ADC R3, R11 Op Code: 12 3B leaves the value 37h in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared. Example If Working Register R16 contains 16h, the C Flag is not set, Working Register R10 contains 20h, and Register 20h contains 11h, the statement: ADC R16, @R10 Op Code: 13 FA Flag Description C Set if there is a carry from the most significant bit of the result; cleared otherwise. Z Set if the result is zero; cleared otherwise. S Set if the result is negative; cleared otherwise. V Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D Always cleared. H Set if there is a carry from the most significant bit of the low order four bits of the result; cleared otherwise. E src or E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 230 leaves the value 27h in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared. Example If Register 34h contains 2Eh, the C Flag is set, and Register 12h contains 1Bh, the statement: ADC 34h, 12h Op Code: 14 12 34 leaves the value 4Ah in Register 34h. The H Flag is set, and the C, Z, S, V, and D flags are cleared. Example If Register 4Bh contains 82h, the C Flag is set, Working Register R3 con- tains 10h, and Register 10h contains 01h, the statement: ADC 4Bh, @R3 Op Code: 15 E3 4B leaves the value 84h in Register 4Bh. The S Flag is set, and the C, Z, V, D, and H flags are cleared. Example If Register 6Ch contains 2Ah, and the C Flag is not set, the statement: ADC 6Ch, #03h Op Code: 16 6C 03 leaves the value 2Dh in Register 6Ch. The C, Z, S, V, D, and H Flags are all cleared. Example If Register D4h contains 5Fh, Register 5Fh contains 4Ch, and the C Flag is set, the statement: ADC @D4h, #02h Op Code: 17 D4 02

UM001602-0904 Instruction Description 231 leaves the value 4Fh in Register 5Fh. The C, Z, S, V, D, and H Flags are all cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 232 Call Procedure CALL dst Instruction Format Operation SP ← SP–2 @SP ← PC PC ← dst The Stack pointer is decremented by two, the current contents of the Pro- gram Counter (PC) (address of the first instruction following the CALL instruction) are pushed onto the top of the Stack, and the specified desti- nation address is then loaded into the PC. The PC now points to the first instruction of the procedure. At the end of the procedure a RET (return) instruction can be used to return to the original program flow. RET will pop the top of the Stack and replace the original value into the PC. Cycles OPC (Hex) Address Mode dst OPC dst 20 D6 DA OPC dst 20 D4 IRR Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

UM001602-0904 Instruction Description 233 Address mode IRR can be used to specify a 4-bit Working Register Pair. In this format, the destination Working Register Pair operand is specified by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register Pair RR12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the contents of the PC are 1A47h and the contents of the SP (Registers FEh and FFh) are 3002h, the statement: CALL 3521h Op Code: D6 35 21 causes the SP to be decremented to 3000h, 1A4Ah (the address following the CALL instruction) to be stored in external data memory 3000 and 3001h, and the PC to be loaded with 3521h. The PC now points to the address of the first statement in the procedure to be executed. Example If the contents of the PC are 1A47h, the contents of the SP (Register FFh) are 72h, the contents of Register A4h are 34h, and the contents of Regis- ter Pair 34h are 3521h, the statement: CALL @A4h Op Code: D4 A4 causes the SP to be decremented to 70h, 1A4Ah (the address following the CALL instruction) to be stored in R70h and 71h, and the PC to be loaded with 3521h. The PC now points to the address of the first state- ment in the procedure to be executed. E src or E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 234 Complement Carry Flag CCF Instruction Format Operation C ← NOT C The C Flag is complemented. If C = 1, then it is changed to C = 0; or, if C = 0, then it is changed to C = 1. Example If the C Flag contains a 0, the statement: CCF Op Code: EF will change the C Flag from C = 0 to C = 1. Cycles OPC (Hex) OPC 6 EF Flag Description C Complemented Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

UM001602-0904 Instruction Description 235 Clear CLR dst Instruction Format Operation dst ← 0 The destination operand is cleared to 00h. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R6 contains AFh, the statement: CLR R6 Op Code: B0 E6 Cycles OPC (Hex) Address dst OPC dst 6 80 R 6 81 IR Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 236 will leave the value 00h in Working Register R6. If Register A5h contains the value 23h, and Register 23h contains the value FCh, the statement: CLR @A5h Op Code: B1 A5 will leave the value 00h in Register 23h.

UM001602-0904 Instruction Description 237 Complement COM dst Instruction Format Operation dst ← NOT dst The contents of the destination operand are complemented (one’s comple- ment). All 1 bits are changed to 0, and all 0 bits are changed to 1. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Register 08h contains 24h (00100100b), the statement: Cycles OPC (Hex) Address Mode dst OPC dst 6 60 R 6 61 IR Flag Description C Unaffected Z Set if the result is zero; cleared otherwise. S Set if result bit 7 is set; cleared otherwise. V Always reset to 0. D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 238 COM 08h Op Code: 60 08 leaves the value DBh (11011011) in Register 08h. The S Flag is set, and the Z and V flags are cleared. Example If Register 08h contains 24h, and Register 24h contains FFh (11111111b), the statement: COM @08h Op Code: 61 08 leaves the value 00h (00000000b) in Register 24h. The Z Flag is set, and the V and S flags are cleared.

UM001602-0904 Instruction Description 239 Compare CP dst, src Instruction Format Operation dst–src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, Cycles OPC (Hex) Address Mode dst src OPC dst src 6 A2 r r

6 A3 r lr

10 A5 R IR

10 A7 IR IM

C Cleared if there is a carry from the most significant bit of the result. Set otherwise indicating a borrow. Z Set if the result is zero; cleared otherwise. S Set if result bit 7 is set (negative); cleared otherwise. V Set if arithmetic overflow occurs; cleared otherwise. D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 240 if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R3 contains 16h and Working Register R11 contains 20h, the statement: CP R3, R11 Op Code: A2 3B sets the C and S Flags, and the Z and V flags are cleared. Example If Working Register R15 contains 16h, Working Register R10 contains 20h, and Register 20h contains 11h, the statement: CP R16, @R10 Op Code: A3 FA clears the C, Z, S, and V Flags. Example If Register 34h contains 2Eh and Register 12h contains 1Bh, the state- ment: CP 34h,12h Op Code: A4 12 34 clears the C, Z, S, and V Flags. Example If Register 4Bh contains 82h, Working Register R3 contains 10h, and Register 10h contains 01h, the statement: CP 4Bh, @R3 Op Code: A5 E3 4B E src or E dst

UM001602-0904 Instruction Description 241 sets the S Flag, and clears the C, Z, and V Flags. Example If Register 6Ch contains 2Ah, the statement: CP 6Ch, #2Ah Op Code: A6 6C 2A sets the Z Flag, and the C, S, and V Flags are all cleared. Example If Register D4h contains FCh, and Register FCh contains 8Fh, the state- ment: CP @D4h, 7Fh Op Code: A7 D4 FF sets the V Flag, and the C, Z, and S Flags are all cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 242 Decimal Adjust DA dst Instruction Format Operation dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits follow- ing a binary addition or subtraction operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the following table indicates the operation performed. Cycles OPC (Hex) Address Mode dst OPC dst 8 40 R 8 41 IR Instruction Carry Before DA Bits 7–4 Value (Hex) H Flag Before DA Bits 3–0 Value (Hex) Number Added To Byte Carry After DA 0 0–9 0 0–9 00 0 0 0–8 0 A–F 06 0 0 0–9 1 0–3 06 0 ADD 0 A–F 0 0–9 60 1 ADC 0 9–F 0 A–F 66 1

0 A–F 1 0–3 66 1

1 0–2 0 0–9 60 1 1 0–2 0 A–F 66 1 1 0–3 1 0–3 66 1 0 0–9 0 0–9 00 0 SUB 0 0–8 1 6–F FA 0

UM001602-0904 Instruction Description 243 If the destination operand is not the result of a valid addition or subtrac- tion of BCD digits, the operation is undefined. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic. 0001 0101 = 15h + 0010 0111 = 27h 0011 1100 = 3Ch SBC 1 7–F 0 0–9 A0 1 1 6–F 1 6–F 9A 1 Flag Description C Set if there is a carry from the most significant bit; cleared otherwise (see table above). Z Set if the result is zero; cleared otherwise. S Set if result bit 7 is set (negative); cleared otherwise. D Unaffected H Unaffected E dst Instruction Carry Before DA Bits 7–4 Value (Hex) H Flag Before DA Bits 3–0 Value (Hex) Number Added To Byte Carry After DA Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 244 If the result of the addition is stored in Register 5Fh, the statement: DA 5Fh Op Code: 40 5F adjusts this result so the correct BCD representation is obtained. 0011 1100 = 3Ch 0000 0110 = 06h 0100 0010 = 42h Register 5Fh now contains the value 42h. The C, Z, and S flags are cleared, and V is undefined. Example If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic. 0001 0101 = 15h + 0010 0111 = 27h 0011 1100 = 3Ch Register 45F contains the value 5Fh, and the result of the addition is stored in Register 5Fh, the statement: DA @45h Op Code: 40 45 adjusts this result so the correct BCD representation is obtained. 0011 1100 = 3Ch 0000 0110 = 06h 0100 0010 = 42h Register 5Fh now contains the value 42h. The C, Z, and S flags are cleared, and V is undefined.

UM001602-0904 Instruction Description 245 Decrement DEC dst Instruction Format Operation dst ← dst–1 The contents of the destination operand are decremented by one. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R10 contains 2A%, the statement: DEC R10 Op Code: 00 EA Cycles OPC (Hex) Address Mode dst OPC dst 6 00 R 6 01 IR Flag Description C Unaffected Z Set if the result is zero; cleared otherwise S Set if the result of bit 7 is set (negative); cleared otherwise V Set if arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 246 leaves the value 29h in Working Register R10. The Z, V, and S flags are cleared. Example If Register B3h contains CBh, and Register CBh contains 01h, the state- ment: DEC @B3h Op Code: 01 B3 leaves the value 00h in Register CBh. The Z Flag is set, and the V and S flags are cleared.

UM001602-0904 Instruction Description 247 Decrement and Jump if Non-Zero DJNZ r, dst Instruction Format Operation r ← r–1; If r <> 0, PC ← PC + dst The specified Working Register being used as a counter is decremented. If the contents of the specified Working Register are not zero after decre- menting, then the relative address is added to the Program Counter (PC) and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to –128. The original value of the PC is the address of the instruction byte following the DJNZ statement. When the specified Working Register counter reaches zero, control falls through to the statement following the DJNZ instruction. The Working Register being used as a counter must be one of the Registers from 04h to EFh. Use of one of the I/O ports, control or peripheral regis- ters will have undefined results. Cycles OPC (Hex) Address Mode dst r OPC dst 12 If jump taken rA r 10 if jump not taken (R = 0 to F) r Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 248 Example DJNZ is typically used to control a loop of instructions. In this example, 12 bytes are moved from one buffer area in the register file to another. The steps involved are:

• Load 12 into the counter (Working Register R6)
• Set up the loop to perform the moves
• End the loop with DJNZ The assembly listing required for this routine is as follows: LD R6, 12 ;Load Counter LOOP: LD R9, @R6 ;Move one byte to LD @R6, R9 ;new location DJNZ R6, LOOP ;Decrement and Loop until counter ;= 0

UM001602-0904 Instruction Description 249 Decrement Word DECW dst Instruction Format Operation dst ← dst–1 The contents of the destination (which must be an even address) operand are decremented by one. The destination operand can be a Register Pair or a Working Register Pair. Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this format, the destination Working Register Pair operand is spec- ified by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register Pair R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Register Pair 30h and 31h contain the value 0AF2h, the statement: Cycles OPC (Hex) Address Mode dst OPC dst 10 80 RR 10 81 IR Flag Description C Unaffected Z Set if the result is zero; cleared otherwise S Set if the result of bit 7 is set (negative); cleared otherwise V Set if arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 250 DECW 30h Op Code: 80 30 leaves the value 0AF1h in Register Pair 30h and 31h. The Z, V, and S flags are cleared. Example If Working Register R0 contains 30h and Register Pairs 30h and 31h contain the value FAF3h, the statement: DECW @R0 Op Code: 81 E0 leaves the value FAF2h in Register Pair 30h and 31h. The S Flag is set, and the Z and V flags are cleared.

UM001602-0904 Instruction Description 251 Disable Interrupts Dl Instruction Format Operation IMR (7) ← 0 Bit 7 of Control Register FBh (the Interrupt Mask Register) is reset to 0. All interrupts are disabled, although they remain potentially enabled. (For instance, the Global Interrupt Enable is cleared, but not the individual interrupt level enables.) Example If Control Register FBh contains 8Ah (10001010) (interrupts IRQ1 and IRQ3 are enabled), the statement: DI Op Code: 8F sets Control Register FBh to 0Ah (00001010b) and disables these inter- rupts. Cycles OPC (Hex) OPC 6 8F Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 252 Enable Interrupts EI Instruction Format Operation IMR (7) ← 0 Bit 7 of Control Register FBh (the Interrupt Mask Register) is set to 1. This allows potentially enabled interrupts to become enabled. Example If Control Register FBh contains 0Ah (00001010) (interrupts IRQ1 and IRQ3 are selected), the statement: EI Op Code: 9F sets Control Register FBh to 8Ah (10001010b) and enables IRQ1 and IRQ3. Cycles OPC (Hex) OPC 6 9F Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

UM001602-0904 Instruction Description 253 Halt HALT Instruction Format Operation The HALT instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and the external interrupts IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated. In order to enter HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP immediately before the execution of the HALT instruction. Example Assuming the Z8® CPU is in normal operation, the statements: NOP HALT Op Codes: FF 7F place the Z8® CPU into HALT mode. Cycles OPC (Hex) OPC 6 7F Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 254 Increment Instruction Format Operation dst ← dst + 1 The contents of the destination operand are incremented by one. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R10 contains 2Ah, the statement: Cycles OPC (Hex) Address Mode dst dst OPC 6 rE r OPC dst 6 20 R 6 21 IR Flag Description C Unaffected Z Set if the result is zero; cleared otherwise. S Set if the result of bit 7 is set (negative); cleared otherwise. V Set if arithmetic overflow occurs; cleared otherwise. D Unaffected H Unaffected E dst Note:

UM001602-0904 Instruction Description 255 INC R10 Op Code: AE leaves the value 2Bh in Working Register R10. The Z, V, and S flags are cleared. Example If Register B3h contains CBh, the statement: INC B3h Op Code: 20 B3 leaves the value CCh in Register CBh. The S Flag is set, and the Z and V flags are cleared. Example If Register B3h contains CBh and Register BCh contains FFh, the state- ment: INC @B3h Op Code: 21 B3 leaves the value 00h in Register CBh. The Z Flag is set, and the V and S flags are cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 256 Increment Word INCW dst Instruction Format Operation dst ← dst–1 The contents of the destination (which must be an even address) operand is decremented by one. The destination operand can be a Register Pair or a Working Register Pair. Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this format, the destination Working Register Pair operand is spec- ified by adding 1110b (Eh) to the high nibble of the operand. For exam- ple, if Working Register Pair R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code Example If Register Pairs 30h and 31h contain the value 0AF2h, the statement: Cycles OPC (Hex) Address Mode dst OPC dst

10 A0 RR

10 A1 IR

10 A0 R

Z Set if the result is zero; cleared otherwise. S Set if the result of bit 7 is set (negative); cleared otherwise. V Set if arithmetic overflow occurs; cleared otherwise. D Unaffected H Unaffected E dst Note:

UM001602-0904 Instruction Description 257 INCW 30h Op Code: A0 30 leaves the value 0AF3h in Register Pair 30h and 31h. The Z, V, and S flags are cleared. Example If Working Register R0 contains 30h, and Register Pairs 30h and 31h contain the value FAF3h, the statement: INCW @R0 Op Code: A1 E0 leaves the value FAF4h in Register Pair 30h and 31h. The S Flag is set, and the Z and V flags are cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 258 Interrupt Return IRET Instruction Format Operation FLAGS ← @SP SP ← SP + 1 PC ← @SP SP ← SP + 2 IMR (7) ← 1 This instruction is issued at the end of an interrupt service routine. It restores the Flag Register (Control Register FCh) and the PC. It also re- enables any interrupts that are potentially enabled. Example If Stack Pointer Low Register FFh currently contains the value 45h, Reg- ister 45h contains the value 00h, Register 46h contains 6Fh, and Register 47 contains E4h, the statement: IRET Op Code: BF Cycles OPC (Hex) OPC 16 8F Flag Description C Restored to original setting before the interrupt occurred. Z Restored to original setting before the interrupt occurred. S Restored to original setting before the interrupt occurred. V Restored to original setting before the interrupt occurred. D Restored to original setting before the interrupt occurred. H Restored to original setting before the interrupt occurred.

UM001602-0904 Instruction Description 259 restores the FLAG Register FCh with the value 00h, restores the PC with the value 6FE4h, re-enables the interrupts, and sets the Stack Pointer Low to 48h. The next instruction to be executed will be at location 6FE4h.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 260 Jump JP cc, dst Instruction Format Operation If cc (condition code) is true, then PC ← dst A conditional jump transfers Program Control to the destination address if the condition specified by cc (condition code) is true. Otherwise, the instruction following the JP instruction is executed. See Section 12.3 for a list of condition codes. The unconditional jump simply replaces the contents of the Program Counter with the contents of the register pair specified by the destination operand. Program Control then passes to the instruction addressed by the PC. Address mode IRR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Cycles OPC (Hex) Address Mode dst cc OPC dst 12 If jump taken ccD DA 10 if jump not taken cc = 0 to F dst dst 8 30 IRR Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Note:

UM001602-0904 Instruction Description 261 Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the Carry Flag is set, the statement: JP C, 1520h Op Code: 7D 15 20 replaces the contents of the Program Counter with 1520h and transfers program control to that location. If the Carry Flag had not been set, con- trol would have fallen through to the statement following the JP instruc- tion. Example If Working Register Pair RR2 contains the value 3F45h, the statement: JP @RR2 Op Code: 30 E2 replaces the contents of the PC with the value 3F45h and transfers pro- gram control to that location. E dst

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 262 Jump Relative JR cc, dst Instruction Format Operation If cc is true, PC ← PC + dst If the condition specified by the cc is true, the relative address is added to the PC and control passes to the instruction located at the address speci- fied by the PC (See Section 12.3 for a list of condition codes). Otherwise, the instruction following the JR instruction is executed. The range of the relative address is +127 to –128, and the original value of the PC is taken to be the address of the first instruction byte following the JR instruction. Example If the result of the last arithmetic operation executed is negative, the next four statements (which occupy a total of seven bytes) are skipped with the statement: JR Ml, #9 Op Code: 5B 09 Cycles OPC (Hex) Address Mode dst cc OPC dst 12 If jump taken ccB RR 10 if jump not taken cc = 0 to F Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

UM001602-0904 Instruction Description 263 If the result was not negative, execution would have continued with the instruction following the JR instruction. Example A short form of a jump –45 is: JR #–45 Op Code: 8B D3 The condition code is blank in this case, and is assumed to be always true.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 264 Load LD dst, src Instruction Format Operation dst ← src The contents of the source operand are loaded into the destination oper- and. The contents of the source operand are not affected. Cycles OPC (Hex) Address Mode dst src dst OPC src 6 rC r IM 6 r8 r R src OPC dst 6 r9 R* r r = 0 to F OPC dst OPC 6 E3 r Ir

6 F3 Ir r

10 E5 R IR

10 E7 IR IM

UM001602-0904 Instruction Description 265 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example The statement: LD R15, #34h Op Code: FC 34 loads the value 34h into Working Register R15. Example If Register 34h contains the value FCh, the statement: LD R14, 34h Op Code: F8 34 loads the value FCh into Working Register R15. The contents of Register 34h are not affected. Example If Working Register R14 contains the value 45h, the statement: Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected E src or E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 266 LD 34h, R14 Op Code: E9 34 loads the value 45h into Register 34h. The contents of Working Register R14 are not affected. Example If Working Register R12 contains the value 34h, and Register 34h con- tains the value FFh, the statement: LD R13, @R12 Op Code: E3 DC loads the value FFh into Working Register R13. The contents of Working Register R12 and Register R34 are not affected. Example If Working Register R13 contains the value 45h, and Working Register R12 contains the value 00h the statement: LD @R13, R12 Op Code: F3 DC loads the value 00h into Register 45h. The contents of Working Register R12 and Working Register R13 are not affected. Example If Register 45h contains the value CFh, the statement: LD 34h, 45h Op Code: E4 45 34 loads the value CFh into Register 34h. The contents of Register 45h are not affected. Example If Register 45h contains the value CFh and Register CFh contains the value FFh, the statement:

UM001602-0904 Instruction Description 267 LD 34h, @45h Op Code: E5 45 34 loads the value FFh into Register 34h. The contents of Register 45h and Register CFh are not affected. Example The statement: LD 34h, #A4h Op Code: E6 34 A4 loads the value A4h into Register 34h. Example If Working Register R14 contains the value 7Fh, the statement: LD @R14, #FCh Op Code: E7 EE FC loads the value FCh into Register 7Fh. The contents of Working Register R14 are not affected. Example If Register 34h contains the value CFh and Register 45h contains the value FFh, the statement: LD @34h, 45h Op Code: F5 45 34 loads the value FFh into Register CFh. The contents of Register 34h and Register 45h are not affected. Example IIf Working Register R0 contains the value 08h and Register 2Ch (24h + 08h = 2Ch) contains the value 4Fh, the statement: LD R10, 24h(R0) Op Code: C7 A0 24

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 268 loads Working Register R10 with the value 4Fh. The contents of Working Register R0 and Register 2Ch are not affected. Example If Working Register R0 contains the value 0Bh and Working Register R10 contains 83h the statement: LD F0h(R0), R10 Op Code: D7 A0 F0 loads the value 83h into Register FBh (F0h + 0Bh = FBh). Because this is the Interrupt Mask Register, the LOAD statement has the effect of enabling IRQ0 and IRQ1. The contents of Working Registers R0 and R10 are unaffected by the load.

UM001602-0904 Instruction Description 269 Load Constant LDC dst, src Instruction Format Operation dst ← src This instruction is used to load a byte constant from program memory into a Working Register, or vice versa. The address of the program mem- ory location is specified by a Working Register Pair. The contents of the source operand are not affected. Example If Working Register Pair R6 and R7 contain the value 30A2h and program memory location 30A2h contains the value 22h, the statement: LDC R2, @RR6 Op Code: C2 26 Cycles OPC (Hex) Address Mode dst src OPC dst src 12 C2 r Irr OPC dst src 12 D2 Irr r Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 270 loads the value 22h into Working Register R2. The value of program memory location 30A2h is unchanged by the load. Example If Working Register R2 contains the value 22h, and Working Register Pair R6 and R7 contains the value 10A2h, the statement: LDC @RR6, R2 Op Code: D2 26 loads the value 22h into program memory location 10A2h. The value of Working Register R2 is unchanged by the load. This instruction format is valid only for MCUs which can address external program memory. Note:

UM001602-0904 Instruction Description 271 Load Constant Autoincrement LDCI dst, src Instruction Format Operation dst ← src r ← r + 1 rr ← rr + 1 This instruction is used for block transfers of data between program mem- ory and the Register File. The address of the program memory location is specified by a Working Register Pair, and the address of the Register File location is specified by Working Register. The contents of the source loca- tion are loaded into the destination location. Both addresses in the Work- ing Registers are then incremented automatically. The contents of the source operand are not affected. Cycles OPC (Hex) Address Mode dst src OPC dst src 18 C3 Ir Irr OPC dst src 18 D3 Irr Ir Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 272 Example If Working Register Pair R6–R7 contains 30A2h, program memory loca- tion 30A2h and 30A3h contain 22h and BCh respectively, and Working Register R2 contains 20h, the statement: LDCI @R2, @RR6 Op Code: C3 26 loads the value 22h into Register 20h. Working Register Pair RR6 is incremented to 30A3h and Working Register R2 is incremented to 21h. A second LDCI @R2, @RR6 Op Code: C3 26 loads the value BCh into Register 21h. Working Register Pair RR6 is incremented to 30A4h and Working Register R2 is incremented to 22h. Example If Working Register R2 contains 20h, Register 20h contains 22h, Regis- ter 21h contains BCh, and Working Register Pair R6–R7 contains 30A2h, the statement: LDCI @RR6, @R2 Op Code: D3 26 loads the value 22h into program memory location 30A2h. Working Reg- ister R2 is incremented to 21h and Working Register Pair R6–R7 is incre- mented to 30A3h. A second LDCI @RR6, @R2 Op Code: D3 26 loads the value BCh into program memory location 30A3h. Working Reg- ister R2 is incremented to 22h and Working Register Pair R6–R7 is incre- mented to 30A4h.

UM001602-0904 Instruction Description 273 Load External Data LDE dst, src Instruction Format Operation dst ← src This instruction is used to load a byte from external data memory into a Working Register or vice versa. The address of the external data memory location is specified by a Working Register Pair. The contents of the source operand are not affected. Example If Working Register Pair R6 and R7 contain the value 40A2h and external data memory location 40A2h contains the value 22h, the statement: LDE R2, @RR6 Op Code: 82 26 Cycles OPC (Hex) Address Mode dst src OPC dst src 12 82 r Irr OPC src dst 12 92 Irr r Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 274 loads the value 22h into Working Register R2. The value of external data memory location 40A2h is unchanged by the load. Example If Working Register Pair R6 and R7 contain the value 404Ah and Working Register R2 contains the value 22h, the statement: LDE @RR6, R2 Op Code: 92 26 loads the value 22h into external data memory location 404Ah This instruction format is valid only for MCUs which can address external data memory. Note:

UM001602-0904 Instruction Description 275 Load External Data Autoincrement LDEI dst, src Instruction Format Operation dst ← src r ← r + 1 rr ← rr + 1 This instruction is used for block transfers of data between external data memory and the Register File. The address of the external data memory location is specified by a Working Register Pair, and the address of the Register File location is specified by a Working Register. The contents of the source location are loaded into the destination location. Both addresses in the Working Registers are then incremented automatically. The contents of the source are not affected. Cycles OPC (Hex) Address Mode dst src OPC dst src 18 83 Ir Irr OPC src dst 18 93 Irr Ir Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 276 Example If Working Register Pair R6 and R7 contains 404Ah, external data mem- ory location 404Ah and 404Bh contain ABh and C3h respectively, and Working Register R2 contains 22h, the statement: LDEI @R2, @RR6 Op Code: 83 26 loads the value ABh into Register 22h. Working Register Pair RR6 is incremented to 404Bh and Working Register R2 is incremented to 23h. A second LDEI @R2, @RR6 Op Code: 83 26 loads the value C3h into Register 23h. Working Register Pair RR6 is incremented to 404Ch and Working Register R2 is incremented to 24h. Example If Working Register R2 contains 22h, Register 22h contains ABh, Regis- ter 23h contains C3h, and Working Register Pair R6 and R7 contains 404Ah, the statement: LDEI @RR6, @R2 Op Code: 93 26 loads the value ABh into external data memory location 404Ah. Working Register R2 is incremented to 23h and Working Register Pair RR6 is incremented to 404Bh. A second LDEI @RR6, @R2 Op Code: 93 26 loads the value C3h into external data memory location 404Bh. Working Register R2 is incremented to 24h and Working Register Pair RR6 is incremented to 404Ch. This instruction format is valid only for MCUs which can address external data memory. Note:

UM001602-0904 Instruction Description 277 No Operation NOP Instruction Format Operation No action is performed by this instruction. It is typically used for timing delays or clearing the pipeline. Cycles OPC (Hex) OPC 6 FF Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 278 Logical AND AND dst, src Instruction Format Operation dst ← dst AND src The source operand is logically ANDed with the destination operand. The AND operation results in a 1 being stored whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored. The result is stored in the destination operand. The contents of the source bit are not affected. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- Cycles OPC (Hex) Address Mode dst src OPC dst src 6 42 r r 6 43 r lr OPC src dst 10 44 R R 10 45 R IR OPC dst src 10 46 R IM 10 47 IR IM Flag Description C Unaffected Z Set if the result is zero; cleared otherwise S Set if the result of bit 7 is set; cleared otherwise V Always reset to 0 D Unaffected H Unaffected Note:

UM001602-0904 Instruction Description 279 fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R1 contains 34h (00111000b) and Working Register R14 contains 4Dh (10001101), the statement: AND R1, R14 Op Code: 52 1E Example If Working Register R4 contains F9h (11111001b), Working Register R13 contains 7Bh, and Register 7Bh contains 6Ah (01101010b), the statement: AND R4, @R13 Op Code: 53 4D leaves the value 68h (01101000b) in Working Register R4. The Z, V, and S flags are cleared. Example If Register 3Ah contains the value F5h (11110101b) and Register 42h contains the value 0Ah (00001010), the statement: AND 3Ah, 42h Op Code: 54 42 3A leaves the value 00h (00000000b) in Register 3Ah. The Z Flag is set, and the V and S flags are cleared. Example If Working Register R5 contains F0h (11110000b), Register 45h con- tains 3Ah, and Register 3Ah contains 7Fh (01111111b), the statement: E src or E dst

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 280 AND R5, @45h Op Code: 55 45 E5 leaves the value 70h (01110000b) in Working Register R5. The Z, V, and S flags are cleared. Example If Register 7Ah contains the value F7h (11110111b), the statement: AND 7Ah, #F0h Op Code: 56 7A F0 leaves the value F0h (11110000b) in Register 7Ah. The S Flag is set, and the Z and V flags are cleared. Example If Working Register R3 contains the value 3Eh and Register 3Eh contains the value ECh (11101100b), the statement: AND @R3, #05h Op Code: 57 E3 05 leaves the value 04h (00000100b) in Register 3Eh. The Z, V, and S flags are cleared.

UM001602-0904 Instruction Description 281 Logical OR OR dst, src Instruction Format Operation dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. The OR operation results in a one bit being stored whenever either of the corresponding bits in the two operands is a one. Otherwise, a zero bit is stored. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- Cycles OPC (Hex) Address Mode dst src OPC dst src 6 02 r r 6 03 r lr OPC src dst 10 04 R R 10 05 R IR OPC dst src 10 06 R IM 10 07 IR IM Flag Description C Unaffected Z Set if the result is zero; cleared otherwise S Set if the result of bit 7 is set; cleared otherwise V Always reset to 0 D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 282 fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (Ch) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R1 contains 34h (00111000b) and Working Register R14 contains 4Dh (10001101), the statement: OR R1, R14 Op Code: 42 1E leaves the value BDh (10111101b) in Working Register R1. The S Flag is set, and the Z and V flags are cleared. Example If Working Register R4 contains F9h (11111001b), Working Register R13 contains 7Bh, and Register 7B contains 6Ah (01101010b), the state- ment: OR R4, @R13 Op Code: 43 4D leaves the value FBh (11111011b) in Working Register R4. The S Flag is set, and the Z and V flags are cleared. Example If Register 3Ah contains the value F5h (11110101b) and Register 42h contains the value 0Ah (00001010), the statement: OR 3Ah, 42h Op Code: 44 42 3A leaves the value FFh (11111111b) in Register 3Ah. The S Flag is set, and the Z and V flags are cleared. E src or E dst

UM001602-0904 Instruction Description 283 Example If Working Register R5 contains 70h (01110000b), Register 45h con- tains 3Ah, and Register 3Ah contains 7Fh (01111111b), the statement: OR R5, @45h Op Code: 45 45 E5 leaves the value 7Fh (01111111b) in Working Register R5. The Z, V, and S flags are cleared. Example If Register 7Ah contains the value F3h (11110111b), the statement: OR 7Ah, #F0h Op Code: 46 7A F0 leaves the value F3h (11110111b) in Register 7Ah. The S Flag is set, and the Z and V flags are cleared. Example If Working Register R3 contains the value 3Eh and Register 3Eh contains the value 0Ch (00001100b), the statement: OR @R3, #05h Op Code: 57 E3 05 leaves the value 0Dh (00001101b) in Register 3Eh. The Z, V, and S flags are cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 284 Logical Exclusive OR XOR dst, src Instruction Format Operation dst ← dst XOR src The source operand is logically EXCLUSIVE ORed with the destination operand. The XOR operation results in a 1 being stored in the destination operand whenever the corresponding bits in the two operands are differ- ent, otherwise a 0 is stored. The contents of the source operand are not affected. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, Cycles OPC (Hex) Address Mode dst src OPC dst src 6 82 r r 6 83 r lr OPC src dst 10 84 R R 10 85 R IR OPC dst src 10 86 R IM 10 87 IR IM C Unaffected Z Set if the result is zero; cleared otherwise. S Set if the result of bit 7 is set; cleared otherwise. V Always reset to 0 D Unaffected H Unaffected Note:

UM001602-0904 Instruction Description 285 if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R1 contains 34h (00111000b) and Working Register R14 contains 4Dh (10001101b), the statement: XOR R1, R14 Op Code: B2 1E leaves the value BDh (10111101b) in Working Register R1. The Z, and V flags are cleared, and the S Flag is set. Example If Working Register R4 contains F9h (11111001b), Working Register R13 contains 7Bh, and Register 7Bh contains 6Ah (01101010b), the statement: XOR R4, @R13 Op Code: B3 4D leaves the value 93h (10010011b) in Working Register R4. The S Flag is set, and the Z, and V flags are cleared. Example If Register 3Ah contains the value F5h (11110101b) and Register 42h contains the value 0Ah (00001010b), the statement: XOR 3Ah, 42h Op Code: B4 42 3A leaves the value FFh (11111111b) in Register 3Ah. The S Flag is set, and the C and V flags are cleared. E src or E dst

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 286 Example If Working Register R5 contains F0h (11110000b), Register 45h con- tains 3Ah, and Register 3Ah contains 7Fh (01111111b), the statement: XOR R5, @45h Op Code: B5 45 E5 leaves the value 8Fh (10001111b) in Working Register R5. The S Flag is set, and the C and V flags are cleared. Example If Register 7Ah contains the value F7h (11110111b), the statement: XOR 7Ah, #F0h Op Code: B6 7A F0 leaves the value 07h (00000111b) in Register 7Ah. The Z, V and S flags are cleared. Example If Working Register R3 contains the value 3Eh and Register 3Eh contains the value 6Ch (01101100b), the statement: XOR @R3, #05h Op Code: B7 E3 05 leaves the value 69h (01101001b) in Register 3Eh. The Z, V, and S flags are cleared.

UM001602-0904 Instruction Description 287 Pop POP dst Instruction Format Operation dst ← @SP SP ← SP + 1 The contents of the location specified by the SP (Stack Pointer) are loaded into the destination operand. The SP is then incremented automatically. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Cycles OPC (Hex) Address Mode dst OPC dst 10 50 R 10 51 IR Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected E dst

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 288 Example If the SP (Control Registers FEh and FFh) contains the value 70h and Register 70h contains 44h, the statement: POP 34h Op Code: 50 34 loads the value 44h into Register 34h. After the POP operation, the SP contains 71h. The contents of Register 70 are not affected. Example If the SP (Control Registers FEh and FFh) contains the value 1000h, external data memory location 1000h contains 55h, and Working Regis- ter R6 contains 22h, the statement: POP @R6 Op Code: 51 E6 loads the value 55h into Register 22h. After the POP operation, the SP contains 1001h. The contents of Working Register R6 are not affected.

UM001602-0904 Instruction Description 289 Push PUSH src Instruction Format Operation SP ← SP–1 @SP ← src The contents of the SP (stack pointer) are decremented by one, then the contents of the source operand are loaded into the location addressed by the decremented SP, thus adding a new element to the stack. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Cycles OPC (Hex) Address Mode dst

10 Internal Stack 70

OPC src 12 External Stack R

10 Internal Stack IR

10 External Stack 71

Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 290 Example If the SP contains 1001h, the statement: PUSH FCh Op Code: 70 FC stores the contents of Register FCh (the Flag Register) in location 1000h. After the PUSH operation, the SP contains 1000h. Example If the SP contains 61h and Working Register R4 contains FCh, the state- ment: PUSH @R4 Op Code: 71 E4 stores the contents of Register FCh (the Flag Register) in location 60h. After the PUSH operation, the SP contains 60h.

UM001602-0904 Instruction Description 291 Reset Carry Flag RCF Instruction Format Operation C ← 0 The C Flag is reset to 0, regardless of its previous value. Example If the C Flag is currently set, the statement: RCF Op Code: CF resets the Carry Flag to 0. Cycles OPC (Hex) OPC 6 CF Flag Description C Reset to 0 Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 292 Return RET Instruction Format Operation PC ← @SP SP ← SP + 2 This instruction is normally used to return from a procedure entered by a CALL instruction. The contents of the location addressed by the SP are popped into the PC. The next statement executed is the one addressed by the new contents of the PC. The stack pointer is also incremented by two. Each PUSH instruction executed within the subroutine should be coun- tered with a POP instruction in order to guarantee the SP is at the correct location when the RET instruction is executed. Otherwise the wrong address will be loaded into the PC and the program will not operate as appropriate . Cycles OPC (Hex) OPC 14 AF Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Note:

UM001602-0904 Instruction Description 293 Example If SP contains 2000h, external data memory location 2000h contains 18h, and location 2001h contains B5h, the statement: RET Op Code: AF leaves the value 2002h in the SP, and the PC contains 18B5h, the address of the next instruction to be executed.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 294 Rotate Left RL dst Instruction Format Operation C ← dst(7) dst(0) ← dst(7) dst(1) ← dst(0) dst(2) ← dst(1) dst(3) ← dst(2) dst(4) ← dst(3) dst(5) ← dst(4) dst(6) ← dst(5) dst(7) ← dst(6) The contents of the destination operand are rotated left by one bit posi- tion. The initial value of bit 7 is moved to the bit 0 position and also into the Carry Flag, as shown below. Cycles OPC (Hex) Address Mode dst OPC dst 6 90 R 6 91 IR CD 7 D 6 D 5D 4D 3D 2D 1D 0

UM001602-0904 Instruction Description 295 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the contents of Register C6h are 88h (10001000b), the statement: RL C6h Op Code: 80 C6 leaves the value 11h (00010001b) in Register C6h. The C and V Flags are set, and the S and Z flags are cleared. Example If the contents of Register C6h are 88h, and the contents of Register 88h are 44h (01000100b), the statement: RL @C6h Op Code: 81 C6 leaves the value 88h in Register 88h (10001000b). The S and V Flags are set, and the C and Z flags are cleared. Flag Description C Set if the bit rotated from the most significant bit position was 1 ( i.e., bit 7 was 1). Z Set if the result is zero; cleared otherwise. S Set if the result in bit 7 is set; cleared otherwise. V Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. D Unaffected. H Unaffected. E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 296 Rotate Left Through Carry RLC dst Instruction Format Operation C← dst(7) dst(0) ← C dst(1) ← dst(0) dst(2) ← dst(1) dst(3) ← dst(2) dst(4) ← dst(3) dst(5) ← dst(4) dst(6) ← dst(5) dst(7) ← dst(6) The contents of the destination operand along with the C Flag are rotated left by one bit position. The initial value of bit 7 replaces the C Flag and the initial value of the C Flag replaces bit 0, as shown below. Cycles OPC (Hex) Address Mode dst OPC dst 6 10 R 6 11 IR CD 7 D 6 D 5D 4D 3D 2D 1D 0

UM001602-0904 Instruction Description 297 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the C Flag is reset and Register C6 contains 8Fh (10001111b), the statement: RLC C6 Op Code: 10 C6 leaves Register C6 with the value 1Eh (00011110b). The C and V Flags are set, and S and Z flags are cleared. Example If the C Flag is reset, Working Register R4 contains C6h, and Register C6 contains 8Fh (10001111b), the statement: RLC @R4 Op Code: 11 E4 leaves Register C6 with the value 1Eh (00011110b). The C and V Flags are set, and S and Z flags are cleared. Flag Description C Set if the bit rotated from the most significant bit position was 1 (i.e., bit 7 was 1). Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 298 Rotate Right RR dst Instruction Format Operation C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← dst(0) The contents of the destination operand are rotated to the right by one bit position. The initial value of bit 0 is moved to bit 7 and also into the C Flag, as shown below. Cycles OPC (Hex) Address Mode dst OPC dst 6 E0 R

6 E1 IR

UM001602-0904 Instruction Description 299 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the contents of Working Register R6 are 31h (00110001B), the state- ment: RR R6 Op Code: E0 E6 leaves the value 98h (10011000) in Working Register R6. The C, V, and S Flags are set, and the Z Flag is cleared. Example If the contents of Register C6 are 31h and the contents of Register 31h are 7Eh (01111110b), the statement: RR @C6 Op Code: E1 C6 leaves the value 4Fh (00111111) in Register 31h. The C, Z, V, and S flags are cleared. Flag Description C Set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1). Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 300 Rotate Right Through Carry RRC dst Instruction Format Operation C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← C The contents of the destination operand with the C Flag are rotated right by one bit position. The initial value of bit 0 replaces the C Flag and the initial value of the C Flag replaces bit 7, as shown below. Cycles OPC (Hex) Address Mode dst OPC dst 6 C0 R

6 C1 IR

UM001602-0904 Instruction Description 301 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by add- ing 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the contents of Register C6h are DDh (11011101b) and the C Flag is reset, the statement: RRC C6h Op Code: C0 C6 leaves the value 6Eh (01101110b) in register C6h. The C and V Flags are set, and the Z and S flags are cleared. Example If the contents of Register 2Ch are EDh, the contents of Register EDh is ← (00000000b), and the C Flag is reset, the statement: RRC @2Ch Op Code: C1 2C leaves the value 02h (00000010b) in Register EDh. The C, Z, S, and V Flags are reset. Flag Description C Set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1). Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 302 Set Carry Flag SRC Instruction Format Operation C ← 1 The C Flag is set to 1, regardless of its previous value. Example If the C Flag is currently reset, the statement: SCF Op Code: DF sets the Carry Flag to 1. Cycles OPC (Hex) OPC 6 DF Flag Description C Set to 1 Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

UM001602-0904 Instruction Description 303 Set Register Pointer SRP src Instruction Format Operation RP ← src The specified value is loaded into the Register Pointer (RP) (Control Reg- ister FDh). Bits 7-4 determine the Working Register Group. Bits 3-0 selects the Expanded Register Bank. Addressing of un-implemented Working Register Group, while using Expanded Register Banks, will point to Bank 0. Example SRP TD addresses Working Register Group 7 of Bank 0. Cycles OPC (Hex) Address Mode dst OPC src 6 31 IM Register Pointer (FDh) Working Register Group Actual Registers Contents (Bin) (Hex) (Hex) 1111 0000 F F0–FF 1110 0000 E E0–EF 1101 0000 D D0–DF 1100 0000 C C0–CF 1011 0000 B B0–BF 1010 0000 A A0–AF 1001 0000 9 90–9F

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 304 1000 0000 8 80–8F 0111 0000 7 70–7F 0110 0000 6 60–6F 0101 0000 5 50–5F 0100 0000 4 40–4F 0011 0000 3 30–3F 0010 0000 2 20–2F 0001 0000 1 10–1F 0000 0000 0 00–0F Register Pointer (FDh) Contents (Hex) Expanded Register Bank (Hex) xxxx 1111 F xxxx 1110 E xxxx 1101 D xxxx 1100 C xxxx 1011 B xxxx 1010 A xxxx 1001 9 xxxx 1000 8 xxxx 0111 7 xxxx 0110 6 xxxx 0101 5 xxxx 0100 4 xxxx 0011 3 xxxx 0010 2 Register Pointer (FDh) Working Register Group Actual Registers Contents (Bin) (Hex) (Hex)

UM001602-0904 Instruction Description 305 When an Expanded Register Bank , other than Bank 0 is selected, access to the Z8® Standard Register File is possible except for the Port Register and general purpose registers 04h to 0Fh. fpr Register Addresses 0h to Fh Example The statement: SRP F0h Op Code: 31 F0 sets the Register Pointer to access expanded Register Bank 0 and Working Register Group F in the Z8® Standard Register File. All references to Working Registers now affect this group of 16 registers. Registers F0h to FFh can be accessed as Working Registers R0 to R15. Example The statement: SRP 0Fh Op Code: 31 0F xxxx 0001 1 xxxx 0000 0 Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Register Pointer (FDh) Contents (Hex) Expanded Register Bank (Hex) Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 306 sets the Register Pointer to access Expanded Register Bank F, Reg ← to Reg 0Fh, as the current Working Registers. All references to Working Registers now affect this group of 16 registers. These registers are now accessed as Working Registers R0 to R15. Port Registers are now not accessable. Example Assume the RP currently addresses the Control and Peripheral Working Register Group and the program has just entered an interrupt service rou- tine. The statement: SRP 70h Op Code: 31 70 retains the contents of the Control and Peripheral Registers by setting the RP to 70h (01110000b). Any reference to Working Registers in the inter- rupt routine will point to registers 70h to 7Fh.

UM001602-0904 Instruction Description 307 Shift Right Arithmetic SRA dst Instruction Format Operation C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← dst(7) An arithmetic shift right by one bit position is performed on the destina- tion operand. Bit 0 replaces the C Flag. Bit 7 (the Sign bit) is unchanged and its value is shifted into bit 6, as shown below. Cycles OPC (Hex) Address Mode dst OPC dst 6 D0 R

6 D1 IR

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 308 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working Register operand is specified by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If the contents of Working Register R6 are 31h (00110001B), the state- ment: SRA R6 Op Code: D0 E6 leaves the value 98h (00011000) in Working Register R6. The C Flag is set, and the Z, V, and S flags are cleared. Example If Register C6 contains the value DFh, and Register DFh contains the value B8h (10111000B), the statement: SRA @C6 Op Code: D1 C6 leaves the value DCh (11011100B) in Register DFh. The C, Z, and V Flags are reset, and the S Flag is set. Flag Description C Set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1). Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Always reset to 0. D Unaffected H Unaffected E dst Note:

UM001602-0904 Instruction Description 309 Stop STOP Instruction Format Operation This instruction turns off the internal system clock (SCLK) and external crystal (XTAL) oscillation, and reduces the standby current. STOP mode is terminated by a RESET which causes the processor to restart the appli- cation program at address 000Ch. In order to enter STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP immediately before the execution of the STOP instruction. Example The statements: NOP STOP Op Codes: FF 6F place the Z8® CPU into STOP mode. Cycles OPC (Hex) OPC 6 6F Flag Description C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 310 Subtract SUB dst, src Instruction Format Operation dst ← dst–src The source operand is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed by adding the two’s complement of the source operand to the destination operand. Cycles OPC (Hex) Address Mode dst src OPC dst src 6 22 r r 6 23 r lr OPC src dst 10 24 R R 10 25 R IR OPC dst src 10 26 R IM 10 27 IR IM Flag Description C Cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a borrow. Z Set if the result is 0; cleared otherwise. V Set if arithmetic overflow occurred (if the operands were of opposite sign and the sign of the result is the same as the sign of the source); reset otherwise. S Set if the result is negative; cleared otherwise. H Cleared if there is a carry from the most significant bit of the low order four bits of the result; set otherwise indicating a borrow. D Always set to 1.

UM001602-0904 Instruction Description 311 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example ]If Working Register R3 contains 16h, and Working Register R11 con- tains 20h, the statement: SUB R3, R11 Op Code: 22 3B leaves the value F6h in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H flags are cleared. Example If Working Register R15 contains 16h, Working Register R10 contains 20h, and Register 20h contains 11h, the statement: SUB R16, @R10 Op Code: 23 FA leaves the value 05h in Working Register R15. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example If Register 34h contains 2Eh, and Register 12h contains 1Bh, the state- ment: SUB 34h, 12h Op Code: 24 12 34 leaves the value 13h in Register 34h. The D Flag is set, and the C, Z, S, V, and H flags are cleared. E src or E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 312 Example If Register 4Bh contains 82h, Working Register R3 contains 10h, and Register 10h contains 01h, the statement: SUB 4Bh, @R3 Op Code: 25 E3 4B leaves the value 81h in Register 4Bh. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example If Register 6Ch contains 2Ah, the statement: SUB 6Ch, #03h Op Code: 26 6C 03 leaves the value 27h in Register 6Ch. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example If Register D4h contains 5Fh, Register 5Fh contains 4Ch, the statement: SUB @D4h, #02h Op Code: 17 D4 02 leaves the value 4Ah in Register 5Fh. The D Flag is set, and the C, Z, S, V, and H flags are cleared.

UM001602-0904 Instruction Description 313 Subtract With Carry SBC dst, src Instruction Format Operation dst ← dst–src–C The source operand, along with the setting of the C Flag, is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed by adding the two’s complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry (borrow) from the subtraction of low order operands to be subtracted from the subtraction of high order operands. Cycles OPC (Hex) Address Mode dst src OPC dst src 6 32 r r 6 33 r lr OPC src dst 10 34 R R 10 35 R IR OPC dst src 10 36 R IM 10 37 IR IM

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 314 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example Working Register R3 contains 16h, the C Flag is set to 1, and Working Register R11 contains 20h, the statement: SBC R3, R11 Op Code: 32 3B leaves the value F5h in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are all cleared. Example If Working Register R15 contains 16h, the C Flag is not set, Working Register R10 contains 20h, and Register 20h contains 11h, the statement: SBC R16, @R10 Op Code: 33 FA Flag Description C Cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a borrow. Z Set if the result is 0; cleared otherwise. V Set if arithmetic overflow occurred (if the operands were of opposite sign and the sign of the result is the same as the sign of the source); reset otherwise. S Set if the result is negative; cleared otherwise. H Cleared if there is a carry from the most significant bit of the low order four bits of the result; set otherwise indicating a borrow. D Always set to 1. E src or E dst Note:

UM001602-0904 Instruction Description 315 leaves the value 05h in Working Register R15. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example :If Register 34h contains 2Eh, the C Flag is set, and Register 12h con- tains 1Bh, the statement: SBC 34h, 12h Op Code: 34 12 34 leaves the value 13h in Register 34h. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example If Register 4Bh contains 82h, the C Flag is set, Working Register R3 con- tains 10h, and Register 10h contains 01h, the statement: SBC 4Bh, @R3 Op Code: 35 E3 4B leaves the value 80h in Register 4Bh. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example If Register 6Ch contains 2Ah, and the C Flag is not set, the statement: SBC 6Ch, #03h Op Code: 36 6C 03 leaves the value 27h in Register 6Ch. The D Flag is set, and the C, Z, S, V, and H flags are cleared. Example If Register D4h contains 5Fh, Register 5Fh contains 4Ch, and the C Flag is set, the statement: SBC @D4h, #02h Op Code: 37 D4 02

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 316 leaves the value 4Ah in Register 5Fh. The D Flag is set, and the C, Z, S, V, and H flags are cleared.

UM001602-0904 Instruction Description 317 Swap Nibbles SWAP dst Instruction Format Operation dst(7-4) ↔ dst(3-0) The contents of the lower four bits and upper four bits of the destination operand are swapped. Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working Register operand is specified by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Register BCh contains B3h (10110011B), the statement: Cycles OPC (Hex) Address Mode dst OPC dst 6 F0 R

6 F1 IR

Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Undefined D Unaffected H Unaffected E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 318 SWAP B3h Op Code: F0 B3 will leave the value 3Bh (00111011B) in Register BCh. The Z and S flags are cleared. Example If Working Register R5 contains BCh and Register BCh contains B3h (10110011B), the statement: SWAP @R5h Op Code: F1 E5 will leave the value 3Bh (00111011B) in Register BCh. The Z and S flags are cleared.

UM001602-0904 Instruction Description 319 Test Complement Under Mask TCM dst, src Instruction Format Operation (NOT dst) AND src This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified by setting a 1 bit in the corre- sponding bit position in the source operand (the mask). The TCM instruc- tion complements the destination operand, and then ANDs it with the source mask (operand). The Zero (Z) Flag can then be checked to deter- mine the result. If the Z Flag is set, then the tested bits were 1. When the TCM operation is complete, the destination and source operands still con- tain their original values. Cycles OPC (Hex) Address Mode dst src OPC dst src 6 62 r r 6 63 r lr OPC src dst 10 64 R R 10 65 R IR OPC dst src 10 66 R IM 10 67 IR IM Flag Description Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Always reset to 0. D Unaffected H Unaffected

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 320 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R3 contains 45h (01000101b) and Working Register R7 contains the value 01h (00000001b) (bit 0 is being tested if it is 1), the statement: TCM R3, R7 Op Code: 62 37 will set the Z Flag indicating bit 0 in the destination operand is 1. The V and S flags are cleared. Example If Working Register R14 contains the value F3h (11110011b), Working Register R5 contains CBh, and Register CBh contains 88h (10001000b) (bit 7 and bit 3 are being tested if they are 1), the statement: TCM R14, @R5 Op Code: 63 E5 will reset the Z Flag, because bit 3 in the destination operand is not a 1. The V and S Flags are also cleared. Example If Register D4h contains the value 04h (000001000b), and Working Reg- ister R0 contains the value 80h (10000000b) (bit 7 is being tested if it is 1), the statement: TCM D4h, R0 Op Code: 64 E0 D4 E src or E dst Note:

UM001602-0904 Instruction Description 321 will reset the Z Flag, because bit 7 in the destination operand is not a 1. The S flag will be set, and the V flag will be cleared. Example If Register DFh contains the value FFh (11111111b), Register 07h con- tains the value 1Fh, and Register 1Fh contains the value BDh (10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 1), the statement: TCM DFh, @07h Op Code: 65 07 DF will set the Z Flag indicating the tested bits in the destination operand are 1. The S and V flags are cleared. Example If Working Register R13 contains the value F2h (11110010b), the state- ment: TCM R13, #02h Op Code: 66 ED, 02 tests bit 1 of the destination operand for 1. The Z flag will be set indicat- ing bit 1 in the destination operand was 1. The S and V flags are cleared. Example If Register 5Dh contains A0h, and Register A0h contains 0Fh (00001111b), the statement: TCM @5D, #10h Op Code: 67 5D 10 tests bit 4 of the Register A0h for 1. The Z flag will be reset indicating bit 1 in the destination operand was not 1. The S and V flags are cleared.

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 322 Test Under Mask TM dst, src Instruction Format Operation dst AND src This instruction tests selected bits in the destination operand for a 0 logi- cal value. The bits to be tested are specified by setting a 1 bit in the corre- sponding bit position in the source operand (the mask). The TM instruction ANDs the destination operand with the source operand (the mask). The Zero (Z) Flag can then be checked to determine the result. If the Z Flag is set, then the tested bits were 0. When the TM operation is complete, the destination and source operands still contain their original values. Cycles OPC (Hex) Address Mode dst src OPC dst src 6 72 r r 6 73 r lr OPC src dst 10 74 R R 10 75 R IR OPC dst src 10 76 R IM 10 77 IR IM Flag Description Z Set if the result is zero; cleared otherwise. S Set if the result bit 7 is set; cleared otherwise. V Always reset to 0. D Unaffected H Unaffected

UM001602-0904 Instruction Description 323 Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is speci- fied by adding 1110b (Eh) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECh will be used as the destination operand in the Op Code. Example If Working Register R3 contains 45h (01000101b) and Working Register R7 contains the value 02h (00000010b) (bit 1 is being tested if it is 0), the statement: TM R3, R7 Op Code: 72 37 will set the Z Flag indicating bit 1 in the destination operand is 0. The V and S flags are cleared. Example Working Register R14 contains the value F3h (11110011b), Working Register R5 contains CBh, and Register CBh contains 88h (10001000b) (bit 7 a bit 3 are being tested if they are 0), the statement: TM R14, @R5 Op Code: 73 E5 will reset the Z Flag, because bit 7 iin the destination operand is not a 0. The S flag will be set, and the V Flag is cleared. Example If Register D4h contains the value 08h (00001000b), and Working Reg- ister R0 contains the value 04h (00000100b) (bit 2 is being tested if it is 0), the statement: TM D4h, R0 Op Code: 74 E0 D4 E src or E dst Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 324 will set the Z Flag, because bit 2 in the destination operand is a 0. The S and V Flags will be cleared. Example If Register DFh contains the value ← (00000000b), Register 07h con- tains the value 1Fh, and Register 1Fh contains the value BDh (10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 0), the statement: TM DFh, @07h Op Code: 75 07 DF will set the Z Flag indicating the tested bits in the destination operand are 0. The S is set, and the V Flag is cleared. Example If Working Register R13 contains the value F1h (11110001b), the state- ment: TM R13, #02h Op Code: 76 ED, 02 tests bit 1 of the destination operand for 0. The Z flag will be set indicat- ing bit 1 in the destination operand was 0. The S and V flags are cleared. Example If Register 5Dh contains A0h, and Register A0h contains 0Fh (00001111b), the statement: TM @5D, #10h Op Code: 77 5D 10 tests bit 4 of the Register A0h for 0. The Z flag will be set indicating bit 4 in the destination operand was 0. The S and V flags are cleared.

UM001602-0904 Instruction Description 325 Watch-Dog Timer WDT Instruction Format Operation The WDT (Watch–Dog Timer) is a retriggerable one shot timer that will reset the Z8® CPU if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction. Each subsequent execution of the WDT instruction refreshes the timer and prevents the WDT from tim- ing out. The WDT instruction should not be used following any instruction in which the condition of the flags is important. Example If the WDT is enabled, the statement: WDT Op Code: .BYTE 5Fh refreshes the Watch–Dog Timer. Cycles OPC (Hex) OPC 6 5F Flag Description Z Undefined S Undefined V Undefined D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 326 Example The first execution of the statement: WDT Op Code: .BYTE 5Fh enables the Watch–Dog Timer.

UM001602-0904 Instruction Description 327 Watch-Dog Timer Enable During Halt Mode WDh Instruction Format Operation When this instruction is executed it will enable the WDT (Watch–Dog Timer) during HALT mode. If this instruction is not executed the WDT will stop when entering HALT mode. This instruction does not clear the counter, it just makes it possible to have the WDT function running during HALT mode. A WDh instruction executed without executing WDT (5Fh) has no effect. The WDh instruction should not be used following any instruction in which the condition of the flags is important. Example If the WDT is enabled, the statement: WDh Op Code: .BYTE 4Fh will enable the WDT in HALT mode. Cycles OPC (Hex) OPC 6 4F Flag Description Z Undefined S Undefined V Undefined D Unaffected H Unaffected Note:

Z8 Family of Microcontrollers User Manual Instruction Description UM001602-0904 328 This instruction format is valid only for the Z86C04, Z86C08, Z86E04, Z86E07, and Z86E08 MCUs. Note:

UM001602-0904 Customer Feedback 329 Customer Feedback If you note any inaccuracies while reading this Reference Manual, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Product Information Customer Information Return Information San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific prob- lem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. Z8 CPU Serial # or Board Fab #/Rev. # Software Version 1.1.0 Document Number UM001602-0904 Host Computer Description/Type Name Country Company Phone Address Fax City/State/Zip E-Mail