Z86E0812SEG ZILOG | Alldatasheet
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——— eee yp PRELIMINARY PRODUCT SPECIFICATION Z86E04/E08 CMOS Z8 OTP MICROCONTROLLERS a PRODUCT DEVICES Part Oscillator Operating Operating ROM Number Type Voc Temperature (KB) Package Z86E0412PSC1866 Crystal 4.5V-5.5V Orci70°C 1 18-Pin DIP 2Z86E0412PSC1903 RC 4.5V-5.5V 0°c/70°C 1 18-Pin DIP Z86E0412PEC1903 RC 4.5V-5.5V —40°C/105°C 1 18-Pin DIP 2Z86E0412SEC Crystal 4.5V-5.5V —40°C/105°C 1 18-Pin SOIC 2Z86E0412SSC1866 Crystal 4.5V-5.5V 0°C/70°C 1 18-Pin SOIC Z86E0412SSC1903 RC 4.5V-5.5V 0°C/70°C 1 18-Pin SOIC 286E0412SEC1903 RC 4.5V-5.5V —40°C/105°C: 1 18-Pin SOIC Z86E0812PEC Crystal 4.5V-5.5V —40°C/105°C 2 18-Pin DIP Z86E0812PSC1866 Crystal 4,.5V-5.5V 0°C/70°C 2 18-Pin DIP Z86E0812PSC1903 RC 4.5V-5.5V a°c/70°C 2 18-Pin DIP Z86E0812PEC1903 RC 4.5V-5.5V —40°C/105°C 2 18-Pin DIP Z86E0812SEC Crystal 4.5V-5.5V ~40°C/105°C 2 18-Pin SOIC Z86E0812SSC1866 Crystal 4.5V-5.5V o°c/70°C 2 18-Pin SOIC Z86E0812SSC1903 RC 4.5V-5.5V O°C/70°C 2 18-Pin SOIC Z86E0812SEC1903 RC 4.5V-5.5V —40°C/105°C 2 18-Pin SOIC Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the us- er’s application requirements. DS97Z8X1104 PRELIMINARY 1
CMOS Z8 OTP Microcontrollers Zilog LL
FEATURES
@ 14 Input/Output Lines im =Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler @ Six Vectored, Prioritized Interrupts (3 falling edge, 1 rising edge, 2 timers) @ WDT/ Power-On Reset (POR) @ Two Analog Comparators @ On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock m Program Options: - Low Noise @ Clock-Free WDT Reset ~ ROM Protect m Low-Power Consumption (50 mw typical) - Auto Latch — Watch-Dog Timer (WDT) @ Fast Instruction Pointer (1s @ 12 MHz) - EPROM/Test Mode Disable m RAM Bytes (125) GENERAL DESCRIPTION Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time _ Note: All Signais with an overline, “™ are active Low, for Programmable (OTP) members of Zifog’s single-chip Z8® example: BAW (WORD is active Low); B/W (BYTE is active MCU family that allow easy software development, debug, _Low, only). Prototyping, and small production runs not economically . desirable with masked ROM versions. Power connections follow conventional descriptions be- low: For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are Connection Circuit Device grouped into three ports, and are configurable under soft- ‘Power. Vag Ware control to provide timing, status signals, or paralle! Ground GND Vee Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data com- munications.
2 PRELIMINARY DS97Z8X1104
Figure 1. Functional Block Diagram
Figure 2. EPROM Programming Mode Block Diagram
4 PRELIMINARY DS97Z8X1104
Figure 3. 18-Pin EPROM Mode Configuration Figure 4. 18-Pin DIP/SOIC Mode Configuration Table 1. 18-Pin DIP Pin Identification Table 2. 18-Pin DIP/SOIC Pin Identification
5 Voc Power Supply 5 Vog Power Supply SSS
8 COE OutputEnable input_ sg P3t Port 3, Pin 1, ANT Input
9 EPM EPROM Prog Mode Input 9 P32 Port 3, Pin 2, AN2 Input
10 Ver Prog Voltage Input 70 P33 Port 3, Pin 3, REF Input
1 Clear Clear Clock Input 11-13 POO-P02 Port 0, Pins 0,1,2 tn/Output
12 Clock Address Input 14 GND Ground a
13 PGM Prog Mode Input 15-18 P20-P23_ Port2, Pins 0,1,2,8 __In/Output
14 GND Ground
CMOS Z8 OTP Microcontrollers Zilog NN ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maxi- dissipation should not exceed 462 mW for the package. mum Ratings may cause permanent damage to the de- _— Power dissipation is calculated as follows: vice. This is a stress rating only; functional operation of the device at any condition above those indicated in the oper- Total Power Dissipation = Vpp x [Ipp—(sum of lon) ational sections of these specifications is not implied. Ex- f (Vip -Vou) x | posure to absolute maximum rating conditions for an ex- + sum of [(Voo-Vou) * lou tended period may affect device reliability. Total power + Sum Of (Vo. X lou) SS Parameter Min Max Units Note Ambient Temperature under Bias —40 +105 Cc Storage Temperature 65 +150 Cc Voltage on any Pin with Respect to Vs 0.7 412 Vv 1 Voltage on Vpp Pin with Respect to Vgg 0.3 +7 Vv Voltage on Pins 7, 8, 9, 10 with Respect to Veg 0.6 Vop+1 Vv 2 Total Power Dissipation 1.65 Ww Maximum Allowable Current out of Ves 300 mA Maximum Allowable Current into Vpp 220 mA Maximum Allowable Current into an input Pin 600 +600 pA 3 Maximum Allowable Current into an Open-Drain Pin 600 +600 pA 4 Maximum Allowable Output Current Sinked by Any /O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Total Maximum Output Current Sinked by a Port 60 mA Total Maximum Output Current Sourced by a Port 45 mA er een ee ee Notes: 1. This applies to all pins except where otherwise noted. Maximum current into pin must be + 600 pA. 2. There is no input protection diode from pin to Vpp (not applicable to EPROM Mode). 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state. — ee
6 PRELIMINARY DS97Z8X1104
Figure 5. Test Load Diagram Ta = 25°C, Vcc = GND = OV, f = 1.0 MHz, unmeasured pins returned to GND.
CMOS 28 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS Standard Temperature T,=0°C to+70°C Typical Sym Parameter Vecl4] = Min Max @25°C Units Conditions Notes Vinmax Max Input Voltage 4.5V 12 Vi |in<250 pA 1 Vou Clock Input High 45V 0.8Vog Voce +0.3 2.8 V__ Driven by External Voltage Clock Generator 5.5V 0.8Vog Voc t0.3 28 V__ Driven by External Clock Generator Vou Clock Input Low 45V — Vgg-0.3 (0.2 Veg 1.7 V__ Driven by External Voltage Clock Generator 5.5V — Vgg-0.3 0.2 Veg 1.7 V__ Driven by External Clock Generator Vin Input High Voltage 45V 0.7Voo Voct0.3 2.8 V ~ 5.5V 0.7 Veg Vogt0.3 2.8 Vv Vi Input Low Voitage 4.5V — Vgg-0.3 0.2 Veg 1.6 Vv 5.5V — Vsg-0.3 0.2Vog 1.8 Vv Vox Output High Voltage 4.6V— Vgo-0.4 48 V low =—2.0 mA 5 BBV Voo-0.4 48 Vlg =—2.0 mA 5 45V Voc-0.4 48 V__LowNoise @ Io, =-0.5 mA 5.5V — Vo¢-0.4 48 V Low Noise @ Io, = -0.5 MA Vor: Output Low Voltage 4.5V 0.8 01 Vig. = +4.0 mA 5 5.5V 0.4 04 Vig. =+4.0mA 5 4.5V 0.4 0.1 V_ Low Noise @ Ig, = 1.0mA 5.5V 0.4 04 V_ Low Noise @ Io, = 1.0 mA Voie Output Low Voltage 4.6V 08 08 V_ lop =+12mA, 5 5.5V 08 08 Vlg =+l2mA, 5 Vorrser Comparator Input 4.5V 25.0 10.0 mV Offset Voltage 5.5V 25.0 10.0 mv Viv Voc Low Voltage 22 30 28 V__@6 MHz Max. Auto Reset Int. CLK Freq. tie Input Leakage 4.5V -1.0 1.0 HA Vin = OV, Veg een tail of Sev 1.0 1.0 vA Vw= OV, Voc Io. Output Leakage 45V 1.0 1.0 PA Vin = OV, Vog 5.5V -1.0 1.0 BA Viy=OV, Veg Vick Comparator Input 0 Voo-1.0 Vv Common Mode Voltage Range
8 PRELIMINARY DS97Z8X1104
Zilog . CMOS Z8 OTP Microcontrollers ———— ee Ta = 0°C to +70°C Typical Sym Parameter Veco [4] Min Max @25°C Units Conditions Notes log Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 4.5V 15.0 8.2 mA AllOutputand/O Pins 5,7 Floating @ 8 MHz 5.5V 15.0 8.2 mA All Output and I/O Pins 5,7 Floating @ 8 MHz 4.5V 20.0 12.0 mA All Output and I/O Pins 5,7 Floating @ 12 MHz 5.5V 20.0 12.0 mA Ail Output and I/O Pins 5,7 Floating @ 12 MHz Iocy ~~ Standby Current 4.5V 4.0 25 mA _ HALT Mode Vix = OV, 5,7 Voc @ 2 MHz 5.5V 4.0 25 mA HALT Mode Viy = OV, 5,7 Veo @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode Vin = OV, 5,7 Voc @ 8 MHz 5.5V 5.0 3.0 mA_ HALT Mode Vy = OV, 5,7 Veg @ 8 MHz 4.5V 7.0 4.0 mA_ HALT Mode Vy = OV, 5,7 Voc @ 12 MHz 5.5V 7.0 4.0 mA HALT Mode Vy = OV, 5,7 Veg @ 12 MHz log Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 7 (Low Noise Mode) Floating @ 1 MHz 5.5V 11.0 68 mA All Output and I/O Pins 7 Floating @ 1 MHz 4.5V 13.0 7.5 mA All Output and I/O Pins 7 Floating @ 2 MHz 5.5V 13.0 75 mA All Output and /O Pins 7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 7 Floating @ 4 MHz _ 5.5V 15.0 8.2 mA All Output and 1/0 Pins 7 Floating @ 4 MHz SSS OING@ AMZ DS97Z8X1104 PRELIMINARY 9
CMOS Z8 OTP Microcontrollers Zilog LL DC ELECTRICAL CHARACTERISTICS (Continued) Sees Ta = 0°C to +70°C Typical Sym Parameter Vec [4] Min Max @25°C Units Conditions Notes loc: | Standby Current 4.5V 4.0 25 mA HALT Mode Vy = OV, 7 (Low Noise Mode) Voc @ 1 MHz 5.5V 40 2.5 mA HALT Mode Vy = OV, 7 Voc @ 1 MHz 4.5V 4.5 2.8 mA HALT Mode Vy = OV, 7 Voc @ 2 MHz 5.5V 45 2.8 mA HALT Mode Viy = OV, 7 Veg @ 2 MHz 45V 5.0 3.0 mA HALT Mode Viy = OV, 7 Veg @ 4 MHz 5.5V 5.0 3.0 mA HALT Mode Vy = OV, 7 Voc @ 4 MHz lecg Standby Current 4.5V 10.0 1.0 pA STOP Mode Vix = OV, Veo 78 WDT is not Running 5.5V 10.0 1.0 HA STOP Mode Viy = OV,Veg 7.8 WDT is not Running Tau Auto Latch Low 4.5V 32.0 16 WA OV <Viy<Voo Current 5.5V 32.0 16 BA O0V<Vy<Veg latn Auto Latch High 45V —16.0 80 pA OV<Vin<Voo Current 5.6V 16.0 80 WA 0V<Viy<Veg A Notes: 1. Port 2 and Port 0 only 2. Veg = OV = GND 3. The device operates down to Vy of the specified frequency for Vy The minimum operational Vgc is determined on the value of the voltage Vy at the ambient temperature. The Vy increases as the temperature decreases. 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at Voc or Vgg level. 8. If analog comparator is selected, then the comparator inputs must be at Veg level. EEE —_ eee
10 PRELIMINARY DS97Z8X1104
Zilog CMOS Z8 OTP Microcontrollers ——— DC ELECTRICAL CHARACTERISTICS Extended Temperature Ta = 40°C to +105°C Typical Sym Parameter Vecl4] Min Max @25°C Units Conditions Notes Vinmax Max Input Voltage 4.5V 12.0 Vo ly < 250 pA 1 5.5V 12.0 Vly <250 pA 1 Vou Clock Input High 45V 0.8Vog Voo+0.3 28 V___ Driven by External Voltage Clock Generator 5.5V 0.8Vog Vgct0.3 2.8 V___ Driven by External Clock Generator Ver Clock Input Low 4.5V Vg5-0.3 0.2 Veg 1.7 V___ Driven by External Voltage Clock Generator 5.5V Vgg-0.3 0.2 Veg 1.7 V___ Driven by External Clock Generator Vin Input High Voltage ~~ 4.5V(0.7Vog Voot0.3 2.8 Vv : 55V 0.7Vog Veot0.3 28 V Vic Input Low Voltage 4.5V Vg5-0.3 0.2 Vog 1.5 Vv “SEV Vgg03 02Vo 15 #V Vou Output High Voltage 4.5V = Vo¢-0.4 4.8 Vi loy =-2.0 mA 5 5.5V Voo-0.4 48 Voy =—2.0 mA a: 45V Voo-0.4 V___ LowNoise @ Ip, =-0.5 mA B.5V Veg-0.4 V___ Low Noise @ Io, =—0.5 mA 5.5V 0.4 01 Volo. =+4.0mA 5 4.5V 0.4 0.1 V_ Low Noise @ Ip, = 1.0 mA 5.5V 0.4 0.1 V_ Low Noise @ Ip, = 1.0 mA Voz Output Low Voltage 4.5V 1.0 0.3 Vo lg, = +12 mA, 5 5.5V 1.0 03 Vig. =+12mA, 5 Vorrset Comparator Input 4.5V 25.0 10.0 mV Offset Voltage 5.5V 25.0 10.0 mV Auto Reset CLK Freq. Ie Input Leakage 4.5V -1.0 1.0 HA Vin = OV, Vog Cr eonnperse) 5.5V -1.0 1.0 HA Vin=OV, Veg To. Output Leakage 4.5V =1.0 1.0 pA Vin=OV, Veo Vion Comparatorinput ===—=S=S*=*«sS*~<C~C gg SSSC“‘CO’SCNC#O#U;WWOSNCSC~S*SSSCSSSS Common Mode Voltage Range DS97Z8X1104 PRELIMINARY 1
CMOS Z8 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS (Continued) Ta = 40°C to +105°C Typical Sym —_ Parameter Voc [4] Min Max @25°C Units Conditions Notes loo Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins 5,7 Floating @ 2 MHz 5.5V 11.0 6.8 mA All Output and /O Pins 5,7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 5,7 Floating @ 8 MHz 5.5V 15.0 8.2 mA All Output and /O Pins 5,7 Floating @ 8 MHz 4.5V 20.0 12.0 mA _ All Output and I/O Pins 5,7 Floating @ 12 MHz 5.5V 20.0 12.0 mA All Output and I/O Pins 5,7 Floating @ 12 MHz loc) Standby Current 4.5V 5.0 25 mA HALT Mode Vy = OV, 57 Voc @ 2 MHz 5.5V 5.0 2.5 mA _— HALT Mode Vy = OV, 5,7 Veco @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode V,, = OV, 57 Voc @ 8 MHz 5.5V 5.0 3.0 mA HALT Mode Vy = OV, 5,7 Veg @ 8 MHz 45V 7.0 4.0 mA HALT Mode Viy = OV, 5,7 Voc @ 12 MHz 5.5V 7.0 4.0 mA HALT Mode Vy = OV, 5,7 Veg @ 12 MHz loo Supply Current 45V 11.0 6.8 mA All Output and 1/0 Pins 7 (Low Noise Mode) Floating @ 1 MHz 5.5V 11.0 6.8 mA Alt Output and I/O Pins 7 Floating @ 1 MHz ~45V 13.0 75 mA All Output and I/O Pins 7 Floating @ 2 MHz 5.5V 13.0 7.5 mA All Output and I/O Pins 7 Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins 7 Floating @ 4 MHz 5.6V 15.0 8.2 mA All Output and /O Pins 7 Floating @ 4 MHz $$ ONG AMZ ‘eS PRELIMINARY s97z8x1 104
Zilog . CMOS Z8 OTP Microcontrollers ee __ Ta = 40°C to +105°C Typical Sym Parameter Vee [4] Min Max @25°C Units Conditions Notes loot Standby Current 4.5V 4.0 25 mA HALT Mode Vy = OV, 7 (Low Noise Mode) Veco @ 1 MHz 5.5V 4.0 2.5 mA HALT Mode Vy = OV, 7 Voc @ 1 MHz 4.5V 45 2.8 mA HALT Mode Vjy = OV, 7 Voc @ 2 MHz 5.5V 45 28 mA HALT Mode Vy = OV, 7 Veo @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode Vy = OV, 7 Voc @ 4 MHz 5.5V 5.0 3.0 mA HALT Mode Viy = OV, 7 Veg @ 4 MHz Ioo2 Standby Current 4.5V 20 1.0 pA STOP Mode Viy=O0V,Veg 7,8 WDT is not Running 5.5V 20 1.0 vA STOP Mode Viy=O0V, Veg 7,8
7 WDT is not Running
Tau ‘Auto Latch Low 45V 40 16 pA OV<Viy<Voo Current 5.5V 40 16 pA OV <Viy<Voo Thun Auto Latch High 45V 20.0 -8.0 pA 0V<Viy<Voo Current 5.5V =20.0 =8.0 HA O0V<Vin<Voo Notes: 1. Port 2 and Port 0 only 2. Vgg = OV = GND 3. The device operates down to V.y of the specified frequency for Vy . The minimum operational Vg is determined on the value of the voltage V,y at the ambient temperature. The Vy increases as the temperature decreases. 4. Voc = 4.5V to 5.5V, typical values measured at Vog = 5.0V 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at Voc oF Vgg level. 8. If analog comparator is selected, then the comparator inputs must be at Vgc level. een 0 —— ee DS97Z8X1104 PRELIMINARY 13
Figure 6. AC Electrical Timing Diagram
14 PRELIMINARY DS97Z8X1104
Zilog . CMOS Z8 OTP Microcontrollers AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Standard Temperature
15 Taz 0 °C to +70 °C
8 MHz 12 MHz
No Symbol Parameter Vee Min Max Min = Max Units Notes 1 TpC Input Clock Period 4.5V 125 DC 83 DC ns 1 5.5V 125 DC 83 [iej ns 1 2 TC, TIC Clock Input Rise 4.5V 25 15. sons 1 and Fall Times 5.5V 25 15 ns 1 3 TwC Input Clock Width 4.5V 62 41 ns 1 5.5V 62 4 ns 1 4 TwTine Timer Input Low Width 4.5V 100 100 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 1 55V. 5TpC 5TpC 1 6 TpTin Timer Input Period 4.5V 8TpC 8TpC 1 5.5V 8TpC 8TpC 1 7 TrTin, Timer Input Rise 4.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100 100 ns 1 8 Twi Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwlH int. Request Input 4.5V 5TpC 5TpC 1,2 High Time 5.5V 5TpC 5TpC 7 1,2 10 Twat Watch-Dog Timer 4.5V 12 12 ms 1 Delay Time for Timeout 5.5V 12 12 ms 1 11 Tpor Power-On Reset Time 4.5V 20 80 20 80 ms 1 5.5V 20 80 20 80 ms 1 Notes: 1. Timing Reference uses 0.7 Vg for a logic 1 and 0.2 Vag for a logic 0. 2. Interrupt request through Port 3 (P33—P31). DS97Z8X1104 PRELIMINARY 15
CMOS Z8 OTP Microcontrollers Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Extended Temperature Ty= 40 °C to +105 °C No Symbol Parameter Vee Min Max Min Max Units Notes 1 TpC Input Clock Period 4.5V 125 bc 83 DC ns 1 5.5V 125 Dc 83 DC ns 1 2 TrC,TFC = Clock Input Rise 4.5V 25 15 ns 1 and Fall Times 5.5V 25 15 ns 1 3 Two Input Clock Width 4.5V 62 41 ns 1 5.5V 62 41 ns 1 4 Tint Timer Input Low Width 4.5V 70 70 ~ ns 1 5.5V 70 70 ns 1 5 TwTinH — Timer Input High Width 4.5V 5TpC 5TpC 1 5.5V 5TpC 5TpC 1 6 ‘TpTin Timer Input Period 4.5V 8TpC 8TpCc 1 5.5V 8TpC 8TpC 1 7 TrTin, Timer input Rise 4.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100 400 ns 1 8 TIL Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwlH Int. Request Input 4.5V 5TpCc STpC 1,2 High Time ~5.6V 5TpC 5TpC 12 10 “Twat Watch-Dog Timer 4.5V 10 10 ms 1 Delay Time for Timeout 5.5V 10 10 ms 1 1 Tpor Power-On Reset Time 4.5V 12 100 12 100 ms 1 5.5V 12 100 12 100 ms 1 Notes: 1. Timing Reference uses 0.7 Vgc for a logic 1 and 0.2 Veg for a logic 0. 2. Interrupt request made through Port 3 (P33-P31).
16 PRELIMINARY DS97Z8X1104
Zilog CMOS Zé OTP Microcontrollers etter liidiitihtetlaahidl AC ELECTRICAL CHARACTERISTICS Low Noise Mode, Standard Temperature ee Ta= 0 °C to 470°C
1 MHz 4 MHz
No Symbol Parameter Veo Min Max Min Max Units Notes 1 TPC Input Clock Period 4.5V 1000 [oye] 250 Pye} ns 1 5.5V 1000 bc 250 DC ns 1 2 TrC Clock Input Rise 4.5V 26 25 ns 1 TIC and Fall Times 5.5V 25 25 ns 1 3 TwC Input Clock Width 4.5V 500 125 ns 1 5.5V 500 125 ns 1 4, TwTint, Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 1 5.5V_2.51pC 2.51 pC 1
6 Tptin Timer Input Period 45V_4TpC 4TpC 1
5.5V 4TpC 4TpC 1 7 Trin, Timer Input Rise 4.5V 100 100 ns 1 TtTin and Fall Time 5.5V 100. 100 ns 1 8 TIL Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 12 9 TwiIH Int. Request Input 4.5V 2.5TpC 2.5TpC 1,2 High Time 5.5V_2.5TpC 2.5TpC 1,2 10 Twat Watch-Dog Timer 4.5V 12 12 ms 1 Delay Time for Timeout ~~ §.5V 12 12 ms 1 Notes: 1. Timing Reference uses 0.7 Veg for a logic 1 and 0.2 Vag for a logic 0. 2. Interrupt request through Port 3 (P33-P31). DS97Z8X1104 PRELIMINARY 17
CMOS Z8 OTP Microcontrollers Zilog ——— AC ELECTRICAL CHARACTERISTICS (Continued) Low Noise Mode, Extended Temperature Ta= 40 °C to +105 °C No Symbol Parameter Vee Min Max Min Max Units Notes 1 TPC Input Clock Period 4.5V 1000 DC 250 DC ns 1 5.5V 1000 bc 250 DC ns 1 2 TrC Clock Input Rise 4.5V 25 25 ns 1 TIC and Fall Times 5.5V 25 25 ns 1 3 TwC Input Clock Width 4.5V 500 125 ns 1 5.5V 500 125 ns 1 4, TWTinl Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 Twin Timer Input High Width 45V_2.5TpC 2.5TpC 1 5.5V 2.5TpC 2.5TpC 1 6 TpTin Timer Input Period 4.5V 4TpC 4TpC 1 5.5V 4TpC 4TpC ~ 1 7 TrTin, Timer Input Rise 4.5V 100 100 ns 1 TiTin and Fall Time ~~ 5.5V 100 100 ns 1 8 Twi Int. Request Input 4.5V 70 70 ns 1,2 Low Time 5.5V 70 70 ns 1,2 9 TwiH Int. Request Input 4.5V 2.5TpC 2.5TpC 1,2 High Time 5.5V_2.51pC 2.5TpC 4,2 10 Twat Watch-Dog Timer 4.5V 10 10 ms 1 Delay Time for Timeout 5.5V 10 10 ms 1 Notes: 1. Timing Reference uses 0.7 Vag for a logic 1 and 0.2 Veg for a logic 0. 2. Interrupt request through Port 3 (P33-P31).
18 PRELIMINARY DS97Z8X1104
Zilog CMOS Z8 OTP Microcontrollers LL _ LOW NOISE VERSION Low EMI Emission ™ Output drivers have resistances of 500 Ohms (typical). The Z86E04/E08 can be programmed to operate in a Low B Oscillator divi -two circuitry elimi EMI Emission Mode by means of a mask ROM bit option. scilator divide-by-two circuitry eliminated. Use of this feature results in: The Low EMI Mode is mask-programmable to be selected lm Allpre-driver slew rates reduced to 10 ns typical. by the customer at the time the ROM code is submitted. @ = Internal SCLK/TCLK operation limited to a maximum of 4 MHz-250 ns cycle time. ee PIN FUNCTIONS OTP Programming Mode Clock Address Clock. This pin is a clock input. The internal D7-D0 Data Bus. Data can be read from, or written to, the address counter increases by one with one clack cycle. EPROM through this data bus. PGM Program Mode (active Low). A Low level at this pin Voc Power Supply. It is typically 5V during EPROM Read programs the data to the EPROM through the Data Bus. Mode and 6.4V during the other modes (Program, Pro- It gram Verity, and so on). Application Precaution The production test-mode environment may be enabled CE Chip Enable (active Low). This pin is active during accidentally during normal operation if excessive noise EPROM Read Mode, Program Mode, and Program Verify surges above Vg occur on the XTAL1 pin. Mode. __ In addition, processor operation of Z8 OTP devices may be OE Output Enable (active Low). This pin drives the Data _ affected by excessive nolse surges on the Vpp, CE, EPM, Bus direction. When this pin is Low, the Data Busis output. OE pins while the microcontroller is in Standard Mode. When High, the Data Bus is input. Recommendations for dampening voltage surges in both EPM EPROM Program Mode. This pin controls the differ- test and OTP Mode include the following: ent EPROM Program Modes by applying different voltages. @ Using a clamping diode to Vgg. Vpp Program Voltage. This pin supplies the program volt- | ™ Adding a capacitor to the affected pin. age. Clear Clear (active High). This pin resets the internal ad- | Note: Programming the EPROM/Test Mode Disable dress counter at the High Level. option will prevent accidental entry into EPROM Mode or Test Mode. DS97Z8X1104 PRELIMINARY 19
(8 MHz or 12 MHz max) to the on-chip clock oscillator and reduces excessive supply current flow in the input buffer. Port 0, P02—P00. Port 0 is a 3-bit bidirectional, Schmitt- Auto Latches enabled. Figure 7. Port 0 Configuration
20 PRELIMINARY DS97Z8X1104
These eight I/O lines can be configured under software ther push-pull or open-drain (Figure 8). Figure 8. Port 2 Configuration
lines can be configured under software control as digital ure 9). Schmitt-trigger inputs or analog inputs. Figure 9. Port 3 Configuration
22 PRELIMINARY DS97Z8X1104
comparators reference voltage P33 (REF) is common to __tios are 90 dB and 60 dB, respectively. Typical applications for the on-board comparators; Zero _ output, or on the falling edge of Comparator 1's output. (P33) for use as IRQ1 and/or P33 input. Figure 10. Internal Reset Configuration following conditions: board RC oscillator.
Table 3. Control Registers be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
24 PRELIMINARY DS97Z8X1104
register addressing using the Register Pointer. eral-purpose registers. Proactive tence ssuwer gausenes driven by the internal clock source only (Figure 14). R quest IRQ4 (TO) or IRQS (T1) is generated. 2 areas tinue counting (Modulo-N Continuous Mode). “Expanded Register Group (0) i selected inthis figure gate input for the internal clock. by handing bis D3 to DO as *0"in Register RZESIRP. Figure 13. Register Pointer
26 PRELIMINARY DS97Z8X1104
- Note: By passed, if Low EMI Mode is selected.
Figure 14. Counter/Timers Block Diagram
(Figure 15). The sources are divided as follows: the falling determine which of the interrupt requests needs service. workaround must be employed). Figure 15. Interrupt Block Diagram
28 PRELIMINARY DS97Z8X1104
ramic resonator, or any suitable external clock source from each pin directly to device ground pin 14 (Figure 16). be AT cut, up to 12 MHz max., with a series resistance to Vgg, Pin 14 to reduce Ground noise injection. (RS) of less than or equal to 100 Ohms. Figure 16. Oscillator Configuration
Table 5. Typical Frequency vs. RC Values Table 6. Typicat Frequency vs. RC Values
30 PRELIMINARY DS97Z8X1104
Zilog CMOS Z8 OTP Microcontrollers LL __.. HALT Mode. This instruction turns off the internal CPU = Watch-Dog Timer (WDT). The Watch-Dog Timer is en- clock but not the crystal oscillation. The counter/timers and —_abled by instruction WDT. When the WDT is enabled, it external interrupts IRQO, IRQ1, IRQ2 and IRQ3 remain ac- —_ cannot be stopped by the instruction. With the WDT in- tive. The device is recovered by interrupts, either external- _struction, the WDT is refreshed when it is enabled within ly or internally generated. An interrupt request must be ex- —_ every 1 Twat period; otherwise, the controller resets itself, ecuted (enabled) to exit HALT Mode. After the interrupt © The WDT instruction affects the flags accordingly; Z=1, service routine, the program continues from the instruction S=0, V=0. after the HALT. WOT = 5F (Hex) Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode. Opcode WDT (5FH). The first time Opcode 5FH is execut- STOP Mode. This instruction turns off the internal clock eo, re Dn As enabled and subsequ atleast avery Tee and external crystal oscillation and reduces the standby otherwise, the WDT times out and generates a reset. The current to 10 yA. The STOP Mode is released bya RESET generated reset is the same as a power-on reset of Tpop, through a Stop-Mode Recovery (pin P27). A Low input plus 18 XTAL clock cycles. The software enabled WDT condition on P27 releases the STOP Mode. Program exe- dogg not run in STOP Mode. cution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the /O port Mode reg- ~— Opcode WDH (4FH). When this instruction is executed it isters are not reconfigured to their default power-on condi- enables the WDT during HALT. If not, the WDT stops tions. This prevents any I/O, configured as output when the — when entering HALT. This instruction does not clear the STOP instruction was executed, from glitching to an un- —_ counters, it just makes it possible to have the WDT running known state. To use the P27 release approach with STOP —_ during HALT Mode. A WOH instruction executed without Mode, use the following instruction: executing WDT (5FH) has no effect. LD P2M, #1XXX XXXXB Permanent WDT. Selecting the hardware enabled Perma- NOP nent WDT option, will automatically enable the WDT upon STOP exiting reset. The permanent WDT will always run in HALT 7 Mode and STOP Mode, and it cannot be disabled. X = Dependent on user's application. Auto Reset Voltage (V_\\). The Z8 has an auto-reset built- Note: A low level detected on P27 pin will take the device —_in. The auto-reset circuit resets the Z8 when it detects the out of STOP Mode even if configured as an output. Veg below Viy. In order to enter STOP or HALT Mode, it is necessary to Figure 17 shows the Auto Reset Voltage versus tempera- first flush the instruction pipeline to avoid suspending exe- —_ture. If the Voce drops below the VCC operating voltage Cution in mid-instruction. To do this, the user executes a range, the Z8 will function down to the Vy unless the inter- NOP (opcode=FFH) immediately before the appropriate —_ nal clock frequency is higher than the specified maximum SLEEP instruction, such as: Viy frequency. FF NOP ; Clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; Clear the pipeline TF HALT enter HALT Mode DS97Z8X1104 PRELIMINARY 31
Figure 17. Typical Auto Reset Voltage
32 PRELIMINARY DS97Z8X1104
@ Ailldrivers slew rates reduced to 10 ns (typical). ™ Output drivers have resistances of 500 ohms (typical). both a diode and a 100 pF capacitor. programmed will globally disable all Auto Latches. In addition to Vpp and GND (Vgg), the Z8 changes all its pin . . Table 7. OTP Programming Table
- Vin= As per specific Z8 DC specification.
- V= As per specific Z8 DC specification.
- X = Not used, but must be set to V,, or Viy level.
- NU = Not used, but must be set to either V,, or Vi, level.
- Ipp during programming = 40 mA maximum.
- Iog during programming, verify, or read = 40 mA maximum.
- * Voc has a tolerance of +0.25V.
(Clock). Each clock signal increases the address by one _shows the timing of programming waveforms. address input. of the Z8 programming algorithm. Table 8. Timing of Programming Waveforms
1 Address Setup Time 2 my
2 Data Setup Time 2 us
3 V,p Setup 2 us
4 Vee Setup Time 2 ps
5 Chip Enabie Setup Time 2 as
7 Data Hold Time 2 ps
8 OE Setup Time 2 fry
9 Data Access Time 188 ns
10 Data Output Float Time 100 ns
12 EPM Setup Time 2 us
13 PGM Setup Time 2 ys
14 Address to OE Setup Time 2 us
15 Option Program Pulse Width 78 ms
16 OE Width 250 ns
17 Address Valid to OF Low 125 ns
34 PRELIMINARY DS97Z8X1104
Figure 18. Z86E04/E08 Address Counter Waveform
CMOS Z8 OTP Microcontrollers Zilog NN FUNCTIONAL DESCRIPTION (Continued) VIH. Adiress vi Address Stable VIH ®@ Data i VIH @ Vit. | mf ; EPM 1 Vib Ne Veo Q a J—_ cE a OE VIL ve HOt Hr PGM ] Vit _ Figure 19, Z86E04/E08 Programming Waveform (EPROM Read)
36 PRELIMINARY DS97Z8X1104
Figure 20. Z86E04/E08 Programming Waveform
Figure 21. Z86E04/E08 Programming Options Waveform
38 PRELIMINARY DS97Z8X1104
Figure 22. Z86E04/E08 Programming Options Waveform
Figure 23. Z86E04/E08 Programming Algorithm
40 PRELIMINARY DS97Z8X1104
0 Disable TO Count 01-00 HEX)
1 Enable TO Count To Current Value
1 Load T+
0 Disable T1 Count
00 External Clock Input
01 Gate Input
Figure 24. Timer Mode Register (F1,,; Read/Write) 1 0 ModuioN Figure 25. Counter Timer 1 Reglster (F2,,; Read/Write) eo} >s]o«] oes Jo
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 29. Port 2 Mode Register (F6,,: Write Only)
0 Digital Mode
Figure 26. Prescaler 1 Register (F3,,: Write Only) Reserved (Must be 0) Figure 30. Port 3 Mode Register (F7,,: Write Only)
Figure 34. Interrupt Mask Register Figure 31. Port 0 and 1 Mode Reglster Figure 32. interrupt Priority Register Troan Regier rt Figure 33. Interrupt Request Register
42 PRELIMINARY DS97Z8X1104
Zilog ‘ CMOS Z8 OTP Microcontrollers MOS 28 OTP Microcontrotiors
PACKAGE INFORMATION
. j [roo meweren ner T at [Tosi [os | 020 | ose _| a ee [cs [aaa ass [as er | [ e | zee [eis | 300 | a20_| [si | eee [eae [ees | oss | [eas te [00 | [Tea [yer [aes | aio] ase [ou [sie [ae [ies 7 aso _| [a | use [36s | 060 | 065 _| Ls] oes [16s [035 | 065_| n co f 42 CONTROLLING DIMENSIONS « INCH Lt AL Ss @ B 18-Pin DIP Package Diagram ° [ne] Sconnaaaa T [ew a | ma faw faa Poe Pa [a | ose | 046 | 0014 | 0018 | qi: 7 Te [ozs | 030 | o.009 | oor ee ee [aa oe — qe) Teno [oss Dee Te HHUYRYE EE t RE OHRGEGE VS ee Te ase Career ar Tose Poon] at a | SOORESA San eo ts wx al J Le dL, ‘SEATING PLANE oe. Lt 18-Pin SOIC Package Diagram ee DS97Z8X1104 PRELIMINARY 43
CMOS Z8 OTP Microcontrollers Zilog LN
ORDERING INFORMATION
Standard Temperature Standard Temperature 18-Pin DIP 18-Pin SOIC 18-Pin DIP 18-Pin SOIC Z86E0412PSC Z86E0412SSC Z86E0812PSC Z86E0812SSC Z86E0412PEC Z86E0412SEC Z86E0812PEC Z86E0812SEC For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Codes Preferred Package Speeds P = Plastic DIP 12 =12 MHz Longer Lead Time Environmental $= SOIC C = Plastic Standard Preferred Temperature S$ =0°C to +70°C E=-40°C to +105°C Example: Z 86E04 12 PSC is a Z86E04, 12 MHz, DIP, 0°C to +70°C, Plastic Standard Flow L Environmental Flow Temperature Package Speed Product Number Zilog Prefix
44 PRELIMINARY DS97Z8xX1104
Zilog . Preliminary Product Specification DS97Z8X1104 eS Pre-Characterization Product: The product represented by this CPS is newly introduced —_ found, either by Zilog or its customers in the course of and Zilog has not completed the full characterization of the further application and characterization work. In addition, product. The CPS states what Zilog knows about this Zilog cautions that delivery may be uncertain at times, due product at this time, but additional features or to start-up yield issues. nonconformance with some aspects of the CPS may be © 1998 by Zilog, Inc. All rights reserved. No part of this Zilog, Inc. shall not be responsible for any errors that may document may be copied or reproduced in any form or by —_ appear in this document. Zilog, Inc. makes no commitment any means without the prior written consent of Zilog, Inc. to update or keep current the information contained in this The information in this document is subject to change document. without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing —Zilog’s products are not authorized for use as critical in Zilog, Inc. Terms and Conditions of Sale only. components in life support devices or systems unless a specific written agreement pertaining to such intended use ZILOG, INC. MAKES NO WARRANTY, EXPRESS, _ is executed between the customer and Zilog prior to use. STATUTORY, IMPLIED OR BY DESCRIPTION, Life support devices or systems are those which are REGARDING THE INFORMATION SET FORTH HEREIN __ intended for surgical implantation into the body, or which OR REGARDING THE FREEDOM OF THE DESCRIBED sustains life whose failure to perform, when properly used DEVICES FROM INTELLECTUAL PROPERTY in accordance with instructions for use provided in the INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY labeling, can be reasonably expected to result in OF MERCHANTABILITY OR FITNESS FOR ANY _ significant injury to the user. PURPOSE. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com oe