Microcontroller

Z86E0812PSC1866

Zilog, Inc.

CMOS Z8 OTP MICROCONTROLLERS

Manufacturer: Zilog, Inc.

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P RELIMINARY P RODUCT S PECIFICATION Z86E04/E08 CMOS Z8 OTP M ICROCONTROLLERS PRODUCT DEVICES Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the us- er’s application requirements. Part Oscillator Operating Operating ROM Number Type V CC Temperature (KB) Package Z86E0412PEC Crystal 4.5V–5.5V –40 C/105 C 1 18-Pin DIP Z86E0412PSC1866 Crystal 4.5V–5.5V 0 C/70 C 1 18-Pin DIP Z86E0412PSC1903 RC 4.5V–5.5V 0 C/70 C 1 18-Pin DIP Z86E0412PEC1903 RC 4.5V–5.5V –40 C/105 C 1 18-Pin DIP Z86E0412SEC Crystal 4.5V–5.5V –40 C/105 C 1 18-Pin SOIC Z86E0412SSC1866 Crystal 4.5V–5.5V 0 C/70 C 1 18-Pin SOIC Z86E0412SSC1903 RC 4.5V–5.5V 0 C/70 C 1 18-Pin SOIC Z86E0412SEC1903 RC 4.5V–5.5V –40 C/105 C 1 18-Pin SOIC Z86E0812PEC Crystal 4.5V–5.5V –40 C/105 C 2 18-Pin DIP Z86E0812PSC1866 Crystal 4.5V–5.5V 0 C/70 C 2 18-Pin DIP Z86E0812PSC1903 RC 4.5V–5.5V 0 C/70 C 2 18-Pin DIP Z86E0812PEC1903 RC 4.5V–5.5V –40 C/105 C 2 18-Pin DIP Z86E0812SEC Crystal 4.5V–5.5V –40 C/105 C 2 18-Pin SOIC Z86E0812SSC1866 Crystal 4.5V–5.5V 0 C/70 C 2 18-Pin SOIC Z86E0812SSC1903 RC 4.5V–5.5V 0 C/70 C 2 18-Pin SOIC Z86E0812SEC1903 RC 4.5V–5.5V –40 C/105 C 2 18-Pin SOIC

CMOS Z8 OTP Microcontrollers Zilog P R E L I M I N A R Y DS97Z8X1104

FEATURES

14 Input/Output Lines

n Six Vectored, Prioritized Interrupts (3 falling edge, 1 rising edge, 2 timers) n Two Analog Comparators n Program Options: – Low Noise – ROM Protect – Auto Latch – Watch-Dog Timer (WDT) – EPROM/Test Mode Disable n Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler n WDT/ Power-On Reset (POR) n On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock n Clock-Free WDT Reset n Low-Power Consumption (50 mw typical) n Fast Instruction Pointer (1 m s @ 12 MHz) n RAM Bytes (125) GENERAL DESCRIPTION Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zilog’s single-chip Z8 MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under soft- ware control to provide timing, status signals, or parallel I/O. Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data com- munications. Note: All Signals with an overline, “ ”, are active Low, for example: B/W (WORD is active Low); B/W (BYTE is active Low, only). Power connections follow conventional descriptions be- low: Connection Circuit Device Power V CC V DD Ground GND V SS

Figure 1. Functional Block Diagram

Figure 2. EPROM Programming Mode Block Diagram

Figure 3. 18-Pin EPROM Mode Conﬁguration Table 1. 18-Pin DIP Pin Identiﬁcation

6 NC No Connection

9 EPM EPROM Prog Mode Input

11 Clear Clear Clock Input

12 Clock Address Input

13 PGM

14 GND Ground

Figure 4. 18-Pin DIP/SOIC Mode Conﬁguration Table 2. 18-Pin DIP/SOIC Pin Identiﬁcation

8 P31 Port 3, Pin 1, AN1 Input

9 P32 Port 3, Pin 2, AN2 Input

10 P33 Port 3, Pin 3, REF Input

CMOS Z8 OTP Microcontrollers Zilog P R E L I M I N A R Y DS97Z8X1104 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; functional operation of the device at any condition above those indicated in the oper- ational sections of these specifications is not implied. Ex- posure to absolute maximum rating conditions for an ex- tended period may affect device reliability. Total power dissipation should not exceed 462 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = V DD x [I DD –(sum of I OH + sum of [(V DD OH ) x I OH + sum of (V x I Parameter Min Max Units Note Ambient Temperature under Bias –40 +105 C Storage Temperature –65 +150 C Voltage on any Pin with Respect to V SS –0.7 +12 V 1 Voltage on V DD Pin with Respect to V SS –0.3 +7 V Voltage on Pins 7, 8, 9, 10 with Respect to V SS –0.6 V DD +1 V 2 Total Power Dissipation 1.65 W Maximum Allowable Current out of V SS 300 mA Maximum Allowable Current into V DD 220 mA Maximum Allowable Current into an Input Pin –600 +600 mA3 Maximum Allowable Current into an Open-Drain Pin –600 +600 mA4 Maximum Allowable Output Current Sinked by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Total Maximum Output Current Sinked by a Port 60 mA Total Maximum Output Current Sourced by a Port 45 mA Notes: 1. This applies to all pins except where otherwise noted. Maximum current into pin must be – 600 mA. 2. There is no input protection diode from pin to VDD (not applicable to EPROM Mode). 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state.

TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Figure 5. Test Load Diagram

CMOS Z8 OTP Microcontrollers Zilog

8 P R E L I M I N A R Y DS97Z8X1104

DC ELECTRICAL CHARACTERISTICS Standard Temperature TA = 0°C to +70°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes VINMAX Max Input Voltage 4.5V 12 V I In<250 mA 1 5.5V 12 V I In<250 mA 1 VCH Clock Input High Voltage 4.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator 5.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V V SS –0.3 0.2 V CC 1.7 V Driven by External Clock Generator 5.5V V SS –0.3 0.2 V CC 1.7 V Driven by External Clock Generator VIH Input High Voltage 4.5V 5.5V

0.7 VCC

VCC +0.3 VCC +0.3 2.8 2.8 V V VIL Input Low Voltage 4.5V 5.5V VSS –0.3 VSS –0.3

0.2 VCC

1.5 1.5 V V VOH Output High Voltage 4.5V V CC –0.4 4.8 V I OH = –2.0 mA 5 5.5V V CC –0.4 4.8 V I OH = –2.0 mA 5 4.5V V CC –0.4 4.8 V Low Noise @ I OH = –0.5 mA 5.5V V CC –0.4 4.8 V Low Noise @ I OH = –0.5 mA VOL1 Output Low Voltage 4.5V 0.8 0.1 V I OL = +4.0 mA 5 5.5V 0.4 0.1 V I OL = +4.0 mA 5 4.5V 0.4 0.1 V Low Noise @ I OL = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ I OL = 1.0 mA VOL2 Output Low Voltage 4.5V 0.8 0.8 V I OL = +12 mA, 5 5.5V 0.8 0.8 V I OL = +12 mA, 5 VOFFSET Comparator Input Offset Voltage 4.5V 25.0 10.0 mV 5.5V 25.0 10.0 mV VLV VCC Low Voltage Auto Reset 2.2 3.0 2.8 V @ 6 MHz Max. Int. CLK Freq. IIL Input Leakage (Input Bias Current of Comparator) 4.5V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC IOL Output Leakage 4.5V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC VICR Comparator Input Common Mode Voltage Range CC –1.0 V

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 9 TA = 0°C to +70°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes ICC Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 2 MHz 5,7 5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 2 MHz 5,7 4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz 5,7 5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz 5,7 4.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz 5,7 5.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz 5,7 ICC1 Standby Current 4.5V 4.0 2.5 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5,7 5.5V 4.0 2.5 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5,7 4.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 8 MHz 5,7 5.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 8 MHz 5,7 4.5V 7.0 4.0 mA HALT Mode V IN = 0V, VCC @ 12 MHz 5,7 5.5V 7.0 4.0 mA HALT Mode V IN = 0V, VCC @ 12 MHz 5,7 ICC Supply Current (Low Noise Mode) 4.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz 4.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz 5.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz 5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz

CMOS Z8 OTP Microcontrollers Zilog

10 P R E L I M I N A R Y DS97Z8X1104

DC ELECTRICAL CHARACTERISTICS (Continued) TA = 0°C to +70°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes ICC1 Standby Current (Low Noise Mode) 4.5V 4.0 2.5 mA HALT Mode V IN = 0V, VCC @ 1 MHz 5.5V 4.0 2.5 mA HALT Mode V IN = 0V, VCC @ 1 MHz 4.5V 4.5 2.8 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5.5V 4.5 2.8 mA HALT Mode V IN = 0V, VCC @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 4 MHz 5.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 4 MHz ICC2 Standby Current 4.5V 10.0 1.0 mA STOP Mode V IN = 0V, VCC WDT is not Running 7,8 5.5V 10.0 1.0 mA STOP Mode V IN = 0V,VCC WDT is not Running 7,8 IALL Auto Latch Low Current 4.5V 32.0 16 mA 0V < V IN < VCC 5.5V 32.0 16 mA 0V < V IN < VCC IALH Auto Latch High Current 4.5V –16.0 –8.0 mA 0V < V IN < VCC 5.5V –16.0 –8.0 mA 0V < V IN < VCC Notes: 1. Port 2 and Port 0 only 2. V SS = 0V = GND 3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases. 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at V CC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level.

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 11 DC ELECTRICAL CHARACTERISTICS Extended Temperature TA = –40°C to +105°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes VINMAX Max Input Voltage 4.5V 12.0 V I IN < 250 mA1 5.5V 12.0 V I IN < 250 mA1 VCH Clock Input High Voltage 4.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator 5.5V 0.8 V CC VCC +0.3 2.8 V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V V SS –0.3 0.2 VCC 1.7 V Driven by External Clock Generator 5.5V V SS –0.3 0.2 VCC 1.7 V Driven by External Clock Generator VIH Input High Voltage 4.5V 0.7 V CC VCC +0.3 2.8 V 5.5V 0.7 V CC VCC +0.3 2.8 V VIL Input Low Voltage 4.5V V SS –0.3 0.2 VCC 1.5 V 5.5V V SS –0.3 0.2 VCC 1.5 V VOH Output High Voltage 4.5V V CC –0.4 4.8 V I OH = –2.0 mA 5 5.5V V CC –0.4 4.8 V I OH = –2.0 mA 5 4.5V V CC –0.4 V Low Noise @ I OH = –0.5 mA 5.5V V CC –0.4 V Low Noise @ I OH = –0.5 mA VOL1 Output Low Voltage 4.5V 0.4 0.1 V I OL = +4.0 mA 5 5.5V 0.4 0.1 V I OL = +4.0 mA 5 4.5V 0.4 0.1 V Low Noise @ I OL = 1.0 mA 5.5V 0.4 0.1 V Low Noise @ I OL = 1.0 mA VOL2 Output Low Voltage 4.5V 1.0 0.3 V I OL = +12 mA, 5 5.5V 1.0 0.3 V I OL = +12 mA, 5 VOFFSET Comparator Input Offset Voltage 4.5V 25.0 10.0 mV 5.5V 25.0 10.0 mV VLV VCC Low Voltage Auto Reset CLK Freq. IIL Input Leakage (Input Bias Current of Comparator) 4.5V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC IOL Output Leakage 4.5V –1.0 1.0 mAV IN = 0V, VCC 5.5V –1.0 1.0 mAV IN = 0V, VCC VICR Comparator Input Common Mode Voltage Range 0 V CC –1.5 V

CMOS Z8 OTP Microcontrollers Zilog

12 P R E L I M I N A R Y DS97Z8X1104

DC ELECTRICAL CHARACTERISTICS (Continued) ICC Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 2 MHz 5,7 5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 2 MHz 5,7 4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz 5,7 5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz 5,7 4.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz 5,7 5.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz 5,7 ICC1 Standby Current 4.5V 5.0 2.5 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5,7 5.5V 5.0 2.5 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5,7 4.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 8 MHz 5,7 5.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 8 MHz 5,7 4.5V 7.0 4.0 mA HALT Mode V IN = 0V, VCC @ 12 MHz 5,7 5.5V 7.0 4.0 mA HALT Mode V IN = 0V, VCC @ 12 MHz 5,7 ICC Supply Current (Low Noise Mode) 4.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz 5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz 4.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz 5.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz 4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz 5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz TA = –40°C to +105°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 13 TA = –40°C to +105°C Typical Sym Parameter VCC [4] Min Max @ 25 °C Units Conditions Notes ICC1 Standby Current (Low Noise Mode) 4.5V 4.0 2.5 mA HALT Mode V IN = 0V, VCC @ 1 MHz 5.5V 4.0 2.5 mA HALT Mode V IN = 0V, VCC @ 1 MHz 4.5V 4.5 2.8 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5.5V 4.5 2.8 mA HALT Mode V IN = 0V, VCC @ 2 MHz 4.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 4 MHz 5.5V 5.0 3.0 mA HALT Mode V IN = 0V, VCC @ 4 MHz ICC2 Standby Current 4.5V 20 1.0 mA STOP Mode V IN = 0V, VCC WDT is not Running 7,8 5.5V 20 1.0 mA STOP Mode V IN = 0V, VCC WDT is not Running 7,8 IALL Auto Latch Low Current 4.5V 40 16 mA 0V < V IN < VCC 5.5V 40 16 mA 0V < V IN < VCC IALH Auto Latch High Current 4.5V –20.0 –8.0 mA 0V < V IN < VCC 5.5V –20.0 –8.0 mA 0V < V IN < VCC Notes: 1. Port 2 and Port 0 only 2. V SS = 0V = GND 3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases. 4. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at V CC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level.

14 P R E L I M I N A R Y DS97Z8X1104

Figure 6. AC Electrical Timing Diagram

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 15 AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Standard Temperature

15 TA = 0 °C to +70 °C

8 MHz 12 MHz

No Symbol Parameter VCC Min Max Min Max Units Notes 1 TpC Input Clock Period 4.5V 125 DC 83 DC ns 1 5.5V 125 DC 83 DC ns 1

2 TrC,TfC Clock Input Rise

4.5V 25 15 ns 1 5.5V 25 15 ns 1 3 TwC Input Clock Width 4.5V 62 41 ns 1 5.5V 62 41 ns 1 4 TwTinL Timer Input Low Width 4.5V 100 100 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 1 5.5V 5TpC 5TpC 1 6 TpTin Timer Input Period 4.5V 8TpC 8TpC 1 5.5V 8TpC 8TpC 1

7 TrTin,

4.5V 100 100 ns 1 5.5V 100 100 ns 1 8 TwIL Int. Request Input Low Time 4.5V 70 70 ns 1,2 5.5V 70 70 ns 1,2 9 TwIH Int. Request Input High Time 4.5V 5TpC 5TpC 1,2 5.5V 5TpC 5TpC 1,2

10 Twdt Watch-Dog Timer

4.5V 12 12 ms 1 5.5V 12 12 ms 1

11 Tpor

Power-On Reset Time 4.5V 20 80 20 80 ms 1 5.5V 20 80 20 80 ms 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31).

CMOS Z8 OTP Microcontrollers Zilog

16 P R E L I M I N A R Y DS97Z8X1104

AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Extended Temperature TA = –40 °C to +105 °C No Symbol Parameter VCC Min Max Min Max Units Notes 1 TpC Input Clock Period 4.5V 125 DC 83 DC ns 1 5.5V 125 DC 83 DC ns 1 4.5V 25 15 ns 1 5.5V 25 15 ns 1 3 TwC Input Clock Width 4.5V 62 41 ns 1 5.5V 62 41 ns 1 4 TwTinL Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 1 5.5V 5TpC 5TpC 1 6 TpTin Timer Input Period 4.5V 8TpC 8TpC 1 5.5V 8TpC 8TpC 1 4.5V 100 100 ns 1 5.5V 100 100 ns 1 8 TwIL Int. Request Input Low Time 4.5V 70 70 ns 1,2 5.5V 70 70 ns 1,2 9 TwIH Int. Request Input High Time 4.5V 5TpC 5TpC 1,2 5.5V 5TpC 5TpC 1,2 4.5V 10 10 ms 1 5.5V 10 10 ms 1 Power-On Reset Time 4.5V 12 100 12 100 ms 1 5.5V 12 100 12 100 ms 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request made through Port 3 (P33–P31).

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 17 AC ELECTRICAL CHARACTERISTICS Low Noise Mode, Standard Temperature TA = 0 °C to +70 °C

1 MHz 4 MHz

No Symbol Parameter VCC Min Max Min Max Units Notes 1 TPC Input Clock Period 4.5V 1000 DC 250 DC ns 1 5.5V 1000 DC 250 DC ns 1 2T r C TfC Clock Input Rise and Fall Times 4.5V 25 25 ns 1 5.5V 25 25 ns 1 3 TwC Input Clock Width 4.5V 500 125 ns 1 5.5V 500 125 ns 1 4. TwTinL Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 1 5.5V 2.5TpC 2.5TpC 1 6 TpTin Timer Input Period 4.5V 4TpC 4TpC 1 5.5V 4TpC 4TpC 1 4.5V 100 100 ns 1 5.5V 100 100 ns 1

8 TwIL

Int. Request Input 4.5V 70 70 ns 1,2 5.5V 70 70 ns 1,2

9 TwIH

Int. Request Input 4.5V 2.5TpC 2.5TpC 1,2 5.5V 2.5TpC 2.5TpC 1,2 4.5V 12 12 ms 1 5.5V 12 12 ms 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31).

CMOS Z8 OTP Microcontrollers Zilog

18 P R E L I M I N A R Y DS97Z8X1104

AC ELECTRICAL CHARACTERISTICS (Continued) Low Noise Mode, Extended Temperature TA = –40 °C to +105 °C No Symbol Parameter VCC Min Max Min Max Units Notes 1 TPC Input Clock Period 4.5V 1000 DC 250 DC ns 1 5.5V 1000 DC 250 DC ns 1 2T r C TfC Clock Input Rise and Fall Times 4.5V 25 25 ns 1 5.5V 25 25 ns 1 3 TwC Input Clock Width 4.5V 500 125 ns 1 5.5V 500 125 ns 1 4. TwTinL Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 1 5.5V 2.5TpC 2.5TpC 1 6 TpTin Timer Input Period 4.5V 4TpC 4TpC 1 5.5V 4TpC 4TpC 1 4.5V 100 100 ns 1 5.5V 100 100 ns 1 8 TwIL Int. Request Input Low Time 4.5V 70 70 ns 1,2 5.5V 70 70 ns 1,2 9 TwIH Int. Request Input High Time 4.5V 2.5TpC 2.5TpC 1,2 5.5V 2.5TpC 2.5TpC 1,2 4.5V 10 10 ms 1 5.5V 10 10 ms 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31).

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 19 LOW NOISE VERSION Low EMI Emission The Z86E04/E08 can be programmed to operate in a Low EMI Emission Mode by means of a mask ROM bit option. Use of this feature results in: n All pre-driver slew rates reduced to 10 ns typical. n Internal SCLK/TCLK operation limited to a maximum of 4 MHz–250 ns cycle time. n Output drivers have resistances of 500 Ohms (typical). n Oscillator divide-by-two circuitry eliminated. The Low EMI Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted. PIN FUNCTIONS OTP Programming Mode D7–D0 Data Bus. Data can be read from, or written to, the EPROM through this data bus. VCC Power Supply. It is typically 5V during EPROM Read Mode and 6.4V during the other modes (Program, Pro- gram Verify, and so on). CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the differ- ent EPROM Program Modes by applying different voltages. V PP Program Voltage. This pin supplies the program volt- age. Clear Clear (active High). This pin resets the internal ad- dress counter at the High Level. Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle. PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above VCC occur on the XTAL1 pin. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP , CE, EPM, OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP Mode include the following: n Using a clamping diode to VCC . n Adding a capacitor to the affected pin. Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or Test Mode.

20 P R E L I M I N A R Y DS97Z8X1104

reduces excessive supply current flow in the input buffer. Figure 7. Port 0 Conﬁguration

directional, Schmitt-triggered CMOS-compatible I/O port. ther push-pull or open-drain (Figure 8). Figure 8. Port 2 Conﬁguration

22 P R E L I M I N A R Y DS97Z8X1104

Schmitt-trigger inputs or analog inputs. Figure 9. Port 3 Conﬁguration

serve as a reference voltage to the comparators. tios are 90 dB and 60 dB, respectively. output, or on the falling edge of Comparator 1's output. (P33) for use as IRQ1 and/or P33 input. tecture to provide the user with increased design flexibility. Figure 10. Internal Reset Conﬁguration

18 CLK

24 P R E L I M I N A R Y DS97Z8X1104

Table 3. Control Registers be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.

26 P R E L I M I N A R Y DS97Z8X1104

register addressing using the Register Pointer. starting location of the active working-register group. driven by the internal clock source only (Figure 14). quest IRQ4 (T0) or IRQ5 (T1) is generated. tinue counting (Modulo-N Continuous Mode). gate input for the internal clock. Figure 13. Register Pointer the active working-register group. by handling bits D3 to D0 as "0" in Register R253(RP).

Note: By passed, if Low EMI Mode is selected.

Figure 14. Counter/Timers Block Diagram

28 P R E L I M I N A R Y DS97Z8X1104

interrupt requests (Table 4). that particular interrupt request. determine which of the interrupt requests needs service. workaround must be employed). Table 4. Interrupt Types, Sources, and Vectors Figure 15. Interrupt Block Diagram

(RS) of less than or equal to 100 Ohms. from each pin directly to device ground pin 14 (Figure 16). SS , Pin 14 to reduce Ground noise injection. Figure 16. Oscillator Conﬁguration

30 P R E L I M I N A R Y DS97Z8X1104

Table 5. Typical Frequency vs. RC Values Table 6. Typical Frequency vs. RC Values

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 31 HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac- tive. The device is recovered by interrupts, either external- ly or internally generated. An interrupt request must be ex- ecuted (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 mA. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program exe- cution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode reg- isters are not reconfigured to their default power-on condi- tions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an un- known state. To use the P27 release approach with STOP Mode, use the following instruction: Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output. In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, such as: Watch-Dog Timer (WDT). The Watch-Dog Timer is en- abled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT in- struction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time Opcode 5FH is execut- ed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every T WDT ; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of T POR , plus 18 XTAL clock cycles. The software enabled WDT does not run in STOP Mode. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect. Permanent WDT. Selecting the hardware enabled Perma- nent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT Mode and STOP Mode, and it cannot be disabled. Auto Reset Voltage (V LV). The Z8 has an auto-reset built- in. The auto-reset circuit resets the Z8 when it detects the V CC below VLV. Figure 17 shows the Auto Reset Voltage versus tempera- ture. If the VCC drops below the VCC operating voltage range, the Z8 will function down to the VLV unless the inter- nal clock frequency is higher than the specified maximum V LV frequency. LD P2M, #1XXX XXXXB NOP STOP X = Dependent on user's application. FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode

32 P R E L I M I N A R Y DS97Z8X1104

Figure 17. Typical Auto Reset Voltage

n Less than 1 mA consumed during HALT Mode. n All drivers slew rates reduced to 10 ns (typical). maximum of 4 MHz–250 ns cycle time. n Output drivers have resistances of 500 ohms (typical). n Oscillator divide-by-two circuitry eliminated. both a diode and a 100 pF capacitor. programmed will globally disable all Auto Latches. Table 7. OTP Programming Table

VIH = As per specific Z8 DC specification.
VIL= As per specific Z8 DC specification.
X = Not used, but must be set to VH or VIH level.
NU = Not used, but must be set to either VIH or VIL level.
IPP during programming = 40 mA maximum.
ICC during programming, verify, or read = 40 mA maximum.
* VCC has a tolerance of –0.25V.

34 P R E L I M I N A R Y DS97Z8X1104

shows the timing of programming waveforms. of the Z8 programming algorithm. Table 8. Timing of Programming Waveforms

1 Address Setup Time 2 ms

2 Data Setup Time 2 ms

5 Chip Enable Setup Time 2 ms

7 Data Hold Time 2 ms

9 Data Access Time 188 ns

10 Data Output Float Time 100 ns

12 EPM Setup Time 2 ms

14 Address to OE Setup Time 2 ms

15 Option Program Pulse Width 78 ms

17 Address Valid to OE Low 125 ns

Figure 18. Z86E04/E08 Address Counter Waveform

0 Min

36 P R E L I M I N A R Y DS97Z8X1104

Figure 19. Z86E04/E08 Programming Waveform

Figure 20. Z86E04/E08 Programming Waveform

38 P R E L I M I N A R Y DS97Z8X1104

Figure 21. Z86E04/E08 Programming Options Waveform

Figure 22. Z86E04/E08 Programming Options Waveform

40 P R E L I M I N A R Y DS97Z8X1104

Figure 23. Z86E04/E08 Programming Algorithm

Figure 24. Timer Mode Register (F1H : Read/Write) Figure 25. Counter Timer 1 Register (F2H : Read/Write) Figure 26. Prescaler 1 Register (F3H : Write Only)

0 Disable T0 Count

1 Enable T0 Count

0 No Function

1 Load T0

1 Load T1

0 Disable T1 Count

1 Enable T1 Count

00 External Clock Input

01 Gate Input

10 Trigger Input

Figure 27. Counter/Timer 0 Register Figure 28. Prescaler 0 Register (F5H : Write Only) Figure 29. Port 2 Mode Register (F6H : Write Only) Figure 30. Port 3 Mode Register (F7H : Write Only)

0 T0 Single Pass

1 T0 Modulo N

0 Defines Bit as OUTPUT

1 Defines Bit as INPUT

0 Port 2 Open-Drain

1 Port 2 Push-pull

0 Digital Mode

1 Analog Mode

42 P R E L I M I N A R Y DS97Z8X1104

Figure 31. Port 0 and 1 Mode Register Figure 32. Interrupt Priority Register Figure 33. Interrupt Request Register Figure 34. Interrupt Mask Register Figure 35. Flag Register Figure 36. Register Pointer Figure 37. Stack Pointer

1 Enables IRQ0-IRQ5

1 Enables Interrupts

Zilog CMOS Z8 OTP Microcontrollers DS97Z8X1104 P R E L I M I N A R Y 43

PACKAGE INFORMATION

18-Pin DIP Package Diagram 18-Pin SOIC Package Diagram

CMOS Z8 OTP Microcontrollers Zilog

44 P R E L I M I N A R Y DS97Z8X1104

ORDERING INFORMATION

For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Codes Preferred Package P = Plastic DIP Longer Lead Time S = SOIC Preferred Temperature S = 0°C to +70°C E = –40°C to +105°C Speeds 12 =12 MHz Environmental C = Plastic Standard © 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com Standard Temperature 18-Pin DIP 18-Pin SOIC Z86E0412PSC Z86E0412SSC Z86E0412PEC Z86E0412SEC Standard Temperature 18-Pin DIP 18-Pin SOIC Z86E0812PSC Z86E0812SSC Z86E0812PEC Z86E0812SEC Example: Z 86E04 12 P S C Environmental Flow T emperature Package Speed Product Number Zilog Prefix is a Z86E04, 12 MHz, DIP, 0°C to +70°C, Plastic Standard Flow

Product Information

Z86E0812PSC1866 specifications and overview.

Summary

CMOS Z8 OTP MICROCONTROLLERS

Description

CMOS Z8 OTP MICROCONTROLLERS

Source title Z86E0812PSC1866 Datasheet(PDF) - Zilog, Inc.

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