Z86E09 ZILOG | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 38

Technical content

ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Programming Specification PS009201-0301 Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www .ZiLOG.com Windows is a registered trademark of Microsoft Corporation. Document Disclaimer © 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

Z8 CMOS OTP Microcontrollers PS009201-0301 iii Table of Contents

Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions . . . 17

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification General Description The EPROM Programming interface is a byte-wide data interface with 7 control inputs and a 17-wire connection. This document describes the EPROM interface pertinent to the following parts: Top-Level Programming After powering up, the programming sequence begins by sending the unlock code sequence, followed by the mode selection. The program address must be reset to 0000h after entering EPROM mode. The first data byte to be programmed is then loaded on Port 2. When the programming control sequence is applied, the pro- gramming pulse commences. Data is then verified for correct programming. If the data is incorrect, a count begins to record the number of programming pulse cycles before success is finally achieved. If the data is not programmed after N MAX attempts, it is a failed part. If data is verified, then it must be overpro- grammed for a minimum of 3 times the cumulative programming time. The address counter is then incremented to the next address. The next data byte is sent, and programming continues using the same basic algorithm. See Figure 1. Z86E02 SL1995 Z86E04 SL1995 Z86E08 SL1995 Z86E09 SL1995

Figure 1. Top-Level Programming Sequence

sequence details the unlock procedure. The following unlock sequence is valid for all parts. not the internal Z8 SCLK cycles.

  1. A POR must be completed before unlock operations begin. The X
  2. Any time after POR, when the internal signal IRESET is Low. The unlock

sequence can be sent. See Figure 6 and Table 4.

  1. Apply one clock pulse to X
  2. Force the Port 2 pins with
  3. Apply one clock pulse to the X
  4. Force the Port 2 pins with

Table 3. EPROM Size

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification 8. Apply one clock pulse to X IN 9. Force the Port 2 pins with F0h 10. Apply one clock pulse to X IN 11. Force the Port 2 pins with 0Fh 12. Apply one clock pulse to X IN 13. Force the Port 2 pins with 00h 14. Apply one clock pulse to X IN 15. Force the Port 2 pins with F1h 16. Apply one clock pulse to X IN 17. Force the Port 2 pins with 00h 18. Apply one clock pulse to X IN 19. The part is now in EPROM mode. The only way to exit EPROM mode is to perform a POR. All signals must be stable before the X IN (CE) pin is pulsed High and can- not change until X IN (CE) pin is in a V IL state. The signal should be stable for a minimum of 1µsec. Note:

Figure 6. Unlock Sequence

  1. The device enters EPROM mode at this point when X

Table 4. Unlock Sequence Conditions Table 5. Power-On Reset Pin Conditions

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification EPROM Array Modes EPROM ARRAY READ/WRITE Mode Entry 1. To enter EPROM ARRAY READ/WRITE mode, all pins must be set as per Table 7. 2. EPM is lowered to V IL. 3. OE is lowered to VIL. 4. The V PP is raised to VIH. 5. The CLEAR is pulsed High to V IH and back down to VIL. 6. The V PP is lowered to VIL. 7. After a delay of at least 1µsec minimum, the V PP is raised to VIH. 8. OE is raised to VIH. 9. EPM is raised to V IH. 10. The device now operates in EPROM ARRAY READ/WRITE mode. See Figure 8. The delay between edges should be 1µsec minimum unless specified in the timing specification in Table 14. Note:

Figure 8. EPROM ARRAY READ/WRITE Mode Entry Functional Timing Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions

  1. Perform Steps 1 through 6 of the EPROM ARRAY READ/WRITE mode entry

page) before proceeding to Step 2.

  1. Reset the address counter by pulsing the CLEAR pin. See Figure 9 and

Table 8. Please refer to T

  1. The address counter is incremented on the rising edge of the CLOCK signal.
  2. After resetting the address counter using the CLEAR pin, the address counter
  3. The READ operation is performed by lowering OE

on Port2. Pins P20 to P27 represent the EPROM data D0 to D7, respectively. corresponds to a 0 level stored in the EPROM array. ing EPROM READ mode and data access time.

  1. The next address is read by pulsing the clock pin High, then forcing OE to VIL

and bringing it back High after the data is read.

  1. Repeat Step 7 until the final address is read.
  2. Because the address is sequentially accessed, a previously-accessed

clocking the address counter to increment to the appropriate address. Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions (Continued)

Figure 9. EPROM ARRAY READ Mode Functional Timing Table 8. EPROM ARRAY READ Mode Conditions

  1. Perform the EPROM ARRAY READ/WRITE mode entry (see the EPROM
  2. Reset the address counter by pulsing the CLEAR pin. See Figure 10 and

Table 9. Please refer to Table 14 for minimum and maximum widths of the

  1. The address counter is incremented on the rising edge of the CLOCK signal.
  2. After resetting the address counter using the CLEAR pin, the address counter
  3. The PROGRAM operation is performed by lowering PGM

Figure 10. Please refer to Table 14 for minimum and maximum widths of the

  1. The PROGRAM operation is complete when PGM is raised back to VIH.
  2. The VERIFY operation is performed by lowering OE to VIL and reading the

corresponds to a 0 level stored in the EPROM array.

  1. Please refer to Table 14 for the minimum and maximum width of OE during

EPROM Read mode and data access time.

  1. If the data read shows that the address location is not yet programmed, then
  2. If the address location is not programmed after the 25th try, then the device is
  3. If the address location is programmed, then the address location is

overprogrammed with three times the total accumulated program time.

  1. The next address is accessed by pulsing the CLOCK High to V

Table 8. EPROM ARRAY READ Mode Conditions (Continued)

  1. Repeat Steps 5 to 12 until the last address is read.
  2. Because the address is sequentially accessed, a previously-accessed

Figure 10. EPROM ARRAY PROGRAM AND VERIFY Functional Timing Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions

Table 10 lists the device’s available option bits and their default states.

  1. To enter OPTION BIT PROGRAM AND VERIFY mode, all pins must be set as

per Table 11. The initial state for VPP and CLEAR is VIL while OE is at VIH.

  1. CLEAR is pulsed High to V IH, then Low to VIL. See Table 14 for specifications
  2. After a delay of at least 1µs minimum, V PP is raised to VIH.

Note: Option bits are 0 when programmed and 1 when unprogrammed. Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions (Continued)

  1. After a delay of at least 1µs minimum from V PP rising, OE is raised to VIH.
  2. The CLOCK is raised to V IH.
  3. OE is pulsed Low to VIL, then High to VIH.
  4. The CLOCK is lowered to V IL.
  5. Repeat steps 7 to 9 six more times.
  6. After a delay of at least 1µs minimum, EPM is raised to V
  7. The device is now in OPTION BIT READ/WRITE mode. See Figure 11.

Figure 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Functional Timing Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions

  1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT

PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2.

  1. The CLOCK is pulsed High to V IH, then Low to VIL. Please refer to Table 14 for
  2. The 8 option bit values required in T
  3. The PROGRAM operation is performed by lowering PGM to VIL. Please refer
  4. The PROGRAM operation is complete when the PGM is raised back to VIH.
  5. The VERIFY operation is performed by lowering OE to VIL, then reading the

a VOL level corresponds to a 0 level stored in the EPROM array. ing EPROM READ mode and data access time.

  1. If the data read shows that the address location is not yet programmed, then

Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions (Continued)

  1. If the address location is not programmed after the 25th try, then the device is
  2. If the address location shows that it is programmed, then the address location

is then overprogrammed with three times the total accumulated program time. Figure 12. OPTION BIT PROGRAM AND VERIFY Functional Timing

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification OPTION BIT READ Mode Operation 1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2. 2. CLOCK is pulsed High to V IH, then Low to VIL. Please refer to Table 14 for the minimum and maximum width values of the CLOCK signal. 3. The 8 option bit values required in Table 10 are read from Port2. Option bits D0 to D7 correspond to Port2 pins P20 to P27. Please refer to Table 14 for setup and hold times. 4. The OPTION BIT READ operation is performed by lowering OE to VIL and reading the data on Port2. Pins P20 to P27 represent the option bit data D0 to D7, respectively. See Figure 13. 5. A V OH-level READ on Port2 corresponds to a 1 state, while a VOL-level corresponds to a 0 level stored in the EPROM array. 6. Please refer to Table 14 for the minimum and maximum width of OE during EPROM READ mode and data access time. OE Pin 8 Pin 9 See Figure 12 EPM Pin 9 Pin 10 V IH VPP Pin 10 Pin 11 V IH CLEAR Pin 11 Pin 12 See Figure 12 CLOCK Pin 12 Pin 13 See Figure 12 PGM Pin 13 Pin 14 See Figure 12 Table 12.OPTION BIT PROGRAM AND VERIFY Mode Conditions (Continued)

The following steps outline the power-down operation of the Z86E0x device.

  1. Set up the I/O pins per Figure 14 and Table 13.
  2. V CC is lowered from 5.0V to 2.0V.

Figure 13. OPTION BIT READ Mode Functional Timing

Figure 14. Power-Down Functional Timing

Table 14. Voltage specifications are provided in Table 15. Figure 15. Z86E0x EPROM ARRAY and OPTION BIT PROGRAM AND VERIFY Waveform* Note: *EPROM bits are 0 when programmed, and 1 when unprogrammed.

1 Address setup time 2 µs

2 Chip Enable setup time 2 µs

3 PGM

4 Address to OE setup time 2 µs

5 Data setup time 2 µs

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification Figure 16 illustrates additional timing for the device. Table 16 provides the timing specifications identified in Figure 16.

8 Data hold time 2 µs

9O E setup time 2 µs

10 Data access time 188 ns

12 Data output float time 100 ns

Table 15.Voltage Specifications Symbol Description 20ºC to 30ºC Typical UnitMin Max VPROG Programming supply voltage 4.75 5.25 5.0 V IPROG Programming supply current 50 mA VIH Input High Voltage 0.7 x V PROG VPROG+0.3 2.6 V VIL Input Low Voltage GND –0.3 0.2 x V PROG 1.6 V VOH Output High Voltage V PROG–0.4 4.8 V VOL Output Low Voltage 1.0 0.8 V Table 14.Timing Specifications (Continued) Parameters Name Min Max Units

Figure 16. Z86E0x Additional Timing Waveform

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification Programming Flow Figures 17 and 18 illustrate the flow of the EPROM ARRAY PROGRAM, VERIFY, and READ operations. Figures 19 and 20 illustrate the flow of the OPTION BIT PROGRAM, VERIFY, and READ operations. T11 CLEAR to Address Counter Out Delay 15ns T12 CLOCK Rising to OE Falling 1µs T13 Data Access Time 188ns Table 16.Z86E0x Additional Timing Specifications (Continued) Parameter Name Timing Minimum Maximum

Figure 17. EPROM ARRAY PROGRAM, VERIFY, and READ Algorithm

Figure 18. EPROM ARRAY READ Algorithm

Figure 19. OPTION BIT PROGRAM, VERIFY, and READ Algorithm Note: *It is assumed that the user has already selected the option bits prior to this step.

Figure 20. OPTION BIT READ Algorithm Note: *It is assumed that the user has already selected the option bits prior to this step.

user code and option bits into OTP.

  • Blank check
  • Examine OTP code
  • Program/verify code and option bits
  • Verify code
  • Checksum of OTP

Figure 21. Third-Party Top-Level Algorithm

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification

  • Checksum of buffer/RAM
  • Program option bits as a sole option
  • Read option bits as a sole option Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconfor- mance with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addi- tion, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. ZiLOG, Inc.

910 East Hamilton Avenue, Suite 110

Campbell, CA 95008 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www .zilog.com

Z8 CMOS OTP Microcontrollers PS009201-0301 Programming Specification Third Party Developer Feedback Form The Z86E02/E04/E08/E09 SL1995 Programming Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Third Party Developer Information Third Party Developer Product Information Return Information ZiLOG Worldwide Customer Support Center

4201 Bee Caves Road, Suite C-100

Austin, TX, USA 78746 Phone: 1-877-945-6427 Fax: (512) 306-4042 Email: customerfeedback@zilog.com Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. Name Country Company Phone Address Fax City/State/Zip E-Mail Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type