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ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Preliminary Product Specification PS019402-1103 Z86D73 40/44/48-Pin Low-Voltage IR OTP
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40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y iii Table of Contents
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y
Features
Table 1 shows the features of the Z86D73. Low power consumption–40 mW (typical) Three standby modes Stop—2 µA (typical) Halt—0.8 mA (typical) Low voltage Special architecture to automate both generation and reception of complex pulses or signals: One programmable 8-bit counter/timer with two capture registers and two load registers One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair Programmable input glitch filter for pulse reception Six priority interrupts Three external Two assigned to counter/timers One low-voltage detection interrupt Low-voltage detection with flag Programmable watch-dog/power-on reset circuits Two independent comparators with programmable interrupt polarity Mask selectable pull-up transistors on ports 0, 1, 2 Programmable mask options Oscillator selection: RC oscillator versus crystal or other clock source Table 1. Features
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Oscillator operational mode: normal high-frequency operation enabled or 32-KHz operation enabled Port 0: 0–3 pull-ups Port 0: 4–7 pull-ups Port 1: 0–3 pull-ups Port 1: 4–7 pull-ups Port 2: 0–7 pull-ups Port 0: 0–3 mouse mode: normal mode (.5VDD input threshold) versus mouse mode (.4VDD input threshold) The mask option pull-up transistor has a typical equivalent resistance of 200 KΩ ±50% at VCC=3 V and 450 KΩ ±50% at VCC=2 V. General Description The Z86D73 is an OTP-based member of the MCU family of IR (infrared) micro- controllers. With 237 bytes of general-purpose RAM and 32 KB of ROM, ZiLOG’s CMOS microcontrollers offer fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/ reception, and internal key-scan pull-up transistors. The Z86D73 architecture is based on ZiLOG’s 8-bit microcontroller core with an Expanded Register File to allow access to register-mapped peripherals, input/out- put (I/O) circuits, and powerful counter/timer circuitry. The Z8 offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancil- lary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications. There are four basic address spaces available to support a wide range of configu- rations: Program Memory, Register File, Expanded Register File, and External Memory. The register file is composed of 256 bytes of RAM. It includes 4 I/O port registers, 16 control and status registers, and 236 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Z86D73 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see Figure 1). Also included are a large number of user- selectable modes and two on-board comparators to process analog signals with separate reference voltages (see Figure 2). Note:
Power connections use the conventional descriptions listed in Table 2. Figure 1. Counter/Timers Diagram Table 2. Power Connections
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Figure 2. Functional Block Diagram
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Pin Description The pins are shown in Figure 3, Figure 4, Figure 5, and Figure 6. The pins are described in Table 3. Figure 3. 40-Pin DIP Pin Assignment R/W P25 P26 P27 P04 P05 P06 P14 P15 P07 VDD P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 AS DS P24 P23 P22 P21 P20 P03 P13 P12 VSS P02 P11 P10 P01 P00 Pref1 P36 P37 P35 RESET Z86D73 DIP
Table 3. Pin Identification
Table 3. Pin Identification (Continued)
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Absolute Maximum Ratings Stresses greater than those listed in Table 4 might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifica- tions is not implied. Exposure to absolute maximum rating conditions for an extended period might affect device reliability. 1, 2, 34 17, 28, 29 24, 37, 38 VSS Pref1 R/RL Table 4. Absolute Maximum Ratings
Description
Supply Voltage (*) –0.3 +7.0 V TSTG Storage Temperature –65° +150° C TA Oper. Ambient Temperature. C Notes: *Voltage on all pins with respect to GND. †See Ordering Information on page 85.
the referenced pin (see Figure 7). The capacitances are listed in Table 5. Table 5. Capacitance
Table 6. DC Characteristics
0.8 VCC
0.2 VCC
0.7 VCC
8.0 MHz
8 MHz max
*All outputs excluding P00, P01, P36, and P37.
- All outputs unloaded, inputs at rail.
- 32-kHz clock driver input.
- The VBO increases as the temperature decreases, except inputs at VCC.
- Oscillator stops when VCC falls below VLV limit.
- VBO increases as the temperature decreases.
Table 6. DC Characteristics (Continued) the above peripherals is enabled.
Table 7. External I/O or Memory Read and Write Timing (Preliminary)
Figure 9 and Table 8 describe additional timing characteristics. 1.When using extended memory timing, add 2 TpC.
- Timing numbers given are for minimum TpC.
- Standard Test Load: All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
Table 7. External I/O or Memory Read and Write Timing (Preliminary) (Continued)
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Figure 9. Additional Timing Clock Stop Mode Recovery Source Clock Setup TIN IRQN
Table 8. Additional Timing
WRITE operations, the falling edge of DS indicates that output data is valid. Address Strobe is pulsed one time at the beginning of each machine cycle.
- Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
- Interrupt request through Port 3 (P33–P31).
- Interrupt request through Port 3 (P30).
- For internal RC oscillator.
Table 8. Additional Timing (Continued)
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC net- work to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC net- work to the on-chip oscillator output. R/W Read/Write (Output, Write Low) The R/W signal is Low when the CCP is writing to the external program or data memory. R/RL (Input) This pin, when connected to GND, disables the internal ROM and forces the device to function as a ROMless Z8. When left unconnected or pulled high to VCC, the part functions normally as a Z8 ROM version. Port 0 (P07–P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port or as an address port for interfacing external memory. The output drivers are push-pull or open-drain con- trolled by bit D2 in the PCON register. For external memory references, Port 0 can provide address bits A11–A8 (lower nibble) or A15–A8 (lower and upper nibble), depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for address- ing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. Port 0 is set in the high-impedance mode (if selected as an address output), along with Port 1 and the control signals AS, DS, and R/W through P3M bits D4 and D3 (see Figure 10). A ROM mask option is available to program 0.4 VDD CMOS trip inputs on P00– P03. This option allows direct interface to mouse/trackball IR sensors. Note:
pins when programmed into output mode. Figure 10. Port 0 Configuration
0.4 VDD
more than 256 external locations are required, Port 0 outputs the additional lines. DMA applications. Port 1 can also be configured for standard port output mode. push-pull or open-drain and are controlled by bit D1 in the PCON register. Figure 11. Port 1 Configuration
eight bits of Port 2 configured as inputs. Figure 12. Port 2 Configuration
figured under software control for interrupt and as output from the counter/timers. Figure 13. Port 3 Configuration
edge detect and IRQ modes are described in Table 9. these inputs must be placed into digital mode. Table 9. Pin Assignments
Figure 14. Port 3 Counter/Timer Output Configuration
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Comparator Inputs In analog mode, P31 and P32 have a comparator front end. The comparator refer- ence is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as indicated in Figure 13 on page 23. In digital mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Comparators are powered down by entering Stop Mode. For P31–P33 to be used in a Stop-Mode Recovery source, these inputs must be placed into digital mode. Comparator Outputs These channels can be programmed to be output on P34 and P37 through the PCON register. RESET (Input, Active Low) Reset initializes the MCU and is accomplished either through Power-On, Watch- Dog Timer, Stop-Mode Recovery, Low-Voltage detection, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin Low for the POR time. Any devices driving the external reset line need to be open-drain in order to avoid damage from a possible conflict dur- ing reset conditions. Pull-up is provided internally. Functional Description The Z86D73 incorporates special functions to enhance the Z8’s functionality in consumer and battery-operated applications. Program Memory The Z86D73 addresses 32 KB of OTP memory. The first 12 bytes are reserved for interrupt vectors. These locations contain the five 16-bit vectors that correspond to the five available interrupts. RAM The Z86D73 device features 256 bytes of RAM. See Figure 15. Note:
Figure 15. Program Memory Map (32K OTP)
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Expanded Register File The register file has been expanded to allow for additional system control regis- ters and for mapping of additional peripheral devices into the register address area. The Z8 register address space (R0 through R15) has been implemented as 16 banks, with 16 registers per bank. These register groups are known as the ERF (Expanded Register File). Bits 7–4 of register RP select the working register group. Bits 3–0 of register RP select the expanded register file bank. An expanded register bank is also referred to as an expanded register group (see Figure 16). Note:
Figure 16. Expanded Register File Architecture
exchanges the lower 16 registers to an expanded register bank. Figure 17. Register Pointer
; register group 7 of bank 0 for access. the starting location of the active working register group. working registers and indirect addressing modes. Figure 18. Register Pointer—Detail active working-register group.
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Stack The Z86D73 internal register file is used for the stack. An 8-bit Stack Pointer (R255) is used for the internal stack that resides in the general-purpose registers (R4–R239). SPH is used as a general-purpose register only when using internal stacks. When SPH is used as a general-purpose register and Port 0 is in address mode, the contents of SPH are loaded into Port 0 whenever the internal stack is accessed Table 10.Expanded Register Group D (D)0Ch LVD (D)0Bh HI8 (D)0Ah LO8 (D)09h HI16 (D)08h LO16 (D)07h TC16H (D)06h TC16L (D)05h TC8H (D)04h TC8L (D)03h Reserved (D)02h CTR2 (D)01h CTR1 (D)00h CTR0 Note:
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Register Description LVD(D)0Ch Low-Voltage Detection Register The LVD flag will be valid after enabling the detection for 20 µS (design estimation, not tested in production). LVD does not work at STOP mode. It must be disabled during STOP mode in order to reduce current. Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. HI8(D)0Bh This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register is used to hold the number of counts when the input signal is 1. L08(D)0Ah This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register is used to hold the number of counts when the input signal is 0. Field Bit Position R LV flag set LV flag reset R/W Enable LVD Disable LVD *Default after POR Field Bit Position T8_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position T8_Capture_L0 76543210 R W Captured Data No Effect Note: Note:
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y HI16(D)09h This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the MS-Byte of the data. L016(D)08h This register holds the captured data from the output of the 16-bit Counter/ Timer16. this register holds the LS-Byte of the data. TC16H(D)07h Counter/Timer2 MS-Byte Hold Register TC16L(D)06h Counter/Timer2 LS-Byte Hold Register TC8H(D)05h Counter/Timer8 High Hold Register Field Bit Position T16_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position T16_Capture_LO 76543210 R W Captured Data No Effect Field Bit Position T16_Data_HI 76543210 R/W Data Field Bit Position T16_Data_LO 76543210 R/W Data Field Bit Position T8_Level_HI 76543210 R/W Data
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y TC8L(D)04h Counter/Timer8 Low Hold Register CTR0 Counter/Timer8 Control Register Table 11 lists and briefly describes the fields for this register. T8 Enable This field enables T8 when set (written) to 1. Field Bit Position T8_Level_LO 76543210 R/W Data Table 11. CTR0 (D)00 Counter/Timer8 Control Register T8_Enable R W Counter Disabled Counter Enabled Stop Counter Enable Counter Single/Modulo-N R/W Modulo-N Single Pass Time_Out R W No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T8 _Clock ---43--- R/W 0 0 0 1 1 0 1 1 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_MASK -----2-- R/W Disable Data Capture Int. Enable Data Capture Int. Counter_INT_Mask R/W Disable Time-Out Int. Enable Time-Out Int. P34_Out R/W P34 as Port Output T8 Output on P34 Note: *Indicates the value upon Power-On Reset.
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Single/Modulo-N When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to its location. Writing a 1 is the only way to reset the Terminal Count status condition. Therefore, reset this bit before using/enabling the counter/timers. The first clock of T8 might not have complete clock width and can occur any time when enabled. Care must be taken when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. Example When the status of bit 5 is 1, a timer reset condition occurs. T8 Clock This bit defines the frequency of the input signal to T8. Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. Caution: Note:
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y CTR1(D)01h This register controls the functions in common with the T8 and T16. Table 12 lists and briefly describes the fields for this register. Table 12.CTR(D)01h T8 and T16 Common Functions Field Bit Position Value P36_Out/ Demodulator_Input R/W Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 T8/T16_Logic/ Edge _Detect --54---- R/W Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit_Submode/ Glitch_Filter ----32-- R/W Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter
4 SCLK Cycle
8 SCLK Cycle
Initial_T8_Out/ Rising Edge R/W R W Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Mode If the result is 0, the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. P36_Out/Demodulator_Input In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/ Timers is from P20 or P31. T8/T16_Logic/Edge _Detect In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter In Transmit Mode, this field defines whether T8 and T16 are in the Ping-Pong mode or in independent normal operation mode. Setting this field to “Normal Operation Mode” terminates the “Ping-Pong Mode” operation. When set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In Demodulation Mode, this field defines the width of the glitch that must be fil- tered out. Initial_T8_Out/Rising_Edge In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This Initial_T16_Out/ Falling_Edge R/W R W Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0 Note: *Default upon Power-On Reset Table 12.CTR(D)01h T8 and T16 Common Functions (Continued) Field Bit Position Value
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset the mode, a 1 should be written to this location. Initial_T16 Out/Falling _Edge In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3; D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. CTR2 Counter/Timer 16 Control Register Table 13 lists and briefly describes the fields for this register. Table 13.CTR2 (D)02h: Counter/Timer16 Control Register Field Bit Position Value T16_Enable R W Counter Disabled Counter Enabled Stop Counter Enable Counter Single/Modulo-N R/W Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge Time_Out --5----- R W No Counter Timeout Counter Timeout Occurred No Effect Reset Flag to 0 Note:
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y T16_Enable This field enables T16 when set to 1. Single/Modulo-N In Transmit Mode, when set to 0, the counter reloads the initial value when the ter- minal count is reached. When set to 1, the counter stops when the terminal count is reached. In Demodulation Mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see the description of T16 Demodula- tion Mode on page 50. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. T16 _Clock ---43--- R/W SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W Disable Data Capture Int. Enable Data Capture Int. Counter_INT_Mask R/W Disable Timeout Int. Enable Timeout Int. P35_Out R/W P35 as Port Output T16 Output on P35 Note: *Indicates the value upon Power-On Reset. Table 13.CTR2 (D)02h: Counter/Timer16 Control Register (Continued) Field Bit Position Value
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Counter_INT_Mask Set this bit to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. SMR2 Stop-Mode Recovery Register 2 Table 14 lists and briefly describes the fields for this register. Table 14.SMR2(F)0Dh: Stop-Mode Recovery Register 2* Field Bit Position Value Reserved (Must be 0) Recovery Level W Low High Reserved --5----- Reserved (Must be 0) Source ---432-- W 000† 001 010 011 100 101 110 111 A. POR Only B. NAND of P23–P20 C. NAND of P27–P20 D. NOR of P33–P31 E. NAND of P33–P31 F. NOR of P33–P31, P00, P07 G. NAND of P33–P31, P00, P07 H. NAND of P33–P31, P22–P20 Reserved Reserved (Must be 0) Notes: * Port pins configured as outputs are ignored as a SMR recovery source. † Indicates the value upon Power-On Reset
D3, D2) are filtered out (see Figure 19). Figure 19. Glitch Filter Circuitry 1; if it is 1, T8_OUT is 0. See Figure 20.
Figure 20. Transmit Mode Flowchart
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). T8_OUT level and repeats the cycle. See Figure 21. Figure 21. 8-Bit Counter/Timer Circuits effect when they are loaded.
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y T8 Demodulation Mode Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh (see Figure 24 and Figure 25).
Figure 24. Demodulation Mode Count Capture Flowchart
Figure 25. Demodulation Mode Flowchart
and a status bit (CTR2, D5) is set. See Figure 26. Figure 26. 16-Bit Counter/Timer Circuits effect when they are loaded.
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 cap- tures and reloads on the next edge (rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent edges. This T16 mode is generally used to measure mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode is only valid in Transmit Mode. T8 and T16 must be pro- grammed in Single-Pass Mode (CTR0, D6; CTR2, D6), and Ping-Pong Mode must be programmed in CTR1, D3; D2. The user can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is dis- abled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Inter- rupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 29. Enabling Ping-Pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and then reset the status flags before instituting this operation. Note:
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y During Ping-Pong Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alter- nately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Interrupts The Z86D73 feature six different interrupts (Table 15). The interrupts are maskable and prioritized (Figure 31). The six sources are divided as follows: three sources are claimed by Port 3 lines P33–P31 and two by the counter/timers (Table 15). The Interrupt Mask Register (globally or individually) enables or dis- ables the five interrupt requests.
Figure 31. Interrupt Block Diagram
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y When more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle is activated when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All Z86D73 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Inter- rupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 16. Table 15.Interrupt Types, Sources, and Vectors Name Source Vector Location Comments IRQ0 P32 0,1 External (P32), Rising Falling Edge Triggered IRQ1 P33 2,3 External (P33), Falling Edge Triggered IRQ2 P31, TIN 4,5 External (P31), Rising Falling Edge Triggered IRQ3 T16 6,7 Internal IRQ4 8,9 Internal IRQ5 LVD 10,11 Internal Table 16.IRQ Register* IRQ Interrupt Edge IRQ2 (P31) IRQ0 (P32) F F F R R F R/F R/F Notes: F = Falling Edge; R = Rising Edge *In stop mode, the comparators are turned off.
are required. See Figure 32. capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 32). Figure 32. Oscillator Configuration
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Power-On Reset (POR) A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscilla- tor circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: Power Fail to Power OK status, including Waking up from VBO Standby Stop-Mode Recovery (if D5 of SMR = 1) WDT Timeout The POR timer is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC and LC oscillators). HALT HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/ timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain active. The devices are recovered by interrupts, either externally or internally gen- erated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP This instruction turns off the internal clock and external crystal oscillation, thereby reducing the standby current to 10 µA or less. STOP Mode is terminated only by a reset, such as WDT timeout, POR, SMR, or external reset. This condition causes the processor to restart the application program at address 000Ch. In order to enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspend- ing execution in mid-instruction. Execute a NOP (Op Code = FFh) immediately before the appropriate sleep instruction, as follows: FF NOP ; clear the pipeline STOP ; enter STOP Mode or FF NOP ; clear the pipeline HALT ; enter HALT Mode
located in the expanded register 2 at Bank F, location 00. Figure 33. Port Configuration Register (PCON) (Write Only) push-pull, and a 0 sets the output to open-drain. push-pull, and a 0 sets the output to open-drain.
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Mode Recovery (Figure 34). All bits are write only except bit 7, which is read only. Figure 34. Stop-Mode Recovery Register
0 OFF * *
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
0 OFF
1 ON *
0 Low *
1 High
0 POR *
1 Stop Recovery * *
sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0. Figure 35. SCLK Circuit
Figure 36. Stop-Mode Recovery Source
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Any Port 2 bit defined as an output drives the corresponding input to the default state. This condition allows the remaining inputs to control the AND/OR function. Refer to SMR2 register on page 63 for other recover sources. Stop-Mode Recovery Delay Select (D5) This bit, if low, disables the 5 ms RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the “fast” wake up is selected, the Stop- Mode Recovery source must be kept active for at least 5 TpC. Stop-Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86D73 from STOP Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR). Table 17.Stop-Mode Recovery Source SMR:432 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27 Note:
This register determines the mode of Stop-Mode Recovery for SMR2 (Figure 37). Figure 37. Stop-Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only)
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
nal count. The WDT must initially be enabled by executing the WDT instruction. organized as shown in Figure 38. Figure 38. Watch-Dog Timer Mode Register (Write Only)
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 18. WDTMR During HALT (D2) This bit determines whether or not the WDT is active during HALT Mode. A 1 indi- cates active during HALT. The default is 1. See Figure 39. Table 18.WDT Time Select* Timeout of Internal RC OSC Timeout of XTAL Clock 5 ms min
256 TpC
512 Tpc
1024 TpC
4096 TpC
Note: *TpC = XTAL clock cycle. The default on reset is 10 ms.
Figure 39. Resets and WDT This bit determines whether or not the WDT is active during STOP Mode. during STOP. The default is 1. configuration of this bit is 0, which selects the RC oscillator.
- CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers upon a Low-to-High input translation.
5 Clock Filter
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Mask Selectable Options There are seven Mask Selectable Options to choose from based on ROM code requirements. These are listed in Table 19. Brown-Out Voltage/Standby An on-chip Voltage Comparator checks that the VCC is at the required level for correct operation of the device. Reset is globally driven when VCC falls below VBO. A small drop in VCC causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. Typical Low-Voltage power consumpion in this Low Voltage Standby mode (ILV) is about 20 µA. If the VCC is allowed to stay above Vram, the RAM content is preserved. When the power level is returned to above VBO, the device performs a POR and functions normally. Low-Voltage Detection and Flag A Low-Voltage Detection circuit can be used optionally when the voltage decreases to VLVD. Expanded Register Bank 0Dh register 0Ch bits 0 and 1 are used for this option. Bit D0 is used to enable/disable this function; bit D1 is the sta- tus flag bit of the LVD. Table 19.Mask Selectable Options RC/Other RC/XTAL 32 kHz XTAL On/Off Port 00–03 Pull-Ups On/Off Port 04–07 Pull-Ups On/Off Port 10–13 Pull-Ups On/Off Port 14–17 Pull-Ups On/Off Port 20–27 Pull-Ups On/Off Port 3: Pull-Ups On/Off Port 0: 0–3 Normal Mode (0.5 VDD Input Threshold) versus Mouse Mode (0.4 VDD Input Threshold)
Figure 40. TC8 Control Register ((0D) OH: Read/Write Except Where Noted)
1 Timer8 Output
Figure 41. T8 and T16 Common Control Functions ((0D) 1h: Read/Write)
1 T16_OUT is 1 initially
1 T8_OUT is 1 initially
4 SCLK Cycle Filter
8 SCLK Cycle Filter
0 P36 as Port Output *
0 P31 as Demodulator Input
0 Transmit Mode *
is operating, the CTR1 bit has different functions. disabling the counter/timers. Figure 42. T16 Control Register ((0D) 2h: Read/Write Except Where Noted)
0 P35 is Port Output *
0 Disable T16 Timeout Interrupt
0 No T16 Timeout
1 T16 Timeout Occurs
0 Modulo-N for T16
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
0 T16 Disabled *
1 T16 Enabled
Figure 43. Low-Voltage Detection Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag.
Figure 44. Stop-Mode Recovery Register ((0F) 0Bh: D6–D0=Write Only, D7=Read
0 OFF *
Figure 45. Stop-Mode Recovery Register 2 ((0F) 0Dh:D2–D4, D6 Write Only) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
Figure 46. Watch-Dog Timer Register ((0F) 0Fh: Write Only)
Figure 49. Port 3 Mode Register (F7h: Write Only)
Figure 50. Port 0 and 1 Mode Register (F8h: Write Only)
Figure 51. Interrupt Priority Register (F9h: Write Only)
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
Figure 52. Interrupt Request Register (FAh: Read/Write) Figure 53. Interrupt Mask Register (FBh: Read/Write)
1 Enables IRQ5–IRQ0
Figure 60. 44-Pin QFP Package Design
Figure 61. 48-Pin SSOP Package Design coordinate for chip-on-board assembly.
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y
Ordering Information
For fast results, contact your local ZiLOG sales office for assistance in ordering the part desired. Codes Package P = Plastic DIP F = Plastic Quad Flat Pack H = SSOP V = Plastic Chip Carrier Speed 8 = 8 MHz Environmental C = Plastic Standard Temperature S = 0 °C to +70 °C Example Table 20.Z86D73 Ordering Information
8.0 MHz 40-Pin DIP
8.0 MHz 44-Pin PLCC
8.0 MHz 44-Pin QFP
8.0 MHz 48-Pin SSOP
Please contact ZiLOG. Z 86D73 08 P S C is a Z86D73, 8 MHz, DIP, 0 °C to 70 °C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix
40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconfor- mance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addi- tion, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues. ZiLOG, Inc. San Jose, CA 95126-3432 Telephone: (408) 558-8500 FAX: 408 558-8300 Internet: HTTP://WWW.ZILOG.COM