Z86C83 ZILOG | Alldatasheet
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Technical content
C USTOMER P ROCUREMENT S PECIFICATION
FEATURES
n 28-Pin DIP, SOIC, and PLCC Packages n Clock Speed: 16 MHz n Three Expanded Register Groups n 8-Channel, 8-Bit A/D Converter with Track and Hold, and Unique R-Ladder A GND Offset Control n Z86C84 has two 8-Bit D/A Converters with Programmable Gain Stages, 3 m s Settling Time n Six Vectored, Prioritized Interrupts from Six Different Sources n Two Analog Comparator Inputs with Programmable Interrupt Polarity n Two Programmable 8-Bit Timers, each with a 6-Bit Programmable Prescaler n Auto Latch Mask Option for P00, P01, and P02 n Power-On Reset (POR) Timer n Permanent Watch-Dog Timer (WDT) Mask Option n Software-Programmable Pull-Up Resistors n On-Chip Oscillator for Crystal, Resonator or LC GENERAL DESCRIPTION The Z86C83/C84 Consumer Controller Processors (CCP ) are full-featured members of the CMOS Z8 micro- controller family offering a unique register-to-register ar- chitecture that avoids accumulator bottlenecks for higher code efficiency than RISC processors. The Z86C83/C84 are designed to be used in a wide variety of embedded control applications, such as appliances, process controls, keyboards, security systems, battery chargers, and automotive modules. For applications requiring powerful I/O capabilities, the Z86C83/C84 devices can have up to 21/17 (C83/C84 respectively) pins dedicated to input and output. These lines are grouped into three ports, and are configured by software to provide digital/analog I/O timing and status signals. An on-chip, half-flash 8-bit 1/2 Least Significant Bit (LSB) A/D converter can multiplex up to eight analog inputs. Unused analog inputs revert to standard digital I/O use. Unique, programmable A GND offset control of the A/D resistor ladder compresses the converter's dynamic range for maximum effective 9-bit A/D resolution. The Z86C84 has two 8-bit 1/2 LSB D/A converters. High and low reference voltages provide precise control of the output voltage range. Programmable gain for each D/A converter provides a maximum effective 10-bit resolution for many tasks. On-chip 8-bit counter/timers with many user-selectable modes simplify real-time tasks, such as counting, timing, and generation of PWM signals. The designer can prioritize six different maskable, vectored, internal or external interrupts for efficient interrupt handling and multitasking functions. Z86C83/C84 MCU M ICROCONTROLLERS Device ROM (KB) RAM* (Bytes) I/O Lines Voltage Range Z86C83 4 237 21 3.0V to 5.5V Z86C84 4 237 17 3.0V to 5.5V Note: * General-Purpose
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counter/timers, and I/O port functions (Figure 1). Figure 1. Z86C83/C84 Functional Block Diagram
Table 1. Z86C83 28-Pin DIP, SOIC Pin Identification*
9 XTAL1 Oscillator Clock Input
10 XTAL2 Oscillator Clock Output
11 GND Ground
16 P34 Port 3, Bit 4 Output
17 P36 Port 3, Bit 6 Output
18 P35 Port 3, Bit 5 Output
28 P20
- DIP and SOIC Pin Description and Configuration are identical.
Figure 2. Z86C83 28-Pin DIP and SOIC Pin Table 2. Z86C84 28-Pin DIP, SOIC Pin Identification* Figure 3. Z86C84 28-Pin DIP and SOIC Pin
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Table 3. Z86C83 28-Pin PLCC Pin Identification
10 XTAL1 Oscillator Clock Input
11 XTAL2 Oscillator Clock Output
12 GND Ground
17 P34 Port 3, Bit 4 Output
18 P36 Port 3, Bit 6 Output
19 P35 Port 3, Bit 5 Output
Figure 4. Z86C83 28-Pin PLCC Pin Configuration Table 4. Z86C84 28-Pin PLCC Pin Identification Figure 5. Z86C84 28-Pin PLCC Pin Configuration
operational sections of these specifications is not implied. extended period may affect device reliability.
- This applies to all pins except XTAL and /RESET pins and where otherwise noted.
- There is no input protection diode from pin to V
- Device pin is not at an output Low state.
Figure 6. Test Load Diagram
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TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Min Max Input capacitance 0 20 pF Output capacitance 0 20pF I/O capacitance 0 20 pF
Z8® MCU Microcontrollers DS96DZ80203 7 DC ELECTRICAL CHARACTERISTICS Sym Parameter VCC Note 3 TA = 0° C to +70°C TA = –40°C to +105°C Typical [13] @ 25 °C Units Conditions NotesMin Max Min Max VCH Clock Input High Voltage Generator Generator VCL Clock Input Low Voltage Generator Generator VOH1 Output High Voltage VOL1 Output Low Voltage VOL2 Output Low Voltage 3.0V 1.2 1.2 0.3 V I OL = +6 mA 8 5.5V 1.2 1.2 0.3 V I OL = +12 mA 8 VRH Reset Input High Voltage 3.0V .8 V CC VCC .8 VCC VCC 1.5 V 5.5V .8 V CC VCC .8 VCC VCC 2.1 V VRl Reset Input Low Voltage VOFFSET Comparator Input Offset 3.0V 25 25 10 mV 10 Voltage 5.5V 25 25 10 mV 10 IIL Input Leakage 3.0V -1 1 -1 2 <1 mAV IN = OV, VCC 5.5V -1 1 -1 2 <1 mAV IN = OV, VCC IOL Output Leakage 3.0V -1 1 -1 2 <1 mAV IN = OV, VCC 5.5V -1 1 -1 2 <1 mAV IN = OV, VCC IIR Reset Input Current 3.0V -130 -130 -25 mA 5.5V -180 -180 -40 mA ICC Supply Current 3.0V 20 20 7 mA @ 16 MHz 4, 15 5.5V 25 25 20 mA @ 16 MHz 4, 15 5.0V 7 7 3 mA @ 3.58 MHz 4, 15 5.0V 10 10 5 mA @ 8 MHz 4, 15 I CC1 Standby Current 3.0V 4.5 4.5 2.0 mA HALT Mode V IN = OV, VCC @ 16 MHz 5.5V 8 8 3.7 mA HALT Mode V IN = OV, VCC @ 16 MHz 3.0V 3.4 3.4 1.5 mA Clock Divide-by-16 @ 16 MHz 4 5.5V 7.0 7.0 2.9 mA Clock Divide-by-16 @ 16 MHz 4
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ICC2 Standby Current 3.0V 8 15 1 mA STOP Mode V IN = OV, VCC WDT is not Running 6,11,15 5.5V 10 20 2 mA STOP Mode V IN = OV, VCC WDT is not Running 6,11,15 3.0V 500 600 310 mA STOP Mode V IN = OV, VCC WDT is Running 6,11,14, 5.5V 800 1000 600 mA STOP Mode V IN = OV, VCC WDT is Running 6,11,14, VICR Input Common Mode 3.0 0 V CC -1.0V 0 V CC -1.5V V 10 Voltage Range 5.5 0 V CC -1.0V 0 V CC -1.5V V 10 IALL Auto Latch Low Current 3.0V 8 10 5 mA OV < V IN < VCC 9 5.5V 15 20 11 mA OV < V IN < VCC 9 IALH Auto Latch High Current 3.0V -5 -7 -3 mA OV < V IN < VCC 9 5.5V -8 -10 -6 mA OV < V IN < VCC 9 VLV VCC Low-Voltage Protection Voltage Notes: 1. ICC1 Typical Max Unit Freq Clock-Driven 0.3 mA 5 mA 8 MHz 2. GND = 0V. 3. 3.0V V 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1 = CL2 = 100 pF. Same as note [4] except inputs at VCC . 7. The VLV increases as the temperature decreases. 8. Standard Mode (not Low EMI). 9. Auto Latch (mask option) selected. 10. For analog comparator, inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating. 12. Excludes clock pins. 13. Typicals are at V CC = 5.0V and 3.3V. 14. Internal RC selected. 15. Combined Digital and Analog VCC supply current. Sym Parameter VCC Note 3 TA = 0° C to +70°C TA = –40°C to +105°C Typical [13] @ 25 °C Units Conditions NotesMin Max Min Max
Figure 7. Additional Timing
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AC ELECTRICAL CHARACTERISTICS (Continued) Additional Timing Table (SCLK/TCLK = XTAL/2) No Symbol Parameter VCC Note 6 TA = 0°C to +70°CT A = –40°C to +105°C Units Notes
12 MHz 16 MHz 12 MHz 16 MHz
Min Max Min Max Min Max Min Max 1 TpC Input Clock Period 3.0V 83 DC 62.5 DC 83 DC 62.5 DC ns 1 5.5V 83 DC 62.5 DC 83 DC 62.5 DC ns 1
2 TrC,TfC Clock Input Rise & Fall
3.0V 15 15 15 15 ns 1 5.5V 15 15 15 15 ns 1 3 TwC Input Clock Width 3.0V 41 31 41 31 ns 1 5.5V 41 31 41 31 ns 1 4 TwTinL Timer Input Low Width 3.0V 100 100 100 100 ns 1 5.5V 70 70 70 70 ns 1 5 TwTinH Timer Input High Width 3.0V 5TpC 5TpC 5TpC 5TpC 1 5.5V 5TpC 5TpC 5TpC 5TpC 1 6 TpTin Timer Input Period 3.0V 8TpC 8TpC 8TpC 8TpC 1 5.5V 8TpC 8TpC 8TpC 8TpC 1
7 TrTin, Timer Input Rise & Fall
3.0V 100 100 100 100 ns 1 TfTin 5.5V 100 100 100 100 ns 1 8A TwIL Int. Request Low Time 3.0V 100 100 100 100 ns 1,2 5.5V 70 70 70 70 ns 1,2 8B TwIL Int. Request Low Time 3.0V 5TpC 5TpC 5TpC 5TpC 1,3 5.5V 5TpC 5TpC 5TpC 5TpC 1,3 9 TwIH Int. Request Input High Time 3.0V 5TpC 5TpC 5TpC 5TpC 1,2 5.5V 5TpC 5TpC 5TpC 5TpC 1,2
10 Twsm STOP-Mode Recovery
3.0V 12 12 12 12 ns 5.5V 12 12 12 12 ns 11 Tost Oscillator Startup Time 3.0V 5TpC 5TpC 5TpC 5TpC 4 5.5V 5TpC 5TpC 5TpC 5TpC 4
12 Twdt Watch-Dog Timer Delay
WDTMR Reg. D1 D0 3.0V 25 25 25 25 ms 1 0 3.0V 100 100 100 100 ms 1 1 13 TPOR Power On Reset Delay 3.0V 7 24 7 25 7 24 7 25 ms 5.5V 3 13 3 14 3 13 3 14 ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 0. 5. The V
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AC ELECTRICAL CHARACTERISTICS (Continued) Additional Timing Table (Divide-By-One Mode, SCLK/TCLK = XTAL) No Symbol Parameter Vcc Note 6 TA = 0°C to +70°CT A = –40°C to +105°C Units Notes
4 MHz 4 MHz
1 TpC Input Clock Period 3.0V 250 DC 250 DC ns 1,7,8 5.5V 250 DC 250 DC ns 1,7,8 2 TrC,TfC Clock Input Rise & Fall Times 3.0V 25 25 ns 1,7,8 5.5V 25 25 ns 1,7,8 3 TwC Input Clock Width 3.0V 125 125 ns 1,7,8 5.5V 125 125 ns 1,7,8 4 TwTinL Timer Input Low Width 3.0V 100 100 ns 1,7,8 5.5V 70 70 ns 1,7,8 5 TwTinH Timer Input High Width 3.0V 3TpC 3TpC 1,7,8 5.5V 3TpC 3TpC 1,7,8 6 TpTin Timer Input Period 3.0V 4TpC 4TpC 1,7,8 5.5V 4TpC 4TpC 1,7,8 7 TrTin, Timer Input Rise & Fall Timer 3.0V 100 100 ns 1,7,8 TfTin 5.5V 100 100 ns 1,7,8 8A TwIL Int. Request Low Time 3.0V 100 100 ns 1,2,7,8 5.5V 70 70 ns 1,2,7,8 8B TwIL Int. Request Low Time 3.0V 3TpC 3TpC 1,3,7,8 5.5V 3TpC 3TpC 1,3,7,8 9 TwIH Int. Request Input High Time 3.0V 3TpC 3TpC 1,2,7,8 5.5V 3TpC 2TpC 1,2,7,8 10 Twsm STOP-Mode Recovery Width Spec 3.0V 12 12 ns 4,8 5.5V 12 12 ns 4,8 11 Tost Oscillator Startup Time 3.0V 5TpC 5TpC 4,8,9 5.5V 5TpC 5TpC 4,8,9 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P33-P31). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP mode delay is on. 5. Reg. WDTMR. 6. The V 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For XTAL and LC oscillator, and for oscillator driven by clock driver.
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Figure 8. Input Handshake Timing Figure 9. Output Handshake Timing
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AC ELECTRICAL CHARACTERISTICS (Continued) Handshake Timing Table No Symbol Parameter VCC Note1,2 TA = 0°C to +70°CT A = –40°C to +105°C Data Direction Min Max Min Max Min Max Min Max 1 TsDI(DAV) Data In Setup Time 3.0V 0 0 0 0 IN 5.5V 0 0 0 0 IN 2 ThDI(DAV) Data In Hold Time 3.0V 160 160 160 160 IN 5.5V 115 115 115 115 IN 3 TwDAV Data Available Width 3.0V 155 155 155 155 IN 5.5V 110 110 110 110 IN 4 TdDAVI(RDY) DAV Fall to RDY Fall Delay 3.0V 160 160 160 160 IN 5.5V 115 115 115 115 IN 5 TdDAVId(RDY) DAV Rise to RDY Rise Delay 3.0V 120 120 120 120 IN 5.5V 80 80 80 80 IN 6 TdRDY0(DAV) RDY Rise to DAV Fall Delay 3.0V 0 0 0 0 IN 5.5V 0 0 0 0 IN 7 TdD0(DAV) Data Out to DAV Fall Delay 3.0V 42 31 42 31 OUT 5.5V 42 31 42 31 OUT 8 TdDAV0(RDY) DAV Fall to RDY Fall Delay 3.0V 0 0 0 0 OUT 5.5V 0 0 0 0 OUT 9 TdRDY0(DAV) RDY Fall to DAV Rise Delay 3.0V 160 160 160 160 OUT 5.5V 115 115 115 115 OUT 10 TwRDY RDY Width 3.0V 110 110 110 110 OUT 5.5V 80 80 80 80 OUT 11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay 3.0V 110 110 110 110 OUT 5.5V 80 80 80 80 OUT Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
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Table 5. D/A Converter Electrical Characteristics Table 6. D/A Converter Electrical Characteristics † The C84 Emulator has maximum setting time of 20 msec. (10 msec. typical).
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Table 7. A/D Converter Electrical Characteristics SCLK = System Clock on Bus Speed. Table 8. A/D Converter Electrical Characteristics Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register. SCLK = System Clock on Bus Speed.
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The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above Vcc occur on the /RESET pin. Recommendations for dampening voltage surges in both test and OTP mode include the following: n Using a clamping diode to /RESET n Adding a capacitor to the affected pin XTAL1. Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC network or an external single-phase clock to the on-chip oscillator input. XTAL2. Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC network to the on-chip oscillator output. Port 0 P00-P06. (P03-P06 is not available on the Z86C84). Port 0 is a 7-bit, bidirectional, CMOS-compatible I/O port. These seven I/O lines can be nibble programmable as P00-P03 input/output and P04-P06 input/output, separately (Figure 10). All input buffers are Schmitt-triggered and output drivers are push-pull. There is a ROM mask option to enable 100K (–40%) pull-up resistors to Port 0, P00 to P02. Port 0 Auto Latch. (Auto Latch Mask Option available only on P00-P02. P03-P06 has the Auto Latches permanently enabled.) The Auto Latch provides valid CMOS Levels when P00-P06 (P00-P02 on C84) are selected as inputs and not externally driven. It is impossible to determine if a non-driven input is 1 or 0, however; the Auto Latch will sense the input condition and drive a valid CMOS level, thereby eliminating a floating mode that could cause excessive current. (Auto Latch is a ROM mask option for the Z86C83, Z86C84). Port 2 (P27-P20) Port 2 is an 8-bit, bi-directional, CMOS- compatible I/O port and an 8-channel muxed input to the 8-bit ADC. When configured as a digital input, by programming the Port2 Mode register, the Port 2 register can be evaluated to read digital data applied to Port 2, or the ADC result register can be read to evaluate the analog signals applied to Port 2 after configuring the ADC Control Registers. The direction of each of the eight Port 2 I/O lines can be configured individually (Figure 11). In addition, all four versions of the device provide the capability of connecting 10K (–20%) pull-up resistors to each of the Port 2 I/O lines individually. The pull-ups are connected when activated through software control of P2RES register (Figure 67) when the corresponding Port 2 pin is configured to be an input. The pull-up resistor of a Port 2 I/O line is automatically disabled when the corresponding I/O is an output, regardless of the state of the corresponding P2RES bit value. Note: The Z86C83/C84 Emulator does not emulate the P2RES Register. Selection of the pull-ups are done via jumper settings on the emulator.
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Figure 10. Port 0 Configuration
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Figure 11. Port 2 Configuration
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globally programmed by the software. comparator reference voltage input when in Analog Mode.
- Deletion of Port Auto Latches is available as a ROM
by the customer when the ROM code is submitted.
- Ports 03, 04, 05, 07 have permanently enabled Auto
P33 can be used as a Port 3 register input or IRQ1 source. programming the PCON Register bit D0 to 1. Table 9. Port 3 Pin Assignments
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Figure 12. Port 3 Input Configuration
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- The PCON Register is located in the Expanded Register
File at Bank F, location 00 (Figure 13). Figure 13. Port Configuration Register (PCON) (Write-Only) Figure 14. Port 3 P34 Output Configuration
0 P34 Standard Output*
1 P34 Comparator Output
Power-On Reset, and any WDT Reset.
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
0 P34 Standard Output
1 P34 Comparator Output*
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RESET. (Input, Active Low). This pin initializes the MCU. (POR), Watch-Dog Timer (WDT) Reset, or external reset. reset is driving the reset pin Low for the POR time. conditions. Pull-up is provided internally. After the POR time, /RESET is a Schmitt-triggered input. program memory are reserved for the interrupt vectors. on-chip, mask-programmed ROM. #0X instruction to access the ERF. Figure 15. Program Memory Map
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Figure 16. Expanded Register File Architecture † Will not be reset with a Stop-Mode Recovery , except Bit 0.
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register groups, each occupying 16 continuous locations. active working-register group. working registers and indirect addressing modes. 1.8V. This includes Register R254. working register and indirect addressing modes. register, bit D6. A 1 in D6 enables RAM Protect. Figure 17. Register Pointer Register Figure 18. Register Pointer the active working-register group.
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prescaler is driven by the internal clock only (Figure 19). request, IRQ4 (T0) or IRQ5 (T1), is generated. continue counting (modulo-n continuous mode). non-retriggerable, or as a gate input for the internal clock. Figure 19. Counter/Timer Block Diagram
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Figure 20. Interrupt Block Diagram Table 10. Interrupt Types, Sources, and Vectors
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of the interrupt requests need service. software may poll to identify the state of the pin. configuration is shown in Table 11. Ground noise injection into the oscillator. Table 11. IRQ Register
00 F F
01 F R
10 R F
Figure 21. Oscillator Configuration
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Control Register 1 is configured. also take slightly longer due to smaller input signals. allowing the 8-bit ADC across a narrower voltage range. must be the same value as GND. Figure 22. ADC Architecture
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Channel Select (bits 2, 1, 0). Figure 23. ADC Control Register 0 (Read/Write)
0 No action*
1 Convert channel then stop
Figure 24. ADC Control Register 1 (Read/Write)
0 Disable*
1 Enable
Figure 25. Result Register (Read-Only) Figure 26. Bank C
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compensate the input settling time problem.
- Set the register pointer to Extended Bank (C),that is,
- Next, set ADE flag by loading ADC1 Control Register
range is 2.5V - 5.0V for AVCC = 5.0V.
- Select one of the eight A/D inputs for conversion by
conversion (or digital port I/O).
- Set Bank (C) Register 8, bit 3 to enable A/D
performed to determine A/D readiness if necessary.
- Read the A/D result in Bank (C) Register A. Please
otherwise A/D converter output is tri-stated. Figure 27. Input Impedance of ADC
31 CMOS Digital
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externally-provided reference voltages, VDHI and VDLO. reference voltages should not exceed the supply voltages. Figure 28. DAC Block Diagram
8 Analog
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is initialized to midrange 80H on power-up. for any gain setting (Figure 29 and Figure 31). Figure 29. D/A 1 Control Register Figure 30. D/A 1 Data Register
0 Disable
Figure 31. D/A 2 Control Register Figure 32. D/A 2 Data Register
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RC/LC oscillators with fast start up time). request must be executed (enabled) to exit HALT mode. the application program at address 000CH. Figure 33. Gain Control on DAC
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Bank F of the Expanded Register Group at address 0BH. Recovery, WDT Timeout, and POR. Figure 34. STOP-Mode Recovery Register (Write-
0 OFF* *
000 POR Only and/or External Reset*
001 Reserved
010 P31
100 P33
101 P27
0 OFF
0 Low *
1 High
0 POR
1 Stop Recovery
0 SCLK/TCLK = XT AL/2*
1 SCLK/TCLK = XT AL
Figure 35. Stop-Mode Recovery Register 2 Figure 36. SCLK Circuit
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
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STOP-Mode Recovery Source (D2, D3, and D4). source of the STOP recovery (Figure 37 and Table 12). Analog Comparator’s are powered down in Stop Mode. output level will be read by the SMR circuitry. used for either SMR or SMR2. register then SMR Register Bits D2, D3, and D4 must be 0. Table 12. STOP-Mode Recovery Source Table 13. Stop-Mode Recovery Source
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Figure 37. STOP-Mode Recovery Source
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selected with bit 4 of the WDT register (Figure 38). Registers, but will cause the reset delay to occur. Expanded Register group at address location 0FH. Figure 38. Resets and WDT
18 Clock RESET
128 SCLK
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period. It is configured as shown in Table 14.
- If WDT is permanently selected (always ON mode),
- WDT instructions affect the Z (Zero), S (Sign), and V
the WDT is selected to run during Stop Mode. below the specified voltage (typically 2.6V). the time the ROM mask is ordered (ROM code submitted). Figure 39. Watch-Dog Timer Mode Register Table 14. WDT Time Select (Min. @ 5.0V) The default on a WDT initiated reset is 512 SCLK.
0 On-Board RC
1 XT AL
Table 15. ROM Mask Selectable Options
Figure 40. ADC Control Register 0 (Read/Write) Figure 41. ADC Control Register 1 (Read/Write) Figure 42. AD Result Register (Read Only) 1 = Convert channel then stop.
- Default setting after reset.
Figure 43. D/A 1 Control Register Figure 44. D/A 2 Control Register Figure 45. D/A 1 Data Register Figure 46. D/A 2 Data Register
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Figure 47. Stop-Mode Recovery Register Figure 48. Watch-Dog Timer Mode Register 2 Figure 49. Watch-Dog Timer Mode Register Figure 50. Port Configuration Register (PCON) Power-On Reset, and any WDT Reset.
Figure 51. Reserved Figure 52. Timer Mode Register (F1H : Read/Write) Figure 53. Counter/Timer 1 Register (F2H : Read/Write)
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T0
1 Load T1
0 Disable T1 Count
1 Enable T1 Count
00 External Clock Input
01 Gate Input
10 Trigger Input
Figure 54. Prescaler 1 Register (F3H : Write-Only) Figure 55. Counter/Timer 0 Register (F4H : Read/Write) Figure 56. Prescaler 0 Register (F5H : Write-Only)
0 T1 Single Pass
1 T1 Modulo
1 T1 Internal
0 T1 External Timing Input
0 T0 Single Pass
1 T0 Modulo N
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Figure 57. Port 3 Mode Register (F7H : Write-Only) Figure 58. Port 2 Mode Register (F6H : Write-Only) Figure 59. Port 0 and 1 Mode Register
0 Port 2 Open-Drain*
1 Port 2 Push-Pull
0 Digital*
1 Analog
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
00 Output
01 Input *
Z86C82, but must be set to 00. Figure 60. Interrupt Priority Register (F9H : Write-Only) Figure 61. Interrupt Request Register Figure 62. Interrupt Mask Register (FBH : Read/Write)
000 Reserved
001 C > A > B
010 A > B > C
100 B > C > A
101 C > B > A
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
00 P31 ↓
01 P31 ↓
10 P31 ↑
1 RAM Protect Enabled †
0 RAM Protect Disabled *
1 Enables IRQ5-IRQ0
1 Enables Interrupts
0 Disable interrupts *
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Figure 63. Flag Register (FCH : Read/Write) Figure 64. Register Pointer (FDH : Read/Write) Figure 65. General-Purpose Register Figure 66. Stack Pointer (FFH : Read/Write) Figure 67. Port 2 Pull-up Register
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PACKAGE INFORMATION
Figure 68. 28-Pin DIP Package Diagram Figure 69. 28-Pin SOIC Package Diagram
Figure 70. 28--Pin PLCC Package Diagram
Z8® MCU Microcontrollers
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ORDERING INFORMATION
For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Package P = Plastic DIP S = Plastic SOIC Temperature S = 0° C to + 70° C E = -40°C to +105°C Speed 16 = 16 MHz Environmental C = Plastic Standard Z86C83
16 MHz
28-Pin DIP 28-Pin SOIC 28-Pin PLCC Z86C8316PSC Z86C8316SSC Z86C8316VSC Z86C8316PEC Z86C8316SEC Z86C8316VEC Z86C84 28-Pin DIP 28-Pin SOIC 28-Pin PLCC Z86C8416PSC Z86C8416SSC Z86C8416VSC Z86C8416PEC Z86C8416SEC Z86C8416VEC Example: Z 86C83 16 P S C is a Z86C83, 16 MHz, DIP , 0° to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix