Z86C05 ZILOG | Alldatasheet
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ps PRELIMINARY PRODUCT SPECIFICATION ey CMOS Z8 8-BiT Low-Cost 1K/2K-ROM MICROCONTROLLERS
FEATURES
- Two Programmable 8-Bit Counter/Timers, Part ROM RAM* Speed Auto Permanent 7 : , Number (KB) (Bytes) (MHz) Latch WDT Each with 6-Bit Programmable Prescaler ~Z86C05 1 125 8 Disabled Enabled ™ Power-On Reset (POR) Timer 2Z86C07 2 125 12 Disabled Enabled a_i On-Chip Oscillator that Accepts RC, Crystal, ™ = 18-Pin DIP and SOIC Packages Ceramic Resonance, LC, or External Clock Drive ™@ 3.0V to 5.5V Operating Range ™ = Clock-Free WDT Reset @ = 14 Input / Output Lines ™ Low-Power Consumption (50 mw) m Six Vectored, Prioritized Interrupts from @ Fast Instruction Pointer Six Different Sources (1.5us @ 8 MHz, 1.0 ps @ 12 MHz) lm Two On-Board Comparators ™@ Fourteen Digital Inputs at CMOS Levels; Schmitt-Triggered m ROM Mask Options: - Low Noise ™@ Software Enabled Watch-Dog Timer - ROM Protect ™@ Programmable Interrupt Polarity — Auto Latch (C04/C08) - Permanent Watch-Dog Timer (WDT) (C04/C08) m= Two Standby Modes: STOP and HALT - RC Oscillator @ Low-Voltage Protection - 32 kHz Operation GENERAL DESCRIPTION Zilog’s Z86C05/C07 Microcontrollers (MCU) are members —_— munications. Additionally, two on-board comparators pro- of the Z8 MCU family, which offer easy software/hardware _ cess analog signals with a common reference voltage (Fig- system expansion. ure 1). For applications demanding powerful I/O capabilities, the Note: All signals with a preceding front slash, "/", are Z86C05/C07’s dedicated input and output lines are active Low. For example: B//W (WORD is active Low); grouped into three ports, and are configurable under soft- _ /B/W (BYTE is active Low, only). ware control to provide timing, status signals, or parallel VO. Power connections follow conventional descriptions. Two on-chip counter/timers, with a large number of user Connection Circuit Device selectable modes, off-load the system of administering ——Ppower. Vg real-time tasks such as counting/timing and I/O data com- Ground GND Ve DS97Z8X0600 PRELIMINARY 1-1
Figure 1. Z286C05/C07 Functional Block Diagram
Figure 2. 8-Pin SOIC Pin Configuration Figure 3. 18-Pin DIP Pin Configuration
5 Voc Power Supply Output
6 XTAL2 Crystal Oscillator Clock Input
7 XTAL1 Crystal Oscillator Clock
8 P31 Port 3, Pin 1, AN1 Input
9 P32 Port 3, Pin 2, AN2 Input
10 P33 Port 3, Pin 3, REF Input
14 GND Ground
- This applies to all pins except where otherwise noted. Maximum current into pin must be +600pA.
- There is no input protection diode from pin to V5.
- This excludes Pin 6 and Pin 7.
- Device pin is not at an output Low state.
Figure 4. Test Load Diagram T, = 25°C, V,. = GND = OV, f = 1.0 MHz, unmeasured pins returned to GND.
Zilog CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers So pc ELECTRICAL CHARACTERISTICS ee T, = 0°C Ta = 40°C to +70°C to +105°C Typical Sym Parameter Vecl4] Min Max Min Max @265°C Units Conditions Note Voltage External Clock Generator 55V 08V,, V,,+03 08V,, V+03 28 V Driven by External Clock = Generator Vo. Clock Input Low 30V V0.3 02Vec V.-03 02V, 08 V Driven by Voltage External Clock Generator 55V V0.3 02V,, Vs03 02V, 7 V Driven by External Clock — Generator V,, Input High Voltage“ 3.0V=O7V,, Vi 403 O7V, Viaw0s 18 V 1 5BV O7V,, V,103 O7V,, Vi#03 28 V 1 V, Input Low Voltage“ 3.0V “V0.3 02V,, V,-03 02V, 08 V 1 V,, Output High Voltage = 3.0V V0.4 Voq70.4 3.0 Vv y,=720mA 5 5.5V V 70.4 V,¢70.4 48 Vv Iy=720mA 5 3.0V V,-0.4 V0.4 3.0 V_ Low Noise @ |, =-0.5mA 55V V0.4 Vog-0.4 48 V_ LowNoise @ |, =-0.5mA V,,, Output Low Voltage 3.0V 0.8 0.8 02 Vly =+40mA 5 5.5V 0.4 0.4 0.1 Vv =+40mA 5 3.0V 0.4 0.4 0.2 V_ Low Noise @ Io, =1.0mA 5.5V 0.4 0.4 0.1 V_ Low Noise @ Io, =1.0mA 5.5V 0.8 0.8 0.3 Vv yatt2mA 5 Voceser COMparator Input 3.0V 25 25 10 mV Offset Voltage 5.5V 25 25 10 mv Viv Voc Low Voltage 22 28 26 ~V_ Int.CLKFreq@ Auto Reset 6 MHz Max. 2.0 3.0 2.6 Int. CLK Freq @ 4 MHz Max. Comparator) SS ees DS97Z8X0600 PRELIMINARY 1-5
CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers Zilog LL pc ELECTRICAL CHARACTERISTICS (CONT.) ee Ty = 0°C Ta = -40°C to +70°C to +105°C Sym Parameter Vecl4l = Min Max Min Max @25°C Units Conditions Note EEE ee SOOO NO Vin = OV, Veg INE Viicn Comparator Input 0 Vog71-0 0 Vn 15 Vv Common Mode Voltage Range i, Standby Current 3.0V 25 25 0.7 mA_ HALT mode Vy= OV, (Low Noise Mode) Veg @ 1 MHz 5.5V 4.0 4.0 2.5 mA HALT mode Vy = OV, Veg @ 1 MHz 3.0V 3.0 3.0 0.9 mA HALT mode Vy = OV, Vig @ 1 MHz 5.5V 45 45 2.8 mA _ HALT mode Vy = OV, Veg @ 2 MHz 3.0V 4.0 4.0 1.0 mA HALT mode Viy = OV, Veg @ 2 MHz 5.5V 5.0 5.0 3.0 mA HALT mode Vy = OV, Vig @ 4 MHz loc Standby Current 3.0V 10 20 1.0 yA STOP mode Vy = OV, V,, WOT is not Running 5.5V 10 20 1.0 HA STOP mode Vy = OV, V.¢ WOT is not Running 1. Auto Latch Low 3.0V 12 8.0 3.0 HA OV <Vin <Vog Current 5.5V 32 30 16 pA OV <Viw <Voo Tay Auto Latch High ———-3.0V 8 50 -15 pA OV<Vin<Voo Current 5.5V =16 20° «80 LA OV=<Vin <Vog Notes: 1. Port 0, 2, and 3 only. 2. Vgg = OV = GND. 3. The device operates down to Vy. The minimum operational Vc is determined on the value of the voltage Vy at the ambient tem- perature. The V, increases as the temperature decreases. 5. Standard Mode (not Low EMI mode). 6. Z86C07/C08 only. 7. CL1 = 100 pF, CL2 = 220 pF, RF = 30 kOhm 1-6 PRELIMINARY DS97Z8X0600
Figure 5. AC Electrical Timing Diagram
CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers Zilog eee AC ELECTRICAL CHARACTERISTICS (Continued) Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Ta= 0°C to +70°C T= 40°C to +105°C
8 MHz(C05) = 12 MHz(C07) 8 MHz(CO05) = 12 MHz(C07)
NoSymbol Parameter Veo Min Max Min Max Min Max Min Max_Units Notes 1 Tpc Input Clock Period 3.0V 125 DC 83 DC 125 DC 83 DC ns 1 5.5V 125 DC 83 Dc 125 DC 83 DC ons 1 2 TrC,TIC Clock Input Rise 3.0V 25 15 25 15 ns 1 andFallTimes “5.5V 25 15 25 15 ns 3 TwC Input Clock Width 3.0V 62 4 62 41 1 5.5V 62 4 62 41 ns 1 4 TwTinl Timer InputLow 3.0V 100 100 100 100 ns 1 Width 5.5V 70 70 70 70 ns 1 5 TwTinH Timer Input High 3.0V 5TpC 5TpC 5TpC 5TpC 1 Width 5.5V 5TpC 5TpC 5TpC 5TpC 1 6 TpTin Timer Input Period 3.0V 8TpC 8TpC 8TpC 8TpC 1 5.5V 8TpC 8TpC 8TpC 8TpC 1 7 TrTin, Timer Input Rise 3.0V 100 100 100 100 ns 1 TtTin andFallTimer “S5V ~+100. + # # #+;$§400 #4+1§00 4400. ns 1 8 Twill — Int.Requestinput 3.0V 100 100 100 100 ns 1,2 Low Time 5.5V_70 70 70 70 ns 1,2 9 TwIH — Int.Request Input 3.0V 5TpC 5TpC 5TpC 5TpC 1 High Time 5.5V 5TpC 5TpC 5TpC 5TpC 1,2 10 Twdt = Watch-Dog Timer 3.0V 25 25 25 25 ms 1 Delay Time 5.5V 12 12 10 10 ms 1 11 Tpor 3.0V 24 24 24 24 ms 1 5.5V 12 12 12 12 ms 1 Notes: 1. Timing Reference uses 0.7 Vo, for a logic 1 and 0.2 Veg for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 1-8 PRELIMINARY DS97Z8X0600
Zilog CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers $$ —_ rea eae eeeeeeconron ers AC ELECTRICAL CHARACTERISTICS Low Noise Mode Ta= 0°C to +70°C Ty= 40°C to +105°C
1 MHz 4 MHz 4MHz 1MHz
No Symbol Parameter Veo Min Max Min Max Min Max Min Max Units Notes 1 TPC Input Clock 3.0V. 1000 DC 250 0c 1000 DC 250 DC ns 1 Period 5.5V 1000 DC 260 DC 1000 DC 250 DC ns 1 2 rc Clock Input Rise 3.0V 25 25 25 25 ons 1 TIC and Fall Times 5.5V 25 25 25 25 ns 1 3 Two Input Clock Width 3.0V 500 125 500 125 ns 1 5.5V 500 125 500 125 ns 1 4. TwTinL Timer Input Low 3.0V 100 100 100 100 ns 1 Width 5.5V 70 70 70 70 ns 1 6 TpTin — Timer Input 3.0V 4TpC 4TpC 4TpC 4TpC 1 Period 5.5V 4TpC 4TpC 4TpC 4TpC 1 7 ‘TrTin, ‘Timer Input Rise 3.0V 100 100 100 100 ns 1 TtTin —_andFall Timer 5.5V 100 100 100 100 ons 1 8 Tw _ int. Request 3.0V 100 100 100 100 ns 1,2 Input 55V 70 70 70 70 ns 1,2 Low Time High Time 10 Twat Watch-Dog Timer 3.0V 26 25 25 25 ms 1 Delay Time 5.5V 12 12 10 10 ms 1 Notes: 1. Timing Reference uses 0.7 Voc for a logic 1 and 0.2 Veg for a logic 0. 2. Interrupt request through Port 3 (P33-P31). DS97Z8X0600 PRELIMINARY 1-9
output; (3) switched output. @ Output drivers have resistances of 200 ohms (typical). @ Oscillator divide-by-two circuitry eliminated. by the customer at the time the ROM code is submitted. Figure 6. Typical Low Noise Measurements
to the on-chip clock oscillator and buffer. low) or |,., (low to high). be determined. A valid CMOS level, rather than a floating —_ inputs or all outputs (Figure 7). Figure 7. Port 0 Configuration
port. These eight I/O lines can be configured under soft- _either push-pull or open-drain (Figure 8). Figure 8. Port 2 Configuration
CMOS-compatible port with three fixed input (P33-P31) _ IRQ3 and as the timer input signal (T, iw) (Figure 9). Figure 9. Port 3 Configuration
CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers Zilog LL PIN DESCRIPTION (Continued) Comparator Inputs. Two analog comparators are addedto _Interrupts are generated on either edge of Comparator 2’s Port 3 inputs for interface flexibility. Typical applications for —_ output, or on the falling edge of Comparator 1's output. these on-board comparators are: Zero-Crossing detection, | The comparator output may be used for interrupt genera- AID conversion, voltage scaling, and threshold detection. tion, Port 3 data inputs, or T,, through P31. Alternately, the comparators may be disabled, freeing the reference input The dual comparator (common inverting terminal) features (P33) for use as IRQ1 and/or P33 input. a single power supply which discontinues power in STOP mode. The common voltage range is 0-4V when the Veg is 5.0V. 1-14 PRELIMINARY DS97Z8X0600
for T,o, MS, plus 18 clock cycles, and then starts program _ control registers’ reset value is shown in Table 1. Figure 10. Internal Reset Configuration Table 1. Z86C04/C08 & C05/C07 Control Registers Note: Registers are not reset after a STOP-Mode Recovery using P27 pin. on the port pins ordevice reliability may be affected.
CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers Zilog SSS FUNCTIONAL DESCRIPTION (Continued) Program Memory. The Z86C05/CO7 can address up to _ register group. Upon power-up, the general purpose regis- 1K/2K bytes of internal program memory (Figure 11). The _ ters are undefined. first 12 bytes of program memory are reserved for the in- terrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0- Location Indentifiers 1023/2047 are on-chip mask-programmed ROM. 255 (FFH) SPL omnenr FHTEFH — 259(FDH|____—RegsterPotor | RP Lovatono Onchi 252 (FCH| Program Convol lags | FLAGS First Byte of ROM Executed weet eee eee ee 251 (FBH) Interrupt Mask Register AterFESET 4p och 250 FAM) ira a 09H 27 (FH PoM Co 246 (FH) pan Vector (uope' Be)? on 2at 1H TWA Not Impl 0 00H 127 (7FH) Le Gonerat Purpose Registers 4 (04H) Register File. The Register File consists of three I/O port 2 (02H) P2 registers, 125 general-purpose registers, and 14 control | Reserved and status registers (RO, R2-R3, R4-R127, and Re4i- —t O1H) Reserved pt R255, respectively; see Figure 12). Note that R254 is 0 (00H) PO available for general purpose use. The Z8 instructions can access registers directly or indirectly through an 8-bit ad- dress field. This allows short 4-bit register addressing us- Figure 12. Register File ing the Register Pointer. In the 4-bit mode, the register file is divided into eight working register groups, each occupy- ing 16 continuous locations. The Register Pointer (Figure 13) addresses the starting location of the active working- ee 1-16 PRELIMINARY DS97Z8X0600
Vy reset if the V,, drops below 1.8V. ‘by handling bits DS to DO as "0" in Register R253(RP). Figure 13. Register Pointer
be driven by the internal clock source only (Figure 14). continue counting (modulo-n continuous mode). as a gate input for the internal clock. Note: Divide-by-two is not used in Low EMI Mode. Figure 14. Counter/Timers Block Diagram
(Figure 15). The six sources are divided as follows: the fall- determine which of the interrupt requests needs service. ables the six interrupt requests (Table 2). supported on the Z86CCPO0ZEM emulator. Figure 15. Interrupt Block Diagram
line when the device executes the STOP instruction. Alow = 1,S=0,V=0.
32 KHz = XTAL2
32 KHz Crystal Clock Ceramic LC Clock External Clock RC Clock
Figure 16. Oscillator Configuration
ed, the WDT is enabled, and subsequent execution clears _ clock frequency in standard mode. temperatures and operating frequencies in Cases 1 and 2. will enable the WDT during HALT. If not, the WDT will stop — temperature and process parameters (Figure 17). The WOH instruction (4FH) has no effect. mode. Frequency equal or less than 4 MHz. Figure 17. Typical Z86C04/C08 V,, vs. Temperature
1 Load To (Binen Wrtten)
1 Enable Toaunt O00 HER
0 No Function (When READ)
1 LoadT
0 Disable Ty Count
00 External Clock Input (F4,: Read/Write)
01 Gate input
0 Eee ee) R245 PREO
Figure 18. Timer Mode Register L Gount Meee Figure 19. Counter Time 1 Register [07 | os] 0s] 04] 03] 02] 01 [00 |
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
0 Ty Single Pass
1 T1Modulo
0 T 4 External Timing Input
Figure 20. Prescaler 1 Register ° Digital Figure 24. Port 3 Mode Register
Figure 25. Port 0 and 1 Mode Register Figure 31. Interrupt Mask Register Figure 26. (F8,: Write Only) Figure 32, (FB,: Read/Write)
001 C>A>B User Flag F2
010 A>B>C Half Carry Flag
100 B> CoA Decimal Adjust Flag
101 C>B>A Overflow Flag
10 B>A>C 5
111 Reserved Sign Flag
1 IRQ4>1RQ1 Cary Flag
1 IRQO> IRQ2 (FC:
0 IRQS > IRQS
1 IRQ3 > IRQS
Figure 27. Interrupt Priority Register Le Figure 28. (F9,: Write Only) [ Reserved (Must be 0, Figure 35. Register Pointer Figure 37. Stack Pointer Figure 29. Interrupt Request Register Figure 38. (FF,,: Read/Write) Figure 30. (FA,,: Read/Write)
Figure 39. Typical I, vs. Frequency
00 SSS
2 SS=S= SSS SSE
Figure 40. V,,V,, vs. Temperature
20 S VA ZN
Figure 43. Typical I,, vs. Vq.
30 INES
Figure 44. Typical WDT Time Out Period vs. V,, Over Temperature
CMOS Z8 8-Bit Low-Cost 1K/2K-ROM Microcontrollers Zilog eo
ORDERING INFORMATION
- Z86C05 286C07 (8 MHz) (12 MHz) Standard Temperature Standard Temperature 18-Pin DIP 18-Pin SOIC 18-Pin DIP 18-Pin SOIC Z86C0408PSC Z86C0408SSC Z86C0812PSC Z86C0812SSC Extended Temperature Extended Temperature 18-Pin DIP 18-Pin SOIC 18-Pin DIP 18-Pin SOIC 286C0408PEC Z86C0408SEC Z86C0812PEC Z86C0812SEC For fast results, contact your local Zilog sale offices for assistance in ordering the part(s) desired. ee CODES Preferred Package Longer Lead Time P=DIP E =—40°C to +105°C Longer Lead Time Speeds $= SOIC 08 = 8 MHz 12 = 12 MHz Preferred Temperature . $ =0°C to 470°C Environmental C = Plastic Standard Example: Z 86C05 08 PS C is a Z86C05, 8 MHz, DIP, 0°C to +70°C, Plastic Standard Flow L Environmental Flow Temperature Package Speed Product Number Zilog Prefix a 1-28 PRELIMINARY DS97Z8X0600
Zilog Preliminary Customer Procurement Specification DS97Z8x0600 NT Pre-Characterization Product: The product represented by this CPS is newly introduced __ either by Zilog or its customers in the course of further and Zilog has not completed the full characterization ofthe application and characterization work. In addition, Zilog product. The CPS states what Zilog knows about this cautions that delivery may be uncertain at times, due to product at this time, but additional features or non- start-up yield issues. conformance with some aspects of the CPS may be found, © 1997 by Zilog, Inc. All rights reserved. No part of this Zilog’s products are not authorized for use as critical document may be copied or reproduced in any form or by components in life support devices or systems unless a any means without the prior written consent of Zilog, Inc. specific written agreement pertaining to such intended use The information in this document is subject to change _is executed between the customer and Zilog prior to use. without notice. Devices sold by Zilog, Inc. are covered by _Life support devices or systems are those which are warranty and patent indemnification provisions appearing _ intended for surgical implantation into the body, or which in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. sustains life whose failure to perform, when properly used makes no warranty, express, statutory, implied or by in accordance with instructions for use provided in the description, regarding the information set forth herein or labeling, can be reasonably expected to result in regarding the freedom of the described devices from __ significant injury to the user. intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. 210 East Hacienda Ave. Zilog, Inc. shall not be responsible for any errors that may | Campbell, CA 95008-6600 appear in this document. Zilog, Inc. makes nocommitment — Telephone (408) 370-8000 to update or keep current the information contained in this / FAX 408 370-8056 document. Internet: http://www.zilog.com ———