Z8622812PSC

Z8622812PSC ZILOG | Alldatasheet

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wN cjLas a Gus TOMER PROCUREMENT SPECIFICATION _ Le | —MARCOM) DC4243 DocuMENT CONTROL_ MASTER LINE 21 CLOSED CAPTION CONTROLLER (L21C GENERAL DESCRIPTION The 286228 (Line 21 Closed-Caption Controller) isasingle by the FCC ‘Report and Order’ on GEN Docket No. 91-1, |.C. designed to provide the functional performance ofa dated April 12, 1991. In addition, the device conforms to \\21C Decodermodule. This Superintegration™ VLSIdevice the Electronic Industry Association's Recomended Practice is completely self contained requiring only composite 608, which provides supplemental guidelines for the video, a horizontal timing signal as input and an external transmission of captions, text, and Extended Data Services keyer (i.¢., video switch between TV video and Closed- (EDS) on NTSC Field 2. Extended Data Services (EDS) Caption video) to produce captioned video. The 286228 Packets encoded on Field 2 , may be displayed in either of uses a wired logic approach to perform the functions two screen formats, If and when PAL and SECAM TV selected through its input control signals. It is fabricated standards define a protocol using the Line 21 format, this using standard CMOS technology and designed to achieve design will be readily convertible to that standard. the lowest possible cost. The Line 21 Closed Captioning System The 286228 is intended for use in a set-top decoder or in The L21C system provides for the transmission of CAPTION any television receiver conforming to the NTSC standard. information and other TEXT material as an encoded It is capable of processing and displaying all standard composite data signal. This is during the unblanked portion L21C format transmissions including the codes specified of Line 21, field 1, of the standard NTSC video signal. The video signal conforms to the Standard Synchronizing Waveform for Color Transmission given in Sub-part E, Part 73 of the FCC Rules and Regulations.

ASiLaS PRELIMINARY cps poses eer LO -00 PIN DESCRIPTION OD DONF/SEN [] 1 187] LNG/SCK NRESET [] 2 17 i CT/SDA Box [] 3 16] ] NSIN . tum [] 4 157] vob (Digital) R[{] 5 141] VOD (Analog) G[]e 137] HLF Bi] 7 1217] Sst HFI [|] 38 1[] ov VSS (Digital) [] 9 107] vss (Analog) 18-Pin DIP Package Diagram SSS Pin No. Signal Description Pin No. Signal Description oe eeEeEEEEai0ce eee

1 Composite Video Input (CVI) 2 NRESET

Composite NTSC video, nominally 1.0V p-p,. Master reset for the I.C. and must be used in the band limited to 600 kHz. Circuit operates with Parallel Control Mode. It may be tied High in the signal variations between 0.7-1.4V p-p. It is Serial Mode if reset is to be performed through recommended that this signal pin be driven by the serial data stream. emitter follower th ha 0.4 itor, | an emitter follower through a 0.1 uF capacitor. 18 LAGISCK Input (control

12 Sync Slice Level (SSL) In Parallel Mode this input selects the Data

Capacitor (0.1F) to store sync slice level Channel to be processed (along with CT). CMOS voltage. input High=LANGUAGE I, Low=LANGUAGE II. @ HFiyback input (HF) In Serial Mode this input is Serial Clock In. Horizontal sync input at CMOS levels, polarity 3 Box Output (Box) independent. Typically derived from the H Active High, CMOS level “black box” keying Flyback pulse or any other horizontal timing signal for Caption/Text display area. signal “4 Luminance Output(\\UM).——SOSOS=~S~S~S~S 13 H Loop Filter (HLF) Active High, CMOS level signal. Value to be specified Character video luminance signal.

9 Veg (Digital) Digital Ground 5,6,7 Color signals, RGB Outputs

Connect to system ground Active High, CMOS level color character video a for color receiver use.

1 DONF/SEN Input (control) ee

In Parallel Mode this input controls the Decoder 15 Vp Digital Power pin. Connect to +5V source. On/Off function CMOS input with High = On, Wa V.Analog” Low = Off. In Serial Mode this inputis the Enable oo Analog for serial data input. 10 V,,Analog. Analog Ground. Connect to 17 CT/SDA Input (control system ground. In Parallel Mode this input selects the Data 46 (NSIN) input (Control) Channel to be processed (along with LNG). Selects the mode to be used in interpreting the CMOS inputwith High=CAPTIONS, Low =TEXT. signals on the three Control pins. High = Parallel In Serial mode this input is serial data input. Mode, Low = Serial Mode. Sues oe 2 t

ASiLaS PRELIMINARY cps Dosrah —_— eee HB -0 Horizontal Timing The timing of the output signals; Box, Luminance, and RGB case time for the NRESET signal to propagate through is set so that the start of the leading box Preceding the first the various gates. displayable character cell will occur at 13.6*ps. (“Value may be altered by a Mask change - consult factory.) This | 2. Send NRESET command through the serial interface. is after the midpoint of the leading edge of the horizontal The result is the same as in number 1. sync pulse of the composite video signal measured at pin 11 of the 286228. It is assumed that the delay through the + FULL RESETis useful during power-up. A FULL RESET of low pass filter will be 220 ns (refererence Figure). the part during normal operation is not necessary. There are two ways to execute a FULL RESET of the A Partial reset may also be executed through the serial 286228: interface only. This is the COMMAND PROCESSORRESET. Basically, all internal timing circuits continue to operate, 1. Hold NRESET Low for 100 ns. This stops all internal — butthe caption display is removed from the screen and the circuits. The part is static and the 100 ns is the worst 286228 waits for new line 21 data. This is useful for situations such as channel change. ess DC CHARACTERISTICS Sym Parameter Min Max Units Conditions Vi Input Voltage Low (e) 0.2Vo Vv Vu Input Voltage High 0.7Vog Vo Vv Vow Output Voltage Low 0.4 Vv lg, = 1.00 mA

1 Vv log = 50 pA [1]

Vou Output Voltage High Vee-0.4 Vv |, = 0.75 mA [2] I Input Leakage -.0 3.0 pA OV, Veg leo Supply Current 25 mA [3] a Notes: (1] Pin 13 (HLF) (2] Pin 17 (CT/SDA) is Open-Drain. [3] Vag Digital + V,,, Analog combined. Stress greater than those listed under Absolute Maximum ABSOLUTE MAXIMUM RATINGS Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections _Sym__ Description Min’ “Max Units of these specifications is not implied. Exposure to absolute Veg Supply Voltage* 0.3 +7.0 Vv maximum rating conditions for an extended period may Tota Storage Temp -65°C +150° CC affect device reliability. T, Oper Ambient Temp o° 70° c #8 SSS Notes: * Voltages on all pins with respect to GND. 21k ——— eeSeSeFSFFFFFFFFFffsseF From Output STANDARD TEST CONDITIONS Under Test The characteristics listed below apply for standard test ‘ope 250 pA conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin in Standard Test Load. Standard Test Load 3 H

• R ASILAS PRELIMINARY cps pe-A0 eee ES OE S-00 AC AND TIMING CHARACTERISTICS* (Reference Line 21 AC/DC Timing) eee Composite Video Input Amplitude: 1.0 V p-p, 3 dB Polarity: - Sync tips negative Bandwidth 600 kHz Horizontal Signal Input (preferably H Flyback) Amplitude: CMOS level signal, Low < 0.2Vo¢, High 2 0.7Veg Polarity: Any Frequency: 15,734,263 Hz, + 3% —eSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS Line 21" Input Parameters (at 1.0 V p-p) Code Level: 50 IRE + 10 IRE Clock Run-in Start?: 10.5 ys, +0.5ps SSS Input Signal-to-Random Noise Performance Unit will function down to a 25 dB ratio (CCIR weighted) with one error per row or better at that level. SSeS Internal Syne Circuits The internal sync circuits will lock to all 525 line signals having a vertical sync pulse that meets the following conditions: @ Itis at least 2.5H long. @ It starts at the proper 2H boundary for its field. |f equalizing pulse serrations are present they must be less than 0.125H in width. a eeeeeeSSSSSSSSSSSSSSSSSSSSSSSSSSSseeeeee Timing Signals Dot Clock: 768 x FH = 12.0839 MHz Dot Period: 82.75 nsec Character Cell Width: 1.324 usec Width of Row (Box): 45.018 psec Width of Row (Char): 42.370 usec — eeEeEEeSSFSSSSSSSSSSMMMMHHeeeeee *All values are nominal and not fully characterized. EE SE

A SiLaS PRELIMINARY crs ne Ss Eos 0-4283-00 AC/DC TIMING Line 21 ‘Center of Active Video + f- Coll Width = 1.324 us er “worms . 3 Fi (100) IRE Blanking 0 IRE 3 a 3 aw ne — 0) “ne (40) IRE CHAR LUM = 42.370 us BOX = 45.018 us 13.68 35.73p8 Comp Vide LUM @ FILTER g Line 21 AC/DC Timing

Aasitas PRELIMINARY PS Doar evK———O SHI AC CHARACTERISTICS T, =0°C to + 70°C; Veo = +4.75V to +5.25V Tekd Tekl Tenl ‘Tekh SCK Za Serial Mode Timing Diagram Symbol Description Min. Max. Units Tour Output enable time, ENA rising edge to Data Out 200 ns Tore Output disable time, CLK or ENA falling edge to Data Hi-Z 100 ns Toxo Data read time, ENA rising edge to CLK low 200 ns Tox, CLK low time 200 ns Troe CLK high time 200 ns Tosy Data set-up time 100 ns Ton Data hold time 100 ms Ten ENA low time 200 ns Thay AO set-up time 100 ns Tuy AO hold time 100 ns eee 6 |

ASiiLas PRELIMINARY Ps Dedia8 Les a Low Margin: Customer is advised that this product does not meet stated on the front and back of the slaes order Zilog's internal guardbanded test policies for the acknowledgement, Zilog makes no claim as to quality and specifcation requested and is supplied on an exception _ reliability under the CPS. The product remains subject to basis. Customer is cautioned that delivery may be uncertain standard warranty for replacement due to defects in and that, in addition to all other limitations on Zilog liability — materials and workmanship. —_— To sss Pre-Characterization Product: The product represented by this CPS is newly introduced —_ conformance withsome aspects of the CPS may be found, and Zilog has not completed the full characterization ofthe __ either by Zilog or its customers in the course of further product. The CPS states what Zilog knows about this application and characterization work. In addition, Zilog product at this time, but additional features or non- cautions that delivery may be uncertain at times, due to Start-up yield issues. —_ SS oe © 1994 by Zilog, Inc. All rights reserved. No partof this document Zilog's products are not authorized for use as critical compo- may be copied or reproduced in any form or by any means _nentsinlife support devices or systems unless a specific written without the prior written consent of Zilog, Inc. The information in agreement pertaining to such intended use is executed between this document is subject to change without notice. Devices sold the customer and Zilog prior to use. Life support devices or by Zilog, Inc. are covered by warranty and patent indemnification systems are those which are intended for surgical implantation Provisions appearing in Zilog, Inc. Terms and Conditions of Sale into the body, or which sustains life whose failure to perform, only. Zilog, Inc. makes no warranty, express, statutory, implied or when properly used in accordance with instructions for use by description, regarding the information set forth herein or Provided in the labeling, can be reasonably expected to result in regarding the freedom of the described devices from intellectual significant injury to the user. Property infringement. Zilog, Inc. makes no warranty of mer- chantability or fitness for any purpose. Zilog, Inc. shall not be Zilog, Inc. 210 East Hacienda Ave. responsible for any errors that may appear in this document. Campbell, CA 95008-6600 Zilog, Inc. makes no commitment to update or keep current the Telephone (408) 370-8000 information contained in this document. Telex 910-338-7621 FAX 408 370-8056