Z86217 ZILOG | Alldatasheet
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CUSTOMER PROCUREMENT SPECIFICATION Part ROM RAM* I/O Speed Number (Kbytes) (Bytes) Lines (MHz) Z86217 2 124 14 4 Z86C17 2 124 14 4 Z86217/C17 CMOS Z8® 8-BIT MICROCONTROLLERS (POINTING DEVICE/TRACKBALL) * General-Purpose n 18-Pin DIP and SOIC Packages n 3.0- to 5.5-Volt Operating Range n 0°C to 70°C Operating Temperature Range n Permanent Watch-Dog Timer (WDT) n Oscillator Filter n Two Programmable 8-Bit Counter/Timers n Low-EMI Operation n Scalable Trip-Point Buffer n On-Board Pull-Up Resistors n High Drive Ports Can Sink 20 mA Per Pin, with Three Pins Maximum GENERAL DESCRIPTION The Z86217/C17 are members of Zilog's Z8 ® family of microcontrollers designed to reduce external system com- ponents and offer easy software/hardware development tools for pointing device and trackball applications. The devices feature on-board pull-up resistors, and a scalable trip-point buffer to accommodate opto-transistor outputs. The high drive ports are capable of up to 20 mA (at V OL = 0.8-volt) current sinking per pin, with three pins maximum, providing extra sinking current capability. The Z86217/C17's permanently enabled Watch-Dog Timer (WDT) operates upon power-up of the MCU, and provides added operational reliability for pointing device and trackball environments. An oscillator filter assists in separating out high-frequency noise from the oscillator input pin. Two on-chip counter/timers with a large number of selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. Notes: Refer to the DC electrical characteristics for detailed specification of the sinking current. On the Z86C17, P24-P27 has a 20K pull-up, and P32 has a 47K pull- down. The Z86217 does not have these functions. All Signals with a preceding front slash, "/", are active Low, e.g.; B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power V CC VDD Ground GND V SS
Timers (2) Interrupt Control Port 2 I/O (Bit Programmable) ALU FLAG Register Pointer Register File 144 x 8-Bit Machine Timing & Inst. Control Prg. Memory 2048 x 8-Bit Program Counter VSS XTAL VDDInput Port 0 I/O PIN DESCRIPTIONS Functional Block Diagram P23 P22 P33 P21 P20 VSS P02 P01 P00 P24 P25 P32 P26 P27 VDD XTAL2 XTAL1 P31 18-Pin SOIC Configuration 11 8P24 P27 VDD XT AL2 XT AL1 P31 P32 P23 P22 P21 P20 VSS P02 P01 P00 P33 P25 P26 18-Pin DIP Configuration
TA = GND = 0V, f = 1.0 MHz, unmeasured pins to GND Parameter Max Input capacitance 10 pF Output capacitance 20 pF I/O capacitance 25 pF Vdd SPECIFICATION Vdd = 3.0V to 5.5V ABSOLUTE MAXIMUM RATINGS Sym Parameter Min Max Units VDD Supply Voltage (*) –0.3 +7 V TSTG Storage Temp –65 ° +150° C TA Oper Ambient Temp † † C Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: * Voltages on all pins with respect to GND † See Ordering Information The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load). Test Load Diagram From Output Under T est 150 pFI
DC ELECTRICAL CHARACTERISTICS TA = 0°C to +70°C Typical Symbol Parameter V DD Min Max @ 25 °C Units Conditions Max Input Voltage 3.0V 12 V V IN = 250 µA 5.5V 12 V V IN = 250 µA VCH Clock Input High 3.0V 0.7 V DD VDD + 0.3 2.0 V Driven by External Voltage Clock Generator 5.5V 0.7 V DD VDD + 0.3 3.0 V Driven by External Clock Generator VCL Clock Input Low 3.0V V SS – 0.3 0.2 V DD 0.8 V Driven by External Voltage Clock Generator 5.5V V SS – 0.3 0.2 V DD 1.5 V Driven by External Clock Generator VIH Input High Voltage 3.0V 0.7 V DD VDD + 0.3 1.6 V Schmitt-Triggered 5.5V 0.7 V DD VDD + 0.3 2.6 V VIH Input High Voltage 3.0V 0.7 V DD VDD + 0.3 1.4 V CMOS Input 5.5V 0.7 V DD VDD + 0.3 2.6 V VIL Input Low Voltage 3.0V V SS – 0.3 0.2 V DD 1.4 V Schmitt-Triggered 5.5V V SS – 0.3 0.2 V DD 2.6 V VIL Input Low Voltage 3.0V V SS – 0.3 0.2 V DD 1.3 V CMOS Input 5.5V V SS – 0.3 0.2 V DD 2.4 V VOH Output High Voltge 3.0V V DD – 0.4 2.8 V I OH = –2.0 mA 5.5V V DD – 0.4 5.5 V I OH = –2.0 mA VOL1 Output Low Voltage 3.0V 0.4 0.13 V I OL = +4.0 mA 5.5V 0.4 0.07 V I OL = +4.0 mA VOL2 Output Low Voltage 3.0V 1.5 0.8 V I OL = 20.0 mA,
3 Pin Max
5.5V 0.8 0.3 V I OL = 20.0 mA, VLV VCC Low Voltage 2.7 2.3 V @ 2 MHz Max Protection Voltage VTP Trip Point 3.0V 0.4 V DD V Voltage 5.5V IIL Input Leakage 3.0V –1.0 1.0 µAV IN = OV, VCC 5.5V –1.0 1.0 0.4 µAV IN = OV, VCC IOL Output Leakage 3.0V –1.0 1.0 0.4 µAV IN = OV, VCC 5.5V –1.0 1.0 µAV IN = OV, VCC Note: For 2.75V operating, the device operates down to V LV. The minimum operational V DD is determined on the value of the voltage V LV at the ambient temperature. The VLV increases as the temperature decreases.
TA = 0°C to +70°C Typical Sym Parameter V DD Min Max @ 25 °C Units Conditions IDD Supply Current 3.0V 1.5 0.41 mA All Output and I/OPins Floating @ 1 MHz 5.5V 3.0 1.44 mA All Output and I/O Pins Floating @ 1 MHz 3.0V 2.0 0.93 mA All Output and I/O Pins Floating @ 2 MHz 5.5V 4.0 2.60 mA All Output and I/O Pins Floating @ 2 MHz 3.0V 3.0 1.64 mA All Output and I/O Pins Floating @ 4 MHz 5.5V 6.0 4.28 mA All Output and I/O Pins Floating @ 4 MHz IDD1 Standby Current 3.0V 0.6 0.15 mA HALT Mode V IN = 0V, VCC @ 1 MHz 5.5V 1.3 0.70 mA HALT Mode V IN = 0V, VCC @ 1 MHz 3.0V 0.8 0.20 mA HALT Mode V IN = 0V, VCC @ 2 MHz 5.5V 1.5 0.80 mA HALT Mode V IN = 0V, VCC @ 2 MHz 3.0V 1.0 0.3 mA HALT Mode V IN = 0V, VCC @ 4 MHz 5.5V 2.0 1.0 mA HALT Mode V IN = 0V, VCC @ 4 MHz IDD2 Standby Current 3.0V 200 120 µA STOP Mode V IN = 0V, VCC WDT is Running 5.5V 200 120 µA STOP Mode V IN = 0V, VCC WDT is Running IPU Pull-Up Current Port P20-P23 (100K) 3.0V –35 –13 µA 5.5V –100 –57 µA Port P24-P27* (20K) 3.0V –100 –58 µA 5.5V –400 –270 µA Port P00-P03 3.0V –35 –13 µA Port P31, P33 5.5V –100 –56 µA IPD Pull-Down Current 3.0V 80 40 µA Port P32* (47K) 5.5V 250 160 µA Note: *Available on the Z86C17 only.
AC ELECTRICAL CHARACTERISTICS TA = 0°C to +70°C
1 MHz 4 MHz
No Symbol Parameter V DD Min Max Min Max Units Notes 1 TpC Input Clock Period 3.0V 1,000 100,000 250 100,000 ns [1] 5.5V 1,000 100,000 250 100,000 ns [1] 2 TrC,TfC Clock Input Rise 3.0V 25 25 ns [1] and Fall Times 5.5V 25 25 ns 3 TwC Input Clock Width 3.0V 475 100 ns [1] 5.5V 475 100 ns [1] 4 TwTinL Timer Input Low Width 3.0V 100 100 ns [1] 5.5V 70 70 ns [1] 5 TwTinH Timer Input High Width 3.0V 2.5TpC 2.5TpC [1] 5.5V 2.5TpC 2.5TpC [1] 6 TpTin Timer Input Period 3.0V 4TpC 4TpC [1] 5.5V 4TpC 4TpC [1] 7 TrTin, Timer Input Rise 3.0V 100 100 ns [1] TtTin and Fall Timer 5.5V 100 100 ns [1] 8 TwIL Int. Request Input 3.0V 100 100 ns [1,2] Low Time 5.5V 70 70 ns [1,2] 9 TwIH Int. Request Input 3.0V 2.5TpC 2.5TpC [1] High Time 5.5V 2.5TpC 2.5TpC [1,2] 10 Twdt Watch-Dog Timer 3.0V 25 25 ms [1] Time Out Timer 5.5V 10 10 ms [1] 11 T POR Power-On Reset 3.0V 6 6 ms [1] Time 5.5V 2 2 ms [1] Notes: [1] Timing Reference uses 0.9 VDD for a logic 1 and 0.1 VDD for a logic 0. [2] Interrupt request through Port 3 (P33-P31)
Zilog’s products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com © 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of mer- chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con- formance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Low Margin: Customer is advised that this product does not meet Zilog’s internal guardbanded test policies for the specifi- cation requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workman- ship. 1 3 2 2 3 T IRQ IN N 7 7 Clock TIMING DIAGRAM Electrical Timing Diagram