Z86130

Z86129 ZILOG | Alldatasheet

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Technical content

P RELIMINARY P RODUCT S PECIFICATION

FEATURES

n Complete Stand-Alone Line 21 Decoder for Closed- Captions and Extended Data Services (XDS). n Preprogrammed to Provide Full Compliance with EIA- 608 Specifications for Extended Data Services. n Automatic Extraction and Serial Output of Special XDS Packets such as Time of Day, Local Time Zone, and Program Rating ( V-Chip n Cost-Effective Solution for NTSC Violence Blocking inside Picture-in-Picture (PiP) Windows. n Minimal Communications and Control Overhead Provides Simple Implementation of Violence Block, Closed Caption, and Auto Clock Set Features. n Programmable, Full Screen On-Screen Display (OSD) for Creating OSD or Captions inside a Picture-in- Picture (PiP) Window (Z86129 only). n I C Serial Data and Control Communication n User-Programmable Horizontal Display Position for easy OSD Centering and Adjustment (Z86129 only). GENERAL DESCRIPTION The Z86129/130/131 is a stand-alone integrated circuit, capable of processing Vertical Blanking Interval (VBI) data from both fields of the video frame in data conforming to the transmission format defined in the Television Decoder Circuits Act of 1990 and in accordance with the Electronics Industry Association specification 608 (EIA-608). The Line 21 data stream can consist of data from several data channels multiplexed together. Field 1 has four data channels, two Captions and two Text. Field 2 has five additional data channels, two Captions, two Text and Extended Data Services (XDS). XDS data structure is defined in EIA-608. The Z86129 can recover and display data transmitted on any of these nine data channels. The Z86130 and Z86131 are derivatives of the Z86129 which can recover XDS data and output the recovered data via the serial port. The Z86130 and Z86131 do not have OSD capability, but are ideally suited for Line 21 data slicer applications. The Z86129/130/131 can recover and output to a host processor via the I C serial bus any XDS data packet defined in EIA-608. On-chip XDS filters are fully programmable, enabling recovery of only those XDS data packets selected by the user, making the Z86129/130 an ideal choice for implementing NTSC Violence Block. The Z86131 is designed especially for extracting XDS time information for Automatic Clock-Set features in TVs, VCRs, and Set-Top boxes. In addition, the Z86129/130 is ideally suited to monitor Line 21 of video displayed in a PiP window for violence blocking purposes. A block diagram of the Z86129/130/131 is shown in Figure 1. Z86129/130/131 NTSC L INE 21 D ECODER Speed Pin Count/ Standard On-Screen Display Automatic Data Extraction Devices (MHz) Package Types Temp. Range & Closed Captioning V-Chip Time of Day Z86129 12 18-Pin DIP , SOIC 0 to +70 C Y es Y es Y es Z86130 12 18-Pin DIP , SOIC 0 to +70 C No Y es Y es Z86131 12 18-Pin DIP , SOIC 0 to +70 CN o N o Y e s

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Figure 1. Z86129 Block Diagram

Figure 2. Z86129/130/131, 18-Pin DIP/SOIC Table 1. 18-Pin DIP and SOIC Pin Identification

4 SEN Serial Enable Input

5 HIN Horizontal In Input

6 SMS Serial Mode Select Input

7 VIDEO Composite Video Input

8 CSYNC Composite Sync Output

9 LPF Loop Filter Output

10 RREF Resistor Reference Input

13 VIN/INTRO Vertical In/Interrupt Out In/Output

14 SDA Serial Data In/Output

15 SCK Serial Clock Input

16 SDO Serial Data Out Output

the Z86130/Z86131 do not have signals on pins 2, 3, 18 and 19. Maximum ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.

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Figure 3. Standard Test Load

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ELECTRICAL CHARACTERISTICS

Non Standard Video Signals must have the following characteristics: Horizontal Signal Input (preferably H Flyback) Line 21 Input Parameters (at 1.0V p-p) Note: Line 21 must be in its proper position to the leading edge of the Vertical Sync signal. Timing Signals Parameter Conditions Sync Amplitude 200 mV minimum Vertical Pulse Width 3H 0.5H Vertical Pulse Tilt 20 mV maximum H Timing Phase Step (Head Switch) m s maximum Fh Deviation (long term) 0.5% maximum Fh p-p Deviation (short term) 0.3% maximum Vertical Sync Signal The internal sync circuits will lock to all 525 or 625 line signals having a vertical sync pulse that meets the following conditions: 1. It is at least 2H wide. 2. It starts at the proper 2H boundary for its field. 3. If equalizing pulse serrations are present, they must be less than 0.125H in width. Minimum Signal-to-Noise The Z86129/130/131 will function down to a 25 dB signal-to-noise ratio (CCIR weighted) with one error per row or better at that level. Ratio to Composite Video Input Parameter Conditions Amplitude CMOS level signal where Low <= 0.2 V CC Video Lock Mode: Polarity Frequency Any 15,734.263 Hz HIN Lock Mode: Polarity Frequency Any Same as Display Horizontal Flyback Pulse (HFB) pulse Parameter Conditions Cod Amplitude 50 IRE Code Zero Level 5 IRE, +15 IRE relative to Back Porch Start of Code 10.5 –0.5 ms, (Measured from the midpoint of the falling edge of the last clock run-in cycle to the midpoint of the rising edge of the start bit.) Start of Data 3.972 ms, –0.00 msec, +0.30 ms (Measured from the midpoint of the falling edge of the last clock run-in cycle to the midpoint of the rising edge of the start bit. Parameter Conditions Dot 768 x FH = 12.0839 MHz Dot Period 82.75 ns Character Cell Width 1.324 ms (tH/48) Width of Row (Box) 45.018 ms (34 chars = 17/24 x tH Width of Row (Char) 42.370 ms (32 chars = 2/3 x tH Horizontal Display Timing The timing of the output signals Box and RGB have been set to make a centered display. The positioning of these outputs can be adjusted in 330 ns increments by writing a new value to the Z86129 H Position Register (Address = 02h).

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VIDEO (Pin 7). Composite NTSC video input, 1.0V p-p (nom), band limited to 600 kHz. Circuit will operate with signal variation between 0.7-1.4V p-p. The polarity is sync tips negative. This signal pin should be AC coupled through a 0.1 mF capacitor and driven by a source impedance of 470 ohms or less. HIN (Pin 5). Horizontal sync input at CMOS levels. When the device is used in the VIDEO LOCK mode, this signal pulls the on-chip VCO within the proper range. The circuit uses the frequency of this signal which must be within –3% Fh but can be of either polarity. When used in the H LOCK mode, the VCO phase locks to the rising edge of this signal. The HPOL bit of the H Position register can be set to operate with either polarity of input signal. This is usually the H Flyback signal. The timing difference between HIN rising edge and the leading edge of composite sync (of VIDEO input) is one of the factors which will affect the horizontal position of the display. Any shift resulting from the timing of this signal can be compensated for with the horizontal timing value in H Position Register. SMS (Pin 6). Mode select pin for the Serial Control Port. When this input is at a CMOS High state (1) the Serial Control Port will operate in the SPI mode. When the input is Low (0), the Serial Control Port will operate in the I slave mode. In SPI mode, the SEN pin must be tied High. (See Reset Operation section.) SEN (Pin 4). Enable signal for the SPI mode operation of the Serial Control Port. When this pin is Low (0), the SPI port is disabled and the SDO pin is in the high-impedance state. Transitions on the SCK and SDA pins are ignored. SPI mode operation is enabled when SMS is High (1). SCK (Pin 15). Input pin for serial clock signal from the master control device. In I 2C mode operation the clock rate is expected to be within I2C limits. In SPI mode, the maximum clock frequency is 10 MHz. Reset Operation. When the SMS and SEN pins are both in the Low (0) state, the part will be in the Reset state. Therefore, in the I 2C mode the SEN pin can be used as an NReset input. When SPI mode is used, if three wire operation is desired, both SMS and SEN can be tied together and used as the NReset input. In either mode, NReset must be held Low (0) for at least 100 ns. Input/Output VIN/INTRO (Pin 13). In external (EXT) vertical lock mode of operation, the internal vertical sync circuits will lock to the VIN input signal applied at this pin. The part will lock to the rising or falling edge of the signal in accordance with the setting of the V Polarity command. The default is rising edge. The VIN pulse must be at least 2 lines wide. In INTRO Mode, when configured for internal vertical synchronization, this pin will be an output pin providing an interrupt signal to the master control device in accordance with the settings in the Interrupt Mask Register. SDA (Pin 14). When the Serial Control Port has been set to I 2C mode operation, this pin serves as the bidirectional data line for sending and receiving serial data. In SPI mode operation it operates as serial data input. SPI mode output data is available on the SDO pin. Outputs SDO (Pin 16). Provides the serial data output when SPI mode communications have been selected. This pin is not used in I 2C mode operation. Box (Pin 17*). Black box keying output is an active High, CMOS level signal used to key in the black box in the captions/text displays. This output will be in the high- impedance state when the background attribute has been set to semi-transparent (*Z86129 only). RED, GREEN, BLUE (Pins 2*, 3*, 18*). Positive acting CMOS levels signals (*Z86129 only). Color Mode: Red, Green and Blue character video outputs for use in a color receiver. n Mono Mode: All three outputs carry the character luminance information. Notes: The selection of Color/Mono Mode is user controlled in bit D 1 of the Configuration Register (Address=00h). (See Internal Registers section.).

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 7 Pins With External Components CSync (Pin 8). Sync slice level. A 0.1 mF capacitor must be tied between this pin and analog ground VSS (A). This capacitor stores the sync slice level voltage. LPF (Pin 9). Loop Filter. A series RC low-pass filter must be tied between this pin and analog ground VSS (A). There must also be second capacitor from the pin to VSS (A). Values for the three parts to be specified at a later date. RREF (Pin 10). Reference setting resistor. Resistor must be 10 kohms, –2%. Power Supply VDD (Pin 12). The voltage on this pin is nominally 5.0 Volts and may range between 4.75 to 5.25 Volts with respect to the V SS pins. VSS (Pins 1, 11). These pins are the lowest potential power pins for the analog and digital circuits. They are normally tied to system ground. Note: The recommended printed circuit pattern for implementing the power connection and critical components will be supplied at a later date. Z86129/130/131 BLOCK DIAGRAM DESCRIPTION The Z86129 is designed to process both fields of Line 21 of the television VBI and provide the functional performance of a Line 21 Closed-Caption decoder and Extended Data Service decoder. It requires two input signals, Composite Video and a horizontal timing signal (HIN), and several passive components for proper operation. A vertical input signal is also required if OSD display mode is desired when no video signal is present. The Decoder performs several functions, namely extraction of the data from Line 21, separation of the normal Line 21 data from the XDS data, on-screen display (Z86129 only) of the selected data channel and outputting of the XDS data through the serial communications channel. Input Signals The Composite Video input should be a signal which is nominally 1.0 Volt p-p with sync tips negative and band limited to 600 kHz. The Z86129 will operate with an input level variation of –3 dB. The HIN input signal is required to bring the VCO close to the desired operating frequency. It must be a CMOS level signal. The HIN signal can have positive or negative polarity and is only required to be within 3% of the standard H frequency. When configured for EXT HLK operation, this signal should correspond to the H Flyback signal. The timing difference between HIN rising edge and the leading edge of composite sync (of VIDEO input) is one of the factors that will affect the horizontal position of the display. Any shift resulting from the timing of this signal can be compensated for with the horizontal timing value in the H Position register. Video Input Signal Processing The Comp Video input is AC coupled to the device where the sync tip is internally clamped to a fixed reference voltage by means of a dual clamp. Initially, the unlocked signal is clamped using a simple clamp. Improved impulse noise performance is then achieved after the internal sync circuits lock to the incoming signal. Noise rejection is obtained by making the clamp operative only during the sync tip. The clamped composite video signal is fed to both the Data Slicer and Sync Slicer blocks. The Data Slicer generates a clean CMOS level data signal by slicing the signal at its midpoint. The slice level is established on an adaptive basis during Line 21. The resultant value is stored until the next occurrence of that Line 21. A high level of noise immunity is achieved by using this process. The Sync Slicer processes the clamped Comp Video signal to extract Comp Sync. This signal is used to lock the internally generated sync to the incoming video when the video lock mode of operation has been enabled. Sync slicing is performed in two steps. In the non-locked mode, the sync is sliced at a fixed offset level from the sync tip. When proper lock operation has been achieved, the slice level voltage switches from a fixed reference level to an adaptive level. The slice level is stored on the sync slice capacitor, CSYNC. The Data Clock Recovery circuit operates in conjunction with the Digital H Lock circuit. They produce a 32H clock signal (DCLK) that is locked in phase to the clock run-in burst portion of the sliced data obtained from the Data Slicer. When Line 21 code appears, DCLK phase lock is achieved during the clock run-in burst and used to reclock the sliced data. Once phase lock is established it is maintained until a change in video signal occurs. The Digital H Lock circuit produces the video timing gates, PG, STG, and so on, which are locked in phase with HSYNC, the video timing signal, no matter which H lock mode is used in the display generation circuits. This independent phase lock loop is able to respond quickly to changes in video timing, without concern for display stability requirements.

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Z86129/130/131 BLOCK DIAGRAM DESCRIPTION (Continued) VCO and One Shot All internal timing and synchronizing signals are derived from the on-board 12 MHz VCO. Its output is the Dot Clk signal used to drive the Horizontal and Vertical counter chains and for display timing. The One Shot circuit produces a horizontal timing signal derived from the incoming video and qualified by the Copy Guard logic circuits. The VCO can be locked in phase to two different sources. For television operation, where a good horizontal display timing signal is available, the VCO is locked to the HIN input through the action of the Phase Detector (PH2). When a proper HIN signal is not available, such as in a VCR, the VCO can be locked to the incoming video through the Phase Detector (PH1). In this case the frequency detector (FR) circuit is activated as required to bring the VCO within the pull-in range of PH1. Timing and Counting Circuits The Dot Clk is first divided down to produce the character timing clock CHAR CLK. This signal is then further divided to generate the horizontal timing signals, H, 2H and HSQR. These timing signals are used in the data output (display) circuits. The H signal is further divided in the LINE and FLD CNTR to produce the various decodes used to establish vertical lock and to time the display and control functions required for proper operation. The H signal is also used to generate the Smooth Scroll timing signal for display. The V Lock circuits produce a noise free vertical pulse derived from the horizontal timing signal. When the user selects Video as the vertical lock source, the internal synchronizing signals are phased up with the incoming video by comparing the internally generated vertical pulse to an input vertical pulse derived from the Comp Sync signal provided by the Sync Slicer. In the vertical lock set to VIN mode the VIN signal is used in place of the signal derived from Comp Sync. In either case, when proper phasing has been established, this circuit outputs the LOCK signal which is used to provide additional noise immunity to the slicing circuits. The LOCKed state is established only after several successive fields have occurred in which these two vertical pulses remain in sync. Once LOCKed, the internal timing will flywheel until such time as the two vertical pulses lose coincidence for a number of consecutive fields. Until LOCK is established, the decoder operates on a pulse for pulse basis. Command Processor The Command Processor circuit controls the manipulation of the data for storage and display. It processes the Control Port input commands to determine the display status desired and the data channel selected. During the display time (lines 43-237), this information is used to control the loading, addressing and clearing of the Display RAM and the operations of the Character ROM and Output Logic circuits. During data recovery time (TV lines 21-42), the Command Processor, in conjunction with the data recovery circuits, recovers the XDS data and the data for the selected data channel. Data is sent to the RAM for storage and display and/or to the serial port, as appropriate. Where necessary, the Command Processor converts the input data to the appropriate form. Output Logic (Z86129 only) The output logic circuits operate together to generate the output color signals RED, GREEN and BLUE and the Box signal. When MONOchrome mode is selected all three color outputs will carry the Luminance information. These outputs are positive output logic signals. The character ROM contains the dot pattern for all the characters. The output logic provides the hardware underline, graphics characters and the Italics slant generator circuits. The smooth scroll display is achieved by the smooth scroll counter logic controlling the addressing of the Character ROM. Decoder Control Circuit The Decoder Control circuit block is the users communications port. It converts the information provided to the control port into the internal control signals required to establish the operating mode of the decoder. This port can be operated in one of two serial modes. The SMS pin is used to establish the serial control mode to be used. In the two wire (I 2C) control mode, the Z86129/130/131 will respond to its slave address for both the read and write conditions. If the read bit is Low (indicating a WRITE sequence) then the Z86129/130/131 will respond with an acknowledge. The master should then send an address byte followed by a data byte. If the read bit is High (indicating a READ sequence) then the Z86129/130/131 will respond with an acknowledge followed by a status byte then a data byte. Read data will only be available through indirect addressing. Write addressing will have both indirect and direct modes. The busy bit in the status byte will indicate if the write operation has been completed or if read data is available.

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 9 The SPI mode is a three wire bus with the Z86129/130/131 performing as the slave device. Communication is synchronized by the SCK signal generated by the master. Typically, the serial data output is transmitted on the falling edge of SCK and the received data is captured on the rising edge of SCK. All data is exchanged as 8-bit bytes. Voltage/Current Reference The Voltage/Current reference circuit uses an externally connected resistor to establish the reference levels that are used throughout the Z86129/130/131. The use of an external resistor provides improved internal precision at minimal additional cost. Z86129/130/131 FUNCTIONAL DESCRIPTION The Z86129 provides full function NTSC, Line 21 performance. Input commands are included to enable the decoder to process and display any of the eight Caption/Text data channels (CC1, CC2, CC3, CC4, T1, T2, T3 or T4) contained in Line 21 of either field of the incoming video. XDS data can also be selected for display. The DECODER ON/OFF commands control whether or not the Line 21 data in the selected channel is actually displayed. When switched to the DECODER OFF (TV) state, incoming data in the selected channel will still be processed but not displayed. The Z86129/130/131 can also be configured to operate with PAL or SECAM video signals. It will decode information encoded into its VBI in Line 22. The encoded data must conform to the waveform and command structure defined for NTSC Line 21 operation. VCO Lock The design includes a VCO with stable gain characteristics and good power supply rejection. The internal horizontal and vertical synchronizing circuits provide a high degree of noise immunity. There are options for both horizontal and vertical lock. The VCO can be phase locked either to the horizontal signal derived from the video input signal (VIDEO) or to the externally supplied HIN signal, typically horizontal flyback. HIN lock is used to provide a display having a minimum of observable jitter. This requires an HIN signal derived from the TV display and of the proper polarity. Such a signal is readily available in a television receiver. VIDEO lock mode enables the VCO to lock in phase to the incoming video signal, thus providing good operation in an application where no display related HIN signal is available, such as in a VCR. Video Timing Timing signals are derived from the VCO for use in the line counting and display circuits. Line counting requires proper identification of the input signal's vertical pulse. Default operation uses the vertical sync signal derived from the video input signal as the source for vertical lock. This method results in locking characteristics having good performance and good noise immunity. In the event that OSD operation is required under conditions when no input video is present, it would be necessary to set the Z86129 for VIN lock. In this mode, the vertical timing will be determined from the vertical pulse signal supplied to the VIN pin. The horizontal position of the caption display is determined by the internal timing circuits. A default condition has been established that should result in a well centered display in a typical application. However, since signal delays through video processing circuits can vary between designs, the Z86129 provides the user with the ability to change the default timing. No matter which of the horizontal lock modes are selected, the display horizontal position on the screen can be adjusted in quarter character (330 ns) steps by serial port commands. Displayable Character Set (Z86129 only) Normal Mode. Characters are displayed as white or colored dot matrix characters on an opaque background. The Box is normally black but the Z86129 can be set to a blue background Box with a serial command. The characters are described by a 12 by 18 dot pattern within a character cell which is 16 dots wide by 26 dots high per frame. The location of the character luminance within the character cell varies from character to character to allow for the display of lower case letters with descenders. All characters have at least a 1-dot border of black around each character. Underline is also provided. Figure 4 shows the Z86129 standard character map and font. The character ROM consists of a 12 by 18 dot matrix pattern per character. Figure 5 shows the character font. Alternate rows and columns are read out in each field to produce an interleaved and rounded character. A display row contains a maximum of 32 characters plus a leading and trailing black box, each a character cell in width, making the overall width of a display row 34 x 8 = 272 dots. Successive display rows are butted together so that the total display occupies 195 dots high. The black box 34 character cells wide by 195 dots high results in a box size of 45.018 ms in width by 195 scan lines in height. The Box starts in scan line 43 and extends to scan line 237. Theoretically, the display will be horizontally centered in the video display when the Box starts 13.2 ms after the leading edge of H.

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Z86129/130/131 FUNCTIONAL DESCRIPTION (Continued) The default setting of the Z86129 places the center of the Box at about 13.5 ms to allow for some delay in the normal video path. However, the Box horizontal position can be adjusted by the user in 330 ns increments. The display will be approximately within the safe title area for NTSC receivers. Character width is 42.37 ms also centered on the screen, resulting in a leading and trailing 1.32 ms black border. An optional Caption display mode, Drop Shadow, can be selected by the user through the serial port. This display mode eliminates the black box around the characters and places a 2-dot black shadow to the right and below the character luminance dots when in the 15 scan line per row mode. This display mode is usable in Captions, Text and OSD displays. Figure 5 shows the characters with shadowing added. Extended Features EIA-608 defined new extended features such as optional Background and Foreground display attributes and optional Extended Characters. The Z86129 will always respond to the Extended Characters but the Extended Background/Foreground response can be controlled by the user. The Background and Foreground attributes add codes for background colors, black foreground as well as transparent, opaque and semi-transparent background. The BOX signal output pin will be set to a tri-state condition whenever one of the semi-transparent attribute codes is active. The external keying circuits can then use this condition to implement the intended video display. The font for the Extended Characters are shown in Figure 6. The accented capital letters have been implemented by placing the accent marks above the character cell. When selected, this mode will result in the accent marks being written into the character cell space of the row above. In some operating modes the Z86129 will expand the size of the overall box height by adding two additional scan lines at the top and one additional line at the bottom. This will make room for the accent marks in the topmost row and add a black line below the descenders of any lowercase characters in the last row. This approach is desirable because shrinking the capitals to make room for the accent mark within the character cell makes poor quality characters and in some cases there would be no differentiation between the capital and lower case letter. It also has the advantage of minimizing the ROM size and providing a good readable font that closely matches what is normally seen in print. In the unlikely case of a conflict between an accented capital letter in one row and a lower case descender in the same character position in the row above, the descender is given priority. The improved readability of this approach over shrunk capital letters far outweighs this potential conflict and results in a cost-effective compromise for providing a full, extended features implementation. The Extended Characters share their address space with the OSD Graphics Characters. When a BOX display is used the Extended Character set is in force. However, if a Drop Shadow display is used the Graphics Characters are in force. For Caption and Text display modes, if Drop Shadow is set, the user must also command the Z86129 to switch back to Extended Characters.

Figure 4. Z86129 Standard Character Map and Font

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Figure 5. Caption Display Mode, Drop Shadow

Figure 6. Extended Characters Font

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Z86129/130/131 FUNCTIONAL DESCRIPTION (Continued) Text Mode Display (Z86129 only) When TEXT mode is selected, a black box will be displayed as long as valid Line 21 code in the field selected is being detected. The Z86129 provides the option to make the box blue instead of black. This option holds for Captions as well as Text. The default TEXT display mode uses a 15 row by 34 character black box. TEXT characters will be displayed as they are received starting in the top row. Successive carriage returns will move the display down successive rows until all 15 rows have been displayed. Thereafter, the text will scroll up as new characters are added to the bottom row. If the data for the selected channel is interrupted by a command for another channel, data processing will stop but the display will remain. When a Resume Text command is received, data processing will resume and the new characters will be added starting at the position that the display row/column pointer was in at the interruption of data processing. If a Start Text command is received, the display will be cleared and new characters will be displayed starting in row 1, column 1 (left side). The number of display rows and the location (base row) of the TEXT box, can be altered by the user. In this way, the user can decide how much of the screen can be covered when displaying non-program related information. When scrolling, the display will shift one scan line per frame until a complete row has been scrolled. If a carriage return is received before scrolling is complete, the display will immediately complete the “scroll” by jumping up the remaining scan lines and start displaying the new text. Caption Mode Display (Z86129 only) According to the FCC specifications Caption data can appear in any of the 15 display rows but a single caption may consist of no more than 4 rows. The form of the caption display depends on the caption mode indicated by the transmitted caption command, Pop-on, Paint-on or Roll-up. The Z86129 can display a single caption having as many as eight rows. When any of the CAPTION display modes have been selected, the screen will be transparent. (Display box is only present when a caption is being displayed.) Pop-on captions work with two caption memories. One of them is normally displayed while the other is being used to accumulate new caption data. A new caption is popped-on by swapping the two memories with the End Of Caption (EOC) command. When the on-screen memory is erased, the screen is blank (transparent) and the memory will default to the row/column pointer at row 1, column 1 and monochrome non-underlined. When caption mode is selected, the decoder will process any data following the Resume Caption Loading (RCL) command (or the EOC). Normally, this command will be followed by a Preamble Address Code (PAC) to indicate the row, column and character attributes to be used with the following data. If no PAC is received the data will be added to the location last indicated by the row/column pointer prior to the receipt of the RCL command. Paint-on caption mode is essentially equivalent to the Pop- on mode except that the data received after the Resume Direct Captioning (RDC) command is written to the on- screen memory rather than the off-screen memory. All the rules for PACs, Midcodes, and so on, are otherwise the same. Roll-up caption mode presents a “text” like display that is limited to 2, 3 or 4 rows, depending on the Resume Roll- up (RUn) command used. The PAC following the RUn command is used as the BASE ROW for the ROLL-UP display. The BASE ROW will be the “bottom” row of the ROLL-UP display. In this case, the black box does not appear until characters are being displayed and the box is only wide enough to provide a leading and trailing box in each line. The new data appears in the bottom row and as each carriage return is received, the row scrolls up and the new data added to the bottom. When the number of rows indicated by the Resume command has been reached, the data in the top row scrolls off as new data is added to the bottom. The TAB (INDENT) PAC permits placing Captions starting at 4 character boundaries in any caption row. The TAB OFFSET command provides the means for adjusting the starting position for a Caption at any column position in the current row.

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Display Erase and Autoblanking (Z86129 only) The display is erased in the TEXT mode by the Start Text command (but the box is maintained) and in the CAPTION mode by the Erase Displayed Memory (EDM) command. The non-displayed memory can be erased by the Erase Non-displayed Memory (ENM) command. Four other events can also cause the display to be erased. 1. A change in the display mode, such as from CC1 to T1, CC1 to XDSF, and so forth, will clear the memory and hence the display. 2. A loss of video lock, such as on a channel change, will cause the screen to be cleared. The current active display mode will not be changed. For example if CC1 was selected and ON before the channel change the device will remain in the CC1/ON state after channel change. 3. The third action that will clear the displayed memory is when the autoblanking circuit is activated. The autoblanking circuit monitors the presence of a Line 21 waveform in the video field corresponding to the data channel selected for display. The decoder is held in the Decoder OFF (TV) state until a Line 21 waveform is continuously detected for a period of 0.5 seconds. Once a valid Line 21 waveform has been detected for 0.5 seconds, and assuming that the user has selected the Decoder ON state, the normal display for the data channel selected will be presented. The autoblanking circuit will be not activate again until a valid Line 21 waveform has been lost for 1.5 seconds. Any data received during the 1.5 second period will reset the counter so that autoblanking will only be activated on continuous loss of the Line 21 waveform for 1.5 seconds. Note: Valid Line 21 waveform is defined as the presence of a 7-cycle run-in clock and a start bit on Line 21 of the field being examined. 4. The fourth method of clearing the screen is by the action of the 16 Second Erase Timer. This function is only active when a CAPTION or XDS display mode has been selected. If no data is received for the display channel selected for a 16 second period, the on-screen memory will be erased. The decoder will still be in the selected channel and with the decoder ON, so that when data for the selected channels resumes, it will be displayed. Z86129/130/131 FEATURE SET The primary features of the Z86129/130/131 are briefly described below. More complete descriptions can be found in later sections of this document. VBI Data Processing The Z86129/130/131 extracts the data in Line 21 of the incoming video. All data channels, in both video fields are supported. Specifically, the Z86129 can: n Process data from both fields of Line 21 simultaneously. n Output XDS data through the serial port while displaying selected data. n Output XDS data through the serial port raw or filtered. n XDS filters are selectable from a list of pre- programmed values including Program Rating and Time of Day/Local Time. n NTSC or PAL operation selectable. The data extracted from Line 21 of the incoming video by the Z86129 may be displayed in different ways according to the user selection and the type of data. The display features available on the Z86129 only are: n Ten different Line 21 data display modes; CC1-CC4, T1-T4, plus two standard templates for XDS displays. n Pop-on, Paint-on and Roll-up CAPTION displays. n TEXT display default is a full screen, 15 row display. n User can vertically reduce and reposition the TEXT display as desired. n Color or Monochrome display mode selectable. n XDSG Display Mode (channel grazing): automatic display of Network Name, Call Letters, Program Name, Program Length, and Time In Show data packets. n XDSF Display Mode (full information): automatic display of XDSG Display Mode information plus: Program Type (only basic types), and Program Description.

may be placed anywhere on the screen. than a solid, “black box” background).

1. A three wire, serial peripheral interface (SPI).
2. A total of five device pins are dedicated to the serial

brought Low, with SMS also Low, the part will be reset. Table 2. Z86129/130/131 Serial Control Signals SCK = Serial port clock for either Serial Mode. SDA = Serial port data for I2C Mode and Data In for SPI Mode. SDO = Serial Data Out for SPI Mode. Not used in I2C Mode. SEN = SPI Mode Enable signal. Must be High for I2C Mode.

18 DS96TEL0200

simultaneously, the part will be reset.

1. An INPUT pin for acceptance of an external VSYNC
2. An OUTPUT pin for interrupt generation on a selected

interrupt only when the desired packet is found. and Default Conditions upon Reset. Table 3. Z86129 Display Modes

2 N/A

Table 4. RESET Default Conditions

cases the Z86129/130/131 acts as a slave device. output. These pins are designated as shown in Table 5. is configured as an output, providing the INTRO signal. interrupt by writing to the Interrupt Request Register.

1. Data transfer can only be started when the bus is not
2. During data transfer, data transitions must not occur

Not Busy: Data and Clock lines both High. Acknowledge (NACK) is SDA=High. will read the data, MSB first, on the rising edge of SCK. Table 5. Z86129/130/131 Serial Control Signals SCK = Serial port clock for either Serial Mode. I2C Mode and Data In for SPI Mode. SDO = Serial Data Out for SPI Mode. Not used in I2C Mode. SEN = SPI Mode Enable signal. Must be High for I2C Mode. Table 6. Z86129/130/131 I2C Slave Addresses to an NRESET signal or tied High if no reset is desired.

20 DS96TEL0200

All write commands are either one or two byte commands. without a Stop condition will begin a new sequence. Slave ACK-DATA (master)/Slave ACK-Stop. register DAV bit to indicate availability of data. the Z86129/130/131output registers. are read in sequence separated by acknowledges. byte read) alone. All data is output MSB first. Figure 9. I

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SERIAL COMMUNICATIONS INTERFACE (Continued) SPI Bus Operation When the SMS pin is High the Z86129/130/131 will be in the SPI serial control mode. The clock line should be tied to the SCK pin. The DATA IN signal and DATA OUT signal from the master device should be connected to the SDA and SDO pins respectively. The SEN pin is used to select the Z86129/130/131 when there are multiple peripherals on the bus. As noted above, when both the SMS and SEN pins are Low, the part is in the RESET state. When the SPI bus is used in a dedicated fashion between the master and the Z86129/130/131, both the SEN and SMS pins would be tied High. The RESET function would require that both of these pins be tied to the NRESET signal. To ensure synchronization, the master should send the serial synchronization signal after the reset is released. When the SPI mode is used in a multiple peripheral environment, the SEN pin is used as the Z86129/130/131 enable signal. SMS could then be used for the NRESET signal as long as reset was only applied while SEN was Low. In this case, there would be no need for the master to send a serial synchronization string after reset if there was at least 100 ns between the end of reset and the start of port enable. A command string can be interrupted at any time and the port resynchronized by sending the Serial Sync signal or by the rising edge of SEN. The SPI bus is a three wire bus when used in a dedicated manner between the Z86129/130/131 and the master device. If other peripherals are connected to the bus, then the SEN pin must be used to place this device on the bus at the appropriate time. When SEN is Low, the SDO pin will be tri-state and transitions on the SCK and SDA pins will be ignored. If data output is not required from the Z86129/130/131, then control can be accomplished using only the SCK and SDA pins. Since this type of operation precludes the ability to check the RDY bit, it is very important that commands be spaced by at least two frames (133 msec) to ensure that one command has been executed before initiating another. The bus is controlled by the master device, which generates the serial clock (SCK) and initiates all actions. Clocking data in on SDA will simultaneously produce data out on SDO. The master should always check for the appropriate handshake signal before executing any command other than NOP. Writing to the part requires that the RDY bit be set while reading from the part requires checking the SS register to see if the DAV bit is set. Both of these bits are contained in the Serial Status (SS) register. Writing to the Z86129/130/131 will concurrently output the contents of the SS register, MSB first, unless other data is being output as a result of one of the READ commands. If it is desired to read the SS without executing a command, the NOP command can be written at any time, even if the serial status RDY bit is not set. The RDY status bit is driven onto the SDO pin between command transmissions. The controlling MCU can test the state of this pin without clocking in order to determine if subsequent serial transfers are possible. The DAV bit can only be checked by outputting the contents of the SS register. Writing to the SPI Bus All write commands are either one or two byte commands. The number of data bytes to be received by the Z86129/130/131 is inherent in the command. If the master writes more bytes than expected, the command may be overwritten or corrupted by the extraneous bytes. A write to the Z86129/130/131 should always be preceded by executing a Status read to verify that the device is ready. The serial status is output by the device concurrent with the input of any command byte. If the RDY bit of the serial status register is set, the master device can write a new command. The command and data bytes are written MSB first. The first byte of a two byte command is sent first. The bits are clocked into the Z86129/130/131 by placing the data on the SDA input and bringing SCK High. Reading Data Using the SPI Bus With the exception of the SS read, each read operation must be set up before the data can actually be read from the serial output registers of the device. Data is set up for a read operation either automatically or manually. XDS data is set up for READ automatically upon recovery by setting a valid XDS FILTER register selection. All other data read operations must be set up manually, using the READ SELECT commands RDS1 and RDS2. These commands load the selected data byte or pair of bytes into the serial output registers, set the SS register RD2 bit according to the number of data bytes requested and set the serial status DAV bit to indicate availability of data. The Z86129/130/131 SPI Bus supports two and three byte read sequences. In SPI mode, the SS must be read before a read sequence is started so that the DAV and RD2 bits can be checked. The number of data bytes available is indicated by the state of the RD2 bit. The special command READ1 or READ2 is then used to read the one or two available data bytes. The serial status is clocked out during

1. The first bit of the first output byte is driven out on SDO

of the READ1 or READ2 command.

1. Three-wire bus with Clock signal on SCK pin, Serial
2. SEN pin Low disabled the port, placing SDO in tri-

state. Signal transitions on SCK and SDA are ignored.

1. SEN pin High enables the port for operation.
2. SEN and SMS pins Low is a hardware reset for the

part. These pins must be held Low for at least 100 ns.

1. Serial synchronization can be established by clocking

in the minimum required SSR string of FFh, FFh, FEh. sequence can be entered without RDY being set. executed independent of the RDY status. data stream (Closed Caption or Text) for display. Table 8. Basic Serial Commands Figure 12. CPTX-Caption/Text Display

1 LANG CPTX DONOF

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that two bytes will be read. valid in the RDS1 command field AD00:02. recovered data bytes to the output register. Table 9. Caption and Display Commands Table 10. XDS Display Commands

16 Second Erase

Timer has no affect on the current display mode in operation. Figure 13. RDS1-Read One Byte (RDS1 = 40h-47h) Figure 14. RSD2-Read Two Bytes (RDS2 = 60h-66h)

0 AD02 AD01 AD00

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is in Drop Shadow mode (the default condition). screen can only use one set at a time. Table 12. Two-Byte OSD Display Mode Commands (Z86129 Only) row. rr can be any value from 00h to 0Fh. any value from 00h to 20h (column 0-32). Zero is the PAC space. A5h ddh Same as A3 command but specifies a double wide character. approximately the number of frames designated by the nn byte.

Figure 17. Z86129 Graphics or Extended Character Set

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Serial Status (SS) Register Address = Not Rqd. D 5-RD2. Signals the number of bytes available for output. Low = 1 byte, High = 2 bytes. Configuration Register Address = 00h. establish vertical sync lock: Low = Internal, High = VIN. VIN/INTRO pin will default to the INTRO output mode. register if VLK mode is used. lines/row. The default is Low. lines/row. The default is Low. Enhanced Attributes enabled. Figure 18. Serial Status Register Figure 19. Configuration Register (Address = 00h) Figure 20. Display Register (Address = 01h)

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XDS recovery has been enabled. to determine the current state. read to determine if XDS data is active. exactly which caption channels are now active. which TEXT channels are now active. the Interrupt Request Register to clear the Interrupt. Request Register will be used to cause an interrupt. register to zero disables interrupts. Table 13. XDS Secondary Filter Settings

1. Setting this register to 00h turns XDS data recovery off.

data will be output (even Reserved and Undefined).

1. The Time Information Only selection includes the Time of

Day (TOD) and Local Time Zone (LTZ) packets.

1. VCR Information will select TOD, LTZ, Net ID, Local Call

Out of Band Channel Number packets for recovery.

1. Program rating filter available on Z86129 and Z86130

Figure 25. Interrupt Request Register (Address = 06h) Figure 26. Interrupt Mask Register Address = 07h

1. The bit will be cleared to the Low state if no activity is

seconds or if there is a loss of lock. Services (XDS) information from the input video signal. miscellaneous data including time of day. performing its normal caption decoder or OSD functions. groups of packets that are of use in specific applications. state) XDS recovery is disabled. recovery regardless of their position in the video frame. Figure 27. Caption Activity Register (Address = 08h) Table 14. XDS Data Extraction - {C5,1F} All XDS packets recovered. {C5,01} All Current Class packets recovered. Number packets for recovery.

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INTERNAL REGISTERS (Continued) XDS data and header information (including START, CONTINUE, and END commands) are passed through the filter for the XDS class and type specified in the XDS Filter Register. All other Line 21 data is filtered out and will not be output, or used to generate a data available flag (DAV) in the Serial Status Register. To properly read filtered XDS data from the Z86129/130/131, the master device must first write the XDS Filter Register (05h) with its desired XDS Class and Type information. For example, in order to extract ONLY the Line 21 Program Rating information, the master must write the value 61h to the XDS Filter Register. The master should then poll the state of the DAV bit in the SSR until DAV = 1. As soon as DAV=1, the master may initiate a 3-byte read in the normal manner (XDS data bytes always arrive in pairs, so it is safe to assume that RD2=1 when DAV=1 in the SSB). A 3-byte read always yields two data bytes, which in this case will be the first two bytes of the Current Class, Program Rating Type XDS data stream encountered on Line21 field 2. The master device must then interpret those two bytes according to EIA-608 specifications for Current Class, Program Rating Type data. Refer to EIA-608 for data formats. The XDS filters on the Z86129/130/131 greatly reduce the amount of field 2 data passed on to the master device for further processing and interpretation. However, the master device must still interpret the filtered data stream in accordance with EIA-608. The filtered data stream from the Z86129/130/131 will be in full compliance with EIA- 608. In other words, the filtered data stream will contain all the XDS command and data packets, in standard EIA-608 format, but only for the selected XDS Class and Type(s). Note: The Z86129/130 XDS filter for Program Rating information behaves differently than all other Z86129/130 predefined XDS filters. This change has been made to minimize the amount of data passed through the Program Rating XDS filter, thereby minimizing the interpretation and communications load on the master device. When the XDS Filter Register is set to 61h (Class=01h (Current), Type=05h (Program Rating) the only data from Line 21 field 2 that will pass through the filter is: 1. Program Rating Packet: [xxh,00h]. The Current Class Program Rating data byte pair as defined in EIA-608. The program’s rating is encoded per EIA-608 in the byte xxh. 2. The END Packet [0Fh,CHKSUM]. A two-byte packet that includes a CHKSUM computed per EIA-608. The checksum calculation includes the START packet [01h,05h] even though this value was not passed through the filter.

Table 15. Z86129 Summary of Control Commands port itself. This sequence can be entered without RDY being set. independent of the RDY status. output register. Addresses 0h-7h are valid in the RDS1 command field AD00:02. READ1 F8h Command to read one byte in the SPI mode. READ2 F9h Command to read two bytes in the SPI mode. will be the data to be written.

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Table 16. Z86129 OSD Display Mode Commands PHYS ROW SEL A1h,rrh Sets the physical row, where the low order nibble of rr designates the physical row. rr can be any value from 00h to 0Fh. any value from 00h to 20h (column 0-32). Zero is the PAC space. WRITE CHAR A3h,ddh Writes the data byte dd to the current cursor location and then increments the cursor. A5h,ddh Same as A3 command but specifies a Double Wide character. approximately the number of frames designated by the nn byte. GRAPHICS 84h,30h Sets the Graphics Character set in force. EXTENDED 8Ch, 30h Sets the Extended Character set in force. Table 17. Summary of Z86129/130/131 Internal Registers

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 35 ON-SCREEN DISPLAY (Z86129 Only) OSD Operation The Z86129 has a fully programmable, general purpose OSD built in. The user can supply information for display through the serial port. In addition to all the normal and extended features of the VBI data display modes, OSD mode also has available added graphics characters, Double High and Double Wide characters and the ability to position the display anywhere on the screen with an adjustable (vertical) box size. The double-high and double- wide characters are especially useful for creating OSD screens for display inside a Picture-in-Picture (PiP) window. The OSD display mode can use either 13 or 15 lines per row, with box or drop shadow. The default is 15 scan lines per row and drop shadow. Enhanced attributes are always enabled. The 15 scan line per row display can only show 13 rows on screen when in the NTSC mode. Rows 14 and 15 will be off screen and should not be addressed. In the PAL mode all rows will be visible. The 15 scan lines per row mode display can show the full graphic characters and accented capital letters and descenders without the potential overlap that would result from the 13 scan line per row display. If the OSD display mode is changed to a 13 scan line per row mode, the top two scan lines of any graphics or accented capital letter will be “ored” together with the bottom two scan lines from the row above. In 13 line-drop shadow mode this will also result in a side shadow effect. Graphics characters should not be used in the 13 line-drop shadow mode. OSD Character Set There are 256 possible addresses in the OSD character set. Figure 28 shows the address map in the range 00h- BFh. This portion of the addressable space contains the control bytes and regular character set. The address map in the range C0h-FFh is shown in Figure 17. These addresses are shared by the Extended Character set and the Graphics Character set. Any particular OSD screen can use one or the other of these sets of characters but not both. The character set in force is controlled by the type of display mode being invoked. When Drop Shadow is being used, by default, the Graphics Character set will be displayed in response to an address in the C0h-FFh range. However, if a BOX display is used, the Extended Character set is invoked. In either case the user can switch to the other set by means of the appropriate command, GRAPHICS or EXTENDED. The VIN/INTRO pin serves as the input for a Vertical Pulse from the TV receiver when V Lock = VIN mode is enabled. This permits an OSD display even when no video input is present. If this mode is not required the default state V Lock = VIDEO should be active and this pin will then carry the INTRO output signal. OSD Commands OSD commands are one and two byte commands. They are used to control the loading of data for OSD display and their presentation to the screen. Normally OSD display mode uses 15 TV lines per display row to enhance the OSD presentation. The two byte commands enable direct access to any location on the display screen. The user may construct displays of his own choosing by using these commands. Each command byte pair consists of an instruction byte followed by a data byte. (See the Sample Z86129 OSD Programs below.)

36 DS96TEL0200

Figure 28. OSD Character Set

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 37 Note: In this product specification one and two byte commands are written as one or two, two-digit Hex values, separated by a comma, within curly braces. For example, the WRITE CHAR command for entering the letter A as a single width character would be shown in this document as {A3,41}. This command would write the letter A to the current cursor position of the display row being addressed. Refer to Serial Communications Interface and Commands sections for further details of the serial communications and the OSD commands. The one byte commands provide a simple means of creating OSD displays using preset screen formats built into the part. These built-in modes provide the user with a simple way to generate OSD screens. Two preset display modes are available called POPSET and TEXTSET. Using Popset POPSET provides an OSD mode that operates in a fashion similar to the Caption Pop-on mode. The POPSET command organizes the memory into two eight row blocks, one visible on screen and the other off screen. An OSD screen can then be created by loading the off screen memory by the command sequence POP ROW SEL, WRITE CHAR .. WRITE CHAR. The data can then be presented for on-screen display with the FLIP command. The following is an example of a command sequence that will create an OSD screen using the POPSET mode. It creates a typical menu screen used in television receivers. It should be noted that in this document commands are written as either a one, or two byte HEX value, separated by a comma, within curly braces (i.e., a sample two-byte OSD command: {A1,00}). Note: In the sample program below, a comment field is written following the command to describe the action of the command or sequence of commands, where appropriate. The comment field is identified by an asterisk (*) and any text following the * will be taken as a “comment” in the examples that follow. Sample OSD Program OSD Commands Function {33} *Select POP mode. Sets up the Z86129 internal memory organization to support POP mode. The first block of cmds will display > VIDEO in double wide chars. Each character is entered with the WRITE CHARD cmd. {A0,02} *Select POPROW 2, cursor at character column1 {A2,00} *move cursor to 0 {A3,08} *PAC for RED chars written in PAC location. {A5,3e} *Double wide char “>” will display in char col 1 & 2 {A3,02} *Green mid code written to char col {A5,56} *"V" written to char col 4 & 5. *The next block of cmds will display AUDIO in row 4 double width. {A0,04} *select poprow 4, cursor in char col {A2,03} *cursor to char col 3 {A3,02} *Green mid code written to char col {A5,41} *"A" written to char col 4 & 5. [A5,44] *"D" [A5,49] *"I" Notes: *The next set of commands will display the word “TIME” in row 6 with double-wide characters. Spacing is obtained without the A2 Cursor Set command to illustrate an alternate means of col- umn alignment.

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ON-SCREEN DISPLAY (Z86129 ONLY) (Continued) OSD Command Function {A0,06} * Select poprow 6, cursor in char col 1 {A3,02} * Green mid code written to character column 1 {A5,20} * Double wide space char written to character columns 2 & 3 {A5,54} * "T" written to char col 4 & 5. Note: * SET UP will be displayed in row 8 using double-wide chars. OSD Command Function {A0,08} *Select POPROW 8 {A2,03} * cursor to 3 {A3,02} *Green characters Note: * CLOSED CAPTION displayed in row 10 using double- wide characters. The last letter, N, will appear in character col- umn 30 and 31 OSD Command Function {A0,0a} * select poprow a {A2,03} * cursor to 3 {A3,02} * Green char Note: * The line, Select: ENTER EXIT: MENU, will appear in row 12, starting in character column 2. These will be displayed as single-wide characters [A5,4e] * "N" OSD Command Function {A0,0c} * select poprow c {A3,06} * CYAN char {36} * FLIP cmd. Will flip memories, popping the full menu on screen. OSD Command Function Note: * The line, Select: ENTER EXIT: MENU, will appear in row 12, starting in character column 2. These will be displayed as single-wide characters

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 39 Using Textset TEXTSET features an OSD mode that will paint on the screen in a manner similar to a TEXT Mode display. The memory will be organized using the current information in the Text Position register and the display will follow the current setting in the Display register. The default display parameters for OSD are 15 lines per row, Drop Shadow mode. The TEXTSET command can be followed by successive WRITE CHAR commands interspersed with the RETURN command at the appropriate points to paint on an OSD display starting at the top of the Text window as set by the Text Position register and moving to the next line at each RETURN command. The display will scroll if a RETURN command is sent when at the bottom of the Text window. A subsequent TEXTSET command will clear the screen and generate a new OSD screen. The following example shows an OSD display generated using TEXTSET. This screen will paint on rather than pop on. Features like flash are included in the command sequence for demonstration purposes. * The TEXT display is first set to 4 rows at the bottom of the screen. OSD Command Function {C3,D4} * set Textpos reg for base row 13, 4 rows {C1,80} * set OSD display for BOX mode, 15 lines/row {C2,A6} * set BOX to Blue, keep HPOS unchanged {32} * select TEXTSET mode * The next two cmds are used for positioning and color. {A2,05} * cursor to char pos 5 {A3,08} * mid code to make Red chars. Cursor moves to 6 {A3,B9} * mid code to start Flash, Cursor moves to 7 {A5,57} * 'W' double wide, char col 7,8 {A5,41} * 'A' double wide, char col 9,10 {A5,52} * 'R' double wide, char col 11,12 {A5,4E} * 'N' double wide, char col 13,14 {A5,49} * 'I' double wide, char col 15,16 {A5,4E} * 'N' double wide, char col 17,18 {A5,47} * 'G' double wide, char col 19,20 {A5,20} * ' ' double wide, char col 21,22 {30} * Return moves cursor to next row, char pos 1 {A2,00} * Cursor to char pos 0 {A3,0A} * PAC sets color to Y ellow, cursor moves to char pos 1 {A3,54} * 'T' single width, cursor moves to char pos 2 {A3,68} * 'h' {A3,65} * 'e' {A3,72} * 'r' {A3,65} * 'e' {A3,20} * ' ' {A3,69} * 'i' {A3,73} * 's' {A3,20} * ' ' {A3,61} * 'a' {A3,20} * ' ' {A3,74} * 't' {A3,6F} * 'o' {A3,72} * 'r' {A3,6E} * 'n' {A3,61} * 'a' {A3,64} * 'd' {A3,6F} *'o' {A3,20} *' ' {A3,69} *'i' {A3,6E} *'n' {A3,20} *' ' {A3,74} *'t' {A3,68} *'h' {A3,65} *'e' {A3,20} *' ' {A3,61} *'a' {A3,72} *'r' {A3,65} *'e' {A3,61} *'a' {A3,2E} *'.' {30} * Return moves cursor to next row, char pos 1 {A3,50} *'P' {A3,6C} *'l' {A3,65} *'e' {A3,61} *'a' {A3,73} *'s' {A3,65} *'e' {A3,20} *' ' {A3,74} *'t' {A3,61} *'a' {A3,6B} *'k' {A3,65} *'e' OSD Command Function

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ON-SCREEN DISPLAY (Z86129 ONLY) (Continued) * At this point all 4 rows are on screen. The following wait command will hold the display for a period = (12x16)/30 seconds. {a6,c0}* wait for 6.4 seconds. * Create a smooth scroll to clear the screen with the following 4 row sequence. * Create a new screen display {A3,20} *' ' {A3,61} *'a' {A3,6C} *'l' {A3,6C} *'l' {A3,20} *' ' {A3,6E} *'n' {A3,65} *'e' {A3,63} *'c' {A3,65} *'e' {A3,73} *'s' {A3,73} *'s' {A3,61} *'a' {A3,72} *'r' {A3,79} *'y' {30} * {A3,70} *'p' {A3,72} *'r' {A3,65} *'e' {A3,63} *'c' {A3,61} *'a' {A3,75} *'u' {A3,74} *'t' {A3,69} *'i' {A3,6F} *'o' {A3,6E} *'n' {A3,73} *'s' {A3,20} *' ' {A3,69} *'i' {A3,6D} *'m' {A3,6D} *'m' {A3,65} *'e' {A3,64} *'d' {A3,69} *'i' {A3,61} *'a' {A3,74} *'t' {A3,65} *'e' {A3,6C} *'l' {A3,79} *'y' {A3,2E} *'.'. OSD Command Function OSD Command Function {30} *Return, first row. {a6,0f} *wait 15 frames {30} *Return second row. {a6,0f} {30} *Return third row. {a6,0f} {30} *Return fourth row. {a6,0f} OSD Command Function {a3,74} *'t' {a3,68} *'h' {a3,69} *'i' {a3,73} *'s' {a3,20} *' ' {a3,77} *'w' {a3,61} *'a' {a3,73} *'s' {a3,20} *' ' {a3,6f} *'o' {a3,6e} *'n' {a3,6c} *'l' {a3,79} *'y' {a3,20} *' ' {a3,61} *'a' {a3,20} *' ' {a3,74} *'t' {a3,65} *'e' {a3,73} *'s' {a3,74} *'t' {30} *Return {a3,64} *'d' {a3,6f} *'o'

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 41 Using the WAIT Command The WAIT command will suspend serial port communications for a period of time. The TEXTSET example above used the WAIT command in two ways. First to hold a display on screen for a period of time before taking a second action. Then it was used to create a smooth scroll by timing the wait to the scroll rate. The WAIT command can also be used to control the appearance of two OSD displays in sequence without tying up the master device for the total display time. In the following example, the POPSET mode is used to pop on two sequential menu screens with a built-in pause between the two displays. In this case the WAIT is placed just before the last FLIP command. This allows the entire command sequence to be sent to the Z86129 at once, since the RDY bit will be set by the WAIT command, thus allowing the FLIP to be input as well. The command sequence would be as follows: * FLIP cmd. Will flip memories, popping the second menu on screen. Using The Graphics Character Set The following example creates an OSD screen which illustrates several features of the Z86129 including the use of the Graphics character set to generate a large font word. The particular features shown are purely for demonstration purposes and not intended to suggest a particular application. For the sake of brevity, the "text" to be displayed will be shown as a string within quotes rather than as the actual command sequences required. Single quotes, ', will signify standard characters while double quotes, ", will signify double wide characters. {a3,6e} *'n' {a3,27} *''' {a3,74} *'t' {a3,20} *' ' {a3,70} *'p' {a3,61} *'a' {a3,6e} *'n' {a3,69} *'i' {a3,63} *'c' {a3,2e} *'.' OSD Command Function {33} *select pop mode { .. } *screen generation commands for first display { .. } { .. } {36} * FLIP command. Will flip memories, popping the first menu on screen. {38} * OENM, to ensure non-displayed memory is erased. { .. } * screen generation commands for second display { .. } { .. } {A6,C0} *wait 6 seconds {36} OSD Command Function OSD Cmd Code Function {33} *select pop mode {A0,02} *select poprow 2 {A2,00} *Move cursor to 0 {A3,03} * PAC, GREEN chars 'THIS IS A DEMONSTRATION OF OSD' {A0,03} * select poprow 3 {A2,00} * cursor to 0 {A3,08} * PAC, RED char 'The Z86129 has many features' {A0,04} *select poprow 4 {A2,00} * cursor to 0 {A3,04} * Blue char 'besides displaying Captions.' {A0,06} *select poprow 6 {A2,00} *Move cursor to 0 {A3,07} * PAC, Cyan Underlined 'Color and Underline may be used' {A0,08} *select poprow 8 {A2,00} *Move cursor to 0 {A3,0a} * PAC, Y ellow chars *" DOUBLE WIDE" {A0,09} *select poprow 9 {A2,00} *Move cursor to 0 {A3,0c} * PAC, Magenta chars

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Manual Row Mapping and Control For most OSD displays the POPSET, POP ROW SEL, FLIP, TEXTSET and RETURN commands should be used to control row positioning. TEXTSET mode provides automatic row allocation from top to bottom of the screen with all rows continuously visible. Additionally, TEXTSET screens have a definable vertical window size and position and support automatic text scrolling at the bottom of the window. POPSET screens are created in off-screen memory while the previous screen is displaying. Up to 8 rows of characters can be defined. These rows can be mapped to any of 15 display rows using the POP ROW SEL command. Double high rows may also be defined with POP ROW SEL. The FLIP command is then used to "pop- on" up to 8 rows of characters replacing the previous screen. The off-screen rows may be mapped to the same row numbers as the on-screen rows. In some applications it may be necessary to access the display hardware at a lower level to achieve special screen effects. Examples of these special situations include the following: 1. More than 8 on-screen rows required in a "pop-on" style screen 2. Characters need to be added dynamically to an on- screen display 3. On-screen rows need to be dynamically moved, disabled or enabled The Z86129 supports manual screen mapping and display control commands to handle these special applications. These commands allow each of the 16 physical rows of character memory implemented in the device to be mapped to any of 15 display row positions. *'Graphics can be created like' *The next group of cmds will use Graphic Char patterns to make the two row * word HELLO. The data byte of the WRITE CHAR cmd is the address * location for the graphic cell desired as shown in Fig. 5. {A0,0b} *select poprow 11 {A2,00} *Move cursor to 0 {A3,06} *PAC, Cyan chars {84,30} * Set Graphics mode in case another user had changed it earlier. {A3,eb} * Graphic Cell {A3,ea} *Graphic Cell {A3,fb} * Graphic Cell {A3,ea} * Graphic Cell {A3,ea} * Graphic Cell {A3,fa} * Graphic Cell {A3,f5} * Graphic Cell {A0,0c} *select poprow 12 {A2,00} *Move cursor to 0 {A3,06} *PAC, Cyan chars {A3,ea} * Graphic Cell {A3,ea} * Graphic Cell {A3,eb} * Graphic Cell OSD Cmd Code Function {A3,eb} * Graphic Cell {A3,eb} * Graphic Cell {A3,eb} *Graphic Cell {A3,d7} * Graphic Cell {36} * flip OSD Cmd Code Function

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 43 Additionally the 16 physical rows can be set for single or double height and independently enabled and disabled. Manual row mapping and control commands should only be used in the POPSET OSD mode. The procedure for manual row control is as follows: 1. Use the POPSET command to select the OSD pop-up mode. This command prepares the Z86129 for OSD input, clears the row maps and erases character memory. 2. Select a physical row (0 through 15) using the PHY ROW SEL command. 3. Use the WRITE MAP command to set the display row (1 through 15), double high bit, and enable bit of the selected physical row. The CURSOR SET, WRITE CHAR and WRITE CHARD commands are used to position the cursor and write the characters in the selected physical row. A physical row may be re-selected at any time to change its characters, row maps, double high mode or enable status. For example, it may be desirable to load several rows of characters into physical memory without enabling them. All of the rows could then be made to "pop" onto the screen all at once by setting their enable bits. The following example uses manual row mapping and control to write three rows of characters. The first row is a double high row that is enabled before the characters are sent. This allows the characters to "paint" onto the screen as they are received. The second and third row are not initially mapped or enabled when the characters are written. They are then mapped and enabled after a two second pause. A new row is then created off-screen to replace the third row. Finally, after a 2 second pause the second row is moved to a new display row, the original third row is disabled and the new third row is mapped and enabled. OSD Command Code Function {33} *select POPSET mode {A1,00} *select physical row 0 {A4,31} * map it to display row 1, enable, double {A2,02} *cursor to 1 {A3,02} *green * double wide text *"The First Row " {A1,01} *select physical row 1 {A2,00} *cursor to 0 {A3,0a} * yellow *single wide text '*These two rows are' {A1,07} *select prow 7 {A2,00} *cursor to 0 {A3,06} *cyan *Single wide text '*enabled after a pause' {A6,40} *wait 2 seconds *do the map and enable {A1,01} *select physical row 1 {A4,16} {A4,16} *map it to display row 6, enable {A1,07} *select prow 7 {A4,17} *map it to drow 7, enable *prepare a new row to replace row 7 {A1,08} *select physical row 8 {A2,00} *cursor to 0 {A3,06} *cyan *Single wide text '*moved after a pause'

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Communicating with the Z86129 Communications with the Z86129 is accomplished using its serial communications interface. Through hardware setup, this interface can be configured into either of two serial protocols, I 2C or SPI. The details of hardware setup have been provided in the Serial Communications Interface section and will not be dealt with here. It is assumed that the user is familiar with the serial protocol requirements. Note: In the following descriptions <ENTER> means press the Enter key. An asterisk (*) signifies that everything following the asterisk in that line is a comment. I2C Operation The Z86129 is configurable as an I2C slave device with the seven-bit Slave Address=14h. Zilog can provide C language programs which enable a PC to perform as the I 2C master device in an application. The PC communicates with the Z86129 through its parallel port. These programs are not intended as examples of how to program the application but are only provided as a means of illustrating the serial control process and the capability of the Z86129. The three programs available are titled IICO, SCRIPTI and XDSCAP. These programs have been compiled and run satisfactorily with the Z86129 in a test board. Compiled versions are available on disk. Contact your local Zilog sales office for further information on these programs. IICO Program This program will send one byte to the Z86129 without checking the status of the READY bit. The program returns the contents of the Serial Status (SS) Register after the command has been entered. When the program is active the screen will display: IIC Command Byte > The user may enter any valid one byte command such as FBh (Reset) or 00h (NOP) and then hit the ENTER key. The screen will then display the byte entered and the SS register contents as follows: IIC Byte = 00 IIC Status = 83h The text above shows the NOP command was entered. The SS register contents, 83h, indicates that the RDY, FLD and LOCK bits are High indicating that the serial port is ready for further input, that the input video signal was in Field 1 at the time the status was read and that the part is operating in video lock mode. The IICO program is exited by entering a Control+C (^C) character. For example, entering the following single byte commands would: The commands that control most of the display capability of the Z86129 are all one byte commands which can be entered using the IICO program. These commands are tabulated below for convenience. {A6,40} * wait 2 seconds *make the modified display {A1,01} *select physical row 1 {A4,1A} *map it to display row 10, enable, double {A1,07} *select prow 7 {A4,00} *disable it {A1,08} *select prow 8 {A4,1B} *map it to row 11,enable, double OSD Command Code Function FBh, FC00h, 00h Reset the part. Reset the part. 17h *Set the part to CC1 display mode, decoder ON. 23h *Change to the XDS Graze display mode, 16 Second Timer ON. 17h *Return to the CC1 display mode, decoder ON.

Timer has no affect on TEXT mode displays. The responding slave address is reported to the screen. Figure 29. CPTX - Caption/Text Display

16 SECOND

er has no affect on the current display mode in operation.

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DEMONSTRATION PROGRAMS (Continued) Script Files Script files can be generated to perform all of the setup and control functions required to use the part in an application. The script files shown below are examples of such files used to setup the Z86129 for different operating conditions. Some of the files contain only a single command while others include several commands. The user should refer to the Command and Registers section for details. Although the following examples are organized according to a particular register, some of the files contain information for several registers. Configuration Register Script Files Display Register Script Files H Position Register Script Files Text Position Register Script Files XDSCAP Program This program performs the application's task of XDS data recovery. XDS recovery must first have been enabled through the appropriate XDS Filter command. Examples of Script files for setting the XDS Filter Register are shown below. The program is invoked by typing: xdscap<ENTER> When the program is invoked the PC screen will show: EEG CCD2 XDS Data Recovery Test Program Version x.xx Slave Address is 28h The responding slave address is reported to the screen. Once communication is acknowledged the program will display all XDS data recovered from those packets that were enabled through the XDS Filter command. For example: {01,03}Current Program{00}{0F,7F}....etc The ASCII characters are shown as ASCII characters while the non-printing characters are displayed by their Hex value within curly braces. Byte pairs, such as Class,Type, are shown as pairs within the curly braces, separated by a comma, i.e. {01,03}. File Name CMD {xxh,yyh} Comments FIGM {c0,02} * set config to mono FIGVH {c7,00} * set INT Mask register clear {c0,0c} * set config to ext VLK & HLK {83,12} * bit set ext V pulse for pos {c2,1d} * center h display FIGN {c0,00} * set config back to default state {c2,26} *return h display to center FIGPAL {c1,d2} *change display register to C15 & T15 {c3,ff} *change text pos register to base row 15, 15 rows {c0,01} *set config register to TVS=1. Changes VBI line to L22 PAL. File Name CMD {xxh,yyh} Comments DN {c1,c0} * set display register to default conditions DT1 {c1,c1} * set display register to TEXT drop shadow DT2 {c1,c2} * set display register to TEXT 15 lines per row DT3 {c1,c3} *set display register to TEXT drop shadow, 15 lines DT3A {c1,c3} * 15 tv lines and drop text {c3,dd} * 13 rows of text, base row 13 DCE {c1,e0} * disable CAP Enhanced mode File Name CMD {xxh,yyh} Comments HPOSC {c2,26} * center box HPOSR {c2,1d} * move box right 2.97 ms (from center) HPOSL {c2,29} * move box left 0.99 ms (from center) HPOSCB {c2,a6} * center box & make Box Blue File Name CMD {xxh,yyh} Comments TPOS15 {c3,ff} * Text, base row 15, 15 rows TPOS13 {c3,fd} * text base row 15, 13 rows TPOS10 {c3,fa} * text base row 15, 10 rows TPOS10A {c3,ba} * text base row 11, 10 rows

P R E L I M I N A R Y NTSC Line 21 Decoder DS96TEL0200 47 If no data is received within approximately 45 seconds, the program will time out, report "Data Not Available", and exit the program. Note: The XDSCAP program can also be exited by entering a Control C (^C) character. XDS Filter Register Script Files Using Interrupts Interrupts involve the use of the Line 21 Activity Register, the Interrupt Request Register and the Interrupt Mask Register. The Z86129 must be configured for VLK internal so that the VINTRO signal, Pin 13 is an output providing the interrupt output signal. The interrupt status can be polled through bit D3 of the Serial Status (SS) Register if the interrupt signal cannot be used. Interrupts are disabled when the Interrupt Mask Register has been set to all zeros. Conversely, interrupts are enabled by setting one or more of the active bits to a one. When enabled, the INTRO signal will become a one when the enabled mask event(s) becomes active. If more than one event has been activated, the Interrupt Request Register must be queried to determine which event has occurred. The DLE and EOF interrupts will be cleared at the end of the field in which they occurred. Interrupt Mask Register Script Files SPI Operation The serial port of the Z86129 may be configured to operate as an I 2C or SPI interface. The Z86129 always acts as the slave device with the master generating the required clock and input data signals. Two C language programs available from Zilog enable a PC to perform as the I 2C or SPI master device of an application. The PC communicates with the Z86129 through it's parallel port. These programs are not intended as examples of how to program the application but are only provided as a means of illustrating the serial control process. The two programs available, SEROUT and SCRIPT are the SPI equivalent to the I 2C programs IICO and SCRIPTI, respectively. These programs have been compiled and run satisfactorily with the Z86129 in a test board. Compiled versions are available on disk. SEROUT Program This program will send one byte to the Z86129 without checking the status of the READY bit. The program returns the contents of the Serial Status (SS) Register after the command has been entered. When the program is active the screen will display: SPI Command Byte The user may enter any valid one byte command such as 00h (NOP) and then hit the ENTER key. The screen will then display the byte entered and the SS register contents as follows: SPI Byte = 00 SPI Return Val = 83h The illustration above shows the NOP command was entered. The SS register contents, 83h, indicates that the RDY, FLD and LOCK bits are "ones" indicating that the serial port is ready for further input, that the input video signal was in Field 1 at the time the status was read and that the part is operating in video lock mode. When this program is used, a modified version of the RESET can only be used. It is entered as two, one-byte commands; FBh and 00h. The SEROUT program is exited by entering a Control C (^C) character. File Name CMD {xxh,yyh} Comments FILA {c5,1F} * set xds filter to all FIL0 {c5,00} * set xds filter to none. Turns off xds recovery FILCA {c5,01} * set xds filter to all current class FILC {c5,41} * set xds filter to current, in band class FILFA {c5,02} * set xds filter to all future class FILCH {c5,04} * set xds filter to channel class FILM {c5,08} * set xds filter for misc. info FILTIME {c5,28} * set xds filter time only FILVCR {c5,9e} * set xds filter vcr info File Name CMD {xxh,yyh} Comments INTRD {c7,02} * set DLE active INTRLK {c7,08} *set dLOK active INTRX {c7,20} *set dXDS active INTRC {c7,12} * set DLE & dC/T active

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DEMONSTRATION PROGRAMS (Continued) Script Program This program is designed to send any number of one or two-byte commands to the Z86129. The list of commands to be executed are contained in Script files that have the extension .SER. The Script files used with the I 2C version, SCRIPTI, can be used with this program. The program is invoked by typing: SI File_name<ENTER> Note: File_name without the .SER extension The screen will display: EEG CCD2 Serial Interface Script Player Version x.xx Script File Done When all the commands in the file have been successfully sent to the Z86129, the PC will return to the system prompt. The program checks the RDY status before sending each byte. If, during the entry of a command, the RDY bit is not found to be a "one", the program will report the contents of the SS register and then continue checking for RDY.

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ORDERING INFORMATION

For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Package P = Plastic DIP S = Plastic SOIC Temperature S = 0°C to + 70°C Speed 12 = 12 MHz Environmental C = Plastic Standard Z86129 (12 MHz ) 18-Pin DIP 18-Pin SOIC Z8612912PSC Z8612912SSC Z8613012PSC Z8613012SSC Z8613112PSC Z8613112SSC Example: Z 86129 12 P S C is a Z86129, 12 MHz, DIP , 0° to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix