Z08611 ZILOG | Alldatasheet
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WS AIL Ng ee et Product Specification “atts ; Teda-iA-07 June 1987 : - Z8601/Z8603 : : 78611/Z8613 Z8® ce ~ 78601 Single-Chip MCU with 2K ROM
78603 Prototyping Device with 2K EPROM Interface
: 28611 Single-Chip MCU with 4K ROM . . 28613 Prototyping Device with 4K EPROM Interface EE ooo Features m Complete microcomputer, 2K (8601) or 4K @ Full-duplex UART and two programmable (8611) bytes of ROM, 128 bytes of RAM, 32 8-bit counter/timers, each with a 6-bit V/O lines, and up to 62K (8601) or 60K (8611) programmable prescaler. bytes addressable external space each for @ Register Pointer so that short, fast instruc . program and data memory. . tions can access any of nine working register @ 144-byte register file, including 124 general- groups in ] ps. purpose registers, four I/O Port registers, @ On-chip oscillator which accepts crystal or and 16 status and control registers. external clock drive. @ Average instruction execution time of 1.5 ys, @ Single +5 V power supply—all pins TTL maximum of 1 ps. compatible. @ Vectored, priority interrupts for I/O, w 12.5 MHz. counter/timers, and UART. . General The Z8 microcomputer introduces a new level stand-alone microcomputer with 2K or 4K bytes Description _ of sophistication to single-chip architecture. of internal ROM, a traditional microprocessor Compared to earlier single-chip micro- that manages up to 124K bytes of external . computers, the Z8 offers faster execution; more memory, or a parallel-processing element ina efficient use of memory; more sophisticated * system with other processors and peripheral interrupt, input/output and bit-manipulation , controllers linked by the Z-BUS® bus. In all capabilities; and easier system expansion. configurations, a large number of pins remain . Under program control, the Z8canbetailored —_ available for I/O. . to the needs of its user. It can be configured as a : ay, west ev : +svCj1 4017 P3, TIMING nw GND xTat2 [J 2 39 [] P3, contaon os XTALI xratt [3 38 fy 2; BE XTAL2 ‘eLock . ps, C4 a7] py PO P2 pa, Cs 36 [J pay PO, - P2, Reset (J 6 35 [] Pa, PO, P2 aw (}7 34 [7] p2, PROGRAMMABLE) Po, P2y ‘GRAMMABLE) AS{)9 32L] p2, YO OR As-Ais any zeco Ps vo P35 [] 10 Zeeotit 31 [7] Pay PO, out P25 Tr) Pag ‘ Pty . Py Po, (] 13 28 [] Pt, Py 23, . Po, [] 14 a] Pn ; : Ph P, Po, [] 15 26] Pts eeyTe Pty P3 SERIAL AND Pos [16 25} Pte PROGRAMMABLE) Pi, Pa, PARALLEL 1/0. Po, [) 17 at}, | WO OR ADp-ADy Pts Pa AND CONTROL Po, [| 18 23] pi, . Pty Pa Po, C] 19 22,7] Pt, Pty P3, ro, [J 20 211] Pte Figure 2a. 40-pin Dual-In-Line Package (DIP), : Pin Assignments —SSFSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSsSSS
Pin KS. Address Strobe (output, active Low), program execution begins from internal Description Address Strobe is pulsed once at the begin- program location 000Cy. -ning of each machine cycle. Addresses output — . fe nin : via Port Hor all external program or data P ROMless. (input, active LOW). This pin is only - ” memory transfers are valid at the trailing edge available on the 44 pin version of the Z8611. of AS. Under program control, AS can be . When connected to GND disables the internat placed in the high-impedance state along with ROM and forces the part to function as a Z8681 Ports 0 and 1, Data Strobe and Read/Write. ROMless Z8. When left unconnected or pulled ; DS. Data Strobe (output, active Low). Data pane Veg the part will function normally as a Strobe is activated once for each external . : memory transfer. R/W. Read/Write (output). R/W is Low when _ _, P09-P07, Plo-Ply, P29~P27, P3g-P37. I/O Port the Z8 is writing to external program or data Lines (input /outputs, TTL-compatible). These memory. 32 lines are divided into four 8-bit I/O ports ; XTALI, XTAL2. Crystal 1, Crystal 2 (time-base that can be configured under voriace.. control input and output). These pins connect a parallel for 1/O or external memory interface. resonant 12.5 MHz crystal or an external single- RESET. Reset (input, active Low). RESET ini- phase 12.5 MHz clock to the on-chip clock . tializes the Z8. When RESET is deactivated, oscillator and buffer. > x : , LEELEE COOL . 6 & 4 3 2 1 44 43:42 41:40 preset |7 a9} Nc RW Ie - 38 | P2, DS is 37 | P23, KS 10 36 | P22 PIs [14 a5 | Pa; ono 12 aan 34 | P29 . ° . P32 113 cu 33 | P33 . POp [14 320 P34 Po, J 15 3t | Piz P02 116 30] Pig " ROMiess | 17 29] Pts - 18 19 20 21 22 23 24 25 26 27 28 . PPM Mh ees Figure 2b, 44-pin Chip Carrier, Pin Assignments .
—_— Architecture 28 architecture is characterized by a flexible Three basic address spaces are available to V/O scheme, an efficient register and address support this wide range of configurations: space structure and a number of ancillary program memory (internal and external), data - features that are helpful in many applications. memory (external) and the register file (inter- . Microcomputer applications demand power- nal), The 144-byte random-access register file ful /O capabilities. The Z8 fulfills this with 32 is composed of 124 general-purpose registers, . * pins dedicated to input and output. These lines four I/O port registers, and. 16 control and are grouped into four ports of eight lines each status registers. . and are configurable under software control to To unburden the program from coping with | . provide timing, status signals, serial or parallel real-time problems such as serial data com- V/O with or without handshake, and an address/ munication and counting/timing, an asynchro- data bus for interfacing external memory. nous receiver/transmitter (UART) and two Because the multiplexed address/data bus is counter/timers with a large number of userse- merged with the I/O-oriented ports, the Z8 can lectable modes are offered on-chip. Hardware assume many different memory and I/O con- support for the UART is minimized because one figurations, These configurations range from of the on-chip timers supplies the bit rate. a self-contained microcomputer to a micropro- : . cessor that can address 124K (Z8601) or 120K (28611) bytes of external memory. . . oureur iwPur Veo GND XTAL AS DS RW RESET PROGRAM 200g BT FLAGS LJ . oop E8IT : @ am} | |_ i CONTROL, . = fo uo ADDRESS OR WO ADDRESSIDATA OR UO (GIT PROGRAMMABLE) (NIBBLE PROGRAMMABLE) . (BYTE PROGRAMMABLE) 7 . Figure 3. Functional Block Diagram
The first 2048 (Z8601) or 4096 (28611) bytes program memory space. reserved for the interrupt vectors. These loca- shown in Figure 6. Figure 4. Program Memory Map Figure 5. Data Memory Map -
255 SPL 288
. 0 rR . the eclive working-register group.
28 POM 147
248 PREC
0 Po 0
. divided into nine working-register groups, each = A 16-bit Stack Pointer (R254 and R255) is used for occupying 16 continguous locations (Figure 6). the external stack, which can reside anywhere in The Register Pointer addresses the starting data memory between locations 2048 (8601) or location of the active working-register group. 4096 (8611) and 65535. An 8-bit Stack Pointer Stacks. Either the internal register file or the (R255) is used for the internal stack that resides external data memory can be used for the stack. within the 124 general-purpose registers (R4-R127). Serial Port 3 lines P3g and P37 canbe programmed as __ selection. If parity is enabled, the eighth bit is Input/ serial I/O lines for full-duplex serial asynchro- the odd parity bit. An interrupt request (IRQ,) is Output nous receiver/transmitter operation. The bitrate generated on all transmitted characters. is controlled by Counter/Timer 0, at 12 MHz. Received data must have a start bit, eight data . bits and at least one stop bit. If parity is on, bit 7 . The Z8 automatically adds a start bit and two of the received data is replaced by a parity error stop bits to transmitted data (Figure 8). Odd flag. Received characters generate the IRQ3 Parity is also available as an option. Eight data interrupt request. : . bits are always transmitted, regardless of parity . Transmitted Data ° Received Data . (No Parity) (No Parity) Le sean ar ~ Legranr oe EIGHT DATA BITS. = EIGHT OATA BITS: "7WO STOP BITS ONE STOP BIT Transmitted Data Received Data - (With Parity) (With Parity) ; Lesran ar . LL santo Ss SEVEN DATA SITS : SEVEN DATA BITS ‘ ODD PARITY PARITY ERROR FLAG TWO STOP BITS ONE STOP BIT . Figure 8. Serial Data Formats —_— eee Counter/ The Z8 contains two 8-bit programmable pass mode) or to automatically reload the initial Timers counter/timers (Tg and T}), each driven by its value and continue counting (modulo-n contin- own 6-bit programmable prescaler. The T) uous mode). The counters, but not the presca- . prescaler can be driven by internal or external Jers, can be read any time without disturbing clock sources; however, the Tg prescaler is their value or count mode. driven by the internal clock only. The clock source for T) is user-definable and The 6-bit prescalers can divide the input fre- can be the internal microprocessor clock quency of the clock source by any number from divided by four, or an external signal input via 1 to 64. Each prescaler drives its counter, which Port 3. The Timer Mode register configures the decrements the value (1 to 256) that has been external timer input as an external clock, a loaded into the counter. When the counter trigger input that can be retriggerable or non- reaches the end of count, a timer interrupt retriggerable, or as a gate input for the internal request—IRQ, (to) or IRQs (T})—is generated. clock. The counter/timers can be programmably The counters can be started, stopped, cascaded by connecting the Tg output to the restarted to continue, or restarted from the input of T). Port 3 line P3g also serves as a timer initial value. The counters can also be pro- output (Toyr) through which To, T) or the inter- grammed to stop upon reaching zero (single- nal clock can be output.
1/O Ports The Z8 has 32 lines dedicated to input and outputs, timing, status signals, serial I/O, and output. These lines are grouped into four portsof _ parallel I/O with or without handshake. All ports eight lines each and are configurable as input, have active pull-ups and pull-downs compatible output or address/data. Under software control, with TTL loads. . soot the ports can be programmed to provide address . Port 1 can be programmed as a byte I/O port allowing the Z8 to share common resources in or as an address/data port for interfacing multiprocessor and DMA applications. Data external memory. When used as an I/O port, Port _ transfers can be controlled by assigning P33 asa 1 may be placed under handshake con- Bus Acknowledge input and P34 as a Bus trol. In this configuration, Port 3 lines P33 and + Request output. . P34 are used as the handshake controls RDY) . and DAV) (Ready and Data Available). . . Memory locations greater than 2048 (28601) or PORT a 4096 (28611) are referenced through Port 1. To . MOOR ADEA) interface external memory, Port 1 must be zB programmed for the multiplexed Address/Data : Mcu mode. If more than 256 external locations are HANDSHAKE CONTROLS required, Port 0 must output the additional ) pa AN no mt . ines. Port 1 can be placed in the high-impedance - . state along with Port 0, AS, DS and R/W, . Figure Sa, Port 1 Port 0 can be programmed as a nibble I/O the lower nibble is used for addressing. When port, or as an address port for interfacing Port 0 nibbles are defined as address bits, they external memory, When used as an I/O port, can be set to the highimpedance state along with Port 0 may be placed under handshake con- - Port 1 and the control signals AS, DS and R/W. trol. In this configuration, Port 3 lines P32 and ‘ . Pg are used as the handshake controls DAVo 1 . and RDYp. Handshake signal assignment is , dictated by the I/O direction of the upper nibble Ponto PO4-PO7. : za WOOR ALA) . For external memory references, Port 0 can. MCU provide address bits Ag-Aj) (lower nibble) or |< | HANDSHAKE CONTROLS Ag-Aj5 (lower and upper nibble) depending on ) Bavg ano nove the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while Figure th. Port 0 Port 2 bits can be programmed independently . as input or output. The port is always available . . for I/O operations. In addition, Port 2 can be — : configured to provide open-drain outputs. 28 <> } pont 20) Like Ports 0 and 1, Port 2 may also be MCU placed under handshake control. In this con- figuration, Port 3 lines P3; and P3g are used as > } BNPAND mgs nots the handshake controls lines DAV2 and RDY2. ’ ae AND Pad . The handshake signal assignment for Port 3 lines . P3) and P3¢ is dictated by the direction (inputor ~ . Figure 9c, Port 2 output) assigned to bit 7 of Port 2. Port 3 lines can be configured as I/O or . control lines. In either case, the direction of the . <— . eight lines is fixed as four input (P39-P33) and four output (P34-P37). For serial I/O, lines P39 . 28 {HOGA CONTROL) . and P3,7 are programmed as serial in and serial MCU out respectively. . . uo . Port 3 can also provide the following con- . trol functions: handshake for Ports 0, 1 and 2 (DAV and RDY); four external interrupt request signals (IRQg-IRQs); timer input and Figure 9d. Port 3 . output signals (Ty and Toyr) and Data : Memory Select (DM)! -— 2037-008
Interrupts The Z8 allows six different interruptsfrom ~ cycle is entered. This disables all subsequent eight sources: the four Port 3 lines P39-P33, interrupts, saves the Program Counter and status Serial In, Serial Out, and the two counter/timers. _ flags, and branches to the program memory These interrupts are both maskable and vector location reserved for that interrupt. This prioritized. The Interrupt Mask register globally memory location and the next byte contain the or individually enables or disables the six inter- 16-bit address of the interrupt service routine for . rupt requests. When more than one interrupt is that particular interrupt request. pending, priorities are resolved by a pro- Polled interrupt systems are also supported. To grammable priority encoder that is controlled by accommodate a polled structure, any or all of the the Interrupt Priority register. interrupt inputs can be masked and the Interrupt : All Z8 interrupts are vectored. When an inter- Request register polled to determine which of the . rupt request is granted, an interrupt machine interrupt requests needs service. nS SEY Clock . The on-chip oscillator has a high-gain, (C, s 18 pF) from each pin to ground. The . parallel-resonant amplifier for connection toa specifications for the crystal are as follows: crystal or to any suitable external clock source m AT cut, parallel resonant (XTAL] = Input, XTAL2 = Output). @ Fundamental type, 12.5 MHz maximum The crystal source is connected across XTALI m Series resistance, R. < 1002 . and XTAL2, using the recommended capacitors ue
Z8603/13 The Z8 Protopack is used for prototype equipped with 12 ROM address lines, 8 ROM Protopack development and preproduction of mask- data lines and necessary control lines for inter- Emulator programmed applications. The Protopack is a face to 2732 EPROM for the first 4K bytes of ROMless version of the standard 28601 or Z8611_-- program memory. housed in a pin-compatible 40-pin package Pin compatibility allows the user to design the (Figure 11). pc board for a final 40-pin maskprogrammed . To provide pin compatibility andinterchange- —_Z8, and, at the same time, allows the use of the ability with the standard maskprogrammed Protopack to build the prototype and pilot device, the Protopack carries piggy-back a 24- production units. When the final program is pin socket for a direct interface to program established, the user can then switch over to the . memory (Figure 1). The 28603 24-pin socket is * 40-pin mask-programmed Z8 for large volume . equipped with 11 ROM address lines, 8 ROM production. The Protopack is also useful in data lines and necessary control lines for inter- small volume applica tions where masked ROM face to 2716 EPROM for the first 2K bytes of pro- _ setup time, mask charges, etc., are prohibitive gram memory. The 28613 24-pin socket is and program flexibility is desired. : Compared to the conventional EPROM A . versions of the single-chip microcomputers, the Ps ~~ . . Protopack approach offers two main . 4 LF a . advantages: Ext ~ tied : Ease of developing various programs during ae i Fe the prototyping stage. For instance, in appli- . { tne: eee i ey . cations where the same hardware configura- aes hee ‘= oF tion is used with more than one program, the N Os) 2 0 his Protopack allows economical program ” OR Pe Puig storage in separate EPROMs (or PROMs), . . . <P . whereas the use of separate EPROM-based : t single-chip microcomputers is more costly. @ Elimination of long lead time in procuring Figure 11, The 28 Microcomputer Protopack Emulator EPROM-based microcomputers. a Instruction Addressing Modes. The following notation is used Assignment of a value is indicated by the symbol Set to describe the addressing modes and instruction “=", For example, Notation operations as shown in the instruction summary. dst — dst + sre IRR _Indirect register pair or indirect working-register indicates thal the source data is added to the. ede reci : ‘destination location. The notation "addr(n)” is used indirect working-register pair only to refer to bit “n’ of a given location. For example, x Indexed address . DA _ Direct address . dst (7) RA Relative address refers to bit 7 of the destination operand, IM Immediate ‘ . e R Register or working-register address ee Control Register R252 contains the following r Working-register address only IR Indirect-register or indirect working-register c Carry flag address r4 Zero flag Ir Indirect working-register address only s Sign flag . RR Register pair or working register pair address v Overflow flag Symbols. The following symbols are used in D —_Decimal-adjust flag. : describing the instruction set. H Hali-carry flag : dst Destination location or contents ‘Affected flags are indicated by: stc Source location or contents ce Condition code (see list) . 0 Cleared to zero @ _ Indirect address prefix 1 Set to one SP _ Stack pointer (control registers 254-255) * Set or cleared according to operation PC Program counter . - Unatfected - : FLAGS Flag register (control register 252) x Undefined . RP _Regisler pointer (control register 253) IMR Interrupt mask register (control register 251) .
Codes | 1000 . ‘Always true .
0101 Mi Minus S$ =1
1110 NE Not equal Z =0
1001 GE Greater than or equal (S XOR V) = 0 ,
0001 LT Less than (8 XOR V) = 1
- GT Greater than [Z OR (S XOR V)] = 0
011) ULT Unsigned less than Cel .
1011 UGT _ Unsigned greater than (C=0ANDZ=0) =1
0011 ULE Unsigned less than or equal (CORZ) =1
0000 Never true ~
. [mone | ore] LDE,LOEI, [Mone | orc | ba . Figure 12. Instruction Formats
Instruction Instruction Addr Mode Opsode Flags Affected Instruction Addr Mode Opeode Flags Affected Summary and Operation dst mc (Hex) CZSVDH and Operation “ast src (Hex) GC ZSVDH dst — dst + src + C dst — sro muy r 92. ADD dst,sro (Note 1)° oo tee ea Oe *LDEI dst,sro Irs ier 83 ween ane dst — dst + sro dst ~ sro In Ir 93 AND dst,sre (ote) sO -eeo-- fotthemed . see. Ps 26 4 IRR D4 dst — dst OR sro . CCF EF *----- dst-@SP IR 51 C-NOTC SP - SP +1 dt-O 7 ORT BE SP SP-1; @SP~sro IR n COM dst R 60 -#*0-- RCF CF O0----- dst — NOT det IR 61 c-0 CP dst,src (Note 1) AO ee a RET : AF eoceee dst ~ sro PC — @SP; SP~SP +2 DA dst R 40 #4*X-- RL dst R 9 «eee-- dst — DA det IR 4l "od ik 91 DEC dst R 00 -#eee- RIC dst R 1 #eee-- dst—dst-1 AR a aH fh un DECW dst RR 80 ~#*+-— Rast GF R EO «++. dst — dat~ 1 IR al - oe ecko RE a as RRC dst (oq) B co tee eee DI : : IR Cl IMR (7) — 0 oF LL SS ee SBC dst,arc (Note 1) 3c) tee ele DINZ rdet RA TA can cae~ ait=dst-sro+C rer-l 1=0-F : SCF DF ol----- TBE ope + ant cnt -PC+ a nee R : +127, -128 . . SRA dst R DO eeeQee IMR (7) ~ 1 RP ~ sro ING dst r ve -**+*-- §gUpdaue Noob age dst — dst + 1 R 150-F SUB detiro (Note 1) 20 te eel IR 21 SWAP dst ty B HO x «ex - INCW det RR AO -eee--) — ere dst — dst +1 IR Al TCM dst,sre (Note 1) 60 -*+#0-- iRET BF wees (NOT dst) AND sro FLAGS ~ @SP; SP—SP +1 ‘TM dst, sre (Note 1) 70. -+*+*0-- PC — @SP; SP— SP + 2; IMR(7) —} dst AND sre if co is true cn 0-F XOR dstare we (Note 1) BDO *+0 POR dt RR TR co,dst RA cB -~----- Note! a sole tres ast o=0-F ‘Thos instructions haye an identical et of adaressing 2 - modes, which are enc for brevity. The first opcode . . Range: +127,-128 tbe is found in the instruction set fable above. The LD dst,src r Im roe second nibble is expressed symbolically by a 1 in this dst — sre r R 18 : fable, and Sts value is found in the following table fo the R r rg right of the applicable addressing mode pair. r=0-F For example, to determine the opcode of a ADC r x C7 instruction use the addressing modes r (destination) and xX of D7 Ir (cource). The result is 13, ror E3 kor F3 —_ oR EA. Addr Mode Lower . R IR E5 aoe . . R in Fe an are Opcode Nibble : IR Im, £7 —_ OO mR oR’ FS r r [ey LDC, dst,sre rol C2 =----- r Ir. fe] 0 dst — erc Ir or D2 . RR . @ ost Tth mer + i" * Bs R IM i) . IR IM a .
Registers R240 SIO R244 TO . Serial 1/O Register © , Counter/Timer 0 Register (FOy; Read/Write) : (F4y; Read/Write) : ‘Te CUARENT VALUE (WHEN READ) . R241 TMR R245 PREO . Timer Mode Register : Prescaler 0 Register (Fly; Read/Write) (F5y; Write Only) uy MODES 0 = No FUNCTION L wor Uata'o' 00 Le = LOAD Ty - eee Leeass TeQUT = 04 0 = DISABLE T, COUNT 4 = 12 MOBULON INTERNAL CLOCK GUT = 11 1» ENABLE Tp COUNT Ty MODES 0 = NO FUNCTION RESERVED TRIGGER INPUT = 10 4 = ENABLE T; COUNT PRESCALER MODULO r (RANGE: 1-64 DECIMAL (RETRIGOERABLE) . “ -RA2 Th R246 P2M Counter Timer 1 Register. Port 2 Mode Register (F2y; Read/Write) (F6y; Write Only) . : [2,]>Jo.]>.]os]021>,]0.} CACACACA CAAA Ty NITIAL VALUE CHEN whtTTEND 25-2, LO DEFINITION : (RANGE 1-255 DECIMAL 01-00 HE) ODEFINES BIT AS OUTPUT T, CURRENT VALUE (WHEN READ) 4 DEFINES BIT AS INPUT R243 PREL . . R247 P3M Prescaler 1 Register Port 3 Mode Register - (F3q; Write Only). (F7y; Write Only) = Ty SINGLEPASS 4 PORT 2 PULLUPS ACTIVE 1 = T, MODULON ReSERVED . : Lock souRcE : = 092 = INPUT pas = OUTPUT SS RINTERNAL ve ineur 4 233 = BAVORDYO P35 © ROYODAYD (To) MODE 90 P33= INPUT P24 = OUTPUT . PRESCALER MODULO O3)poa = INPUT, pb = OM GRANGE: {64 DECIMAL 11 P92 = DAVIIROYS P34 = ADYIIDAVI , 223 ZARA = RE . 9730 = (NPUT a7 = OUTPUT : 190 = SERIALIN P37 = SERIAL OUT
0 PARITY OFF
. 1 PARITY ON
Registers ~ ‘R248 POM R252 FLAGS (Continued) Port 0 and I Mode Register Flag Register {F83; Write Only) (FCy; Read/Write) #04-P0; MODE y-P0, MODE . | Lose FLAG FI apr] Lyrae SER AO 2 ah oe : Me Aran HALF CARRY FLAG ‘EXTERNAL MEMORY THING STACK SELECTION DECIMAL ADJUST FLAG a "EN ame senna . $02 ADpADr CARRY FLAG 4 HIGH-IMPEDANCE ADg-AD?, - AS, 0S, RAT, As-Ats, Arz-ALS iF SELECTED , 249 IPR R253 RP Interrupt Priority Register Register Pointer : . - (F8y; Write Only) (FDy; Read/Write) seseaveo—] ‘TEBRUPT GROUP PRIORITY ol Tow cane #803, INOS PRIORITY (GROUP A) G>A>B = O01 recisten . ' : #809, 1RO2 PRIORITY (GROUP 8 G>esAq 101 . " . FRQH, [ROS PRIORITY (GROUP C) . = IRs > 4A . 4 tos > ROL : R250 IRQ - R254 SPH ‘Interrupt Request Register Stack Pointer . (FAy; Read/Write) . (FEq; Read/Write) sesenveo—) nae 1 B32 INPUT (Oa = sna) STACK POINTER UPPER . 1RQ2 = P3, INPUT BYTE GPeSPad 1RQ3 = P39 INPUT, SERIAL INPUT IRQ4 © To, SERIAL OUTPUT . ROS = Ty R251 IMR . R255 SPL . Interrupt Mask Register : Stack Pointer (FBy; Read/Write) . (FFy; Read/Write) EN CACACACACACSC [e:]>.Jos]o.[0,[o.] >, [0]
1 ENABLES (RGO-IRGS
. {Op » IAG) STACK FOINTER LOWER . RESERVED BYTE (6Py-SP,) +1 ENABLES INTERRUPTS
Opcode : Lower Nibble (Hex) : Map . . o 1 2 3 4 5 6 7 8 9 A OB c »D E F @ | DEC ADD] ADD| ADD| ADD| ADD} LD | LD | pnz| IR | LD | P | INC Ra rilra | RayRa| TR2,Ri| RiyIM| TRIM] 3,Rz | r2,Ri | 11,RA | co,RA | r1,IM | ec,DA] 1
1 RLC ADC} ADC) ADC) ADC
IR: Ra,Ri| IR2,Ra| Ri,IM| 1Ri,1M 68 | 658 | 68 | 10,5 | 10,6 | 10,5| 10,5
2 INC | SUB| SUB} SUB| SUB| SUB| SUB
Tr | rayra | rilea | RaRa| IRaRa| Ri/IM| 1Ra,1M tRR, | 1M | razz | ritea| Ra,Ri| IR2,R| Ri IM| 1a,IM 8,5 8,5 6,5 6,5 10,5 10,5 10,5 10,5 4 | DA | DA | OR | oR | OR | OR | OR| OR . Ri | Ra | raea | radea | Ra,Ri | IR2.Ri | Ri,IM| 1Ri,IM 10,6 10,5 10,5 10,5 10,6 10,5 . 5 | PoP | PoP AND | AND | AND |. AND Ri Thi R2,Ri | IR2,Ri | Ri,IM} 1Ri,IM 6,5 6,5 65 10,5 10,5 10,5 8 | com) com | tom Tom | TCM| TCM . a Ri {| ma | raz TR2,Ri | Ri,IM| 1Ri,IM FE Ra WRa_| tira Ra,Ri | Ta, Ra TR, IM % 10,8 | 10,5 18,0 & @ |pecw|DEcw LDEI FS RR: | IR In1,Irr2 68 18,0
9 RL LDEI ot
Ri r2,Irra 10,8 | 10,6 10,8 . A cP | cP cP Ra Ra | IRz,Ri 1, 1M B | CLR | CLR | xoR | xor | xoR | xor | XOR| XOR Ri | Ri_|{ ryxz | ra,tr2 | Ra, Ri | IR2,Rs | Ri,IM | 111M 65 | 6,6 18,0 10,5 | c | rec | RRC LDCI ID Ri 1Ri ry, Irrz 1, x, R2 65 | 65 | 12,0 | 18,0 | 20,0 10,8 65 D | sRA | SRA | LDC | LDCI |CALL* LD SCF Ri | WRa_|ra Tera [Iez, Tera] IRR 1,3, Ri 65 | 65 10,8 | 10,8 | 10,5 | 10,8 = | RR | RR LD | LD | LD | LD Ri | om Ra, Ri | IRa,R1 | Ra,TM | 18,1 2s | 3s | 10,5 60 F | SWAP| SWAP 1D NOP Ri mR Ra, IRi Bytes per C : Instruction 2 3 2 : 3 1 Lower . Opcode Nibble : Execution { Pipeline Legend: , , gend: : Cycles 4 Cycles R = 8-Bil Address 1 = 4-Bit Address Upper 10,8 Ri or rs = Dat Address
7 Opcode —> A | CP Mnemonic Ra of ta = Sto Address
Nibble Ra, Ry : Sequence: . Firat Second Opcode, First Operand, Second Operand : Operand Operand Note: The blank areas are not defined. *2-byte instruction; fetch cycle appears as a 3-byte instruction :
: mum Ratings may cause permanent damage to the device. Figure 14. Test Load 1 poled Symbol Parameter Min: Max Unit Condition .
Figure 15. External I/O or Memory Read/Write .
1 TdA(AS) Address Valid to AS t Delay 50 35 2,3
2 TdAS(A) | AS tto Address Float Delay 60 45 2,3
3 TdAS(DR) KS t to Read Data Required Valid 320 220 1,2,3
8 TdDSR(DR) DS J to Read Data Required Valid * 200 130 1,2,3
9 ThDR(DS) Read Data to DS t Hold Time i¢) 0
10 TdDS(A) DS t to Address Active Delay 80 er) 23
13 TdDS(R/W) DS t to R/W Not Valid 60 35 : 2,3
14 TdDW(DSW) Write Data Valid to DS (Write) | Delay 50 38 2,8
18 TdDS(DW) DS t to Write Data Not Valid Delay ~ 80 45 2,3
16 TdA(DR) Address Valid to Read Data Required Valid 410 2588 1,2,3
17 TdAS(DS) AS t toDS { Delay 80 55 2,3
1, When using extended memory timing add 2TpC. 1 Test Load 1.
- See clock cycle time dependent characteristics table, * Allunits in nanoseconds (ns).
1 Tpc Input Clock Period 125 1000 80 1000 - 1
3 Two Input Clock Width 37 26 1
4 TwTinL Time Input Low Width 100 70 2
2 TTm,TfTin Timer Input Rise And Fall Times 100 100 2
9 TwIH Interrupt Request Input High Time 3Tpc 3TpC 2,3
1, Clock timing references uses 3.8 V for a logic "1" and 0.8 V for ’ 3, Interrupt request vie Port 3 (P3}-P3g). alogic "0", - 4, Interrupt request via Port 3 (P3q). 2, Timing reference uses 2.0 V for a logic "I" and 0.8 V for * Units in nanoseconds (ns). Figure 17. Memory Port Timing :
1 TdA(DI) Address Valid to Data Input Delay 320 1,2
2 = ThDI(A) Data In Hold time 0 lo. 1, Test Load 2. “Units are nanoseconds unless otherwise specified.
- This is a Clock-Cycle-Dependent parameter. For clock frequencies
rvarranaad ara ), Ti ig . @ | _ oo po} : . : . @ ® . Rov OUTPUT ‘ . . Figure 18a. Input Handshake . : . DATA OUT DATA OUT VALID : BaV . court ———— i ae oy ® . q@ruT) : Figure 18b, Output Handshake SS No. Symbol Parameter Min Max Notes* eee MeCN to 1 TeDI(DAV) Data In Setup Time . 10
2 ThDIDAV) Data In Hold time 160
3 TwDAV . Data Available Width 120
4 TdaDAVIK(RDY) DAV J Input to RDY J Delay 120 | 12
6 TdDAVIr(RDY) DAV t Input toRDY t Delay 120 12
7 ‘TaDAVOr(RDY) — DAV t Outputto RDY f Delay 0 et) 8 TdDO(DAY) Data Out to DAV | Delay . 30 : 1.
9 TdRDY(DAV) - Ray J Inputto DAV t Delay : 0 M00 1
NOTES: - 1. Test load 1 * Units in nanoseconds (ns). 2. Input handshake. 3. Output handshake . 1 All timing references use 2.0 V for a logic™1” and 0.8 V for . alogic“0". ae ee Clock- Cycle-Time- Number Symbol Equation = * . Dependent I I Characteristics ! TAA(AS) TpC-50 2 ‘TAAS(A) TpC-40 :
3 TdAS(DR) 4TpC-110*
: 4 ‘TwAS TpC-30 -
2 TwDsw 2TpC-55*
. 8 TdDSR(DR) 3TpC-120*
10 TdA(DSJA : TpC-40
11 TADS(AS) TpC-30 :
13 TdDS(R/W) : TpC-50 :
14 TdaDW(DSW) - TpC-80
15 TaDS(DW) TpC-40 .
16 TAA(DR) STpC-160* :
17‘ TdAS(DS) TpC-30* oS *Add 2TpC when using extended memory timing. .