DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 56
Technical content
Copyright ©2012 Zilog, Inc. All rights reserved. www.zilog.com
PS011804-0612 Life Support Policy Z84C90 KIO Serial/Parallel Counter/Timer Product Specification ii DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT TH E EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. AS USED HEREIN Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. DOCUMENT DISCLAIMER ©2012 Zilog, Inc All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and ma y be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATI ON, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. ZMOTION, Z8 Encore! XP and eZ8 are trademarks or registered trademarks of Zilog, Inc. (An IXYS Company). All other product or service names are the property of their respective owners. Warning:
Z84C90 KIO Serial/Parallel Counter/Timer Product Specification iii
Revision History
Each instance in the following revision history table reflects a change to this document from its previous version. For more details, refer to the corresponding pages or appropriate links provided in the table. Date Revision Level Description Page Number Jun 2013 04 Corrected to remove internal discussion tags. N/A Jun 2012
03 Updated to include missing information covered in the
DC8321-00 Databook (2Q94). All Sep 2002
02 Added Z84C90 KIO Peripheral: Serial/Parallel Counter/
Timer Packages table, modified AC Characteristics of the Z84C90 table. 2, 38 Sep 2002 01 Original issue. All
PS011804-0612 Table of Contents Z84C90 KIO Serial/Parallel Counter/Timer Product Specification iv Table of Contents
PS011804-0612 Introduction Z84C90 KIO Serial/Parallel Counter/Timer Product Specification Introduction Zilog’s Z84C90 Serial/Parallel Counter/Timer KIO is a multichannel, multipurpose I/O peripheral device designed to provide the end user with a cost-effective and powerful solu- tion to meet an assortment of peripherals requirements. The Z84C90 KIO Peripheral com- bines the features of one Z84C30 CTC, one Z84C20 PIO and a Z84C4x SIO, plus an 8-bit, bit-programmable I/O port and a crystal oscillator into a single 84-pin PLCC or 100-pin LQFP package. Utilizing fifteen internal registers for data and programming information, the KIO can easily be configured to any given system environment. Although optimum performance is obtained with a Z84C00 CPU, the KIO can just as easily be used with any other CPU.
Features
The Z84C90 Serial/Parallel Counter/Timer KIO offers the following features:
- Two independent synchronous/asynchronous serial channels
- Three 8-bit parallel ports
- Four independent counter/timer channels
- On-chip clock oscillator/driver
- Software/hardware resets
- Designed in CMOS for low power operations
- Supports Z80 Family interrupt daisy chain
- Programmable interrupt priorities
- 8, 10 and 12.5 MHz bus clock frequency
- Single +5 V power supply Table 1 lists the differing frequencies offered for the Z84C90 KIO Peripheral by package and part number.
interface are keyboards, printers and EPROM/PAL programmers. interrupt vectors when the CPU responds. Z8420/Z84C20 PIO Product Specification (PS0180). Figure 2. Z84C20 Parallel Input/Output Block Diagram
active and RD has been detected as inactive. and serial baud rate clock generation. unique interrupt vector in response to the interrupt acknowledge cycle. Figure 3. Parallel Interface Adapter Block Diagram
protocols (Monosync, Bisync and SDLC/HDLC), byte- or bit-oriented. Figure 4. Counter/Timer Block Diagram
DMA control signals can be obtained through the PIA port. Z8420/Z84C20 PIO Product Specification (PS0180). Figure 5. SIO Block Diagram
reference output. Zilog recommends a fundamental parallel resonant crystal; see Figure 6. The preferred value of the two capacitors C1 and C2 is 33 pF each. Figure 6. Crystal Connection
Figure 8. 100-Pin LQFP Configuration
PS011804-0612 Pin Descriptions Z84C90 KIO Serial/Parallel Counter/Timer Product Specification Pin Descriptions A0–A3. Address bus (inputs). Used to select the port/register for each bus cycle. ARDY, BRDY. Port Ready (outputs, active High). These signals indicate that the port is ready for a data transfer. In Mode 0, the signal indicates that the port has data available to the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for the peripheral device, but that the data is not be placed onto PA0–PA7 until the ASTB sig- nal is Active. BRDY indicates that Port A is able to accept data from a peripheral device. Port B does not support Mode 2 operation and can only be used in Mode 3 when Port A is programmed for Mode 2. BRDY is not associated with Port B when it is operating in Mode 3. ASTB, BSTB. Port Strobe (inputs, active Low). These signals indicate that the peripheral device has performed a transfer. In Mode 0, the signal indicates that the peripheral device has accepted the data present on the port pins. In Mode 1, the signal causes the data on the port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present on the Port A pins to be latched into the Port A input data latch. The end of the current transaction is noted by the rising edge of these signals. Port B does not support Mode 2 operation, and can only be used in Mode 3 when Port A is programmed for Mode 2. BSTB is not associated with Port B when it is operating in Mode 3. CLK/TRG0–CLK/TRG3. External Clock/Timer Trigger (inputs, user-selectable active High or Low). These four pins correspond to the four counter/timer channels of the KIO. In Counter mode, each active edge causes the downcounter to decrement. In Timer mode, an active edge starts the timer. CLKOUT. Clock Out (output). This output is a divide-by-two of the oscillator (XTAL) input. CLOCK. System Clock (input). This clock must be the same as (or a derivative of) the CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be connected together. Note: Note:
PS011804-0612 Pin Descriptions Z84C90 KIO Serial/Parallel Counter/Timer Product Specification CS. Chip Select (input, active Low). Used to activate the internal register decoding mech- anism and allow the KIO to perform a data transfer to/from the CPU. CTSA, CTSB. Clear to Send (inputs, active Low). These signals are modem control sig- nals for the serial channels. When programmed for Auto Enable, a Low on these pins enables their respective transmitters. If not programmed as Auto Enable, these pins may be used as general-purpose input signals. D0–D7. Data Bus (bidirectional, active High, tristated). Used for data exchanges between the CPU and the KIO for programming and data transfer. The KIO also monitors the data bus for Return from Interrupt (RETI) instructions to maintain its Interrupt Under Service (IUS) status. DCDA, DCDB. Data Carrier Detect (inputs, active Low). These signals are modem control signals for the serial channels. When programmed for Auto Enable, a Low on these pins enables their respective receivers. If not programmed as Auto Enable, these pins may be used as general-purpose input signals. DTRA, DTRB. Data Terminal Ready (outputs, active Low). These signals are modem con- trol signals for the serial channels. They follow the state programmed into their respective serial channels, and are multiplexed with Port C, bits 5 and 2, respectively. IEI. Interrupt Enable In (input, active High). This signal is used with Interrupt Enable Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that no higher-priority device is requesting an interrupt. IEO. Interrupt Enable Out (output, active High). This signal is used with Interrupt Enable In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that this device is requesting an interrupt, and that no higher- priority device, is not requesting an interrupt. A Low blocks any lower-priority devices from requesting an interrupt. IORQ. Input/Output Request (input, active Low). IORQ is used with RD, A0–A3, and CS to transfer data between the KIO and the CPU. When IORQ, RD, and CS are active Low, the device selected by A0–A3 transfers data to the CPU. When IORQ and CS are active Low, but RD is active High, the device selected by A0–A3 is written into by the CPU. When IORQ and M1 are both active Low, the KIO may respond with an interrupt vector from its highest-priority interrupting device. M1. Machine Cycle 1 (input, active Low). When M1 and RD are Low, the Z80 CPU fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI instruction sequence is being executed. When M1 and IORQ are both active, the KIO decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its highest-priority interrupting device.
PS011804-0612 Pin Descriptions Z84C90 KIO Serial/Parallel Counter/Timer Product Specification OSC. Oscillator (output). This output is a reference clock for the oscillator. PA0–PA7. Port A Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PA0 is the least-significant bit of the bus. PB0–PB7. Port B Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PB0 is the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Dar- lington transistors. PC0–PC7. Port C Bus (bidirectional, tristated). PC0 is the least-significant bit of the bus. These pins are multiplexed between the 8-bit PIA and additional modem control signals for the serial channels. RD. Read (input, active Low). When RD is active, a memory or I/O read operation is in progress. RD is used with A0–A3, CS and IORQ to transfer data between the KIO and CPU. RESET. Reset (input, active Low). A Low on this pin forces the KIO into a Reset condi- tion. This signal must be active for a minimum of three clock cycles. When the KIO is reset, the following events occur:
- The PIO ports are in Mode 1 operation
- Handshakes are inactive and interrupts are disabled
- The PIA port is in Input mode and active
- CTC channel counting is terminated and interrupts are disabled
- SIO channels are disabled
- Marking with interrupts is disabled All control registers must be rewritten after a hardware reset. RTSA, RTSB. Request to Send (outputs, active Low). These signals are modem control signals for their serial channels. They follow the inverse state programmed into their respective serial channels, and are multiplexed with Port C, bits 4 and 3, respectively. RxCA, RxCB. Receive Clock (inputs, active Low). These clocks are used to assemble the data in the receiver shift register for their serial channels. Data is sampled on the rising edge of the clock. RxDA, RxDB. Receive Data (inputs, active High). These pins are the input data pins to the receive shift register for their serial channels. SYNCA, SYNCB. Synchronization (bidirectional, active Low). In the Asynchronous mode of operation, these pins act much like the CTS and DCD pins. Transitions affect the Sync/
are multiplexed with Port C, bits 6 and 1, respectively. from the transmitter for their serial channels. pins are multiplexed with Port C, bit 7 and 0, respectively. XTALI. Crystal/Clock Connection. (input). XTALO. Crystal Connection. (output). responding downcounter reaches 0. Address lines A0–A3 determine which one of the 16 control registers is being accessed. Table 2. KIO Registers CPU, applying a 1 or a 0 respectively on the RD pin.
Table 2. KIO Registers (Continued) CPU, applying a 1 or a 0 respectively on the RD pin.
Figure 9. KIO Register Addressing
while a 0 indicates output. this word is required with in Mode 3. See Figure 12. Figure 12. PIO I/O Register Control Word
- Regardless of the operating mode, setting bit D4 = 1 causes any pending
- The port interrupt is not enabled until the interrupt function enable is
Figure 13. PIO Interrupt Control Word
1 H / L 0111
enabled or disabled at any time. Mode. Bit D6 selects either Timer Mode or Counter Mode. by-16 or divide-by-256 is available. an external trigger can be selected. constant data for the downcounter. as a count of 256. See Figure 17. Figure 16. CTC Channel Control Word
Note: *Variable if Status Affects Vector is also programmed. Figure 21. SIO Read Register 2 (Channel B only)
interfacing of the CPU to other devices in addition to the Z80 CPU (or the Z180/Z280). Figure 30. PIA Control Register Figure 31. KIO Command Register A
111 None
to allow software control of the RETI. register are shown in Figure 32. there are other peripherals on the upper interrupt daisy chain, caution must be exercised. Figure 32. KIO Register 15: KIO Command Register B
Z84C90 KIO Serial/Parallel Counter/Timer Product Specification
Electrical Characteristics
The data in this chapter represents all known data prior to qualification and characteriza- tion of the Z84C90 KIO device and is therefore subject to change. Additional electrical characteristics can be found in the individual chapters of this document. Absolute Maximum Ratings Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This rating is a stress rating only. Operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Standard Test Conditions The DC Characteristics and Capacitance sections that follow apply to the following stan- dard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows into the referenced pin. Available operating temperature ranges are:
- S = 0°C to +70°C Voltage Supply Range: +5.0V ± 10% All AC parameters assume a load capacitance of 100 pF, as shown in Figure 33. Add a 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address and control lines. AC timing measurements are referenced to 1.5 volts (except for CLOCK, which is referenced to the 10% and 90% points. Voltage on VCC with respect to VSS –0.3V to +7.0V Voltages on all inputs with respect to VSS –0.3V to VCC +0.3V Operating Ambient Temperature See Ordering Information Storage Temperature –65°C to +150°C
VCC = 5.0 V ± 10% unless otherwise specified. Figure 33. Test Load Diagram Table 3. DC Characteristics of the Z84C90
8 MHz 15 mA
10 MHz 15 mA
12.5 MHz 15 mA
Figure 34. I/O Read/Write Timing (M1 = 1) Table 3. DC Characteristics of the Z84C90 (Continued)
Table 5 lists the alternating current characteristics for the Z84C90 KIO Peripheral. Figure 41. Op Code Fetch Cycle Table 4. Capacitance
Table 5. AC Characteristics of the Z84C90
1 TcC Clock Cycle Time 125 DC 100 DC 80 DC ns
2 TwCh Clock Pulse Width (High) 55 DC 42 DC 32 DC ns
3 TwCl Clock Pulse Width (Low) 55 DC 42 DC 32 DC ns
4 TfC Clock Fall Time 10 10 10 ns
5 TrC Clock Rise Time 10 10 10 ns
6 TsA(Rlf) Address, CS
7 TsRl(Cr) RD , IORQ to ClockR i s e S e t u p 5 05 04 0n s
8 Th Hold Time for Specified Setup 15 15 15 ns
9 TdCr(DO) CLOCK Rise to Data Out Delay 100 80 65 ns
10 TdRlr(DOz) RD
11 ThRDr(D) M1 ,RD,IORQ Rise to Data Float 15 15 15 ns
12 TsD(Cr) Data in to Clock Rise Setup 30 25 22 ns
13 TdIOI(DOI) IORQ Fall to Data Out Delay
14 ThIOr(D) IORQ Rise to Data Float
15 THIOr(A) IORQ Rise to Address Hold 15 15 15 ns
16 TsM1f(Cr) M1 Fall to Clock Rise Setup 40 40 40 ns
17 TsM1r(Cf) M1 Rise to Clock Fall Setup
18 TdM1f(IEOf) M1 Fall to IEO Fall Delay
19 TsIEI(IOf) IEI to IORQ Fall Setup3 ns
- Maximum SIO data rate is f CLOCK ÷ by 5, in which fCLOCK = 1 ÷ TCC.
- For a Z80 CPU operating above 8 MHz, one wait state is required to meet this parameter.
- These daisy chain parameters include contributions fr om the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
- Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
- If the CPU is a Z80 CPU and if it is required to have mu ltiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
- Any open-drain output must add a Re gister-Capacitor (RC) time constant to the specification value.
20 TdIEIf(IEOf) IEI Fall to IEO Fall Delay 3 160 150 125 ns
21 TdIEIf(IEOr) IEI Rise to IEO Rise Delay
22 TsIEI(Cf) IEI to Clock Fall Setup (for 4D
23 TsIOr(Cf) IORQ Rise to Clock Fall Setup
24 TdCf(RDYr) Clock Fall to RDY Rise Delay 100 100 100 ns
25 TdCf(RDYf) Clock Fall to RDYFall Delay 100 100 ns
26 TwSTB STB Pulse Width 100 80 60 ns
27 TsSTBr(Cf) STB Rise to ClockFall Setup
28 TdIOf(PD) IORQ Fall to Port Data Valid
29 TsPD(STBr) Port A,B Data to STB Rise Setup
30 TdSTBI(PD) STB Fall to Port A,B Data Valid
31 TdSTBr(PDz) STB Rise to Port Data Float Delay
32 TdPD(INTf) Port Data Match to INT Fall Delay
33 TdSTBr(INTf) STB Rise to INT Fall Delay 290 220 190 ns
34 TsPD(RIf) PIA Port Data to RD , IORQ Fall
Table 5. AC Characteristics of the Z84C90 (Continued)
- Maximum SIO data rate is f CLOCK ÷ by 5, in which fCLOCK = 1 ÷ TCC.
- For a Z80 CPU operating above 8 MHz, one wait state is required to meet this parameter.
- These daisy chain parameters include contributions fr om the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
- Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
- If the CPU is a Z80 CPU and if it is required to have mu ltiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
- Any open-drain output must add a Re gister-Capacitor (RC) time constant to the specification value.
35 TdCr(PD) Clock Rise to Port Data Valid
36 TdCr(INTf) Clock Rise to INT Rise Delay TcC+100 TcC+80 TcC+75 ns
37 TsCTRr(Cr)c CLK/TRG Rise to Clock Rise
38 TsCTRr(Cr)t CLK/TRG Rise to Clock Rise
39 TdCTRr(INTf) CLK/TRG Ri se to INT Fall Delay
40 TcCTR CLK/TRG Cycle Time 4 (2TcC) DC (2TcC) DC (2TcC) DC ns
41 TwCTRh CLK/TRG Width High 90 DC 90 DC 75 DC ns
42 TwCTRI CLK/TRG Width Low 90 DC 90 DC 75 DC ns
43 TrCTR CLK/TRG Rise Time 30 30 30 ns
44 TfCTR CLK/TRG Fall Time 30 30 30 ns
45 TdCr(ZCr) Clock Rise to ZC/TO Rise Delay 80 80 80 ns
46 TdCf(ZCf) Clock Fall to ZC/TO Fall Delay 80 80 80 ns
47 TdIOf(W/Rf) IORQ
48 TdCr(W/Rf) Clock Rise to WT /RDY Delay
49 TdCf(W/Rz) Clock Fall to WT /RDY Float Delay
- Maximum SIO data rate is f CLOCK ÷ by 5, in which fCLOCK = 1 ÷ TCC.
- For a Z80 CPU operating above 8 MHz, one wait state is required to meet this parameter.
- These daisy chain parameters include contributions fr om the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
- Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
- If the CPU is a Z80 CPU and if it is required to have mu ltiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
- Any open-drain output must add a Re gister-Capacitor (RC) time constant to the specification value.
50 TwPh Pulse Width High 150 120 100 ns
51 TwPI Pulse Width Low 150 120 100 ns
52 TcTxC TxC Cycle Time 250 DC 200 DC 160 DC ns
53 TwTxCh TxC W i d t h H i g h 8 5D C8 0D C7 0D Cn s
54 TwTxCl TxC Width Low 85 DC 80 DC 70 DC ns
55 TrTxC TxC Rise Time 60 60 60 ns
56 TfTxC TxC Fall Time 60 60 60 ns
57 TdTxCf(TxD) TxC Fall to TxD Delay (x1 mode) 160 120 115 ns
58 TdTxCf(W/Rf) TxC Fall to WT/RDY Fall Delay
59 TdTxCf(INTf) TxC Fall to INT Fall Delay5 5959 5 9 n s
60 TcRxC RxC Cycle Time 250 DC 200 DC 160 DC ns
61 TwRxCh RxC W i d t h H i g h 8 5D C8 0D C7 0D Cn s
62 TwRxCl RxC Width Low 85 DC 80 DC 70 DC ns
63 TrRxC RxC Rise Time 60 60 60 ns
64 TfRxC RxC Fall Time 60 60 60 ns
65 TsRxD(RxCr) RxD to RxC Rise Setup 0 0 0 ns
66 ThRxCr(RxD) RxC Rise to RxD Hold Time 80 60 50 ns
67 TdRxCr(W/Rf) RxC Rise to W/RDY Fall Delay
68 TdRxCf(INTf) RxC to INT Fall Delay5 10 13 10 13 10 13 ns
69 TdRxCr
- Maximum SIO data rate is f CLOCK ÷ by 5, in which fCLOCK = 1 ÷ TCC.
- For a Z80 CPU operating above 8 MHz, one wait state is required to meet this parameter.
- These daisy chain parameters include contributions fr om the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
- Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
- If the CPU is a Z80 CPU and if it is required to have mu ltiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
- Any open-drain output must add a Re gister-Capacitor (RC) time constant to the specification value.
10 MHz and 12 MHz daisy chain parameters.
70 TsSYNCf
71 TdCf(IEOr) Clock Fall to IEO Rise Delay 90 75 60 ns
72 TdCf(IEOf) Clock Fall to IEO Fall Delay 110 90 75 ns
73 ThDI(M1r,Rdr) Data Hold Time to M1
74 TsM1/RD(C) Setup time for M1 and RD to clock
Figure 42. Internal Daisy Chain Configuration
- Maximum SIO data rate is f CLOCK ÷ by 5, in which fCLOCK = 1 ÷ TCC.
- For a Z80 CPU operating above 8 MHz, one wait state is required to meet this parameter.
- These daisy chain parameters include contributions fr om the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
- Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
- If the CPU is a Z80 CPU and if it is required to have mu ltiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
- Any open-drain output must add a Re gister-Capacitor (RC) time constant to the specification value.
The data that support the calculations in Table 6 are tabulated in Table 7. Table 6. Daisy Chain Parameters
181 TdM1(IEO) (PIO at #1) 160 150 125 ns
192 TsIEI (IO) (PIO at #3) 170 140 115 ns
203 TdIEI(IEOf) 160 150 125 ns
214 TdIEI(IEOr) 160 150 125 ns
- Parameter 18: M1 falling to IEO delay TdM1(IEO) = Td M1(IEO)#1 + TdIEI(IEO)#2 + TdIEI(IEO)#3 + Output
Buffer Delay), in which TdIEI(IEO) refers to the worst-case number value between TdIEI(IEOr) and TdIEI(IEOf).
- Parameter 19: IEI to IORQ falling setup time TsIEI(IO) = TdIEI(IEO)#1 + TdIEI(IEO)#2 + TdIEI(IEO)#3 + Input
Buffer Delay), in which TdIEI(IEO) refers to the worst-case number value between TdIEI(IEOr) and TdIEI(IEOf).
- Parameter 20: IEI falling delay = TdIEI(IEOf) = TdIEI(IE Of)PIO + TdIEI(IEOf)CTC + TdIEI(IEOf)SIO + (Input
buffer Delay) + (Output Buffer Delay).
- Parameter 21: IEI rising to IEO rising delay (after ED decode) – TdIEI(IEOr) = TdIEI(IEOr)PIO + TdIEI(IEOr)CTC
+ TdIEI(IEOr)SIO + ((Input buffer Delay) + (Output Buffer Delay).
- In notes 1–4, TdIEI(IEO) refers to the worst-case number value between the parameters TdIEI(IEOr) and
Table 7. Daisy Chain Calculation Data*
8 MHz PIO Part CTC Part SIO Part ns
10 MHz PIO Part CTC Part SIO Part ns
12.5 MHz PIO Part CTC Part SIO Part ns
**Table 7. Daisy Chain Calculation Data* (Continued)**
Z84C90 KIO Serial/Parallel Counter/Timer Product Specification Packaging Zilog’s Z84C90 KIO is available in the following packages:
- 84-pin Plastic Chip Carrier (PLCC)
- 100-Pin Quad Flat Pack (LQFP) Current diagrams for each of these packages are published in Zilog’s Packaging Product Specification (PS0072), which is available free for download from the Zilog website.
Z84C90 KIO Serial/Parallel Counter/Timer Product Specification
Ordering Information
Order your Z84C90 KIO Serial/Parallel Counter/Timer products from Zilog using the part numbers shown in Table 8. For more information about ordering, please consult your local Zilog sales office. The Sales Location page on the Zilog website lists all regional offices. Part Number Suffix Designations Zilog part numbers consist of a number of components, as indicated in the following example. Example. Part number Z84C9008ASG is an 8-bit Z80-powered MCU operating at an
8 MHz frequency in a 100-pin LQFP package, operating within a 0ºC to +70ºC tempera-
ture range and built using lead-free solder. Table 8. Z84C90 KIO Ordering Matrix
PS011804-0612 Precautions & Limitations Z84C90 KIO Serial/Parallel Counter/Timer Product Specification Precautions & Limitations The following issues describe the possible limitations and resulting workarounds when working with Revision A of the Z84C90 KIO Peripheral. Daisy-Chain If the KIO has an interrupt pending during an Interrupt Acknowledge cycle, the KIO misses the status of the IE1 pin. As a result, vector contention is produced if there is a higher interrupting device. However, operation is as expected if only one device is in the system. Workaround: There is no problem if the application has only one peripheral in the daisy chain. For two or more peripherals in the system, a hardware workaround circuit is required. Please contact your local Zilog representative to obtain more information. Reset KIO requires the M1 signal to exit from a Reset state. If the M1 signal is not received, the KIO cannot be programmed. This problem does not exist for users of the Z80 CPU. Workaround: If the CPU is other than a Z80 CPU, an M1 signal is required to exit RESET status. Otherwise, the KIO cannot be programmed. Port C When Port C is used as a parallel I/O (and not as modem signals for an SIO ) and there is a status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes. Workaround: Before using Port C as a parallel port, set the SIO modem signal mode back to Port C. This procedure avoids the problem. Interrupt Acknowledge Cycle The KIO modifies the contents of the KIO Control Register (specifically, the KIO modi- fies the daisy-chain configuration) if the CE pin is active during the Interrupt Acknowl- edge cycle (assuming other conditions are satisfied). This problem can occur under the following narrowly-defined conditions:
- The CE signal is active throughout the Interrupt Acknowledge cycle
- The address on the bus, A3–A0, is 110b
- Bit D3 is 1
PS011804-0612 Precautions & Limitations Z84C90 KIO Serial/Parallel Counter/Timer Product Specification
- At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ signal
- During the time period in which CE is active, IORQ is active, and M1 returns to the inactive state, all of which occur during the rising edge of the clock. This problem does not exist with the Z80 CPU; however, other CPUs could be affected. One of the possible workarounds is to add the M1 not active condition to generate a CE signal.
PS011804-0612 Customer Support Z84C90 KIO Serial/Parallel Counter/Timer Product Specification Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other fac- ets about Zilog product offerings, please visit the Zilog Knowledge Base at http:// zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com.