Z8000

Zilog, Inc.

CPU Central Processing Unit

Manufacturer: Zilog, Inc.

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ZILOG INC L?E D = M@ 9984043 0011879 1 a Bar A] SSE ies RET AD VANCED INFORMATION “eee apes, eee g Bree, Soe eene Product Specification = Ane . T-44~17-07 | Z8001°/Z8002° \\ , Z8000° CPU Central Processing Unit ! SS ; . . October 1988, —SSSSSSSSS——OeseFeFFsSSSSSseF FEATURES . | m Regular, easy-to-use architecture ™ Resource-shaping capabilities. for multiprocessing @ Instruction set more powerful than many minicomputers- _~ SYS¥ems i = Directly addresses 8 Mbytes = Mult-programming support ‘ m Eight user-selectable addressing modes = Compiler support - p ‘| Memory management and protection provided by : Seven datatypes that range from bits to 32-bit long words < and byte and word stings 28010 Memory Management Unit a System and Normal operating modes 82-bit operations, including signed multiply and divide 1m Separate code, data, and stack spaces = Z-BUS compatible Sophisticated interrupt structure 4,6, and 10 MHz.clock rate : SSS GENERAL DESCRIPTION The Z8000 is an advanced high-end 16-bit microprocessor . - ‘tu that spans wide variety of applications ranging from simple ws ton stand-alone computers to complex parallel-processing rea bon + systems. Essentially a monolithic minicomputer central i so . processing unit, the Z8000 CPU is characterized by an Newnevveem ae instruction set more powerful than many minicomputers; evtesORD ro ae abundant resources in registers, data types, addressing eravus 10, Appnessy \\ : modes and addressing range, and a regular architecture fad Aor |e-e (DATA sus i ; that enhances throughput by avoiding critical bottlenecks in i | | such as implied or dedicated registers. mm za001 ta, | CPU resources include sixteen 16-bit general-purpose couf —efumr PY nif registers, seven data types that range from bits to 32-bit long conrnot) heron rife | words and byte and word strings, and eight user-selectable i) addressing modes. The 110 distinct instruction types can cont{ aoane me CS) e800 be combined with the various data types and addressing os ot modes to form a powerful set of 414 instructions. Moreover, mm el ee - “the instruction set is regular; most instructions can use any —=INTERRUPTs. nn wowoen | i of the five main addressing modes and can operate on byte, nw 1 om i i word, and long-word data types. muttimcne { im Vo \\ The CPU can operate in either the system or normal mode. Sonne <— 1H | gale —seouer | The distinction between these two modes permits privileged Lo-plom_ i operations, thereby improving operating system organization and implementation. Multiprogramming is : supported by the “atomic” Test and Set instruction; t8Y GND ie : : multiprocessing by a combination of instruction and . . Se 128

ZILOG INC L7E D Mm 9984043 0011880 6 mm j — T-49-17-07 | hardware features; and compilers by multiple stacks, ‘ To meet the requirements of complex, memory-intensive : special instructions, and addressing modes. applications, a companion memory-management device is - offered for the Z8001. The Z8010 Memory Management ‘The 28000 CPU Is offered in three versions: the Z8001/ Unit manages the large address space by providing fea- 2160 segmented CPUs and the Z8002 nonsegmented tures such as segment relocation and memory protection. CPU (Figure 1). The main difference is in addressing The 78001 can be used with or without the Z8010. If used range. The 28001 can directly address 8 megabytes of by itself, the Z8001 still provides an 8 megabyte direct ad- : memory; the 2160 directly addresses 2 megabytes; the dressing range, extendable to 48 megabytes. . 28002 directly addresses 64 kilobytes. The two operating modes system and normal - and the distinction between The Z8001, 28002 and Z80 10 are fabricated with high-den- code, data, and stack spaces within each mode allows sity, high-performance scaled n-channel silicon-gate Memory extension up to 48 megabytes for the Z8001, 12 —_depletion-load technology, and are housed in dual-in-line megabytes for the 2160 and 384 kilobytes for the 28002. packages (DIPs) and leadless chip carriers (LCC). SSS . REGISTER ORGANIZATION "The 28000 CPU is a register-oriented machine that offers multiple registers (Figures 2 and 3). For byte operations, the sixteen 16-bit general-purpose registers and a set of special _first eight 16-bit registers (RO... R7) are treated as sixteen as accumulators and all but one as index registers or registers are grouped in pairs (RRO... R14) to form 32-bit memory pointers. long-word registers. Similarly, the register set is grouped in Register flexibility is created by grouping and overlapping Uadruples (RAO... RQ12) to form 64-bit registers. a CT CC a : no { | so { \\ mt my : noo Roo na i | Sa | ma m| ma a a | as (es ras nas hd { a a Ca | : ee ane | a SS | se { | ne Re | ae | a oa. nos ~ ant aio i cc | a | | { | : ania ansz : (ne | | , fet! [SYSTER STACK FOMTER SEC WOT ~~] | rave cn | Ratz mis > Figure 2.28001 General-Purpose Registers Figure 3.28002 General-Purpose Registers _ 129 :

ZILOG INC L7E D MM 9984043 0011881 T mm i STACKS T-49-17-07 ' The 28001, 28002 and Z160 can use stacks located stack pointers with any instruction available for register anywhere In memory. Call and Return instructions as well as —_ operations. interrupts and traps use implied stacks. The distinction In the 28001, register pair R14 is the implied stack between normal and system stacks separates system Pointer. Register R14 contains the 7-bit segment number Information from the application program information. Two 5 ‘ . and R15 contains the 16-bit offset. In the Z8002, register stack pointers are available: the system stack pointer and BS je ariticg 46 bit stack potato, the normal stack pointer. Because they are part of the Impl pointer. general-purpose register group, the user can manipulate the i ee REFRESH . The Z8000 CPU contains a counter that can be used to _ period can be programmed by 1 to 64 ys with a 4 MHz automatically refresh dynamic memory. The refresh counter _clock. Refresh can be disabled by programming the refresh register consists of a 9-bit row counter, a 6-bit rate counter, _ enable/disable bit. and an enable bit (Figure 4). The 9-bit row counter can address up to 256 rows and is incremented by two each wou 2 e time the rate counter reaches end-of-count. Thé rate counter | determines the time between successive refreshes. It : consists of a programmable 6-bit modulo-n prescaler(n = 1 10.64), driven at one-fourth the CPU clock rate. The refresh Figure 4. Refresh Counter aa eee te th PROGRAM STATUS INFORMATION ‘This group of status registers contains the program counter, four words: a two-word program counter, the flag and con- flags, and control bits. When an interrupt or trap occurs, the trol word, and an unused word reserved for future use. entire group is saved and a new program status group is Seven bits of the first PC word designate one of the 128 loaded, memory segments. The second word supplies the 16-bit Figure 5 illustrates how the program status groups of the ofiset that designates a memory location within the seg- 28001 and 28002 differ. In the nonsegmented 28002, the "ent program status group consists of two words; the program 7 i Counter (PC), and the flag and control word (FCW). Inthe With the exception of the segment enable bit in the 28001 : program status group, the flags and contro! bits are the | segmented 28001, the program status group consists of same for both CPUs. i 1" n 1 ‘ | jose [fee Pelee T =] fete : GeesesDwebo = 6 Tee To Todo ToT eo] eB CT fe

78001 Program Status Registers =”

. + 7002 Program Stole Ares Pointer

78001 Program Status Area Pointer

so Figure 5. 28000 CPU Special Registers : . 7 ! SSS 130

. ZILOG INC L7E D MM 9984043 0011882 4 = ——,. T-49-17-07 INTERRUPT AND TRAP STRUCTURE The 28000 provides a very flexible and powerful interrupt descending order of priority for traps and interrupts is: and trap structure. Interrupts are external asynchronous _ internal traps, nonmaskable interrupt, segmentation trap, events requiring CPU attention, and are generally triggered vectored interrupt, and non-vectored interrupt. Oven LH Te ae TAPS 210 SYNCHONOUS Winer anintrruptor rap occurs, he curent program satus Haale "” _ is automatically pushed on the system stack. The program Both are processed ina similar manner by the CPU. status consists of the processor status (PC and FCW) plus a The CPU supports three types of interrupts (non-maskable, 16-bit identifier The identifier contains the reason or source vectored, and non-vectored) and four traps [system call,” of the trap or interrupt. For internal traps, the identifier is the Extended Process Architecture (EPA) instruction, privileged first word of the trapped instruction. For external traps or instructions, and segmentation trap]. The vectored and interrupts, the identifiers the vector on the data bus resd by non-vectored interrupts are maskable. Of the fourtraps, the the CPU during the interrupt-acknowledge or trap- only external one is the segmentation trap, which Is acknowledge cycle. Generated by the 28010. Atter saving the current program status, the new program i The remaining traps occur when instructions limited to the status is automatically loaded from the program status area . ‘system mode are used in the normal mode, or asa resultof in system memory. This area is designated by the program the System Call instruction, or for an EPA instruction. The status area pointer (PSAP). . DATA TYPES . . 28000 instructions can operate on bits, BCD digits (4 bits), except strings can reside ether in registers or memory. bytes (6 bits), words (16 bits), long words (82 bits), and byte Strings are stored in memory only. bet reek en aa oe ond evestong} Bie can be " The basic data element is the byte, The number of bytes operations; bytes are used for characters or small Integer Sed when manipulating a data elementis either implied by sons 5 ; i the operation or—for strings and multiple register values; words are used for integer values, instructions and operations —explicily specified in the instruction Nonsegmented addresses; long words are used for long °P explicitly sp . integer values and segmented addresses. Alll data elements ' Se SEGMENTATION AND MEMORY . MANAGEMENT High-level languages, sophisticated operating systems, t + large programs and data bases, and decreasing memory toateat aooness[ seaMeNT WO. | [ore] . Prices are all accelerating the trend toward larger memory Taenan ~~~] E----4 . Fequirements in microcomputer systems. The Z8001 meets | MANRGMenr | this requirement with an eight megabyte addressing space. your 1 This large address space is directly accessed by the CPU i case { - using a segmented addressing scheme and can be ! Aeoaees H managed by the 28010 Memory Management Unit. | rue pg 1 1 Segmented Addressing | IT H \\ A segmented addressing space—compared with linear H Ce addressing—is closer to the way a programmer uses 1 ro I . memory because each procedure and data space resides 1 ints own segment. The 8 megabytes of 28001 addressing’. | Ca ! space Is divided into 128 relocatable segments up to 64 i J \\ kilobytes each. A 23-bit segmented address uses a 7-bit ! 23 onary { * segment address to point tothe segment, and a 16-bit offset | to address any location relative to the beginning of the LL a ™anipulated separately. The segmented 28001 can run any . Code written for the nonsegmented 28002 in any one of its Figure 6. Logical-to-Physical Address 128 segments, provided it is set to the nonsagmented Translation mode. . . 131

ZILOG INC 17E D MM 9984043 0011883 3 mm $$$ —SSSSSSSSSSSSSSSSSSSSSSSSSsSs T-49-17-07 | In hardware, segmented addrésses are contained in a where information is actually located in the physical register pair or long-word memory location. The segment — memory. | number and offset can be manipulated separately or — The relocation process is transparent to user software. A Hi together by all the available word andlong-word operations. translation table in the Memory Management Unit : hr ‘ . associates the 7-bit segment number with the base address Whencontainedinaninsiruction, asegmentedaddresshas Cre physical memory segment. The 16-bit offset is added ifferent representations: long offset and short offset. . 4 5 " to the physical base address to obtain the actual physical The long offset occupies two words, whereas the short offset Ic = — address. The system may dynamically reload translation requires only one and combines in one word the 7-bit tates as tasks are created, suspended, or changed segment number with an 8-bit offset (range 0-256). The } Susp 2 ged. short offset mode allows very dense encoding of addresses —_ In addition to supporting dynamic segment relocation, the and minimizes the need for long addresses required by Memory Management Unit also provides segment direct accessing of this large address space. protection and other segment management features. The protection features prevent illegal uses of segments, such as | Memory Management writing into a write-protected zone, . ‘The addresses manipulated by the programmer, used by Each Memory Management Unit stores 64 segmententries * instructions and output by the Z8001, are called /ogical _that consist ofthe segment base address, its attributes, size, addresses. The Memory Management Unit takesthe logical _ and status. Segments are variable in size from 256 bytes to addresses and transforms them into the physical addresses 64 kilobytes in increments of 256 bytes. Pairs of tequired for accessing the memory (Figure 6). This address ~~ Management Units support the 128 segment numbers transformation process is called relocation. Segment available for each of the six CPU address spaces. Within an relocation make8 user software addresses independent of address space, several Management Units can be used to the physical memory so the user is freed from specifying “create multiple translation tables. t EXTENDED PROCESSING ARCHITECTURE The Zilog Extended Processing Architecture (EPA) provides The processing power of the Zilog Z8000 16-bit an extremely flexible and modular approach to expanding microprocessor can be boosted beyond its intrinsic both the hardware and software capabilities of the Z8000 capability by Extended Processing Architecture, Simply CPU, Features of the EPA include: stated, EPA allows the 28000 CPU to accommodate up to ™ Specialized instructions for external processors or Ur Extended Processing Units (EPUs), which perform software traps may be added to CPU instruction set. specialized functions in parallel with the CPU's main - ips may . instruction execution stream (Figure 7). a Increases throughput of the system by using up to four - sali hl The use of extended processors to boost the main CPU's allel I. Specialized external processors in paralialwith t@CPU. — rtomance capability has been proven with large ™ Permits modular design of Z8000-based systems. mainframe computers and minicomputers. In these ‘i systems, specialized functions such as array processing, = Provides easy management of multiple microprocessor Sar incutoutput processing, and data communications configurations via “single instruction _ stream’ 4 ‘communicati processing are typically assigned to extended processor inication. . hardware. These extended processors are complex 4 @ Simple interconnection between extended processing —_ computers in their own right. . : it it tional external . . i Coe ances eatltes no aeidlonal exerél te 710g Extended Processing Architecture combines the . " best concepts of these proven performance boosters with i ™ Supports debugging of suspect hardware against — thelatestin high-density MOS integrated-circuit design. The ' proven software. result is an elegant expansion of design capability—a powerful microprocessor architecture capable of t= Standard features on ll Zilog 28000 CPUs. Connecting single-chip EPUs thet permits very effective Specific benefits include: parallel processing and makes for a smoothly integrated : i ti m from the Z8000 programmer's point of m= EPUs can be added as the system grows and as EPUs instruction stream f mmers point 0 with specialized functions are developed. view. A typical addition to the current 28000 instruction sets ; : . a set of Floating Point Instructions. | = Control of EPUsis accomplished viaa "single instruction +1, Etended Processing Units connect directly to the : stream’ in the 28000 CPU, eliminating mary significant 73445 \\Bue (-BUS) and continuoceh itor the CPU system’ software and bus contention management (24 us g -BUS) Wh con Tnemtartied rt i i i obstacles that occur in other multiprocessor (e.g., Gotente othe ream. into EPU wom e ‘i baling 's master-slave) organization schemes. ected, the appropriate responds, obteining or H 132 - ‘ ener

delivering operands and data to it. The EPU recognizes " . m Register . EPA and CPU instruction execution are shown in Figure 8. @ Direct Address EPU meanwhile monitors the Z-BUS for its own instructions. emulate the desired EPU function—a very useful deactivates the STOP line and CPU transactions continue. PERIPHERAL PERPHERAL wanageatenr . Figure 7. Typical Extended Processor Configuration

ZILOG INC L7E D M@ 9984043 0011685 7 me —_ eS T-49-17-07 i : | ra 1] AND BLAcES on wMernuorion . ° 1 No No 1 A INO a ee ‘STOR cru EPATRAP UNGAT CeO Figure 8, EPA and Z8000 CPU Instruction Execution ee SEP TO Oreeeeee INPUT/OUTPUT A set of I/O instructions performs 8-bit or 16-bit transfers Two types of /O instructions are available: standard and between the CPU and I/O devices. 1/0 devices are special. Each has its own address space. The I/O addressed with a 16-bit I/O port address. The /O port __ instructions include a comprehensive set of In, Out, and address is similar to a memory address; however, /O Block I/O instructions for both bytes and words. Special /O address space need not be part of the memory address instructions are used for loading and unloading the Memory space. I/O port and memory addresses coexist on the same Management Unit. The status information distinguishes bus lines and they are distinguished by the status outputs. between standard and special I/O references. iii heeled naaa cahine deinen gina MULTI-MICROPROCESSOR SUPPORT . ‘Multi microprocessor systems are supported in hardware Multi-microprocessor systems are supported in software by and software. A pair of CPU pins is used in conjunction with the instructions Multi-Micro Request, Test Multi-Micro In, Set certain instructions to coordinate multiple microprocessors. Multi-Micro Out, and Reset Multi-Micro Out. In addition, the The Muiti-Micro Out pin issues a request for the resource, _ eight megabyte CPU address space is beneficial in multiple while the Multi-Micro In pin is used to recognize the state of microprocessor systems that have large memory the resource, Thus, any CPU in a multiple microprocessor —_requirements. ‘system can exclude all other asynchronous CPUs from a . critical shared resource. . _ | a 134 . .

ZILOG INC L7E D MM 9984043 0011486 9 me \\ SSS ADDRESSING MODES T-49-17-07 The information included in 28000 instructions consists of Figure @ illustrates the eight addressing modes: Register the function to be performed, the type and size of data (R), Immediate (IM), Indirect Register (IR), Direct Address elements to be manipulated, and the location of the data (0A), Index (x), Relative Address (RA), Base Address (BA), elements. Locations are designated by register addresses, and Base Index (BX). In general, an addressing mode memory addresses, or I/O addresses. The addressing explicitly specifies elther register address space or memory mode of a given instruction defines the address space it address space. Program memory address space and I/O references and the method used to compute the address address space are usually implied by the instruction. Itself. Addressing modes are explicitly specified or implied by the instruction, Addressing Mode Operand Addressing Operand Value 7 : —_ Terri Inthe Instruction Ind Register In Memory. . R ee IM . Immediate In the fastruction eee “IR Indirect . | The content of the location Sa DA : The content ofthe locaton whose address fg in the naka, Ge} [ara] plied . The content of the loca- lade [Cex] tion whore address the index iddress in the instruc L_ssesconss | O—Lemmmio] Fitts content ale working register, ee RA The content of the location . whose address Is the : Address [_ssreacenenr O—+[ereeano] Sermon ut by the Instruction “BA address in the rogiater, Address. [_snscewent_] © ‘ist by the daplacensent Jn the fastruction a *BX The content of the loca- Baso [ens anon ton whose address ts | Index [ostensonase] of eer} +) thar neha | nother register, ; EE * “Do not use RO or RRO as indirect, index, or base registers, ‘ . Figure 9. Addressing Modes - 135 Sa aaennmnmere

ZILOG INC 17E D M™@ 9984043 0011887 O mm INSTRUCTION SET SUMMARY : T-49-17-07 ‘The 28000 provides the following types of instructions: i Bit Manipulation = Load and Exchange 1m Rotate and Shift : = Arithmetic __ Block Transfer and String Manipulation i @ Logical ot & Input/Output ; Program Control + = CPUControl ij . ee : LOAD AND EXCHANGE ° ° Clack Cyctes* . Addr, Word, Byte LongWord =~ Mnemonics Operands Modes NS SS SL NS SS SL Operation —— OE EEE cLR dst R 7 07 ~«°7 Clear CLRB R 6 8 8 dst~0 . DA 11 1214 x 120 12 15 . a EX Ry sre R 6 6 6 Exchange + EXB . IR 12012012 Res . DA 15 1618 . x 1% 16 19 a eSeeesssSSseesesesesesFsFsFsFsFsFFseFSSSSeS Lo R, sre R 3 3 3 5 6 65 Loadinto Register LB iM 7 7 7 1 44 11 Re sre tL. iv 5 (byte only) : R 77 7 Mo OH . DA » 10 2 12 18 15 x 10 10 13 13 «13 «16 i BA 14 14 147717. ' : Bx 4 14 14 7 a to dst, R IR 8 8 8 11 11 11 Load into Memory (Store) LOB OA 11 12 14 «140 «15 17 dst R LoL x 12.12 «15 «#415 «18 18 BA 140 141417197), 17 i . BX 14 14 14 17 7 W : j ee up dst, IM IR WoW on Load Immediate into Memory : LOB DA 14°16 17 dst - IM : x 16 18 (18 a . LDA R, src DA 1213815 Load Address x 181316 R = source address BA 15 1615 . BX 18 15 15 ee LOAR Ry src RA 16 1518 Load Address Relative . R + source address eee Lok Rysre IM 5 6 5 Load Constant i — ee 1 LDM Rysro,n R41 11 14480 Load Multiple OA 14 415 1748 R «sre (n consecutive words) | ‘ *NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset | SSS 136 / z | SSS a *

ZILOG INC 17E D M@ 9984043 00114683 2 sss LOAD AND EXCHANGE (Continued) : T-49-17-07 a Clock Cycles* Addr. Word, Byte LongWord =. Mnemonics Operands Modes NS SS SL NS SS SL Operation LOM ga : LOM dst, Rn iR Wt +3n Load Multiple (Store Multiple) CA 14 18 1743 dst R (n consecutive words) a Lor R, sre RA 4 14 14171747 Load Relative LORB Resi t LDRL (range - 32768... +32767) : DOR gm LoR dst,R RA 14 14 14 «17 1717 Load Relative (Store Relative) : LORB . dst-R LDRL (range - 32768... +32767) AG TSP TEB 492767) PoP dst, IR R 8 8 8 12 12 ‘12 Pop POPL iR 12012 «120« 19° «19 «19 dst=iR an DA 16 16 18 23 23-25 —Autoincrement contents of R x 16 16 «419 «423 «023 (26 BUS PUSH IR, arc R 9 9 9 2 12 12 Push PUSHL IM 12 12 12 19 19 19 —_Autodecrement contents of R IR 18 138 13° 200 20 20 Rest DA 14 14 16 att X 14 14 170 otto ad i ARITHMETIC | a apc R, sre R 5 6 5 ‘Add with Carry ADCB R“R + src + carry RR OR cay ADD Ri sre R 4 4 4 8 8 8 Add ADDB M 7 7 7 14 14 14 ReR48I ADDL : IR 7 7 7 14 14 14 DA 9 10 2 16 16 18 : x 10 10 13 16 16 © 19 cp R,sre R 4.4 4 68 8 8 Compare with Register CPB iM 7 7 7 14 44 14 R= 60 CPL IR 7 7 7 140 14 44 . DA 9 10 2 1 16 18 i x 10 10 13 #16 «#16 «619 : ara cp dst, IM in woo 41 Compare with Immediate . cPB DA 14 15 17 dst — IM x 15 15 18 : Soe DAB dst R 5 6 § Decimal Adjust ! ea ectmatAjust "DEC dst, R 4 4 4 Decremented by n | DECB IR a dst + dst - n ! x 4 14°17 “NS =Nonsegmented SS = SegmentedShort Offset SL = Segmented Long Offeat i I 137 a eee

ZILOG INC L7E D M@ 9984043 0011889 4 om j SO ARITHMETIC (Continued) T-49-17-07 ClockCycles* Addr. Word, Byte Long Word Mnemonics Operands “Modes NS SS SL NS SS SL Operation en ow R, sro R 107 107 107 744 744 744 — Divide signed) t DIVE, IM 107 107 107744744744 Word: Raat Rona + 810 | (R107 107 107-744 «744744 Rn + remainder | DA = 108 109111745746 748 LongWord: Rn+2,n43%Fin, nea tsre Xx 109 109 112 746 746 749 Ran+2 remainder nei . EXTS dst | R W411 14141111. Extend Sign EXTSB Extend sign of low order half of dst EXTSL through high order halt of det NN ncler ote inc dst. R 4 4 4 Increment by n . ' INCB IR WoW on : dst dst +n : DA 138 1416 (0 = 1... 16) x 414417 . f a i MULT R, src R 70 70 70 2e2t 2e2t 2e2t Multiply (signed) : MULTL IM 70 70 70 282t 2e2t 2e2t Word: Ranet Rost ® 810 IR 70 70 70 2e2t 2e2t 2e2t LongWord: Rn..n+3*Rn+20+9 DA 71-72, 74-—2B3t 2847 286+ —_tPlus seven cycles for each 1 inthe : x 72 72 75 2eat 2e4t 287t — multiplicand EO Oe NEG dst R 7 7° 7 : Negate NEGB IR 12 12 «- 42 dst +0 — dst DA 15 1618 x 16 16 «(19 SBC Ry sre R 5 6 5 Subtract with Carry SBCB - R“R-~ se -cany ee TY suB R, sre R 4 4 4 8 8 8 Subtract SUBB IM 7 7 7 14 14 14 ReR-s0 SUBL IR 707° 7 14 14 14 . DA 9 10 12 15 16 18 x 10 10 18 16° 6 19 SSS LOGICAL ees ' * AND R, sto Roo 4 4 4 AND | | ANDB IM 7 7 «7 R+RANDsrc - IR 7 7 7 . DA 9 10 12 x 10 10 «13 eee com dst R 7°77 Complement COMB IR 120 12 «12 dst + NOT dst DA’ 16 16 18 x 16 16 «(19 a oR Rysre R 4. 4 °° 4 _ OR : ORB IM 7 7 «7 R+RORsro ! IR 7 7 7 DA 9 10 12 . x 10 10° 13 a “NS =Nonsegmented $$ = SegmenledShort Offset - SL = Segmented ong Offset . 138 :

t ZILOG INC L7E D Mm 9984043 0011890 0 mm , . SS LOGICAL (Continued) | T-49-17-07 Clock Cyctes* . Adde, Word, Byte Long Word : Mnemonics Operands Modes NS SS SL NS SS SL Operation Tec 0, dst R 5 5 5 Test Condition Code ; Tecs Set LSBifccis true | EB Hoste TEST dst R 7 7 7 13 AZ 13 Test : TESTB IR 8 8 6 13 13 13 dstORO TESTL DA W 12 14 16 17 19 x 12 12 15 17 17 20 nner eee XOR R,stc R 4 4 4 Exclusive OR XORB IM 7 7 7 R+RXOR sic IR 7 7. 7 : DA 9 10 12 ! x 10 10 13 | a i PROGRAM CONTROL . : cc CALL dst IR 10 16 15 Call Subroutine - DA 12 18 20 Autodecrement SP x 13 18 21 @sP+PC PO+dst Se CALR dst RA 10 10 15 Call Relative Autodecrement SP . @sP+Pc : PC“PC+ dst (range ~ 4094 to +4096) PPO + ast (Fange ~ 409410 + 4096), DJINZ R, dst RA Ww W 1 Decrement and Jump if Non-Zero DBJNZ R+R-1 IER #0: PC+PC + dst(range — 264 to 9) CERRO PON PC + ds(range 264 t0 9) | IRETT - - 13 13 16 Interrupt Return . PS+@sP Autoincrement SP $a OCHS JP ce, dst IR 10 10 15 (taken) Jump Conditional IR 7 7 7 (not taken) Ifecis true: PC - dst DA 7 8 10° : x 8 8 W ee JR co, dst RA 6 6 6 Jump Conditional Relative Hecistrue: PC+PC + dst (range - 266 to +254) . GH HY +254) RET co > 10 10 13 (taken) Return Conditional 7 7 7 (not taken) Iocistrue: PC - @ SP. i Autoincrement SP. Hi = eincrement SP sc ste M 33 93 39 System Call | Autodecrement SP t : @SP<old PS Push instruction 7 - PS = System Call PS *NS = Non-segmented $$ = Segmented Short Oifset SL = Segmented Long Offset Privileged instruction, Executed in system mode only. SSS 139 es ee

ZILOG INC L7E D M@ 9984043 0011491 2 mm BIT MANIPULATION . T-49-17-07 : Clock Cycles* ve Addr. Word, Byte Long Word Mnemontes Operands Modes ‘NS SS SL NS SS SL Operation BIT dst, b R 404 4 __ Test Bit Static BITB IR 8 8 8 Ztlag + NOT dst bit specified by b . DA 10 1118. x 1. 1 14 ; BIT dst, R R 10 10 «10 Test Bit Dynamic BITS Z lag ~ NOT dst bit specified by . contents of R RES dsb > OR 4 4 4 Reset Bit Static ESB IR woot on Reset dst bit specified by b | PA 18 416 x 141617 RES dst, R 'R 10 10 «10 Reset Bit Dynamic RESB Reset dst bit specified by contents R SET dst, b R 4 4 4. Set Bit Static SETB R nT) . Set dst bit specified by b ! DPA 181416 x 4 4 O17 SET dst, R R 10 10 10 Set Bit Dynamic SETB . Set dst bit spécified by contents of R TSET | dst R 7 7 TF Test and Set TSETB IR noon S flag ~ MSB of dst DA 14° 16 «17 ~ * dst+all 1s x 16 15 18 ROTATE AND SHIFT AL dst, R 6torn=1 Rotate Left : ALB R Tiorn=2 bynbits (n = 1,2) RL dst, R 6forn=1 Rotate Left through Carry RLCB R Ttorn=2 bynbits(n = 1,2) . RLOB : Ry sro R 9 9 9 Rotate Digit Left . RR stn R 6forn=t Rotate Right RRB R 7 for n=2 bynbits(n = 1,2) RRC dst, R 6forn=1 Rotate Right through Carry RRCB R + Tforn=2 + bynbits (a = 1,2) RRDB Ry sc R 9 9 9 Rotate Digit Right SDA dst,R R (15 + 3n) (15 + 3n) Shift Dynamic Arithmetic | SDAB Shift dst left or ight by : SDAL : contents of R spL © dst, R R, (15 +3n) (15 +3n) Shift Dynamic Logical SDLB : . ‘Shift dst lett or right by SDLL contents of R “NS = Nonsegmented SS = Segmented Short Oliset SL = Segmented Long Offset . 140

‘ ZILOG INC L7E D M@ 99484043 0011892 4 mm ROTATE AND SHIFT (Continued) T-49-17-07 rr . Clock Cycles . . Addr. Word, Byte Long Word Mnemonics Operands Modes NS SS SL NS SS SL Operation $$ SE erctiocn SLA dst,n R (13 + 3n) (13 + 8n) Shift Left Arithmetic * SLAB . bynbits SLAL . Se SLL dst,n R (13 + 3n) (13 + 3n) Shift Left Logical sua by nbits - SLLL . . SRA . asta R (13 + 3n) (13 + 3n) Shift Right Arithmetic SRAB byn bits SRAL : SRL dst, R (13 + 3n) (13 + 3n) Shift Right Logical SRLB . by nbits SRLL ee BLOCK TRANSFER AND STRING MANIPULATION cPD Ry,src,Rycc iR 20 20 20 Compare and Decrement - CPDB Rx = sro. Autodecrement src address . : RyRy - 1 | CPDR Rysto,Ryec IR (11 +9) Compare, Decrement, and Repeat CPDRB Rx ~ ste . Autodecrement sre address RyRy -1 Repeat until ccis true or Ry = 0 cpt RystoRyec = R200 ‘Compare and Increment cPiB Rx ~ sie . . Autoincrement src address. Rye Ry - 1 cPIR Ry,sre,Ryco R - (11+ 9n) Compare, Increment, and Repeat CPIRB Rx - sic Autoincrement src address : RyRy -4 . Repeat until ccis true or Ry = 0 cPsD dst,src,R,co IR 25 25 25 Compare String and Decrement cPSDB : : . dst ~ sto : . Autodecrement dst and src addresses R<R-14 : CPSDR dst,sre,R,oc IR (11+ 14n) Compare String, Decrement, and CPSDRB Repeat ; dst - sro . Autodecrement dst and src addresses R<R~1 =: . . Repeat until cc is true or R = 0 “NS = Non-segmented — §S = Segmented Short Offset. SL = ‘Segmented Long Offset 141

ZILOG INC L7E D Mm 9984043 0011493 6 ml BLOCK TRANSFER AND STRING MANIPULATION (Continued) : T-49-17-07 ° Clock Cycles* . . Addr, Word, Byte Long Word ‘Mnemonics Operands Modes NS SS SL NS SS SL Operation Psi dst,src,R,cc IR 25 25 25 Compare String and Increment CPSIB dst - src . * Autoincrement dst and src addresses R<-R-1 CPSIR dst,src,R,co. IR (11 + 140) Compare String, Increment and CPSIRB Repeat dst — sic . Autoincrement dst and src addresses ReR-1 4 Repeat until cois true orR = 0 LOD dst,sro,R IR 20 200 20 Load and Decrement LDDB dst + sro . . Autodecrement dst and sro addresses: : R<R-1 LDDR dst,sro,R IRo* (11+ 9n) Load, Decrement and Repeat LDORB . dst + sro Autodecrement dst and src addresses R<R-1 . Repeat until R = 0 Lor dst,sr0,R IR 20 20 20 Load and Increment . Low dst sre . Autcincrement dst and src addresses . . ReR-1 LOIR dst,src,R IR (11+ 9n) ‘Load, Increment and Repeat LDIRB dst = sro Autoincrement dst and src addresses . ReR-1 Repeat until R = 0 TROB dst,sic,R IR 2 2 25 Translate and Decrement i dst + src (dst) a Aulodecrement dst address ReR-1 TRORB dst,sre,R IR (14140) Transtate, Decrement and Repeat i dst + sro (dst) . Autodecrement dst address . R-R-1 , Repeat untilR = 0 TRIB dst,sro,R IR 25 25 25 Translate and Increment . dst + src (dst) . Autoincrement dst address } ReR-1 7 . ‘NS = Non-segmented SS = Segmented Short Offset SL = Segmented Long Offset . i “Privileged instruction. Executed in system mode only. 3 . 142

ZILOG INC L7E D M@@ 9984043 0011894 6 me OCK TRANSEER AND aTRina AM ~ 49-17-07 BLOCK TRANSFER AND STRING MANIPULATION (Continued) T-49-17 ee a Clock Cycles* Addr, Word, Byte Long Word ‘ Mnemonics Operands Modes NS SS SL NS SS SL Operation Lae hn . TRIRB dstsro,R IR (11+ 140) Translate, Increment and Repeat dst + sre (dst) Autoincrement dst address R+R-1 Repeat until = 0 Seat TATDB srotsto2R IR 2 258 ‘Translate and Test, Decrement RH1 +src2 (sret) . Autodecrement src 1 address ReR-14 Sener _ TATORB srot,sc2,R IR (114 14n) ‘Translate and Test, Decrement, and ° Repeat . RH1 = s1c2 (erct) ‘ Autodecrement sro1 address ReR-4 . Repeat until = Oor RH1 = 0 ATU S DOFRHT = TATIB srct,sto2R IR 25 255 Translate and Test, Increment RH1 ~ sr02 (srct) Autoincrement sro address. « ReR-1 i TATIRB srci,ste2,R IR (11 + 140) Translate and Test, Increment and Repeat RH1 + src2 (sret) Autoincrement sro 1 address R+R-4 - Repeat untiR = Oor RHI = 0 $A RAEUNTTR S OOFRHT =O INPUT/OUTPUT : a int Rsro IR 10 10 10 Input Inst DA 120 «1212 Resto ee tnot dst.sro,R. IR 2 at oat Input and Decrement inpBt dst + sro . Autodecrement dst address R<R-4 : een . INDRt dst.sro,R IR (11 + 10n) Input, Decrement and Repeat INDRBt dst = sre . Autodecrement dst address : ReR-4 : Repeat until = 0 eI Init dst,sre,R IR 21 21 oat Input and Increment | INIBt : " dst~sro F Autoincrement dst address : ReR-1 : *NS = Non-segmented — SS = Segmented Short Offset. SL = ‘Segmented Long Offset ‘Privileged instruction. Executed in system mode only. 143 [Sn NN

. ZILOG INC G L7E D mm 9984043 OO1l855 T mm SSS INPUT/OUTPUT (Continued) T-49-17-07 See Clock Cycles* Addr. Word, Byte Long Word Mnemonics Operands Modes NS SS SL NS SS SL Operation —$—$ Or INIRt dst,st0,R IR (11 + 10n) Input, Increment and Repeat INIRBT : . dst + src . ‘Autoincrement dst address R+R-1 { Repeat until R = 0 fi outt dst.R IR 10 10 10 Output outst DA 120012012 dst-R. ee ourpt dst,sro,R IR at att ‘Output and Decrement ~ ouTDBt : dst + sro : ‘Autodecrement src address R+R-1 SSS oTprt dst,sr0,R IR (11 + 10) Output, Decrement and Repeat . oTorst dst = sre | Autodecrement sro address . i R<R-1 t : Repeat until = 0 : | ee SSSSSSAOa———rEE outit dst,sro,R R at at at Output and Increment | ouTiBt dst sre ij Autoincrement sic address | R<R-1 1 eee oTiRt dst,sr0,F IR (11 + 10n) Output, Increment, and Repeat oTIRBt dst “sre Auloincrement src address R+R-4 Repeat until R = 0 oe eeeSeSSSSSSSSSSSSSSSSSSS EE Sint Ree DA 12 12012 Special Input SINBt . Rest : sinpt ~ dst,sro,R IR a 21 at Special Input and Decrement SINDBt : dst = sre Autodecrement dst address R<R-1 ] SSS SINDRt dstsro,R IR 11+ 10n) Special Input, Decrement, and SINDRBt Repeat : dst + sro - Autodecrement dst address : R<R-1 . Repeat until R = 0 —eeeeesesesssssSsSssssssSsSSSSSSsSSSSSSSS EE sinit dstsro,R R ers) Special Input and Increment siNiBt dst + sre ' Auloincrement dst address R<R-1 : SS *NS = Non-segmented — SS = Segmented Short Offset SL = Segmented Long Otiset j Privileged instruction, Executed in system mode only. . | SSS

ZILOG INC L?7E D M@ 9984043 0011856 1 me | ee INPUT/OUTPUT (Continued) T-49-17-07 Clock Cycles’ . Addr. Word, Byte Long Word . Mnemonics Operands Modes NS SS SL NS SS SL Operation rato SINIRt dst.sr0,R IR (11 + 10n) Special Input, Increment, and SINIRBt Repeat dst ~ src . Auloincrement dst address ReR-1 Repeat until = 0 souTt ~ dstsro DA 2 12 12 Special Output . 1 souTst dst + sro souTot dst,src,R IR 21 ft ot ‘Special Output and Decrement SOUTDBt dst + sro . : Autodecrement sto address . R<R-1 sotort dst,sro,R R (1+10n) = Special Output, Decrementyand : soToRst Repeat dst sro Autodecrement sre address : R=R-1 : Repeat until R = 0 soutit dst,sro,R IR at 21 at ‘Special Output and Increment soutiat dst + sre Autoincrement src address R<R-1 soTint dst,sro,R ® (11 + 10) Special Output, Increment, and soTinBt Repeat dst~sro . ° Autoincrement src address ' : R<R-1 Repeat until R = 0 CPU CONTROL COMFLG flags = 7° 7° 7. Complement Flag a (Any combination of CZ, 8, P/V) | ort int” - 7 7 7 Disable Interrupt (Any combination of NVI, Vi) | et int - 7 7 7 Enable Interrupt (Any combination of NVI, Vi) HALTY - : (6+ 3n) HALT : Locrit CTLA,src R. 7 7 7 Load into Control Register CTLR sre Loctit dst,CTLR R 7 07° 7 Load from Control Register . dst = CTLR . ANS = Non-segmented SS = SegmentedShort Olfset_ SL = Segmented Long Ofiset ‘Privileged instruction, Executed in system mode only. ay ‘

ZILOG INC 17E D MH 9984043 0011857 3 mm ; Se cc 1 CPU CONTROL (Continued) T-49-17-07 : SSS Clock Cycles* . , Addr. Word, Byte Long Word Mnemonics Operands Modes NS SS SL NS SS _ SL Operation a LOCTLE FLGR,sro R 7 7 «7 Load into Flag Byte Register : FLGR «sro : eS LOCTLB dst,FLGR R 7 7 7 Load from Flag Byte Register . dst FLGR le Lopst src R 12 16 «16 Load Program Status . DA 1620. 22 PS=sro . x 17 20 23 cc MBitt - - 7 7 7 Test Multi-Micro Bit . Set Sif Ml is Low; reset Sif MIis High CSI wrest S IMIS Hig MREQt dst R (12 +n) Multi-Micro Request Or Reguest Mrest - = 5 5 5& Multi-Micro Reset i COSC MseTt - - 5 7 7 Multi-Micro Set OSH NOP - - 7° 7 7 No Operation j POO RESFLG flag - 7° 7° °7 Reset Flag | : (Any combination of C, Z, 8, PV) i COMB ANNA ESPN) SETFLG flag - 7 07 7 Set Flag (Any combination of C, 2, S, P/V) *NS = Non-segmented SS = Segmented Short Offset SL = ‘Segmented Long Ottiset i ‘Privileged instruction. Executed in ‘system mode only. i SSS 146 19 | ES SRR RR SESS SS |

ZILOG INC 1?7E D M@ 1984043 0011898 5 mm gg 17-07 CONDITION CODES | Code Meaning Flag Settings ccField F Always false - - 0000 ° T Always true - 1000 - 2 . Zero Z=1 0110 NZ Not zero Z=0 11107 c Carry C=i “ott + NC No Carry C0 qnn4 PL Plus S=0 1101 MI Minus S=1 . 0101 NE Not equal Z=0 1110 EQ Equal . Ze 0110 Ov Overflow PN=1 © 0100 Nov No overtlow PV =0 1100 PE Parity is even PV=1 . 0100 PO Parity is odd PN=0 1100 . GE Greater than or equal (signed) (SXORP™ = 0 : 1001 uw Less than (signed) (SXOR PM) = 1 0001 . GT Greater than (signed) [ZOR(SXOR PM) = 0 1010. Le Less than or equal (signed) [ZOR(SXORPM)=1 * 0010 UGE Unsigned greater than or equal Cx=0 4411 uLT Unsigned less than Cat ont uaT + Unsigned greater than (C= Q)AND@ =O) =1 1011 ULE Unsigned less than or equal (CORZ) =1 0011 Note that some condition codes have identical flag settings and binary fields in the instruction: . Z = EQ, NZ = NE, C = ULT, NC = UGE, OV = PE, NOV = PO : OO SSSSSSSSSSSSSSSSSSSSSSSSSSsSSSSSSSSSSSSSS ; STATUS CODE LINES SToST3 Definition . . 0000 —_Internal operation 0001 = Memory refresh . 0010“ NOreference . 0011 Special I/O reference (e.g., toan MMU) ) 0100 ‘Segment trap acknowledge . . 0101 Non-maskable interrupt acknowledge

0110 Non-vectored interrupt acknowledge

0111 Vectored interrupt acknowledge

1000 Datamemory request .

1001 Stack memory request

1010 Datamemory request (EPU)

1011 Stack memory request (EPU)

1100 Program reference, nth word . _ 1101 Instruction fetch, first word |

1110 Extension processor transfer |

1111 Reserved ‘ :

: 147 Hy

ZILOG INC L7E D M@ 9984043 00118699 7 ee PIN DESCRIPTION T-49-17-07 ADo-ADj5. Adoress/Data (inputs/outppts, active High, — non-maskable interrupt. The NMI interrupt has the highest 3-state). These multiplexed address and data lines are used _ priority of tHe three types of interrupts. for VO and to address memory. NI. Normal/System Mode (output, Low = System Mode, AS. Address Strobe (output, active Low, 3-state). The rising _3:stale). N/S indicates the CPU is in the normal or system edge of AS indicates addresses are valid. mode, BUSACK. Bus Acknowledge (output active Low). ALow on NVI. Non-Vectored Interrupt (input, active Low). A Low on this line indicates the CPU has relinquished control of the this line requests a non-vectored interrupt. bus. RESET. Reset (input, active Low). A Low on this line resets : BUSREG. Bus Request (input, active Low). This line must the CPU. . be driven Low to request the bus rom the CPU. RAW. Read/Write (ouiput, Low = Write, 9-state). RAT BIW. Byte/Word (output, Low = Word, 3-state). This signal indicates that the CPU is reading from or writing to memory defines the type of memory reference on the 16-bit or l/O. addressidata bus, . SEGT. Segment Tap (input, active Low). The Memory CLK. System Clock (input). CLK is a SV single-phase — Management Unit interrupts the CPU with a Low on this line - time-base input. when the MMU detects a segmentation trap. Input on i DS. Data Strobe (output, active Low, 3-state). This line times 28001 only. | the data in and out of the CPU. SNo'SNg. Segment Number (outputs, active High, 3-state). : MREG. Memory Request (output, active Low, 3:state), A. These lines provide the 7-bit segment number used to Low on ths ine indicates thatthe adress/data bus holdsa pUHeSS One ot 128, ator tol oni memory memory address. 9 - Outp a ii, 10. Mutt-Micro In, MultiMicro Out (input and output, STo-ST. Status (outputs, active High, 3-state). These lines active Low). These two lines form a resource-request daisy SPecify the CPU status (see Status Code Lines). chain that allows one CPU in amulti-microprocessor system STOP, Stop (input, active Low). This input can be used to to access a shared resource. single-step instruction execution. . NMI. Non-Maskable Interrupt (edge triggered, input, active Vj, Vectored Interrupt (input, active Low). A Low on this line Low). A high-to-low transition on NMI requests a requests vectored interrupt. WAIT. Wait input, active Low). This line indicates to the CPU thal the memory or /O device is not ready for data transfer. a0 Dan ao? afew Ade (Js 4s [] sus aon} s «s[] ap, 4onOs . TT any . ao, 401] Any . route afta. aoeQ 2 20 fT a, . stor]? aDsn Adu] 8 38 ao, mee “Bl a0, soul] « a7 ay rove «Lan, Adal] 6 35 AD, F aout] 10 291 an, sropC] 6 251) Avs . i +sv] a8 Fan, mr 24] ADs woe aP}on, route aa ao, mats 79°F Fay ADE] ® 32] Ao, 4 seat G4 35 ctock ssv 0 a1] ano E wa] ufies WG] 7892 3A ciocx { . FeserQj ssf] xc mM 12 apa i WoC) 17 spew Ret Cj 13 zap} ne WanEG [18 af yns weser Cj 14 aD ew Cw olnw wot 26 Ns st, 20 290] sUSACK ‘nee (] 16 25] RA a sn Oa 2) war . wow . 24 [] BUSACK | . st jaz 27) BUshEG si Cie 2a |] WaT . : ste] 23 26D] sno si] 0 22) BUSREG . i ‘sn; [J 26 2siJsn, nO a 2p] Ste . i Figure 10a. 48-pin Dual-In-Line Package (DIP), Figure 11a. 40-pin Dual-In-Line Package (DIP), { Pin Assignments Pin Assignments . i 148 |

ZILOG INC L7E D MM 9984043 0011500 T mm | ese seers oe Tee ea a a a eT STOR |e AB TON wife ss}aoy 10. | 0 wahoo on te foo av iia aan, no | ta aspen : Vii 40] ono Wifis secu ‘SEGT ie es wi a7 37 | RESERVED ABORT RESET |e ae few . Whe Bo ; WEG 20 wine Hupussrenen es : POPP M MH BELLE * Wo = Wo connection . 52-pin Chip Carrier, Pin Assignments . Serres Korres . TET sa Te Rw . sToR 7 a9] aos me 28] is voufe a7} a0, . 0% | 10 ae] a0, sav fit 3s ovo wo | 2 uf cx Vij af aS AV ta 32 | RESERVED AMI 1s ap ew reser | 10 ao| wa wo [7 23] nw te te 20 21 2 23 4 25 25:77 28 . . PPE OE EES . Figure tb. 44pin Chip Carrier, Pin Assignments . SSS Z8000 CPU TIMING . The 28000 CPU executes instructions by stepping through Request instruction (MREQ). set of basic machir les, such as mem« id ine tient . ri . pe ate, VO ‘devioe r read or wate. nko mip a cknowedge The following timing diagrams show the relative timing and internal execution. Each of these basic cycles requires _'@!Ationships of all CPU signals during each of the basic three oten clock cycles to execute. Instructions that require Operations. wen amar nine cycle requies addtional clock more clock cycles to execute are broken up into several cyoles for U intern PO de i ne loc} pee - machine oycles. Thus no machine cycle is longer thanten te, srupt oe ee 4 and wi Sitar Sod by clock ‘cycles and fast response to @ Bus Request is civating he WAIT input, For exact ting information reler a . tothe composite timing diagram. « H The instruction opcode is fetched by anormal memory read ae ott operation. A memory refresh cycle can be inserted just after ening ain dros por synchronizes i sn mares the completion of any first instruction fetch (IF) cycle and ela Can also be inserted while the following instructions are Clock must be met. I asynchronous wal iy oepotd being executed: MULT, MULTL, DIV, DIVL, HALT, all Shift generate , they must be synchronized with the CPU clock _ instructions, all Block Move instructions, andthe Multi-Mioro . Péfore entering the 28000. eS | : 149 ee ne a i

ZILOG INC A7E D MM 9984043 0011501 1m” ————eSSSSSSSSSSSSSSSSSssesesesesFsFSSSSSeF MEMORY READ AND WRITE T-49-17-07 Memory read and instruction fetch cycles are identical, ex- Low, an additional clock periods added between Tp and. cept for the status information on the STo-STs outputs. WAIT is sampled again in the middle of this wait cycle, and During a memory read cycle, a 16-bit address is placedon additional wait states can be inserted: ths allows interfacing the ADo-ADjs outputs early in the first clock period, as “slow memories. No contro! outputs change during wait shown in Figure 12. In the Z8001, the 7-bit segment num- states, . Ror output on SNo-SNe one clock period earlier than th® —ainoyah 78000 memory is word organized, memory is ; ss addressed as bytes. Allinstructions are word-aligned, using : A valid address is indicated by the rising edge of Address —_ even addresses. Within a 16-bit word, the most ‘significant Strobe. Status and mode information become valid early in byte (Dg-D;s) is addressed by the low-order address (A = the memory access cycle and remain stable throughout. Low), and the least significant byte (Do-D7) is addressed by The state of the WATT input is sampled in the midale of the the high-order address (4g = High). second clock cycle by the falling edge of Clock. if WAIT is . TT ONS : . ta th . cock | | , f 1. | Paegureo WAIT CYCLES ADDED} : war - —t Pon —_ status rs | vo —— . I | if a one : J ao wl a a aa waite - Figure 12. Memory Read and Write Timing $$$ : 160 :

Figure 13. Input/Output Timing

ZILOG INC 17E D M™ 9984043 0011903 5 mm eee INTERRUPT AND SEGMENT TRAP T-49-17-07 REQUEST AND ACKNOWLEDGE . The Z8000 CPU recognizes three interrupt inputs — Thiscycle has five automatic wait states, with additional wait (non-maskable, vectored, and nonvectored) and a states possible, as shown in Figure 14. mentation trap input. Any High-to-Low transition on the , . iM input ig asynchronously edge detected and sets the ff the last wait slate, the CPU reads the information on ple TW " ADo-AD4g and temporarily stores it, to be saved on the stack internal NMi latch. The Vi, NVi, and SEGT inputs, as well as later i " " later in the acknowledge sequence. This word identifies the the state of the internal NMI latch, are sampled at the end of source of the interrupt or ti For th tored and Te inthe last machine cycle of any instruction. . foe of the Interrupt or trap. For the nonvactored ar 2 nonmaskable interrupts, all 16 bits can represent peripheral In response to an interrupt or trap, the subsequent IF; cycle _ device status information. For the vectored interrupt, the low is exercised, but ignored. The internal state of the CPU isnot _byte is the jump vector, and the high byte can be extra user altered and the instruction will be refetched and executed status. For the segmentation trap, the high byte is the after the return from the interrupt routine. The program — Memory Management Unit identifier and the low byte is counter is not updated, but the system stack pointer is undefined. . decrementéd in preparation for pushing starting information A iz a . ter the acknowledge cycle, the N/S output indicates the onto the system stack, automatic change to system mode. The next machine cycle is the interrupt acknowledge cycle. . Saeed as ature ya artes ew bal 7 \\7 \\ yaw, sna = £ | . we T/ ES a ° | | . . wea | Figure 14, Interrupt and Segment Trap Request/Acknowledge Timing . i aS SSS : STATUS SAVING SEQUENCE : The machine cycles, following the interrupt acknowledge or —_ (28001/Z8005 only); the flag control word; and finally the H ‘segmentation trap acknowledge cycle, push the old status _interrupt/trap identifier. Subsequent machine cycles fetch information on the system stack in the following order: the the new program status from the program status area, and 16-bit program counter; the 7-bit segment number then branch to the interrupt/trap service routine. a 152 eee

ZILOG INC L7E D Me 9984043 0011904 7 gg tg | BUS REQUEST ACKNOWLEDGE TIMING 7 | A Low on the BUSREG input indicates to the CPU that high-impedance state. The requesting device—typically a another device is requesting the Address/Data and control. DMA--can then control the bus. buses. The asynchronous BUSREG input is synchronized , ; it th ey atthe beginning of any machine cycle Figure 18) BUSREQ When BUSREOis release, itis synchronized wth therising takes priory over WATE I BUSKEG Ie Lon, an intnal 8 edge; the BUSACK output goes High ono clock synchtonous SUSREQ signal Is generated. whishe aftr Period ater indicating thatthe CPU will again ake control of : Completion of the current machine cycle—causes the ebus. . BUSACK output to go Low and all bus outputs to go into the nh Te Ts i % i Tk . tk ik - clock co) a j | | . | . wasneg . Tp || _— . an — WES, Bs, 5, T Sirsa: ~-{----L--- bo. . Figure 15. Bus Request/Acknowledge Timing eee ; - 153

the EPA instruction, both EPA instruction words are fetched —_the CPU continues its operation. Figure 16. Stop Timing .

goes through a sequence of internal operation machine —_can be inserted at the end of any internal machine cycle. Figure 17. internal Operation Timing

IF; cycle or Internal Operation cycle). starting a refresh cycle is therefore not cumulative. (Figure 18). Since the memory is word-organized, Ag is using the refresh prescaler. Figure 18. Memory Refresh Timing .

1 Refresh is disabled first cycle reads the flag and control word from location

. L. . ANS , ! . | § ee

ZILOG INC “U2E D mm 9984043 0011909 6 i -49-17-07 COMPOSITE AC TIMING DIAGRAM 1-49-17 ws pi . : de Gy! eGo] this diagram only for the Fo={ Fox ped eis a <> -O=| -@- - Wo z sro [| Piers Tae: L@-iO-| High Low war l xl > Supt 20y By — GOT FOt per ay enea fT KT] oT = . 0; [=| Lo 2 euock : © © Le ; steam a EE NS i -- le Ke ed tt > oi ® ® , _ pete | ry ing © Hef M . eer eer | Leper je] F 7e © ote) | | ™ ai rete wouroureut if] Loa is -—— ® el 1 @ @ esses 9 oe _- scnhOWEDSE ® Lot aa sry:ar @ | : TER TS

ZILOG INC L?E D M@™ 9984043 0011910 2 = i AC CHARACTERISTICSt . T-49-17-07 | Zaoo112 Z8001/2 Za00112 4MHz 6MHz 40MHz Number Symbol Parameter Min’ Max = Min Max = Min Max

1 ToC Clock Cycle Time 260 2000 165 2000 100 2000

2 wh Clock Width (High) 105 _ 1895 70 1930 40 1960

3 Wel Clock Width (Low) 105 1895 70 1930 40 1960

4 Te ‘Clock Fall Time 20 10 10

5 TC Clock Rise Timo 7 20 15 10

6 TAC(SNv) —_—Clock t to Segment Number Valld (50 pfload) 130 110 90

7 TAC(SNn) —_—_Clockt to Segment Number Not Valid 20 10 0

8 — TdC(B2) Clock t to Bus Float 65 85 50 @ — TdC{A) Clock t to Address Valid 100 75 55

10 TdC(Az) Clock t to Address Float 65 6 50

11 TAA(DR) ‘Address Valid to Read Data Required Valid 475° + 305* 180*

12° TsDR(C) Read Data to Clock + Setup time 30 20 10 13° TdDS(A) DSt to Address Active . 80" 45" 20°

14 TdC(DW) Clock t to Write Data Valid 100 75 60

15 — ThOR(DS) Read Data to DS t Hold Time . 0 0 oO

16 TdDW(DS) — Write Data Valid to DSt Delay * 295° 195" 110"

17° TdA(MR) ‘Address Valid to MREQ # Delay 55° 35* 20° 18 © TdC(MR) Clock +o MEG t Delay 80 70 60

19 TwMRh MEQ Width (High) 210° 135* 8o*

TaMR(A) REG 4 to Address Not Active 7o* 35° 20° ,

21 TdDW(DSW) Write Data Valid to DS 4 (Write) Delay 65" 35 18° 1

. 22 TdMR(DR) MEQ | to Read Data Required Valid 370° - 230° 140° 23° TdC(MR) Clock | MREG t Delay 80 60 50

24 TACIAS Clock t to AS 4 Delay 80 60 45

25 © TAA(AS) ‘Address Valid to AS t Delay 55* as¢ 20¢ 26 © TAC{AS!) Clock + to AS t Delay 80 80 45 _ 27 TAAS(OR) RS t to Read Data Required Valid 360° 220° 140° ! } 28 = TADS(AS) DSt toAS# Delay 70* 35° 15° i . 29° WAS BS Width (Low) 85" 55° 30° . 30 TAAS(A) FS t to Address Not Active Délay 70* 45° 20"

31 TdAz(DSR) Address Float to DS (Read) + Delay ° ° 0

32 TdAS(DSR) AS to DS (Read) + Delay . 80* 55" 30°

33 TADSR(DR) —_DS (Read) #1o Read Data Required Valid 205* 130° 70"

34 TAC(OS1) Clock + to BS t Delay 70 65 50

35 = TdDS(OW) )~—BS t to Write Data Not Valid 75" 45° 25°

36 TdA(DSR) —_Address Valid to DS (Read) 4 Delay 180° 110" 65" i |

. 37 TdC{OSA) —_—Clock to DS (Read) 4 Delay 120 85 6 | 38 © TWwDSR BB (Read) Width (Low) 275" 185* 110"

39 TACIDSW) —Clock 410 DS (Write) + Delay 95 80 65

40° WwOsw DS (write) Width (Low) 185* 110" 75* 1 *Clock-cycle time-dependent characteristics, See Footnotes to AC Characteristics. | Units in nanoseconds (ns), | 159 . !

ZILOG INC VE D mm 9984043 0012921 4 mm SSS 7 AC CHARACTERISTICSt (Continued) 1-49-17-07 2001/2 Z800112 2800112 4MHz 6MHz 40MHz Number Symbot Parameter Min Mex = Min’ Max = Min. Max

41 TADSIDR) —_DB(V/0) 4 to Read Data Required Valid 330¢ 210" 120"

42 TdC(DS) Clock + to BS (VO) 4 Delay - 120 90 65

43° WS DS (VO) Width (Low) 410° 256" 160"

44 TAAS(DSA) —_ASt to D8 (Acknowledge) + Delay 1065* 690° 410° i

45 TdC(DSA) - Clock tto DS (Acknowledge) 4 Delay 120 85 70 .

46 TADSA(OR) —_DS (Acknowledge) 4 to Read Data Required

: Delay 455* 295* 165°

47 TACs) Clock t to Status Valid Delay 110 85 65

48 TdS(As) Status Valid to AS t Delay 50° 30° 20°

49 TsR(C) * RESET to Clock t Setup Time 180 70 50

50 THR(C) RESET to Clock t Hold Time 0 0 0 !

51 TwNMI- | NMI Width (Low) : 100 70 50 :

52 TsNMI(C) NMI to Clock t Setup Time 140 70 50 :

53 TsVi(C) Vi, NVito Clock t Setup Time 110 50 40

$4 ThViC) Wi, NVito Clock t Hold Time 20 20 10 55 — TsSGT(C) SEGT to Clock t Setup Time 7 . 55 40 $6 ThSGT(C) — SEGT to Clock t Hold Time ° ° ° .

57 TsMI(C) ~ Mi to Clock t Setup Time 180 140 80

58 ThMI(C) Mito Clock t Hold Time ° oO 0

59 TdC(MO) Clock tto MO Delay 120 85 80 |

60 TsSTP(C) STOP to Clock + Setup Time 140 100 50

61 —‘ThSTP(C) ‘STOP to Clock # Hold Time o . 0 0

62 TsW(C) WAT to Clock § Setup Time 50 30 20 :

63 ThW(C) WAIT to Clock # Hold Time 10 10 6

64 —TsBRQ(C) —_ BUSREO to Clock t Setup Time 90 80 60 65 = ThBRA(C) BUSRE to Clock t Hold Time 10 10 6 . 66 == TdC(BAKr) Clock t to BUSACK t Delay 100 75 65 :

67 TAC(BAKA) Clock t to BUSACK + Delay 100 75 65 j

68 TWA Address Valid Width 150° 95° 50*

69 TdDS(S) BS t to STATUS Not Valid 80° 85° 30° . “Clock-cycle time-dependent characteristics, See Footnotes to AC Characleristics. i {Units in nanoseconds (ns). | : ! 160 |

ZILOG INC AE Do 9984043 0011912 & ' FOOTNOTES TO AC CHARACTERISTICS T-49-17-07 . 2800112 Z8001/2 8001/2 4MHz 6 MHz . 10 MHz Number Symbol "Equation * Equation Equation W ‘TdA(OR) 2TcC + WwCh - 130ns 2TcC + TwCh - 95ns 2TcC + TwCh - 60ns 13 TdDS(A) ‘WC! - 25ns WC! ~ 25ns TwC! = 20ns

16 TdDW(DS) TeC + TwCh - 60ns ToC + TWwCh - 40ns TeC + TwCh ~ 30ns

7 TdA(MR) ‘TwCh ~ 50ns Woh - 35ns TwCh = 20ns

19 TWMRh TeC = 40ns ToC - 30ns ToC - 20ns °

. 20 TdMR(A) TWOl - 35 ns ‘TwO! - 35ns TwCl - 20ns

21 TdDW(DSW) ‘WCh - 50ns ‘WCh - 35ns WCh - 25ns

22 TdMR(DR) 2ToC ~ 130 As * 2TeC ~ 100ns 2TeC - 60ns

25 TdA(AS) WCh - 50ns WCh - 35ns ‘WCh - 20ns .

27 TdAS(DR) 2TcC - 140ns 2TcC - 110ns 2TcC - 60ns

28 . TdDS(AS) WC! - 35ns WCl - 35ns WC! - 25ns

29 TWAS TwCh ~ 20ns WwCh - 15ns WCh - 10ns

30 TdAS(A) * WwCl- 35ns WC - 25ns WC! - 20ns. 32 TdAS(DSR) WC! - 25ns wel -15ns WC - 10ns 33 TdDSR(DR) TeC + TwCh - 150ns TeC + TwCh ~ 105ns TeC + TwCh - 70ns .

35 TdDS(DW) WwCl - 30ns TwCl - 25ns WCl ~ 15ns

36 TdA(DSR) TeC ~ 70ns ToC - 55ns TcC = 35ns

38 TwDSR TcC + TwCh - 80ns ToC + TwCh - 50ns ToC + TwCh - 30ns

40 Twosw TeC - 65ns TeC ~ 55ns TeC - 25ns

4 TdDSK(DR) 2TcC ~ 170ns 2TcC - 120ns 2TcC = 80ns

43 TwOS: 2TcC ~ 90ns 2TeC - 75s 2TcC - 40ns

44 TdAS(DSA) 4TcC + TwCl - 40ns 4TcC + TwCl - 40ns . 4TcC + TwCl — 30ns.

46 TdDSA(DR) 2TcC + TwCh - 150ns 2TcC + TwCh ~ 105 ns 2TcC + TWCh - 75ns

48 TdS(AS) ‘WCh - 55ns WCh - 40ns wCh - 30ns

6B TwA TcC - 90ns TeC ~ 70ns TeC - 50ns

69 TdDS(s) Wl - 25ns WCl - 150s TwCl ~ 10ns

VoL = 0.8V Von = 2.0 Vi, = 0.8V Vay = 24V : Vac = 0.45V Vine = Voo-0.4V aa) ; |

ZILOG INC . L7E D M@ 9984043 0011913 8 mm T-49-17. ABSOLUTE MAXIMUM RATINGS 17-07 Voltages on all pins with respect ‘Stresses greater than those listed under Absolute Maximum Ratings may Operating Ambient ‘operation of the device at any condition above those indicated in the perating Ambient . ‘operational sections of thse specifications is not implied. Exposure to lo STANDARD TEST CONDITIONS The DC characteristics below apply for the following test uw | Conditions, unless otherwise noted. All voltages are 21K : referenced to GND (OV). Positive current flows into the ‘ teferenced pin. FUNDER TEST i Available operating temperature ranges are: . @ S = 0°Cto +70°C, +4.75V< Veo < +5,25V t00pt ne . 7 F All ac parameters assume a total load capacitance The Ordering Information section lists package temperature H (including parasitic capacitances) or 100 pf max, except for __ ranges and product numbers, . Parameter 6 (0 pf max). Timing references between two . . output signals assume a load difference of 50 pf max. DC CHARACTERISTICS a Symbol Parameter Min Max = Unit Condition . Vou Clock Input High Voltage Vec-04 Voc+0.3 V_ Driven by External Clock Generator Vou Clock Input Low Voltage -03 0.45 V_—_Driven by External Clock Generator Viq InputHigh Voltage : 2.0 Vog+0.3 v j ViH RESET Input High Voltage on RESET pin 24 Voc+0.3 v VinMt Input High Voltage on NMI pin 24 Voc+03 v OME Input Low Voltage -03 0.8 v Vou Output High Voltage 24 Volo = -250yA Vou Output Low Voltage 04 Vo lot = +2.0mA Me Input Leakage . £10 vA O.4SViys +2.4V . litse@T Input Leakage on SEGT pin -100 100 pA . lot Output Leakage +10 vA OARVNS +2.4V lec ‘Voc Power Supply Current 300 mA 4 MHz and 6 MHz commercial : 400 mA _ Extended temperature range 400 mA 10 MHzspeed range | | : | 162 SERRE I RR A RR

ZILOG INC 17E D m@ 9984043 0012311 7 a | PACKAGE INFORMATION T-A0-20 | s 2 | al : . wet \\ ue bis — 00 . - 18-Pin Ceramic Package : {SFaaows s . foren ate J 0.920 D eo ee re : TF Tce bs a | cit a.t00—+} tt . a ESET pai” He ‘i 18-Pin Plastic Package (NOTE: Package dimensions are given in inches, To convert to millimeters, multiply by 25.4 . TT . . red : . a e }-—— a ; Oo | | ei : i aoe Pee bs hatin rane NOTE: Peclage dwn re gia nna. Te convert unt, uly by 2.4. 561 |

° ZILOG INC 17E D Mm 9984043 0012312 97 PACKAGE INFORMATION (Continued) 7-10-20 ati 2 ant . us | IL rd “VS | ——w—- jrsmnaouss Sf ah AAT Rt RM 40-Pin Dual-in-Line Package (DIP), Cerdip | 0 a : Too i ) > | SS | 37 ! fi | eae : L : en RS) i il SAAR AR ARARAR cto opp ! i AOE +3884 gag] Leas —ih-ge 1 basis es 40-Pin Dual-in-Line Package (DIP), ' Plastic . : . | i i NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. i

. ZILOG INC : L7E D M@ 9984043 0012313 0 mm | PACKAGE INFORMATION (Continued) 40-2 . 40 7 2 | | . pies pene eee! mT { : ! want ews | iwenriricaTon v_te 7 a - ~ se - - uae et ee a eS 4 ba fede ut We . Ta . 40-Pin Dual-in-Line Package (DIP), Ceramic ' i "i x a 7 falvisivin vivwlriv van ' boa he te 8 q aie sy a F | 438) 6 # . UP isereeereet dt QeAnnnnnnngy S ovens 44-Pin Plastic Chip Carrler (PCC) | eee . 563 i

. ZILOG INC 1?7E DD M@@ 9984043 0012314 2 mm EE PACKAGE INFORMATION (Continued) T-90-260 nn ne : : ras | | woes] SG cd : one roi bra pe} “ie Lge al gig | =! L288 somenos aS rs ee 3 . 48-Pin Dual-in-Line Package (DIP), . Ceramic eB ; ; piasassennnnnaaaaaannanal abs NCAACATATATEVAYATATATATATACATATATATA" AA AAR fb —— See aso comenunbtti > Tt Eee EER oats SARA AAA TRAY a 48-Pin Dual-in-Line Package (DIP), Plastic a 564

errr ee aaa ke_e_E:seEeewSEeEeEeEeErOororEOorereorreeee—e—e—eEOV ZILOG INC 17E D M@ 9984043 0012315 4 a | PACKAGE INFORMATION (Continued) 90 “20 avncouumn [800 -BBlncanon — <te xeeunuae wont =F § b q 0.9520 ‘edu : q b | osteo | . - ij toon 45" xooromax * [| ont : [ess . : 68-Pin Plastic Chip Carrier (PCC) a wey 2.788 ®. QVOOOOOOOOS—-. x ae fofofoKoxotoxoxoxoforoxores 00 —_—— fof) 1oKo} | OO foFoR| 1o%O} . 1oXO) QO} 1.000 oo ool a0 : eo} foXo} Pc LoXO} LOKO} » te 100 | oo] He 00 ———" 08 9900000000006. 900000000067 st. sr conkEa 128 te : ee : 84-Pin Grid Array (PGA), View toward PC Board

5 Bottom View

| 'NOTE: Package dimensions are givenin inches. To corwert to milimeters, multiply by 25.4 ) — . 565

Product Information

Z8000 specifications and overview.

Summary

CPU Central Processing Unit

Description

CPU Central Processing Unit

Source title Z8000 Datasheet(PDF) - Zilog, Inc.

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