Z80

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ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue  Campbell, CA 95008 User Manual UM008101-0601 Z80 Family CPU Peripherals

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG .com Windows is a registered trademark of Microsoft Corporation. Document Disclaimer ©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT . ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

UM008101-0601 Table of Contents iii Table of Contents Counter/Timer Channels

UM008101-0601 Table of Contents iv Direct Memory Access

Table of Contents UM008101-0601 v Direct Memory Access (continued) Parallel Input/Output

UM008101-0601 Table of Contents vi Parallel Input/Output (continued) Serial Input/Output

Table of Contents UM008101-0601 vii Serial Input/Output (continued)

UM008101-0601 Table of Contents viii

Table 8. Maximum Transfer and Search Speeds (Burst and Continuous Table 9. Reduction in Z80 CPU Throughput per Kbaud Table 11. Contents of Counters After DMA Stops Because of End-of- Table 12. Contents of Counters After DMA Stops Due to Byte Match

Table 22. Contents of Write Registers 3, 4, and 5 in Asynchronous Table 24. Contents of Write Registers 3, 4, and 6 In Table 27. Contents of Write Registers 3, 4, and 5 in SDLC Modes 258

UM008101-0601 List of Tables xviii

/G3c /G1a/G12/G2/G25/G32 /G37/G2/G32 /G47/G54 /G4b/G52 /G4a/G47 /G54/G43 /G4e/G55 /G37 /G55 /G47/G54 /G2/G2f/G43/G50 /G57 /G43/G4e UM008101-0601 Counter/Timer Channels /G13 Counter/Timer Channels CTC FEATURES

• Four independently programmable counter/timer channels (CTC), each with a readable down-counter and a selectable 16 or 256 prescaler. Down-counters are reloaded automatically at zero count  Selectable positive or negative trigger initiates timer operation  Three channels have zero count/timeout outputs capable of driving Darlington transistors  NMOS version for high-cost performance solutions  CMOS version for the designs requiring low power consumption  NMOS Z0843004 - 4 MHz, Z0843006 - 6.17 MHz  CMOS Z84C3006 - dc to 6.17 MHz, Z84C3008 dc to 8 MHz, Z84C3010 - dc to 10 MHz  Interfaces directly to the Z80 CPU. Interfaces to the Z80 SIO for baud rate generation  Standard Z80 Family daisy-chain interrupt structure provides fully vectored, prioritized interrupts without external logic. The CTC may also be used as an interrupt controller  A 6 MHz version supports 6.144 MHz CPU clock operation CTC General Description The Z80 CTC is a four-channel counter/timer that can be programmed by system software for a broad range of counting and timing applications. These four independently programmable channels satisfy common

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G14 microcomputer system requirements for event counting, interrupt and interval timing, and general clock rate generation. System design is simplified by connecting the CTC directly to both the Z80 CPU and the Z80 SIO with no additional logic. In larger systems, address decoders and buffers may be required. The CTC allows easy programming: each channel is programmed with two bytes; a third is necessary when interrupts are enabled. When started, the CTC counts down, automatically reloads its lime constant, and resumes counting. Software timing loops are eliminated. Interrupt processing is simplified because only one vector needs to be specified; the CTC internally generates a unique vector for each channel. The Z80 CTC requires a single +5V power supply and the standard Z80 single-phase system clock. It is packaged in 28-pin DIPs, a 44-pin plastic chip carrier, and a 44-pin Quad Flat Pack. The QFP package is only available for CMOS versions. CTC ARCHITECTURE Overview The internal structure of the Z80 CTC consists of:  A Z80 CPU bus interface, internal control logic  Four sets of Counter/Timer Channel logic  Interrupt control logic The four independent, counter/timer channels are identified by sequential numbers from 0 to 3. The CTC can generate a unique interrupt vector for each separate channel for automatic vectoring to an interrupt service routine. The four channels can be connected in four contiguous slots in the standard Z80 priority chain with channel number 0 having the highest

diagram of the Z80 CTC is depicted in Figure 1. Figure 1. CTC Block Diagram down-counter and an 8-bit prescaler.

CPU address bus. The channel values are described in Table 1. Operating Modes” on page 16 and “CTC Programming” on page 18). Figure 2. Channel Block Diagram Table 1. Channel Values

Table 2. Channel Control Register

7 Interrupt R/W 1

5 Prescaler Value* R/W 1

4 CLK/TRG Edge

3 Time Trigger* R/W 1

2 Time Constant R/W 1

1 Reset R/W 1

0 Control or Vector R/W 1

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G18 the down-counter counts to zero, the down-counter is automatically reloaded with the contents of the Time Constant register. This process divides the System clock by an additional factor of the time constant. Each time the down-counter counts to zero, its output, Zero Count/Timeout (ZC/ TO), is pulsed High. The Time Constant Register The 8-bit Time Constant register is used in both Counter and Timer modes. It is programmed by the CPU just after the channel control word, with an integer time constant value of 1 through 256. This register loads the programmed value to the down-counter when the CTC is first initialized and reloads the same value into the down-counter automatically whenever it counts down thereafter to zero. If a new time constant is loaded into the Time Constant register while a channel is counting or timing, the present down count is completed before the new time constant is loaded into the down counter. For details about writing a time constant to a CTC channel, see “CTC Programming” on page 18 The Down-Counter The down-counter is an 8-bit register that is used in both COUNTER and TIMER modes. This register is loaded by the Time Constant register both initially, and when it counts down to zero. In the COUNTER mode, the down-counter is decremented by each external clock edge. In the TIMER mode, it is decremented by the clock output of the prescaler. By performing a simple I/O Read at the port address assigned to the selected CTC channel, the CPU can access the contents of the down-counter and obtain the number of counts-to-zero. Any of the four CTC channels may be programmed to generate an interrupt request sequence each time the zero count is reached. In Channels 0, 1, and 2, a signal pulse appears at the corresponding ZC/TO pin when the zero count condition is reached. Because of package pin limitations, however, Channel 3 does not have this pin and so may be used only in applications where this output pulse is not required.

interrupt the servicing of lower priority devices or channels. Table 3. Interrupt Vector Register

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G1a A CTC channel may be programmed to request an interrupt every time its down-counter reaches a count of zero. However, using this feature requires that the CPU be in INTERRUPT Mode 2. After the interrupt request, the CPU sends out an interrupt acknowledge. The CTC’s interrupt control logic determines the highest-priority channel requesting an interrupt. If the CTC’s IEI input is active, indicating that it has priority within the system daisy-chain, it places an 8-bit interrupt vector on the system data bus as follows: 1. The high order five bits of this vector were written to the CTC earlier as part of the CTC initial programming process. 2. The next two bits are provided by the CTC’s interrupt control logic as a binary code corresponding to the highest-priority channel requesting an interrupt. 3. The low-order bit of the vector is always zero according to a convention (Figure 3). This interrupt vector is used to form a pointer to a location in memory where the address of the interrupt service routine is stored in a table. The vector represents the least-significant eight bits. The CPU reads the contents of the I register to provide the most-significant eight bits of the 16-bit pointer. The address pointed to in memory contains the low-order byte and the next highest address contains the high-order byte of an address, which in turn contains the first Op Code of the interrupt service routine. Thus, in Mode 2, a single 8-bit vector stored in an interrupting CTC can result in an indirect call to any memory location (Figure 3). Figure 3. Z80 16-Bit Pointer (Interrupt Starting Address)

Contents

Z80 16-Bit Pointer (Interrupt Starting Address)

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Counter/Timer Channels /G1b According to Z80 system convention, all addresses in the interrupt service routine table place their low-order byte in an even location in memory, and their high-order byte in the next highest location in memory. This location is always odd so that the least-significant bit of any interrupt vector is always even. Therefore, the least-significant bit of any interrupt vector always zero. The RETI instruction is used at the end of an Interrupt Service Routine to initialize the Daisy Chain Enable line IEO for control of nested priority interrupt handling. The CTC monitors the system data bus and decodes this instruction when it occurs. Therefore, the CTC channel control logic knows when the CPU has completed servicing an interrupt. CTC PIN DESCRIPTION Pin Functions Diagrams of the Z80 CTC Pin Configuration and Z80 CTC Package Configuration are illustrated in Figure 4 through Figure 7, respectively. This section describes the function of each pin.

Figure 6. 44-Pin Chip Carrier Pin Assignments

Figure 7. 44-Pin Quad Flat Pack Pin Assignments W r i t eo rR e a d .( S e eT a b l e4 ) .

mapped to the four Counter/Timer channels. internally synchronize certain signals. Table 4. Channel Select Truth Table

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G13/G16 IORQ Input/Output Request from CPU (input, active Low). The IORQ signal is used in conjunction with the CE and RD signals to transfer data and channel control words between the Z80 CPU and the CTC. During a CTC Write cycle, IORQ and CE must be true and RD false. The CTC does not receive a specific write signal. Instead it generates one internally from the inverse of a valid RD signal. In a CTC Read cycle, IORQ,C E,a n dR D must be active to place the contents of the down-counter on the Z80 data bus. If IORQ and M1 are both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on the Z80 data bus. RD Read Cycle Status from the CPU (input, active Low). The RD signal is used in conjunction with the IORQ and CE signals to transfer data and channel control words between the Z80 CPU and the CTC. During a CTC Write Cycle, IORQ and CE must be true and RD false. The CTC does not receive a specific write signal, instead it generates one internally from the inverse of a valid RD signal. In a CTC Read cycle, IORQCE,a n dR Dmust be active to place the contents of the down-counter on the Z80 data bus. IEI Interrupt Enable In (input, active High). This signal is used to form a system-wide interrupt daisy-chain which establishes priorities when more than one peripheral device in the system has interrupting capability. A High level on this pin indicates that no other interrupting devices of higher priority in the daisy chain are being serviced by the Z80 CPU. IEO Interrupt Enable Out (output, active High. The IEO signal, in conjunction with IEI, is used to form a system-wide interrupt priority daisy-chain. IEO is High only if IEI is High and the CPU is not servicing

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Counter/Timer Channels /G13/G17 an interrupt from any CTC channel. Therefore, this signal blocks lower- priority devices from interrupting while a higher-priority interrupting device is being serviced by the CPU. INT Interrupt Request (output, open-drain, active Low). This signal goes true when a CTC channel, which has been programmed to enable interrupts, has a zero-count condition in its down-counter. RESET Reset (input, active Low). This signal stops all channels from counting and resets interrupt enable bits in all control registers, thereby disabling CTC-generated interrupts. The ZC/TO and INT outputs go inactive, IEO reflects IEI, and the CTC’s data bus output drivers go to the high- impedance state. CLK/TRG3–CLK/TRG0 External Clock/Timer Trigger (input, user-selectable active High or Low). Four CLK/TRG pins correspond to the four independent CTC channels. In the Counter mode, every active edge on this pin decrements the down-counter. In the TIMER mode, an active edge on this pin initiates the timing function. The user may select the active edge to be either rising or falling. ZC/TO2-AC/TO0 Zero Count/Timeout (output, active High). Three ZC/TO pins correspond to CTC Channels 2 through 0. (Because of package pin limitations Channel 3 has no ZC/TO pin.) In either COUNTER mode or TIMER mode, when the down-counter decrements to zero, an active High pulse appears at this pin.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G13/G18 CTC OPERATING MODES Overview At power-on, the Z80 CTC state is undefined. Asserting RESET puts the CTC in a known state. Before a channel can begin counting or timing, a channel control word and a time constant data word must be written to the appropriate registers of that channel. Additionally, if a channel has been programmed to enable interrupts, an interrupt vector word must be written to the CTC’s interrupt control logic. (For further details, refer the “CTC Programming” on page 18) When the CPU has written all of these words to the CTC, all active channels are programmed for immediate operation in either the COUNTER mode or the TIMER mode. CTC COUNTER Mode In CTC COUNTER mode, the CTC counts edges of the CLK/TRG input. This mode is programmed for a channel when its Channel Control Word is written with bit 6 set. The channel’s external clock (CLK/TRG) input is monitored for a series of triggering edges. After each, in synchronization with the next rising edge ofΦ (the System clock), the down-counter (which is initialized with the Time Constant Data word at the start of each sequence of down-counting) is decremented. Although there is no setup time requirement between the triggering edge of the External clock and the rising edge of Φ (Clock), the down-counter is not decremented until the following pulse. A channel’s External clock input is pre programmed by bit 4 of the channel control word to trigger the decrementing sequence with either a high- or a low-going edge. In Channels 0, 1, or 2, when the down-counter is successively decremented from the original time constant (until it reaches zero), the Zero Count (ZC/ TO) output pin for that channel is pulsed active (High). Due to package pin limitations, this pin does not exist on Channel 3 and so this pin may only be

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Counter/Timer Channels /G13/G19 used in applications where this output pulse is not required. Additionally, if the channel is pre-programmed by bit 7 of the channel control word, an interrupt request sequence is generated. For more details, see the CTC Interrupt Servicing section The zero-count condition also results in the automatic reload of the down- counter with the original time constant data word in the Time Constant register. There is no interruption in the sequence of continued down- counting. If the Time Constant register is written with a new Time Constant Data Word while the down-counter is decrementing, the present count is completed before the new time constant is loaded into the down-counter. CTC TIMER Mode In CTC TIMER mode, the CTC generates timing intervals that are an integer value of the system clock period. This mode is programmed for a channel when its Channel Control Word is written with bit 6 reset. The channel then may be used to measure intervals of time based on the System clock period. The System clock is fed through the prescaler and the down- counter. Depending on the pre programmed bit 5 in the Channel Control Word, the prescaler divides the System clock by a factor of 16 or 256. The output of the prescaler is then used as a clock to decrement the down- counter, which may be pre programmed with any time constant integer between 1 and 256. The time constant is automatically reloaded into the down-counter at each zero-counter condition. At zero count, the channel’s Time Cut (ZC/TO) output (which is the output of the down-counter) is pulsed, resulting in a uniform pulse train of the precise period given by the product as shown below. /G56 /G45 /G2/Gc/G32 /G2/Gc/G36/G25 Where tc is the System clock, P is the prescaler factor of 16 or 256, and TC is the pre-programmed time constant.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G13/G1a Timing may be initialized automatically or with a triggering edge at the channel’s Timer Trigger (CLK/TRG) input. This timing is determined by programming bit 3 of the channel control word. If bit 3 is reset?, the timer automatically begins operation at the start of the CPU cycle following the I/ O Write machine cycle that loads the time constant data word to the channel. If bit 3 is set, the timer begins operation on the second succeeding rising edge of Φ after the Timer Trigger edge following the loading of the time constant data word. If no time constant word is to follow, the timer begins operation on the second succeeding rising edge of Φ after the Timer Trigger edge and following the control word write cycle. Bit 4 of the channel control word is pre programmed to select whether the Timer Trigger is sensitive to a rising or falling edge. There is no setup requirement between the active edge of the Timer Trigger and the next rising edge ofΦ. If the Timer Trigger edge occurs closer than a specified minimum setup time to the rising edge ofΦ, the down-counter does not begin decrementing until the following rising edge of Φ. If bit 7 in the channel control word is set, the zero-count condition in the down-counter causes a pulse at the channel’s Time Out pin, and initiates an interrupt request sequence. (For more details, see “CTC Interrupt Servicing” on page 27). CTC PROGRAMMING Overview To begin counting or timing operations, a Channel Control Word and Time Constant Data Word are written to the appropriate channel by the CPU. These words are stored in the Channel Control or Time Constant registers of each channel. If a channel has been programmed to enable interrupts, an interrupt vector is written to the appropriate register in the CTC. Because of

interrupt vector suffices for all four channels. modes and conditions as indicated in Table 2. Table 5. Channel Control Register

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G14/G12 Bit 7 = 1.Each channel is enabled to generate an interrupt request sequence when the down-counter reaches a zero-count condition. To set the interrupt bit to 1 in any of the four Channel Control registers an interrupt vector is written to the CTC before operation begins. Channel interrupts may be programmed in either Counter or Timer mode. If an updated channel control word is written to a channel in operation, with bit 7 set, the interrupt enable selection is not retroactive to a preceding zero-count condition. Bit 7 = 0. Channel interrupts disabled. Bit 6 = 1. Counter mode selected. The down-counter is decremented by each triggering edge of the External clock (CLK/TRG) input. The prescaler is not used. Bit 6 = 0. Timer mode selected. The prescaler is clocked by the System clock Φ, and the output of the prescaler in turn clocks the down-counter. The output of the down-counter (the channel’s ZC/TO output) is a uniform pulse train of period given by the product as shown below /G56 /G45 /Gc /G32/Gc/G36/G25 CLK/TRG Pulse Starts Timer Automatic trigger when time constant is loaded Number Field R/W Value Description *TIMER mode only

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Counter/Timer Channels /G14/G13 where tc is the period of System clock, P is the prescaler factor of 16 or 256, and TC is the time constant data word. Bit 5 = 1. Defined for Timer mode only. Prescaler factor is 256. Bit 5 = 0. Defined for Timer mode only. Prescaler factor is 16. Bit 4 = 1. TIMER Mode: positive edge trigger starts timer operation. COUNTER Mode: positive edge decrements the down-counter. Bit 4 = 0. TIMER Mode: negative edge trigger starts timer operation. COUNTER Mode: negative edge decrements the down-counter. Bit 3 = 1. TIMER Mode only. External trigger is valid for starting timer operation after rising edge of T2 of the machine cycle following the one that loads the tune constant. The prescaler is decremented two clock cycles later if the setup tune is met, otherwise three clock cycles. Bit 3 = 0. TIMER Mode only. Timer begins operation on the rising edge of T2 of the machine cycle following the one that loads the time constant. Bit 2 = 1. The time constant data word for the Time Constant register is the next word written to this channel. If an updated channel control word and time constant data word are written to a channel while it, is already in operation, the down-counter continues decrementing to zero before the new time constant is loaded. Bit 2 = 0. No time constant date word for the Time Constant register is to follow. The channel control word updates the status of a channel already in operation to channel will not operate without a correctly programmed data word in the lime Constant register. Bit 2 in the channel control word must be set in order to write to the Time Constant register. Bit 1 = 1.Counting and/or timing operation is terminated and the channel is reset. This is not a stored condition. The bits in the Channel Control register are unchanged. If bits 1 and 2 are set to 1, the channel resumes operation upon loading a time constant. Bit 1 = 0. Channel continues current operation.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G14/G14 Loading The Time Constant Register A Time Constant Data Word is written to the Time Constant register by the CPU. This event occurs on the I/O Write Cycle following that of the channel control word. The Time Constant Data Word may be any integer value in the range 1-256 (Table 6). If all eight bits in this word are zero, it is interpreted as 256. If a Time Constant Date Word is loaded to a channel already in operation, the down-counter continues decrementing to zero before the new time constant is loaded. Loading The Interrupt Vector Register The Z80 CTC operates with the Z80 CPU programmed for mode 2 interrupt response. When a CTC interrupt request is acknowledged, a 16-bit pointer is formed to obtain a corresponding interrupt service routine starting address (Figure 8). The upper eight bits of this pointer are provided by the CPU’s I register; the lower eight bits are provided by the CTC in the form of an interrupt vector unique to the requesting channel (Figure 8). For further details, see “CTC Interrupt Servicing” on page 27. The five high-order bits of the interrupt vector are written to the CTC in advance as part of the initial programming sequence. The CPU writes to the I/O port address corresponding to the CTC Channel 0. A 0 in bit 0 signals the CTC to load the incoming word into the interrupt vector register. When the interrupt vector is placed on the Z80 data bus, the interrupt control logic of the CTC automatically supplies a binary code in bits 1 and 2 identifying which of the four CTC channels is to be serviced. T a b l e6 .T i m eC o n s t a n tR e g i s t e r 76543210 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 R/W R/W R/W R/W R/W R/W R/W R/W

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Counter/Timer Channels /G14/G15 Figure 8. Mode 2 Interrupt Operation Table 7. Interrupt Vector Register

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G14/G16 CTC TIMING Overview This section describes the timing relationships of the relevant CTC pins for the following types of operation:  Writing a word to the CTC  Reading a word from the CTC  Counting and timing A timing diagram, Figure 12, relating to interrupt servicing is found in “Interrupt Acknowledge Cycle” on page 28. CTC Write Cycle Figure 9 illustrates the timing associated with the CTC Write cycle. This sequence is applicable to loading a channel control word, an interrupt vector, or a time constant data word. In the sequence shown, during clock cycle T1, the Z80 CPU prepares for the Write cycle with a false (High) signal at CTC input pin RD (Read). Because the CTC has no separate Write signal input, it generates its own input internally from the false RD input. During clock cycle T2, the Z80 CPU initiates the Write cycle with true (Low) signals at CTC input pins IORQ (I/O Request) and CE (Chip Enable). (See Note below.) A 2-bit binary code appears at CTC inputs CS1 and CS0 (Channel Select 1 and 0), specifying which of the four CTC channels is being written to. At this time, a channel control, interrupt vector, or time constant data word may be loaded to the appropriate CTC internal register in synchronization with the rising edge beginning clock cycle T3. must be false to distinguish the cycle from an interrupt acknowledge. Note:

required between the active edge of the CLK/TRG and the rising edge ofΦ. function will be delayed one cycle of Φ. Figure 11. CTC Counting and Timing channel. For further details, refer to the Z80 CPU User’s Manual.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G14/G1a The CTC’s interrupt control logic ensures that it acts in accordance with Z80 system interrupt protocol for nested priority interrupt and proper return from interrupt. The priority of any system device is determined by its physical location in a daisy-chain configuration. Two signal lines (IEI and IEO) are provided in the CTC to form the system daisy chain. The device closest to the CPU has the highest priority. Interrupt priority is predetermined by channel number, with Channel 0 having highest priority. According to Z80 system interrupt protocol, low priority devices or channels may not interrupt higher priority devices or channels that have not had their interrupt service routines completed. High priority devices or channels may interrupt the servicing of lower priority devices or channels. (For further details, see “CTC Architecture” on page 2.) “Return from Interrupt Cycle” on page 29 and “Daisy-Chain Interrupt Servicing” on page 30 describe the nominal timing relationships of the relevant CTC pins for the Interrupt Acknowledge cycle and the Return from Interrupt cycle. “Daisy-Chain Interrupt Servicing” on page 30 discusses a typical example of daisy-chain interrupt servicing. Interrupt Acknowledge Cycle Figure 12 illustrates the timing associated with the Interrupt Acknowledge cycle. After an interrupt is requested by the CTC, the CPU sends out an interrupt acknowledge (M1 and IORQ). To insure that the daisy-chain enable lines stabilize, channels are inhibited from changing their interrupt request status when M1 is active. M1 is active two clock cycles earlier than IORQ and RD is false to distinguish the cycle from an instruction fetch. During this time, the interrupt logic of the CTC determines the highest priority channel requesting an interrupt. If the CTC Interrupt Enable input (IEI) is active, the highest priority interrupting channel within the CTC places its interrupt vector onto the data bus when IORQ goes active. Two Wait States (TW*) are automatically inserted at this time to allow the daisy- chain to stabilize. Additional Wait States may be added.

Figure 14. Daisy-Chain Interrupt Servicing

1. Second ‘RETI’ instruction issued on completion of Channel 2 Service Routine.
2. Channel 1 service routine complete, ‘RETI’ issued, Channel 2 serviced resumed.
3. Channel 1 interrupts, suspends servicing of Channel 2.
4. Channel 2 requests an interrupt and is acknowledged.
5. Priority interrupt daisy chain before any interrupt occurs.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Counter/Timer Channels /G15/G14

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G15/G15 Direct Memory Access DMA OVERVIEW Direct Memory Access (DMA) and DMA Controllers are dedicated to controlling high-speed block transfers of data independently of the CPU. DMA data transfers are usually between memory and I/O, or vice versa. A DMA controller (DMAC) also performs some transfers that have tradi- tionally been done by the CPU. For example, the Z80 DMA can perform memory-to-memory, memory-to-I/O, and I/O-to-memory transfers, as well as search for particular patterns of bits in a byte either simulta- neously with or independently of transfers. The advantages of DMA transfers are:  Transfers bypass the CPU  Transfers are fast CPU Data Transfers In systems without DMA, data transfers must pass through the CPU and be implemented in software. Data transfers through the CPU include executing an instruction sequence for input and output, and tracking each byte of data in the block to be transferred. Figure 15 illustrates the minimum sequence of instructions that must be fetched from memory and executed by conventional CPUs to transfer a block of data one byte at a time. Most CPUs require many more instructions. CPU transfers are relatively slow and tie up the CPU. In addition response time (startup time for the first byte) is also usually slow because the I/O device typically uses interrupts to signal its readiness, and the CPU interrupt service routine causes a significant time lag in transferring the first byte.

Figure 15. Typical CPU I/O Sequence 200 Kbytes/sec and the 4 MHz Z8000 CPU can reach 800 Kbytes/sec.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G15/G17  The I/O device interrupts the CPU and the block transfer instruction is executed in the CPU interrupt service routine. This method has a response time of at least 5 to 10 µs, even in 4 MHz Z80A and Z8000 devices.  The CPU begins executing the device service routine before the I/O device is ready, and a flag bit is constantly polled by the CPU. When the flag bit indicates that the device is ready, the CPU jumps to the block transfer instruction. This method sometimes produces a response time of less than 5 µs, but it uses the entire capability of the CPU.  The CPU begins executing the block transfer instruction in an interrupt service routine before the I/O device is actually ready. The I/O device idles the CPU with the Wait line just after the Read and Chip-Select lines become active. When the I/O device is ready, it releases the wait line and the transfer is completed. This method gives the best response time (250 ns in a 4 MHz Z80A or Z8000 CPU) but ties up the bus. Both transfer and response times on most CPUs are often too slow. While transfer speed can be quite high with the Z80 and Z8000 CPUs, the response time can be too long in interrupt-driven transfer situations. DMA Data Transfers A DMA controller (DMAC) performs direct data transfers between the source and destination without going through the CPU, and without the instruction fetches required by the CPU. It performs all of the steps illus- trated in Figure 15 through hardware. for example, in a memory-to-I/O transfer, the starting address in memory and the length of the block to be transferred are written to the DMA by the CPU before to the transfer. The DMAC begins transferring data when the C P Ue n a b l e st h eD M A Ca n dt h eR e a d yl i n eI / Oo ft h ed e v i c eb e c o m e s active. In most cases, the CPU is idle during a DMA transfer. When the transfer is complete, the DMAC signals the CPU and releases control.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G15/G18 DMACs are used when one or more of the following situations or require- ments are present:  CPU has too much I/O and cannot perform other tasks properly  Data transfer must be faster than the CPU can perform  Transfer response tune (startup) must be faster than the CPU can provide Small and low-performance systems generally run without DMA. Medium-performance systems can also be designed without DMA if the CPU can handle transfers fast enough and still perform other operations. When systems require fast transfers or fast response, DMACs are strong candidates for performance enhancement. Not only do DMACs transfer faster than most CPUs, but the response time is better. Response times can even be improved using the techniques described above for CPU response. The following examples are cases in which DMA is usually the best choice:  Disk and diskette controllers  Scanning operations, such as CRT I/O  Data acquisition  Memory-to-memory transfers  Memory searches  Backup storage (I/O-to-I/O)  Parallel bus systems such as the IEEE 488  Fiber optic links  Block transfers in networking, multiprocessing, or multiprogramming The trade-off for speed is that the CPU typically remains idle and lacks full or partial control of the system bus while the DMA is operating. This condition can affect total system throughput, and can also affect such things as memory refresh and other interrupts.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G15/G19 DMA Characteristics All DMACs are programmable because the CPU must at least write a block length (byte count) and starting memory address to a DMAC before they can begin managing a data transfer. The starting address is incre- mented or decremented as the transfer proceeds, and the byte counter is incremented from zero up to the specified block length. In addition to being programmable, DMACs vary in characteristics and capabilities. Ports and Channels Every data transfer has a source and a destination. For example, in memory-to-I/O transfers, memory is the source and I/O is the destination port. The means of controlling and tracking the data exchange between the two ports is called a channel. A channel includes the hardware for address and byte counting, bus control, and coordination of the entire transfer process. The location for each source and destination for a channel is specified either by the DMA address-generation mechanism or by hardwiring. The Z80 DMA generates addresses for both memory and I/O ports during each byte transfer. Some DMACs have multiple channels, which means that they can keep track of multiple interleaved transfers, and that one DMA can be hardwired to multiple I/O devices. However, because any DMA can execute only one read and/or write cycle at a time, multiple channels do not mean higher throughput than single channels in a given speed. The Z80 DMA is a single-channel device that can generate addresses to perform memory-to- memory data transfers. I/O port addresses on the address bus. The Z80 DMA can also perform internal byte searches. When the Z80 DMA loads bytes to an internal DMAC register during transfers, the result is that, when a byte is loaded, it can be compared with a maskable control byte.

implications when making the trade-off for higher DMA transfer speed. Figure 16. Conceptual Comparison of Various I/O Transfer Methods

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G16/G12 Modes of Operation Within each of the methods illustrated in Figure 16c and Figure 16d there are up to three modes of operation. These are termed Byte, Burst, and Continuous modes in this manual, although they are also sometimes referred to as Single, Demand, and Block modes. Figure 17 illustrates the typical sequence of events for each mode, when the I/O device’s Ready signal to the DMAC becomes active and before the DMA process reaches an end-of-block or other terminating condition. (These figures are expanded in Figure 20 through Figure 23.) In Byte mode, the DMAC transfers only one byte at a time while the I/O device Ready line is active. Control of the system bus is released back to the CPU between each byte. The CPU can then interleave its other activ- ities, until the DMA makes a new request to the CPU for system bus control before transferring the next byte. Byte mode is related to the transparent method of transfer in that both cause interleaving of CPU and DMA func- tions. The Byte mode, however, includes the protocol of requesting and releasing the bus for each byte transfer. In Burst mode, which is the most common mode, the DMAC continues to transfer bytes after gaining control of the system bus until the I/O device Ready line goes inactive. During this time, the CPU typically remains idle. When the Ready line goes inactive, the DMAC releases system bus control back to the CPU. In Continuous mode, the DMAC holds the system bus until the entire block of data has been transferred. If the I/O device Ready line goes inactive before the block is completely transferred, the DMAC waits until it becomes active again, but the system bus is not released as in Burst mode. The Continuous mode is the fastest mode because it has the least response- time overhead when the Ready line momentarily goes inactive and returns active again. However, this mode does not allow any CPU activity for the duration of the transfer.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G16/G13 Bus Control Most DMACs do not control the system bus in the same way that a CPU controls it. For example, many DMACs do not have a straightforward interface to the system data bus but rather multiplex a portion of the memory address onto the data bus, from which it must be latched by external logic. Nor do most DMACs generate all of the bus control signals that the CPU generates, and therefore they lack some degree of bus control when they operate. The Z80 DMA is unique among 8-bit DMACs because it generates exactly the same bus control signals for read and write cycles that the Z80 CPU does, and also because it has exactly the same logical and electrical interface to the data and address buses as the CPU. This means the other system components cannot discern the difference between the Z80 DMA and CPU; control by these devices is totally interchangeable. In the sequential DMA transfer method (a read cycle followed by a write cycle), it also means that the Z80 DMA pins can be tied directly to the corre- sponding Z80 CPU pins without any of the external interfacing logic that some DMACs require. This property considerably simplifies design and lowers part counts. Programmability How a DMAC starts, transfers data, and stops is determined by control information written to the DMAC by the CPU prior to the transfer. Status registers, which can be read by the CPU to determine the transfer condition after the DMAC stops transferring, are also typically provided. The degree of programmability is directly related to the DMACs flexibility in handling a variety of transfer tasks. Most DMACs are limited in their programmability. The Z80 DMA, by contrast, has over 140 bits of control information used to tailor the device (and retailor it between operations) for a wide variety of tasks and environments.

slower than the standard Z80 Family timing. w h i c ht ol a u n c ham o r ed e t a i l e dd i s c u s s i o no ft h eZ 8 0D M A . (See also Figure 20 through Figure 23). Figure 17. Modes of Operation

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G16/G15 DMA FUNCTIONAL DESCRIPTION

Features

 Single Highly Versatile Channel  Dual Port Address Generation with Incrementing, Decrementing, or Fixed Address in Both Ports  Buffered Address and Block-Length Registers  64 Kbyte Maximum Block Length  2.4 or 4 MHz Clock Rates (Z80 or Z80A DMA)  1.25 or 2 MB/s Data Rate (Z80 or Z80A DMA)  Transfer, Search, or Transfer/Search Operations  Bit-Maskable Byte Searching  Sequential (Flow-Through) or Simultaneous (Flyby) Transfers  Compatible with Z80 and Many Other CPUs  Byte, Burst, and Continuous Modes  Auto Restart Capability  Variable Cycle Timing  Wait-Line Cycle Extension  Internally Modifiable Interrupt Vectors  Programmable Interrupts on Ready, End-of-Block, Byte Match  Hardware Priority Daisy-Chains for Bus Requests and Interrupts  Periodic Pulse Generation for External Device  21 Writeable Control Registers  Seven Readable Status Registers

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G16/G16  Programmable Force Ready Condition  Programmable Active State for Ready Line  Programmable DMA Enable  Complete System Bus Mastering  No External Logic Needed for Sequential Transfers in Z80 Environments Overview The Z80 DMA performs data transfers and searches in a wide variety of 8-bit CPU environments. This DMA is unique among DMACs because it takes full control of the system address, data, and control buses, and is therefore a special-purpose processor when enabled by the CPU to function in this unique way. The DMA also provides complete interfacing to the system bus. For example, in a Z80 CPU environment, the Z80 DMA generates the same signal levels and timings, including tristate control, which the Z80 CPU generates to accomplish a transfer. It normally does this without external TTL packages, which other DMAs may require. For this reason, and because of its extensive programmability for operating on data and dataflow, the Z80 DMA can be called a special-purpose transfer processor. It unburdens not only the CPU but also the system designer. The Z80 DMA is also unique in other respects. First, it generates two port addresses instead of one. Because both addresses can be either variable or fixed, the memory-to-memory or I/O-to-I/O transfers can be done with a single channel, whereas other DMACs may require more than one channel or may not do such transfers at all. The capability of the Z80 DMA’s channel surpasses the capability of any other available monolithic DMAC channel to service either fast or slow devices. In addition to having a Wait line for extending cycles, the basic

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G16/G17 read and write cycles can be programmed for different timing requirements. If multiple channels are needed, multiple Z80 DMAs can be easily inte- grated. The interrupt structure is fast and versatile. Interrupt signals and vectors can be generated under several conditions. Finally, the Z80 DMA passes data through itself and can therefore compare bytes against a bit- maskable match byte. An overview of Z80 DMA features are listed below and each point is described more thoroughly in this and other chapters. Throughout the remainder of this manual the Z80 DMA is referred to as the DMA. This DMA is available as either the 2.4 MHz Z80 DMA or the 4 MHz Z80A DMA. Both parts have the same features and differ only in speed. Programming The Z80 DMA has 21 writeable 8-bit control registers and 7 readable 8-bit status registers available to the CPU. Control bytes can be written to the DMA or status bytes can be read from the DMA whenever the DMA is not controlling the bus. Control bytes writeable to the DMA include those that effect immediate command actions such as enable, disable, reset, load starting addresses, continue transferring or searching, clear byte and address counters, clear status bits, and more. In addition, many mode-setting control bytes can be written, including the class and mode of operation, port configuration, starting addresses, block length, address-counting rule, match and match- mask bytes, interrupt conditions, interrupt vector, end-of-block rule, Ready- line and Wait-line rules, and others. Readable status registers include a general status byte that reflects Ready- line, end-of-block, byte-match, and interrupt conditions, as well as registers for the current byte count and port addresses. There is a full chapter on programming on page 90 that explains these functions in detail, and most of them are described in general terms on the pages that follow.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G16/G18 Classes of Operation The Z80 DMA has three basic classes of operation, and two of the classes are each broken into subclasses as follows:  Transfers of data between any two DMA ports: – Sequential transfers (flow-through) – Simultaneous transfers (flyby)  Searches for a particular bit pattern within a byte at a single DMA port  Combined transfers and searches between any two DMA ports: – Sequential transfer/search – Simultaneous transfer/search Figure 18 illustrates these classes. The two subclasses of transfers are illus- trated at the top; the search-only class is depicted in the middle, and the two subclasses of transfer-while-searching are featured at the bottom. In all cases, the DMA assumes full control of the system address, data, and control buses while transferring or searching a given byte. The DMA ports are the source and destination of data; a port is used here to mean either memory or an I/O device. In sequential transfers, which are sometimes called flow-through transfers, each byte transfer includes a read cycle followed by a write cycle. The DMA reads the byte via the data bus to an internal register and sustains the byte on the data bus into the subsequent write cycle. In a Z80 CPU environment, as well as in certain other CPU environments, sequential DMA transfers can be implemented with no external logic between the DMA and the CPU. In simultaneous transfers, which are sometimes called flyby transfers, each byte is simultaneously read from the source into the DMA and written from the source directly to the destination in a single machine cycle. These transfers, therefore, occur at twice the rate of sequential transfers, but they require at least one external logic package to cause the proper signals to appear simultaneously on the control bus (see “The actual number of bytes transferred is one more than specified by the block

Figure 18. Class of Operation

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/G70/G79/G68/G86/G86/G17/G3/G44/G81/G3/G87/G75/G76/G86/G3/G70/G68/G86/G72/G15/G3/G68/G87/G3/G79/G72/G68/G86/G87/G3/G82/G81/G72/G3/G68/G71/G71/G76/G87/G76/G82/G81/G68/G79/G3/G72/G91/G87/G72/G85/G81/G68/G79/G3/G79/G82/G74/G76/G70/G3/G83/G68/G70/G78/G68/G74/G72/G3/G76/G86/G3/G81/G72/G72/G71/G72/G71/G3/G87/G82/G3 /G82/G69/G87/G68/G76/G81/G3/G87/G75/G72/G3/G71/G82/G88/G69/G79/G76/G81/G74/G3/G82/G73/G3/G86/G83/G72/G72/G71/G17 /G41/G76/G74/G88/G85/G72/G20/G28/G3/G86/G88/G80/G80/G68/G85/G76/G93/G72/G86/G3/G87/G75/G72/G3/G73/G88/G81/G70/G87/G76/G82/G81/G86/G3/G82/G73/G3/G72/G68/G70/G75/G3/G70/G79/G68/G86/G86/G3/G82/G73/G3/G61/G27/G19/G3/G39/G48/G36/G3/G82/G83/G72/G85/G68/G87/G76/G82/G81/G3 /G90/G76/G87/G75/G3/G85/G72/G86/G83/G72/G70/G87/G3/G87/G82/G3/G87/G75/G72/G3/G87/G90/G82/G3/G87/G92/G83/G72/G86/G3/G82/G73/G3/G68/G71/G71/G85/G72/G86/G86/G68/G69/G79/G72/G3/G83/G82/G85/G87/G86/G3/G87/G75/G68/G87/G3/G70/G68/G81/G3/G69/G72/G3/G86/G72/G79/G72/G70/G87/G72/G71/G3/G68/G86/G3/G68/G3 /G86/G82/G88/G85/G70/G72/G3/G68/G81/G71/G3/G71/G72/G86/G87/G76/G81/G68/G87/G76/G82/G81/G17/G3/G55/G75/G72/G3/G80/G82/G86/G87/G3/G70/G82/G80/G80/G82/G81/G3/G68/G83/G83/G79/G76/G70/G68/G87/G76/G82/G81/G86/G3/G82/G73/G3/G39/G48/G36/G3/G68/G85/G72/G3 /G87/G85/G68/G81/G86/G73/G72/G85/G86/G3/G73/G85/G82/G80/G3/G80/G72/G80/G82/G85/G92/G16/G87/G82/G16/G44/G18/G50/G3/G82/G85/G3/G44/G18/G50/G16/G87/G82/G16/G80/G72/G80/G82/G85/G92/G15/G3/G90/G76/G87/G75/G82/G88/G87/G3/G86/G72/G68/G85/G70/G75/G15/G3/G68/G81/G71/G3/G80/G82/G86/G87/G3 /G39/G48/G36/G3/G71/G72/G89/G76/G70/G72/G86/G3/G68/G85/G72/G3/G79/G76/G80/G76/G87/G72/G71/G3/G87/G82/G3/G87/G75/G72/G86/G72/G3/G82/G83/G72/G85/G68/G87/G76/G82/G81/G86/G17/G3/G55/G75/G72/G3/G86/G76/G80/G88/G79/G87/G68/G81/G72/G82/G88/G86/G3/G86/G72/G68/G85/G70/G75/G76/G81/G74/G3 /G73/G88/G81/G70/G87/G76/G82/G81/G3/G76/G86/G3/G88/G81/G76/G84/G88/G72/G3/G87/G82/G3/G87/G75/G72/G3/G61/G27/G19/G3/G39/G48/G36/G17/G3/G54/G76/G80/G88/G79/G87/G68/G81/G72/G82/G88/G86/G3/G87/G85/G68/G81/G86/G73/G72/G85/G86/G3/G11/G73/G79/G92/G69/G92/G12/G3/G68/G85/G72/G3 /G79/G76/G80/G76/G87/G72/G71/G3/G87/G82/G3/G87/G85/G68/G81/G86/G73/G72/G85/G86/G3/G69/G72/G87/G90/G72/G72/G81/G3/G80/G72/G80/G82/G85/G92/G3/G68/G81/G71/G3/G44/G18/G50/G17 /G55/G85/G68/G81/G86/G73/G72/G85/G86/G3/G73/G85/G82/G80/G3/G80/G72/G80/G82/G85/G92/G16/G87/G82/G16/G80/G72/G80/G82/G85/G92/G3/G68/G85/G72/G3/G88/G86/G72/G73/G88/G79/G3/G76/G81/G3/G85/G72/G79/G82/G70/G68/G87/G76/G81/G74/G3/G80/G72/G80/G82/G85/G92/G3 /G70/G82/G81/G87/G72/G81/G87/G86/G17/G3/G55/G75/G72/G92/G3/G70/G68/G81/G3/G68/G79/G86/G82/G3/G69/G72/G3/G88/G86/G72/G71/G3/G76/G81/G3/G86/G88/G83/G83/G82/G85/G87/G76/G81/G74/G3/G80/G72/G80/G82/G85/G92/G16/G80/G68/G83/G83/G72/G71/G3/G44/G18/G50/G17/G3/G36/G3 /G53/G72/G68/G71/G92/G3/G70/G82/G81/G71/G76/G87/G76/G82/G81/G3/G70/G68/G81/G3/G69/G72/G3/G83/G85/G82/G74/G85/G68/G80/G80/G72/G71/G3/G76/G81/G87/G82/G3/G87/G75/G72/G3/G39/G48/G36/G3/G87/G82/G3/G86/G76/G80/G88/G79/G68/G87/G72/G3/G68/G81/G3/G68/G70/G87/G76/G89/G72/G3 /G44/G18/G50/G3/G53/G72/G68/G71/G92/G3/G79/G76/G81/G72/G3/G73/G82/G85/G3/G80/G72/G80/G82/G85/G92/G16/G87/G82/G16/G80/G72/G80/G82/G85/G92/G3/G87/G85/G68/G81/G86/G73/G72/G85/G86/G17/G3/G53/G72/G68/G71/G3/G80/G82/G85/G72/G3/G68/G69/G82/G88/G87/G3/G87/G75/G76/G86/G3/G76/G81/G3 /G87/G75/G72/G3/G179/G51/G85/G82/G74/G85/G68/G80/G80/G76/G81/G74/G180/G3/G86/G72/G70/G87/G76/G82/G81/G17 /G55/G85/G68/G81/G86/G73/G72/G85/G86/G3/G73/G85/G82/G80/G3/G44/G18/G50/G16/G87/G82/G16/G44/G18/G50/G3/G70/G68/G81/G3/G69/G72/G3/G88/G86/G72/G71/G3/G76/G81/G3/G68/G83/G83/G79/G76/G70/G68/G87/G76/G82/G81/G86/G3/G86/G88/G70/G75/G3/G68/G86/G3/G85/G72/G68/G79/G16/G87/G76/G80/G72/G3 /G71/G68/G87/G68/G3/G68/G70/G84/G88/G76/G86/G76/G87/G76/G82/G81/G3/G90/G75/G72/G85/G72/G3/G69/G68/G70/G78/G88/G83/G3/G86/G87/G82/G85/G68/G74/G72/G3/G82/G73/G3/G87/G75/G72/G3/G76/G81/G70/G82/G80/G76/G81/G74/G3/G71/G68/G87/G68/G3/G76/G86/G3/G85/G72/G84/G88/G76/G85/G72/G71/G17/G3 /G55/G75/G72/G3/G82/G83/G87/G76/G82/G81/G68/G79/G3/G86/G72/G68/G85/G70/G75/G3/G70/G68/G83/G68/G69/G76/G79/G76/G87/G92/G3/G68/G79/G79/G82/G90/G86/G3/G69/G85/G68/G81/G70/G75/G76/G81/G74/G3/G87/G82/G3/G89/G68/G85/G76/G82/G88/G86/G3/G82/G87/G75/G72/G85/G3/G68/G70/G87/G76/G82/G81/G86/G3 /G90/G75/G72/G81/G3/G68/G3/G69/G92/G87/G72/G3/G80/G68/G87/G70/G75/G3/G76/G86/G3/G73/G82/G88/G81/G71/G3/G68/G86/G3/G76/G81/G3/G80/G72/G80/G82/G85/G92/G16/G87/G82/G16/G80/G72/G80/G82/G85/G92/G3/G87/G85/G68/G81/G86/G73/G72/G85/G86/G17/G3/G48/G72/G80/G82/G85/G92/G3 /G86/G72/G68/G85/G70/G75/G72/G86/G3/G68/G81/G71/G3/G44/G18/G50/G3/G86/G72/G68/G85/G70/G75/G72/G86/G15/G3/G90/G76/G87/G75/G82/G88/G87/G3/G87/G85/G68/G81/G86/G73/G72/G85/G15/G3/G68/G85/G72/G3/G88/G81/G76/G84/G88/G72/G3/G87/G82/G3/G87/G75/G72/G3/G61/G27/G19/G3/G39/G48/G36/G3 /G68/G81/G71/G3/G68/G85/G72/G3/G88/G86/G72/G73/G88/G79/G3/G76/G81/G3/G79/G82/G70/G68/G87/G76/G81/G74/G3/G68/G81/G3/G72/G81/G71/G16/G82/G73/G16/G69/G79/G82/G70/G78/G15/G3/G70/G75/G72/G70/G78/G3/G70/G75/G68/G85/G68/G70/G87/G72/G85/G15/G3/G82/G85/G3/G82/G87/G75/G72/G85/G3 /G86/G83/G72/G70/G76/G68/G79/G3/G69/G92/G87/G72/G3/G76/G81/G3/G68/G3/G69/G79/G82/G70/G78/G17

Figure 19. Basic Functions of the Z80 DMA current byte operation. This is also called demand mode.

1. Transfer Memory-to-I/O (optional search)
2. Transfer I/O-to-Memory (optional search)
3. Transfer Memory-to-Memory (optional search)
4. Transfer I/O-to-I/O (optional search)

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G17/G12 port’s Ready line goes inactive before this occurs, the DMA pauses until the Ready line comes active again. This is also called Block mode. In all modes, the operation on the byte is completed in an orderly fashion when a byte of data is read into the DMA, regardless of the state of other signals (including a port’s Ready line). Figure 20 illustrates the sequence of events that occur in a sequential transfer/search of one byte, whatever of the mode of operation. First, the source port address is incremented or decre- mented, if it was programmed to be a variable-address port. Then, the byte is read from that port to the DMA. Next, the destination port address is incremented or decremented, if it was programmed to be a variable. The byte is then written to the destination port. If a search capability is included, the byte is compared to the match byte. When no byte match occurs, the DMA increments the byte counter and continues. When a byte is found, a status bit is set and the DMA either continues by incrementing the byte counter, stops (releases the bus), or interrupts the CPU, depending on its initial programming. The next three figures illustrate how the three modes function before, during, and after the single-byte operation, which is shown in Figure 20. Operation in the Byte mode (Figure 21) begins with an enabling command from the CPU and a test of the I/O device’s Ready line. When the Ready line is active, the DMA requests the system bus (address, data, and control buses) through the Bus Request line, and the CPU acknowledges and releases control to the DMA. The transfer of and/or search of one byte takes place as in Figure 20. Then, a test is made for end-of-block by checking to see if the byte counter has reached the programmed block length. If the end is not reached, the DMA releases the bus back to the CPU. If the end is reached, a status bit is set and some terminating action occurs, according to the initial programming. Releasing the bus between each byte allows the CPU to execute at least one machine cycle before releasing the bus again to the DMA for the next byte transfer. This means that while the DMA operates more slowly than it could in other modes, CPU activities like interrupt acknowledgement, polling, and memory refresh can be inter- leaved with DMA transfers in the Byte mode.

Figure 20. Transfer/Search One Byte

Figure 21. Byte Mode

Figure 22. Burst Mode CPU and repetitively tests the Ready signal until it comes active again.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G17/G16 attains the bus, the transfers are made at maximum speed. If the transfers are long, however, this mode can interfere with other CPU activities, which come to a halt for the entire duration of DMA transfers. In the Continuous mode (Figure 23), the DMA requests the bus in the same manner as other modes and repetitively transfers bytes in the same manner as Burst mode. However, unlike the Burst mode the bus is retained by the DMA whenever an inactive Ready signal is encountered prior to a stop on end-of-block or byte match. The DMA simply idles, while holding onto the bus, until Ready becomes active again. Then it completes the transfer sequence. This is the fastest of the three modes because it eliminates the necessity of releasing the bus and requesting it again between complete block transfers. In this mode, however, the system bus is continuously preempted by the DMA. This mode is usually used only when very fast transfers are required and when the impact on CPU activities can be tolerated. This might be the case, for instance, when an operating system is b e i n gl o a d e dt om e m o r yf r o md i s k . Due to the DMA ’s high-speed buffered method of reading data, operations on one byte are not completed until the next byte is read in. This means that total transfer or search block lengths must be two or more bytes, even in the Byte mode, and that block lengths programmed into the DMA must be one less than the desired block length. This characteristic is described in detail in Internal Structure under the section entitled, “Address and Byte Counting” on page 75.”

Figure 23. Continuous Mode

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G17/G18 Transfer Speed The Z80 DMA has one of the fastest maximum transfer rates of any 8-bit DMAC device. This rate is achieved in the simultaneous transfer class of operation and, unlike the more common sequential transfer class, it requires at least one external TTL package. But because some other 8-bit DMAs require some external logic, this constitutes a legitimate speed comparison. Table 8 describes the maximum rates that can be achieved in different classes of DMA operation. Maximum CPU block-transfer rates are also given for comparison. All DMA transfers assume the uninterrupted use of Burst or Continuous mode, and they assume read and write cycles that last two cycles (see “Variable Cycle” on page 60). Transfer speed in Byte mode depends on how long the CPU keeps the bus between each byte transfer of the DMA. Therefore, the speed is best expressed from the CPU viewpoint. Table 9 describes the reduction in Z80 throughput (per Kilobaud trans- ferred) caused by byte-mode DMA transfers, and this rate is compared with the reduction in throughput that would occur if the CPU did its own byte transfers using an interrupt service routine of six instructions (a practical lower limit). “Z80 DMA and Z80 SIO Example” on page 139 contains more detail on this data. This data assumes sequential DMA transfers with longer cycle timing than the minimum of two clock cycles per read or write. Simultaneous transfers of two clock cycles would, therefore, result in even lower impact on CPU throughput. Table 8 describes that DMA transfer rates in Burst and Continuous modes can be up to ten times faster than Z80 CPU rates. Table 9 describes that the reduction of CPU throughput with Byte mode DMA transfers is about five times less than the reduction that results when the CPU handles its own byte-mode I/O in the normal interrupt mode.

ation: one address for the source port and another for the destination port. whether the DMA is reading the source or writing to the destination.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G17/G1a Variable addresses can either increment or decrement automatically from the programmed starting address. Fixed addresses are useful for I/O devices and the DMAs capability to generate fixed addresses eliminates the need for transfer/search enabling wires to the I/O device (although Chip Enable hardwiring is still required, as it is with all peripheral circuits). Two readable address counters keep the current address of each port. These counters are distinct from the starting address registers for each port, that is, the counters are buffered by the registers. Therefore, new starting addresses can be written to the DMA whenever the DMA is not holding the bus, for example, between byte transfers in Byte mode. New starting addresses for a new block of data can be loaded into the DMA before the transfer of the current block is finished. Loading new starting addresses does not disturb the contents of the associated port address counters. DMA address generation capabilities can be used in the following ways:  Start at a base address and count up or down.  Automatically step back to the beginning at the completion of an address sequence.  Load new starting addresses or reload previous ones for the next sequence. Byte Matching (Searching) Searches for byte matches can be performed either as a sole function or simultaneously with transfers. When a byte match is found, a status bit in the readable status register is set and the DMA can be programmed to do one of the following:  Stop (release the bus) immediately upon byte match.  Stop and interrupt the CPU immediately upon byte match.  Interrupt the CPU when the DMA stops at the end of a block.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G17/G1b The match byte written into the DMA is masked with another byte so that only certain bits within the match byte can be compared with the corre- sponding bits in the data bytes being searched. Interrupts The DMA can be programmed to interrupt the CPU on three conditions:  Interrupt on Ready  Interrupt on Byte Match  Interrupt on End-of-Block The first condition (I/O-port Ready line becoming active) causes an interrupt before the DMA requests the bus. The other two conditions cause the DMA to interrupt the CPU after the DMA stops (releases the bus). Stopping the DMA on byte match or end-of-block is separately programmed. Any of these conditions (Ready line becoming active, byte match, or end- of-block) causes a readable status bit to be set. In addition, when an interrupt on any of these conditions is programmed, an interrupt-pending status bit is also set, and each type of interrupt can optionally alter the DMAs interrupt vector. The DMA shares the Z80 Family’s versatile interrupt scheme, which provides fast interrupt service in real-time applications. In a Z80 CPU environment where the CPU is using its Mode 2 interrupts, the DMA passes its internally modifiable 8-bit interrupt vector to the CPU, which attaches an additional eight bits to form the memory address of the interrupt routine table. This table contains the address of the beginning of the interrupt routine. In this process, CPU control is transferred to the interrupt routine, so that the next instruction executed after an interrupt acknowledge is the first instruction of the interrupt routine.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G18/G12 Auto Restart Block transfers can be repeated automatically by the DMA. This function causes the byte counter to be cleared and the address counters to be reloaded with the contents of the starting-address registers. The Auto Restart feature relieves the CPU of software overhead for repet- itive operations such as CRT refresh and many others. Moreover, the CPU can write different starting addresses into the buffer registers during transfers in the Byte mode (or Burst mode when the Ready line is inactive and the bus is released) causing the Auto Restart to begin at a new location. Pulse Generation External devices can keep track of how many bytes have been transferred by using the DMA’s Pulse output, which provides a signal at 256-byte intervals. The interval sequence may be offset at the beginning by 1 to 255 bytes. The interrupt line carries the Pulse signal in a manner that prevents inter- pretation by the Z80 CPU as an interrupt request, because the signal only appears when the Bus Request and Bus Acknowledge lines are both active. Under these conditions, the Z80 CPU does not monitor the Interrupt (INT ) line. Variable Cycle The Z80 DMA offers the unique feature of programmable operation-cycle length. This is valuable in tailoring the DMA to the particular requirements of various CPUs and other system components (fast or slow), and in maxi- mizing the data-transfer rate. Also, it often eliminates external logic and reduces CPU software overhead. There are two aspects to the variable cycle feature. First, the entire read and write cycles (periods) associated with the source and destination ports can

Figure 24. Variable Cycle Length o nt h ed a t ab u sf o rw h i c ht h eD M Aw a t c h e s .

pins as illustrated in Figure 25 through Figure 28. Table 10. Events and Actions

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G18/G15 BAI Bus Acknowledge In (input, active Low). Signals that the system buses have been released for DMA control. BAO Bus Acknowledge Out (output, active Low). In multiple-DMA configura- tions, this pin signals that the CPU has relinquished control of the bus. BAI and BAO form a daisy-chain for multiple DMA priority resolution over bus control. Unlike the interrupt daisy-chain formed with the IEI and IEO lines, this chain does not allow preemption of control by a high-priority DMA when a lower-priority DMA is already bus master. The DMA that has the bus is always allowed to finish, regardless of its priority in the chain. BUSREQ Bus Request (bidirectional, active Low, open-drain). As an output, this pin sends requests for control of the system address bus, data bus, and control bus to the CPU. As an input when multiple DMAs are strung together in a priority daisy-chain through BAI and BAO, this pin senses when another DMA has requested the buses and causes this DMA to delay its bus request until the first DMA is finished. Because this bidirectional pin allows simul- taneous bidirectional signals with no means of control, no buffers come between this DMA and other DMAs. There can, however, be buffers between it and the CPU because it is unidirectional into the CPU. A 1.8 Kohms pull-up resistor is typically connected to this pin. CE /WAIT Chip Enable and Wait (input, active Low). Normally, this functions only as aC E line, but it can also be programmed to serve as a WAIT function. As a CE line from the CPU, this pin becomes active when IORQ is active and the I/O port address (up to 16 bits) on the system address bus is the DMA’s address, thereby allowing control bytes to be written from the CPU to the DMA. As a WAIT line from memory or I/O devices, after the DMA has received a bus acknowledge (BUSACK) from the CPU, this pin causes wait

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G18/G16 states to be inserted in the DMA’s operation cycles, thereby slowing the DMA to a speed that matches the memory or I/O device. The Applications chapter contains a description of how the CE and WAIT inputs can be multiplexed by the CPU’s BUSACKline. CLK System Clock (input). This pin is standard Z80 single-phase clock at 2.8 MHz (Z80 DMA) or 4.0 MHz (Z80A DMA). For slower system clocks, a TTL gate with a pull-up resistor may be adequate to meet the timing and voltage level specifications. For higher speed systems, use a clock driver with an active pull-up to meet the VIH specification and rise time require- ments. There should always be a resistive pull-up to the power supply (10 Kohms maximum), ensuring correct power at DMA reset. D7-D0 System Data Bus (bidirectional, tristate). These pins transfer control bytes from the CPU, status byes from the DMA, and data from memory or I/O peripherals. Data transfers or searches by the DMA occur only when the DMA controls both this bus and the address bus. When the CPU controls these buses, it can write or read DMA control or status bytes. IEI Interrupt Enable In (input, active High). This line, combined with the IEO, form a priority daisy-chain when there is more than one interrupting device. A High on this line indicates that no other device of higher priority is inter- rupting, thereby allowing this DMA to interrupt. IEO Interrupt Enable Out (output, active High). IEO is High only when IEI is High and this DMA is not requesting an interrupt. Therefore, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt service routine. Unlike devices in a bus-request daisy-chain, devices in an interrupt daisy-chain can

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G18/G17 be preempted by higher priority devices before the lower priority device has been fully serviced. INT/PULSE Interrupt Request (output, active Low, open-drain). This requests a CPU interrupt when brought Low while the DMA is not the bus master. The CPU acknowledges the interrupt by pulling its IORQ output Low during an M1 cycle. The DMA INT pin is typically connected to the INT pin of the CPU with a pull-up resistor and tied to all other INTpins in the system. This pin can also be used to generate periodic pulses to an external device. It can be used this way only when the DMA is bus master, for example, the CPU’s BUSREQand BUSACK lines are both Low and the CPU cannot sense interrupts. IORQ Input/Output Request (bidirectional, active Low, tristate). Used as an input, this pin indicates that the lower half of the address bus contains a valid I/O port address for transfer of control or status bytes from or to the CPU. This DMA is the addressed port if its CE pin, IORQ pin, and or RD pin are simultaneously active. As an output, after the DMA has taken control of the system buses, this pin indicates that the address bus contains a valid 8-bit or 16-bit port address for another I/O device involved in a DMA transfer of data. When IORQ and M1 are both active inputs to the DMA, an interrupt acknowledge by the CPU is indicated. Machine Cycle One (input, active Low). This pin indicates that the current CPU machine cycle is an instruction fetch. This pin has two purposes in the DMA’s interrupt structure. First, it is used by the DMA to detect return- from-interrupt instructions (RETI, or ED4DH) fetched over the data bus by the CPU at the end of interrupt service routines. Second, an interrupt acknowledge is indicated when both M1 and IORQ are active inputs to the DMA. During 2-byte instruction fetches, M1 is active as each Op Code byte is fetched. In the CMOS DMA, the M1signal has a different function:

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G18/G18 when M1 occurs without an active RD or IORQ for at least two clock cycles, the internal reset is activated at the falling clock after M1returns to the inactive state. This internal reset lasts for three clock cycles. MREQ Memory Request (output, active Low, tristate). This line indicates that the address bus contains a valid address for a memory read or write operation. After the DMA has taken control of the system buses, it indicates a DMA transfer request from or to memory. RD Read (bidirectional, active Low, tristate). As an input, this signal indicates that the CPU is ready to read status bytes from the DMAs read registers. As an output, after the DMA has taken control of the system buses, it indicates a DMA-controlled read from memory or I/O port address. RDY Ready (input, programmable active Low or High). This pin is monitored by the DMA to determine when a peripheral device associated with a DMA port is ready for a read or write operation. When the DMA is enabled to operate, the RDY line indirectly controls DMA activity; the manner in which DMA activity is controlled by RDY depends on what operating mode is selected (Byte, Burst, or Continuous). An active RDY line can be simulated by programming a Force Ready condition. This is useful in memory-to-memory operations. It is preferable to have the RDY signal synchronized to the CLK signal, for example, RDY should become active on the rising edge of CLK. This is particularly important in the Continuous mode of operation. WR Write (bidirectional, active Low, tristate). As an input, this indicates that the CPU is requesting to write control bytes to the DMA write registers when the DMA is selected. As an output, after the DMA has taken control of the

Low in this signal resets the DMA. Figure 25. Pin Functions (CMOS PLCC Package Only)

Figure 26. 40-Pin DIP Pin Assignments

Figure 27. 44-Pin PLCC Pin Assignments (Z8410 NMOS)

Figure 28. 44-Pin PLCC Pin Assignments (Z84C10 NMOS)

Figure 29. Z80 DMA Block Diagram

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/G71/G76/G86/G70/G88/G86/G86/G76/G82/G81/G3/G82/G73/G3/G87/G75/G76/G86/G3/G87/G72/G70/G75/G81/G76/G84/G88/G72/G17/G3/G55/G75/G72/G3/G81/G68/G80/G72/G86/G3/G82/G73/G3/G87/G75/G72/G3/G90/G85/G76/G87/G72/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G3/G86/G75/G82/G90/G81/G3/G76/G81/G3 /G41/G76/G74/G88/G85/G72 /G22/G19/G3/G71/G82/G3/G81/G82/G87/G3/G76/G81/G71/G76/G70/G68/G87/G72/G3/G87/G75/G72/G3/G73/G88/G79/G79/G3/G72/G91/G87/G72/G81/G87/G3/G82/G73/G3/G87/G75/G72/G3/G39/G48/G36/G182/G86/G3/G83/G85/G82/G74/G85/G68/G80/G80/G68/G69/G76/G79/G76/G87/G92/G3 /G69/G72/G70/G68/G88/G86/G72/G3/G80/G68/G81/G92/G3/G80/G82/G71/G72/G86/G3/G68/G81/G71/G3/G73/G88/G81/G70/G87/G76/G82/G81/G86/G3/G68/G85/G72/G3/G86/G72/G87/G3/G90/G76/G87/G75/G3/G86/G76/G81/G74/G79/G72/G3/G69/G76/G87/G86/G3/G76/G81/G3/G87/G75/G72/G3/G69/G68/G86/G72/G3 /G85/G72/G74/G76/G86/G87/G72/G85/G3/G69/G92/G87/G72/G86/G3/G82/G73/G3/G72/G68/G70/G75/G3/G74/G85/G82/G88/G83/G17 /G41/G76/G74/G88/G85/G72 /G22/G19/G3/G79/G72/G73/G87/G15/G3/G76/G79/G79/G88/G86/G87/G85/G68/G87/G72/G86/G3/G87/G75/G72/G3/G90/G85/G76/G87/G72/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G17/G3/G55/G75/G72/G86/G72/G3/G68/G85/G72/G3/G87/G75/G72/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G3/G73/G82/G85/G3 /G90/G75/G76/G70/G75/G3/G76/G81/G83/G88/G87/G86/G3/G73/G85/G82/G80/G3/G87/G75/G72/G3/G71/G68/G87/G68/G3/G69/G88/G86/G3/G68/G85/G72/G3/G86/G75/G82/G90/G81/G3/G76/G81/G3/G87/G75/G72/G3/G73/G76/G74/G88/G85/G72/G17/G3/G38/G82/G80/G83/G68/G85/G72/G3/G87/G75/G76/G86/G3/G73/G76/G74/G88/G85/G72/G3 /G90/G76/G87/G75/G3/G41/G76/G74/G88/G85/G72 /G22/G19/G3/G85/G76/G74/G75/G87/G15/G3/G90/G75/G76/G70/G75/G3/G76/G71/G72/G81/G87/G76/G73/G76/G72/G86/G3/G87/G75/G72/G3/G85/G72/G68/G71/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G17 /G55/G75/G72/G3/G87/G90/G82/G3/G20/G25/G16/G69/G76/G87/G3/G86/G87/G68/G85/G87/G76/G81/G74/G3/G68/G71/G71/G85/G72/G86/G86/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G3/G76/G81/G3/G74/G85/G82/G88/G83/G86/G3/G58/G53/G23/G3/G68/G81/G71/G3/G58/G53/G19/G15/G3/G68/G81/G71/G3/G87/G75/G72/G3 /G20/G25/G16/G69/G76/G87/G3/G69/G79/G82/G70/G78/G16/G79/G72/G81/G74/G87/G75/G3/G85/G72/G74/G76/G86/G87/G72/G85/G3/G76/G81/G3/G74/G85/G82/G88/G83/G3/G58/G53/G19/G15/G3/G75/G68/G89/G72/G3/G20/G25/G16/G69/G76/G87/G3/G70/G82/G88/G81/G87/G72/G85/G86/G3/G68/G86/G86/G82/G70/G76/G68/G87/G72/G71/G3 /G90/G76/G87/G75/G3/G87/G75/G72/G80/G17/G3/G55/G75/G72/G3/G70/G82/G88/G81/G87/G72/G85/G86/G15/G3/G88/G81/G79/G76/G78/G72/G3/G87/G75/G72/G76/G85/G3/G68/G86/G86/G82/G70/G76/G68/G87/G72/G71/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G15/G3/G70/G68/G81/G81/G82/G87/G3/G69/G72/G3/G90/G85/G76/G87/G87/G72/G81/G3 /G87/G82/G17/G3/G55/G75/G72/G3/G87/G90/G82/G3/G68/G71/G71/G85/G72/G86/G86/G3/G70/G82/G88/G81/G87/G72/G85/G86/G3/G74/G72/G81/G72/G85/G68/G87/G72/G3/G87/G75/G72/G3/G68/G71/G71/G85/G72/G86/G86/G72/G86/G3/G87/G75/G68/G87/G3/G68/G85/G72/G3/G83/G79/G68/G70/G72/G71/G3/G82/G81/G87/G82/G3/G87/G75/G72/G3 /G68/G71/G71/G85/G72/G86/G86/G3/G69/G88/G86/G17/G3/G55/G75/G72/G3/G68/G71/G71/G85/G72/G86/G86/G3/G70/G82/G88/G81/G87/G72/G85/G86/G3/G70/G68/G81/G3/G68/G79/G86/G82/G3/G69/G72/G3/G85/G72/G68/G71/G3/G69/G92/G3/G87/G75/G72/G3/G38/G51/G56/G3/G87/G75/G85/G82/G88/G74/G75/G3/G87/G75/G72/G3 /G71/G68/G87/G68/G3/G69/G88/G86/G15/G3/G68/G86/G3/G70/G68/G81/G3/G87/G75/G72/G3/G69/G92/G87/G72/G3/G70/G82/G88/G81/G87/G72/G85/G17/G3/G36/G79/G79/G3/G87/G75/G85/G72/G72/G3/G90/G85/G76/G87/G68/G69/G79/G72/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G3/G86/G72/G85/G89/G72/G3/G68/G86/G3 /G69/G88/G73/G73/G72/G85/G86/G3/G73/G82/G85/G3/G87/G75/G72/G3/G85/G72/G68/G71/G68/G69/G79/G72/G3/G70/G82/G88/G81/G87/G72/G85/G86/G17/G3/G55/G75/G72/G3/G70/G82/G81/G87/G72/G81/G87/G86/G3/G82/G73/G3/G87/G75/G72/G3/G85/G72/G74/G76/G86/G87/G72/G85/G86/G3/G70/G68/G81/G3/G69/G72/G3 /G70/G75/G68/G81/G74/G72/G71/G3/G71/G88/G85/G76/G81/G74/G3/G68/G3/G69/G79/G82/G70/G78/G3/G87/G85/G68/G81/G86/G73/G72/G85/G3/G90/G76/G87/G75/G82/G88/G87/G3/G71/G76/G86/G87/G88/G85/G69/G76/G81/G74/G3/G87/G75/G72/G3/G70/G82/G81/G87/G72/G81/G87/G86/G3/G82/G73/G3/G87/G75/G72/G3 /G70/G82/G88/G81/G87/G72/G85/G86/G17/G3/G55/G75/G76/G86/G3/G73/G72/G68/G87/G88/G85/G72/G3/G76/G86/G3/G88/G86/G72/G73/G88/G79/G15/G3/G73/G82/G85/G3/G72/G91/G68/G80/G83/G79/G72/G15/G3/G71/G88/G85/G76/G81/G74/G3/G37/G92/G87/G72/G16/G80/G82/G71/G72/G3/G87/G85/G68/G81/G86/G73/G72/G85/G86/G15/G3/G76/G81/G3 /G90/G75/G76/G70/G75/G3/G70/G82/G81/G87/G85/G82/G79/G3/G69/G92/G87/G72/G86/G3/G70/G68/G81/G3/G69/G72/G3/G90/G85/G76/G87/G87/G72/G81/G3/G87/G82/G3/G87/G75/G72/G3/G39/G48/G36/G3/G90/G75/G76/G79/G72/G3/G87/G75/G72/G3/G38/G51/G56/G3/G75/G68/G86/G3/G87/G75/G72/G3/G69/G88/G86/G3 /G69/G72/G87/G90/G72/G72/G81/G3/G69/G92/G87/G72/G3/G87/G85/G68/G81/G86/G73/G72/G85/G86/G17/G3/G55/G75/G76/G86/G3/G68/G79/G79/G82/G90/G86/G3/G87/G75/G72/G3/G81/G72/G91/G87/G3/G69/G79/G82/G70/G78/G15/G3/G90/G75/G76/G70/G75/G3/G70/G68/G81/G3/G69/G72/G3/G68/G81/G3/G36/G88/G87/G82/G3 /G53/G72/G86/G87/G68/G85/G87/G3/G69/G79/G82/G70/G78/G15/G3/G87/G82/G3/G69/G72/G74/G76/G81/G3/G84/G88/G76/G70/G78/G79/G92/G3/G68/G87/G3/G68/G3/G81/G72/G90/G3/G79/G82/G70/G68/G87/G76/G82/G81/G17/G3/G49/G82/G87/G76/G70/G72/G3/G87/G75/G68/G87/G3/G87/G75/G72/G3/G69/G79/G82/G70/G78/G3

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G19/G15 which control bytes can be written to the DMA while the CPU has the bus between byte transfers. This allows the next block, which can be an Auto Restart block, to begin quickly at a new location. Notice that the block length counter stops (or Auto Restarts) as a result of a comparison to the block length register. In changing the register, the block length also changes with what may be unpredictable results. The pulse-control byte illustrated in Figure 30 (in the WR4 group) also has a relationship to the byte counter in WR0. The pulse-control byte can be loaded with an offset value between 0 and 255 and this value is continu- ously compared with the lower byte of the byte counter. The NT line generates a pulse each time a match occurs, which happens on every 256 bytes of transfer or search after the initial offset. Because the pulse signals generated on the NT line only occur when the DMA has control of the system bus, for example, when the BUSREQ and BUSACK lines are simultaneously active, the CPU cannot detect theme and they can be directed exclusively to an external gate, counter, or other device. Figure 30 illustrates the seven status registers readable through the data bus. Unlike the write registers, the status registers include no second-level registers or groups. These registers are accessed sequentially according to the read mask written to the WR6 group, except that the status byte can be read separately from the other read registers.

Figure 30. Write Register Organization (left) and Read Register Organization (right)

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G19/G17 Address and Byte Counting Addresses for either port may be fixed at their programmed starting address, or they may be incremented or decremented from the programmed starting address by the address counters. The block length programmed into the DMA is compared with the byte counter, which starts at zero and incre- ments at the completion of each byte operation (Figure 20). The DMA uses a high-speed buffering or pipelining scheme for reading data. When transferring data and stopping on an end-of-block, the effect of this pipelining is that one more transfer is completed than is programmed into the block-length register; the only exception to this rule occurs in simultaneous transfers that use two-cycle variable timing, in which case two extra bytes are transferred if the Ready line remains active. Table 11 describes the contents of the counters in the various classes and the modes of transfer involving stopping or interrupting at an end-of-block (interrupts imply prior stopping). Search and transfer/search operations that are programmed to stop on byte match function somewhat differently, as described in Table 12. Matches are discovered only after the next byte is read. In all classes of transfer/search operations, the matched byte is transferred. In simultaneous transfer/search operations, however, an additional byte is usually also transferred. The only exception to this occurs in Burst and Continuous modes when the Ready line goes inactive while the byte match is being located. During simulta- neous transfer/searches in Burst or Continuous mode, these searches are typically continuous processes performed in memory using a Force Ready condition or a Ready line that will not go inactive. However, when this exception is encountered, the CPU can be programmed to research two bytes when such a match occurs.

address for transfer purposes. necessary only in the case of a fixed destination address.” on page 129. Table 11. Contents of Counters After DMA Stops Because of End-of-Block (Transfer Table 12. Contents of Counters After DMA Stops Due to Byte Match (Search or Transfer/

address for transfer or search. as determined by external hardware. See the 'Applications' chapter. same way that the Z80 CPU controls them to perform read and write cycles. through its dual-purpose CE/WAIT pin.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G19/G1a When the DMA has requested and received the bus from the CPU, other devices on the system do not perceive the change. The CPU is idle during this time because it cannot fetch instructions from memory. Bus Requesting Two conditions enable the DMA to request the bus from the CPU: an enabling command from the CPU, and an active Ready condition, resulting from either an active Ready line from an I/O device or a Force Ready command by the CPU. The DMA requests the bus by latching its BUSREQ line Low. The CPU always responds to a bus request and it does so quickly, in no more than one machine cycle (3 to 10 clock cycles) plus one additional clock cycle by lowering its BUSACK line as an input to the DMA’s BAIline. Both the DMA’s BUSREQoutput and the CPU’s BUSACKoutput remain Low w h i l et h eD M Ah a st h eb u s . The bus is released back to the CPU when the DMA’s BUSREQline goes High; the CPU’s BUSACKline goes High in the next clock cycle. The DMA releases its BUSREQ line in a variety of conditions, including:  Completion of single-byte transfer (Byte mode  Ready line going inactive (Byte and Burst modes)  Byte match (Burst and Continuous modes) if stop-on-match is programmed  End-of-block (all modes), if stop-on-end-of-block is programmed These conditions are explained in the “Timing” chapter. Bus requests cannot be made while the CPU services an interrupt from the DMA. This is prevented by the Interrupt Under Service (IUS) latch, which is discussed later.

requesting the bus. Figure 31 illustrates this procedure. this DMA from also requesting the bus until the other DMA has finished. higher priority DMA cannot preempt it during this time. Figure 31. Bus-Requesting Daisy-Chain

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G1a/G12 Interrupts Conditions and Methods The Z80 CPU prioritizes external events in the following order: 1. Bus Requests (BUSREQ ) 2. Non-Maskable Interrupts (NMI ) 3. Maskable Interrupts (INT ) In addition to bus requests, the DMA normally allows only maskable inter- rupts (INT) and uses them in CPU Mode 2, which allows interrupt vectors. Non-maskable interrupts are typically reserved for extreme priority events such as power-failure signaling. The DMA can be programmed to interrupt the CPU under the following conditions:  After the DMA’s RDY line has gone active and before the DMA requests the bus (interrupt on RDY).  On an end-of-block, when the contents of the byte counter match the contents of the block-length register.  On a byte match, when the contents of the match-byte register (after masking by the mask-byte register) corresponds to a data byte being transferred or searched. The DMA cannot have control of the bus when it interrupts the CPU. S i g n a l i n go nt h eI N T line while the DMA is bus master generates periodic pulses to an external device. These pulses are not perceived by the Z80 CPU. Therefore, at stop-on-end-of-block or byte match, the DMA first releases the bus before interrupting the CPU, as shown in Figure 32. If the DMA is programmed to interrupt on end-of-block and also to Auto Restart on end-of-block, an interrupt occurs (and should be acknowledged for continued operation) at each end-of-block. However, the end-of-block

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G1a/G13 status bit is not set as it would be without the Auto Restart. Therefore, the interrupt vector cannot indicate the specific interrupt cause, for example, Status Affects Vector is not effective. The Z80 CPU acknowledges the interrupt by pulling its M1 and IORQ lines low for one machine cycle (see the “Timing” chapter). This causes the DMA to put its 8-bit interrupt vector on the data bus, thereby identifying itself and optionally identifying the origin of the interrupt. The CPU uses the vector to access an interrupt service routine, which is then executed. The interrupt service routine typically reenables the DMA to request the bus and cause interrupts again. For CPUs that have no interrupt acknowledge or a noncompatible one, DMA control bytes can be written (usually in the interrupt service routine) to simulate the same functions.

Figure 32. Z80 Interrupt Sequence

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G1a/G15 CPU to a temporary register. It normally identifies the interrupting device and it can also identify the cause of the interrupt (actually the current state of certain status bits). The I Register of the Z80 CPU (when the CPU is programmed to Mode 2 state) has the upper byte of a 16-bit address, which is formed with the interrupt vector, and this address points to a jump table e n t r yi nm e m o r y . The jump table location in memory contains an address that is read to the CPU’s program counter (Figure 33b). This address points to the first instruction of the interrupt service routine, which then begins executing. In most DMA applications, the CPU’s interrupt service routine contains instructions that write control bytes back into the DMA through a register in the CPU (Figure 33c). In CPU environments without interrupt vectors, the CPU must poll each peripheral or an external register to determine tristate device interrupted and why.

Figure 33. Interrupt Service Routine but has not yet acknowledged. It holds the INT line Low (Figure 34).

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G1a/G18 Interrupt On Ready Normally, when the DMA has been enabled by the CPU to request the bus while the I/O device’s Ready line is inactive, the Ready line’s transition to the active state causes the BUSREQ line to go Low (Figure 65). It does so within two clock cycles if the setup time to the rising edge of CLK is met. This does not take place, however, when the Interrupt on Ready option (also called the Interrupt Before Requesting Bus option) is selected. When this option is used, the DMA interrupts the CPU when the Ready line comes active. The CPU’s interrupt service routine now writes control bytes to the DMA, which enable the DMA to request the bus after the service routine finishes. As noted earlier, the CPU cannot respond to an interrupt when the DMA is bus master. Thus, when enabled in Continuous mode, the DMA inter- rupts the CPU when the Ready line first becomes active, but not on succeeding transitions. The Interrupt on Ready option is typically used to put new starting addresses into the DMA, so that transfers go to a part of memory that is dynamically determined. Interrupt Service Routines In addition to the DMA’s extensive programmability for mode-setting (usually done at power-up initialization), numerous commands (control bytes) are designed for use in various interrupt service routines. The next chapter on “Programming,” fully explains the commands, but a quick overview follows. Some typical functions for which control bytes are available for use in interrupt service routines include:  Reset the DMA – Enable the DMA for bus requesting – Disable the DMA for bus requesting

Interrupt (RETI or hex ED4D) instruction, which is now explained. Figure 36. Interrupt On Ready (IOR) Latch the interrupt service routine. *NOTE: This latch is only set when the Interrupt-On-Ready option is selected.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G1a/G1a  Resets the Interrupt Under Service (IUS) latch in the DMA, thereby allowing its IEO pin to go High so that lower priority devices can interrupt.  Enables the DMA to request the bus again. This occurs only in the Interrupt on Ready option and only when the Enable DMA control byte is also used. For non-Z80 environments, control bytes are provided to simulate these actions. Interrupt Daisy-Chains Multiple DMAs can be chained together by their IEI and IEO lines, as depicted in Figure 37. In the Z80 Family, the DMA ’s location in the IEI/ IEO chain sets priority. When peripherals simultaneously interrupt the Z80 CPU, the highest priority peripheral (nearest the +5V end of the daisy-chain) is serviced. The CPU receives the winning peripheral’s interrupt vector. The IEI/IEO chain allows only the highest priority interrupting peripheral to place its interrupt vector on the data bus. In non-Z80 environments that have no interrupt vectors, the winning peripheral is determined by successively reading the status of all peripherals. For a device to have priority, its IEI line must be High. When a device needs service, it prevents downstream devices from interrupting by pulling its IEO line Low. The next device in the chain then passes this Low condition on to other downstream devices by pulling its IEO line Low, and so on. Whenever an interrupt is acknowledged (Figure 32), the CPU’s interrupt structure is disabled. It must subsequently be reenabled by an enable inter- rupts instruction before other devices can interrupt again. This normally takes place within the interrupt service routine. When done early in the service routine, this permits higher priority peripherals to interrupt the CPU while the latter is still executing that service routine. Thus, nested interrupts

of the lower priority peripheral’s service routine. Figure 37. Interrupt Daisy-Chain for example, connected to a chip select decoder.

Figure 38. Polling for a Service Request Bit transfers. Table 13 describes these states and their substates in detail. command is written by the CPU to the DMA’s Write Register 6 (WR6). output instruction such as OTIR (in the Z80 CPU).

transfers of control bytes from memory to its own internal registers. should be programmed for Mode-2 maskable interrupts. Table 13. DMA Status its BUSREQ input to CPU low). designed for this situation.

Figure 39. Write-Register Pointing Methods

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G1b/G16 Source and Destination Bit 2 indicates the source port and, by implication, the destination port, if the operation is a sequential transfer. When bit 2 is 0, Port B is the source; when bit 2 is 1, Port A is the source. Search-only operations have only a source port. If the operation is a simultaneous transfer or transfer/search (where the class is set to search-only), external hard wiring determines the destination port. The direction of transfer should only be changed from its current setting after the DMA is disabled by writing some other control byte to it. Therefore, the WR0 byte should not be the first byte written to the DMA if changing the direction of transfer. Port A Starting Address If Port A is used for either source or destination, its starting address must be programmed. Set bits 3 and 4 in the base register byte to 1 so that the next two bytes written to the DMA are recognized as the low and high bytes, respectively, of the Port A starting address. This address is interpreted in the context of the entries in WR1 bits 3 through 5, which differentiate the address as either memory or I/O, fixed or variable, and, if variable, incre- menting or decrementing. If Port A is to be a fixed address destination port, see the section following entitled “Fixed-Address Destination Ports.”

Figure 40. Write Register 0 Group page 75 in “Internal Structure” on page 71 describes this (Table 11). which usually results in a transfer or search of two bytes (Table 12).

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G1b/G18 Write Register 1 Group Bits 7, 2, 1, and 0, as Figure 41 illustrates, select the base register byte for this group. The group is used only when Port A is used, for example, do not program it for a search only, simultaneous transfer, or simultaneous transfer/ search with Port B as the source. It specifies the following characteristics: Device Type (Port A) Bit 3 identifies Port A as either memory or I/O. This specification causes the proper control line MREQ or IORQ to come active for cycles involving that port. Variable/Fixed Addressing (Port A) Bits 4 and 5 specify whether the Port A address increments, decrements, or remains fixed for each byte of data transferred or searched. The first byte of data in an operation uses the starting address entered for Port A in WR0. Incrementing or decrementing begins on the second byte of the operation. Variable Cycle (Port A) If bit 6 is set to 0, the DMA’s variable-cycle timing feature is not used; instead, standard Z80 timing for read and write cycles is used, which is described in the “Timing” chapter. If bit 6 is set to 1, the next byte written to the DMA after the WR1 base register byte is the Port A variable-timing byte. This allows the length of the port’s read and write cycles to be shortened. The choices for overall cycle timing of the DMA, including activation of the IORQ ,M R E Q,R D,a n dW Rlines, are specified in bits 1 and 0 as follows: 4 clock cycles 3 clock cycles 2 clock cycles

on “Timing” illustrates and describes the effect of this in detail. edge than the other control lines. Figure 41. Write Register 1 Group

transfer/search with Port A as the source. Its syntax is the same as WR1. Figure 42. Write Register 2 Group

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G1b/G1b Stop on Match Setting bit 2 of the base register byte to 1 causes the DMA to stop and release the bus when a data byte matches the match byte, which is described later. A search or transfer/search operation must be specified in WR0 to make this bit valid when set. If this bit is 0 (no stop on match), a status flag is still set in the status byte when a match occurs and there still remains the option of interrupting on match (see WR4). No stop or interrupt on match in the search class is used to obtain simultaneous transfers without searching actions. Match Byte When bit 4 of the base register is set to 1, the match byte that is compared with every data byte searched must be specified. A search operation must be specified in WR0 to make this bit valid, as shown in the following function. Mask Byte When bit 3 is set to 1, the mask byte must be subsequently specified. Bit positions that contain 1s in the mask byte cause comparisons at those same bit positions in the match byte (see preceding paragraph) to be ignored. For example, if the mask byte is 00001111, only the high four bits of the match byte is compared to the data bytes being searched. Interrupt Enable A 1 in bit 5 of the base register enables the DMA to generate an interrupt. This function duplicates the ENABLE INTERRUPTS command in WR6.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G12/G13 Starting Address (Port B) The starting address for Port B in the next two bytes may be specified by setting bits 2 and 3 of the base register to 1. This is only needed if Port B is used, and then it specifies the first address at which a byte is read from or written to, depending on whether the port is declared a source or destination in WR0. If Port B is to be a fixed-address destination, see “Fixed-Address Destination Ports” on page 121. Interrupts Bit 4 of the base register byte can point to the interrupt control byte, and bits 4 and 3 of the interrupt control byte can point to the interrupt vector and pulse control bytes, respectively. The interrupt control byte also specifies one or more of the following three interrupt conditions:  I n t e r r u p to nm a t c h( b i t0 ) ,i fs t o po nm a t c ho rs t o po ne n d - o f - b l o c ki s also programmed  Interrupt at end-of-block (bit 1), if stop on end-of-block is also programmed  Interrupt on Ready (bit 6), for example, interrupt before requesting the bus when the Ready line becomes active Setting any of these bits to 1 enables the interrupt condition but not the interrupt circuitry itself, which is enabled either through the ENABLE INTERRUPTS command in WR6 or through bit 5 in WR3. Interrupts do not occur on these conditions if their associated bits are 0 in the interrupt control byte. Table 13 and Table 15 in the previous chapter apply to these interrupt conditions because the DMA releases the bus (stops) before inter- rupting the CPU.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G12/G14 Interrupt Vector Bit 4 of the interrupt control byte allows the interrupt vector to be entered. In addition, when bit 5 of the interrupt control byte (Status Affects Vector) i ss e tt o1 ,b i t s1a n d2o ft h ei n t e r r u p tv e c t o ra r em o d i f i e dt or e f l e c tt h e cause of the interrupt (for example, the state of the Ready line or Status latches) before the vector is placed on the data bus in response to the CPU’s interrupt acknowledge. The Status Affects Vector mode must not be used when both Auto Restart and interrupt on end-of-block have been programmed. The interrupt vector sent at the end of each block in this case cannot be modified to reflect the end-of-block status. Pulse Generation Pulse generation is caused by (1) pointing to the interrupt control byte with the base register byte, (2) setting bits 2 and 3 of the interrupt control byte, and (3) entering an offset value in the pulse control byte. The pulse control byte is compared with the lower byte of the byte counter and a pulse is g e n e r a t e do nt h eI N T line whenever a match occurs, which is every 256- byte transfers or searches after the initial offset number of bytes.

Figure 44. Write Register 4 Group

0 Interrupt Control Byte

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G12/G16 End-of-Block Action Bit 5 specifies either a stop (bus release) or an auto repeat at the end of the b l o c kl e n g t hp r o g r a m m e di nW R 0 .T oi n t e r r u p ta tt h ee n do fab l o c k (WR4), bit 5 should be 0 because the DMA must reset the end-of-block status bit to proceed with a new block. In Auto Restart, the end-of-block status bit is also reset. CE /WAIT Line Use Bit 4 specifies that the DMA ’s CE/WAIT line is to be used in one of two ways: CE Only The CE/WAIT line functions only as a chip enable line, allowing CPU writing and reading of control/status bytes when the DMA is not bus master. See the “Applications” chapter for the method by which this time is decoded from the address bus. CE /WAIT Multiplex This line functions as described in “CEonly” above, when the DMA is not bus master. When the DMA has the bus, however, the line allows external Wait inputs from external logic to extend the DMA's cycle programmed in WR1 and/or WR2. See the “Applications” chapter for hardware interfacing of this option. Ready-Line State Bit 3 specifies that the DMA interprets the Ready (RDY) line as active when High or active when Low. This allows flexibility in interfacing to a variety of other devices.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G12/G18  Reinitialize Ports A and B to standard Z80 cycle timing (see WR1 and WR2) At power-up, one reset command is sent to the DMA prior to the initial- ization program. When aborting an operation sequence, sending six reset commands guarantees resetting (this is because WR4 has five associated registers that can potentially be pointed to). The RESET command does not perform a complete DMA reset. For example, it does not reset the read sequence, which is set by the INITIATE READ SEQUENCE command. R e s e tP o r tAT i m i n g( C 7 ) Resets the Port A variable timing byte in WR1 to standard Z80 timing. The RESET command also perform this function. R e s e tP o r tBT i m i n g( C B ) Resets the Port B variable timing byte in WR2 as described in Reset Port A Timing (C7). Load (CF) This command must be used to write new addresses to the address registers (WR0 and/or WR4) or to restart an operation (except Auto Restart) at the same addresses. It loads the contents of both starting-address registers to their associated address counters (Figure 30). It also clears the byte counter associated with the block-length register, and it unforces an internal Force Ready condition. The starting addresses must be written in WR0 and/or WR4 before the LOAD command is written, if they are to differ from the previous starting addresses. Only the source-port address counter is immediately loaded. The desti- nation-port address counter (if used) is loaded during the first count of the destination-port address. If the destination-port address is fixed, this indi-

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G12/G19 cates that it is never loaded. This special situation is discussed in a later section entitled “Fixed-Address Destination Ports.” If the DMA is in an inactive state (Table 15) when the LOAD command is written, another DMA control byte must precede the LOAD. Any other command, such as DISABLE DMA, serves this purpose. Because LOAD unforces a Forced-Ready condition, the LOAD must precede a FORCE READY command when the latter is used. Continue (D3) This command clears the byte counter to zero but leaves the address counters of both ports with their current contents. Transfers or searches continue from where they left off after an ENABLE DMA command, although the byte count starts over. The CONTINUE command is typically used to transfer several blocks to consecutive locations in memory when it is desirable to know when each block has finished transferring. Specifically, an interrupt at the end of each block may be needed. Use this command rather than a LOAD command to transfer the next block after the interrupt. A new block length can be entered in WR0 in conjunction with the CONTINUE command. If the DMA is in an inactive state (Figure 15) when the CONTINUE command is written, another DMA control byte must precede the CONTINUE. Any other command, such as DISABLE DMA, serves this purpose. Disable Interrupts (AF) The command is used in non-Z80 CPU environments to simulate the Z80 CPU’s automatic interrupt acknowledge to the DMA. When the DMA interrupts a non-Z80 CPU, the CPU writes a DISABLE INTERRUPTS to the DMA early in the service routine. This allows the INT line to go inactive but prevents the DMA from sending subsequent interrupts while

Interrupt Under Service (IUS) latches. Figure 46. Write Register 6 Group

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G12/G1b Enable Interrupts (AB) See the preceding description of DISABLE INTERRUPTS. A Z80 CPU environment uses this command at power-up to enable the interrupt logic at the beginning (the DMA comes up with this logic disabled). It is not needed, however, to enable subsequent interrupts because this function is provided for by the CPU’s fetching and the DMA ’s decoding of the RETI instruction. The only exception is when the DISABLE INTERRUPTS command is used; the ENABLE INTERRUPTS command must also be used to begin DMA operations again. Any conditions selected to cause an interrupt are latched in the DMA even when interrupts are disabled. They can then cause a later interrupt after interrupts are reenabled. The ENABLE INTERRUPTS command must not be written until after the DMA has been configured and the REINITIALIZE STA TUS BYTE command has been written. This command has the same effect as writing a 1t ob i t5o fW R 3 . Reset and Disable Interrupts (A3) This command is useful in CPU environments such as the 8080 and 8085 where there is an interrupt acknowledge function but no RETI instruction, as in the Z80 CPU. This command accomplishes four functions:  Resets the Interrupt Under Service (IUS) latch  Resets the Interrupt Pending (IP) latch  Unforces an internal FORCE READY condition  Disables further interrupts by the DMA (same as the DISABLE INTERRUPTS command) In the non-Z80 environment just described, it would be used as follows: after the DMA interrupt is received and acknowledged, the interrupt vector is sent to the CPU, which branches to the service routine. Near the

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G13/G12 end of the service routine, the CPU writes a RESET AND DISABLE INTERRUPTS command, then an ENABLE INTERRUPTS command, and then an ENABLE DMA command before executing its return-from- interrupt instruction. This command, when followed by an ENABLE INTERRUPTS command, takes the place of the Z80 RETI instruction. It is not needed in a Z80 envi- ronment. Because RESET AND DISABLE INTERRUPTS unforces a FORCED-READY condition, the RESET AND DISABLE INTERRUPTS must precede a FORCE READY command when the latter is used. Enable After RETI (B7) T h i sc o m m a n di su s e do n l yw h e nt h eD M Ai so p e r a t e di nt h eI n t e r r u p tO n Ready mode (programmed in WR4). It enables the DMA to request the bus again after returning from an interrupt. This command is always used in Z80 CPU environments to get further bus requesting after an Interrupt on Ready. It is sometimes used in other environments, such as the 8080. An Interrupt on Ready (IOR) latch is set during such an interrupt. This latch prevents the DMA from requesting the bus from the time the Ready line goes active until the time the latch is reset by the ENABLE AFTER RETI command (in Z80 and some other environments, there is an overlap in bus- request prevention by the IOR and the IUS latches). In a Z80 CPU interrupt service routine, the order of DMA commands and CPU instructions MUST be: 1.  2.  3.  4. ENABLE AFTER RETI command 5. ENABLE DMA command

byte, which is illustrated in “Read Registers” on page 114. the read mask) must be completed before issuing this command. Table 14. Reinitialize Status Byte

0 I/O DMA operation has/has not occurred

1 I/O Ready line active/inactive

2 X Undefined bit

6 X Undefined bit

7 X Undefined bit

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G13/G14 the DMA, reinitialization of the status bits may remove the condition that stopped the DMA and the DMA might immediately request the bus again if it is not disabled. (The REINITIALIZE STATUS BYTE command in WR6 is similar in this respect to the WR0 byte when transfer direction is being changed: both of these control bytes must be preceded by some other control bytes to ensure that the DMA is disabled.) The interrupt pending status (bit 3) of the status bytes can be reinitialized by acknowledging the interrupt, servicing it, and writing a RESET AND DISABLE INTERRUPTS command. The DMA operation status (bit 0) can be reinitialized with a LOAD command. Read Mask Follows (BB) This command points to the read mask (Figure 46). It allows the next control b y t ew r i t t e nt ot h eD M At og ot ot h er e a dm a s kr e g i s t e r .T h er e a dm a s ki s used to set a new sequence, for reading the read registers, RR0 through RR6, and it is normally part of the power-up initialization of the DMA. The read registers are always read in a fixed sequence beginning with RR0 and ending with RR6. However, the registers read in this sequence can be limited by programming the read mask. The read mask is programmed with 1s in the bit positions associated with the registers to be read. For example, if the read mask contains 00011001 , the following read registers are read in the following order: 1. Status byte (RR0) 2. Port A address counter, low byte (RR3) 3. Port A address counter, high byte (RR4) When the read mask has been programmed, it must be initialized to begin at the lowest-order register selected. Do this with the INITIATE READ SEQUENCE command.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G13/G15 Initiate Read Sequence (A7) This command initiates the read-sequence pointer command, allowing the next CPU read instruction to the DMA access to the first (low-order) read register designated as readable by the read mask. When started, the read sequence specified by the read mask must be completed before, for example, giving another INITIATE READ SEQUENCE or a READ STATUS BYTE command. Registers do not need to be read immediately after writing the INITIATE READ SEQUENCE command. Other commands (except INITIATE READ SEQUENCE and READ STATUS BYTE) can be written and can go through bus-request/bus release cycles before executing the first read and subse- quent reads. Force ReadY (B3) This command, in Burst or Continuous mode, forces an internal Ready condition to take the place of an external active Ready signal. It is used for memory-to-memory transfers and memory searches where no Ready line is necessary. Ready active High/Low (bit 3 of WR5) need not be considered when this command is used. The FORCE READY condition is unforced by the following commands and conditions:  RESET command  LOAD command  RESETANDDISABLEINTERRUPTS command  End-of-block termination  Byte-match termination  Bus release by DMA Because bus release by the DMA unforces the Ready condition, this command allows the DMA to transfer only one byte in the byte mode.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G13/G16 Enable DMA (87) This command allows the DMA to request the system bus and proceed with its operation if all other functional conditions are met, for example, if the Ready line is active or the FORCE READY condition is present. This command, and bit 6 of WR3, are the only control bytes that do not disable the DMA. All other control bytes written to the DMA automatically disable the DMA. Therefore, the ENABLE DMA command is always required as the last command after writing or reading any other bytes to or from the DMA. This command enables the DMA ’s bus request logic. It does not affect interrupt logic and it does not reset any functions or latches. This bus- request-enabling function is duplicated in bit 6 of WR3. In an interrupt service routine, the ENABLE DMA command must be the last command to the DMA before the CPU executes its return-from- interrupt instruction. Disable DMA (83) This command prevents the DMA from requesting the bus. It is used to stop DMA action for external reasons, such as a pending power-out, and in the special case of reinitializing the status byte after a stop on end-of-block or a stop on byte match (see the REINITIALIZESTATUSBYTE command). Read Registers Process Read registers by first writing a command to the DMA, then by reading either immediately or later. Accomplish CPU reads by addressing the DMA as an I/O device using input instructions (such as INIR for the Z80 CPU). Commands written to the DMA can be either of the following:

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G13/G17 Read Status Byte This command causes the next CPU read of the DMA to access the status byte, which is the first read register. Initiate Read Sequence This command initializes access to a repeatable series of reads that follow the sequence defined in the read mask. These commands are described in the immediately preceding pages, and Figure 46 illustrates the read mask. As mentioned in the description of these commands, the reading of registers do not need to be contiguous in time with these write commands or with other CPU read instructions accessing registers in the same read sequence. Two other commands are also related to the read registers: Reinitialize Status Byte This command reinitializes bits 4 and 5 of the status byte to 1s. Read Mask Follows This command allows the read mask to be programme. Figure 47 illustrates more clearly the group of the seven read registers in relation to the write registers. The read registers include: Status Byte (RR0) The status byte can be read independently from the other read registers and two of its bits can be reinitialized to identify end-of-block and match bytes. The bits in the status byte are defined as follows:

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G13/G18 Bit 0 Indicates whether the DMA has requested the bus after the fast LOAD command. 1 indicates yes, 0 indicates no. Bit 1 Indicates whether the DMA ’s RDY pin currently has a signal input that is defined as active by bit 3 of WR5. 1 indicates an active Ready line. 0 indicates an inactive Ready line. Bit 2 Undefined. Bit 3 Indicates the state of the Interrupt Pending (IP) latch. A 0 indicates that an interrupt is pending (the DMA has its INT line active if the interrupt has not been acknowledged). A 1 indicates no interrupt pending. Bit 4 A 0 indicates that a match has been found after the last RESET or REINITIALIZE STA TUS BYTE command. A1 indicates no match was found. See Table 11 to determine where the match occurred. Bit 5 A 0 indicates that an end-of-block was reached after the last RESET, LOAD, CONTINUE, or REINITIALIZE STA TUS BYTE command. A 1 indicates no end-of-block was reached. See Table 12 to determine the contents of counters when the DMA stops. Bit 6 Undefined. Bit 7 Undefined.

Figure 47. Read Register 0 through Read Register 6 it starts, even when stopping on byte matches in transfer/search operations.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G13/G1a Table 11 and Table 12 illustrate how the pipelining of data affects the number of bytes transferred or searched in the various classes, modes, and circumstances of operation. In most cases, the number of bytes transferred in a transfer operation that stops at end-of-block is one more than the programmed block length. When the pulse-generation feature is used, the contents of the pulse control byte in WR4 are compared with the lower byte of the byte counter after each byte is transferred. Port A Address Counter (RR3, RR4) This 16-bit counter is loaded from the Port A starting address register in WR0 by the LOAD command. It increments, decrements, or remains fixed according to the specifications in WR1. Table 11 and Table 12 show how this counter reads under various transfer or search conditions. Port B Address Counter (RR5, RR6) This counter is identical to the Port A address counter just described. If either Port A or Port B is a fixed-address destination port, it must be programmed as described in “Fixed-Address Destination Ports” on page 121 to function properly. Review of Programming Sequences This section describes programming the DMA in both the general and in application-specific cases. Also, see Table 16 on page 127 for a sample DMA Program. DMA Initialization Program all registers to be used in the DMA at power-up. None of these registers contain useful defaults. This procedure includes the enabling of

of the control bytes are written. only occur when the CPU is bus master. Table 15. Control Byte Order

Table 15. Control Byte Order (Continued)

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G14/G13 Address Loading Write starting addresses to the starting-address registers for each port using WR0 (Port A) and WR4 (Port B). They are loaded to the address counters by the LOAD command. The addresses must he written to the registers before they are loaded to the counters. New addresses may be written to the address registers at any time when the CPU is bus master, even between transfers and even when the DMA is oper- ating in the Auto Restart mode, for example, in Byte mode between byte transfers. With the exception of the Auto Restart mode, the new addresses must be reloaded before they are used. If a Forced-Ready condition is used, the LOAD command must precede the FORCE READY command. Fixed-Address Destination Ports A special circumstance arises when programming a destination port to have a fixed address. The load command in WR6 only loads a fixed address to a port selected as the source, not to a port selected as the destination. Therefore, a fixed-destination address must be loaded after temporarily declaring its port as a source port. The true source port is subsequently declared (making the other port a destination) and the true source address is then loaded. The following example describes the steps in this procedure, assuming that transfers are to occur from a variable-address source (Port A) to a fixed- address destination (Port B). 1. Write Port B (fixed destination) address to WR4. 2. Temporarily declare Port B as source in WR0 (bit 2 = 0). 3. Load Port B address with the LOAD command. 4. Write Port A (variable source) starting address to WR0. 5. Declare Port A as source in WR0 (bit 2 = 1). 6. Load Port A address with the LOAD command.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G14/G14 7. Enable DMA with the ENABLE DMA command. Interrupts The interrupt vector (WR4) must be written before interrupts using it can occur, and interrupts must be enabled with the ENABLE INTERRUPTS command at initialization or reinitialization. In a Z80 CPU environment, interrupt service routines after DMA initialization usually include the following commands at the end of the routine: 1. Interrupt on End-of-Block or Byte Match ENABLE DMA command RETI instruction 4. Interrupt on Ready (before requesting the bus)

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G14/G15 5. ENABLE AFTERRETI command 6. ENABLE DMAcommand 7. RETI instruction Interrupts at end-of-block, for example, might occur when reading a floppy disk. If the disk transfers 128-byte records, the DMA can be made to interrupt at the end of each record to notify the CPU of its completion. Then the CPU can read the destination (memory) address counter to find the last memory location filled. See Table 12 for address-counter contents. A service routine for continuing inputs to contiguous locations of memory typically contains the CONTINUE, REINITIALIZESTATUS BYTE,a n dENABLEDMA commands before the CPU’s return from interrupt. A service routine for shutting down the DMA after the record arrives typically includes DISABLE DMAand REINITIALIZE STATUS BYTE commands. If the DMA transfer is started by an interrupt from another device, the service routine for that other device includes an ENABLE DMAcommand written to the DMA’s port address. Interrupts on byte match (a search or transfer/search operation) can be implemented so that any ending byte, error indicator, or other character causes the interrupt. This procedure frees the CPU from looking for these characters in a stream of data, increases throughput, and reduces CPU software complexity. For example, the DMA might search for end-of-text (EXT) characters or carriage returns in a communications environment and interrupt the CPU only when the complete message frame has arrived. The service routines for this would be very much like those for interrupts on end-of-block. Interrupts on Ready are somewhat different. First, the DMA cannot be the bus master before the interrupt because the CPU only senses interrupts when the CPU is the bus master (the other types of interrupts are not

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G14/G16 processed until the bus is released). Second, to enable the DMA, the ENABLEAFTERRETI command must be used in the service routine after an Interrupt on Ready. The typical purpose of interrupting when the Ready line comes active is to allow the CPU time to determine where a transfer should go, which it does in the service routine. This often occurs in systems with dynamic memory allocation and it improves the efficiency with which memory can be allocated. For example, the CPU might write and load new starting addresses for a memory destination to the DMA in the service routine. Only at the end of the service routine is the DMA enabled to request the bus. The ENABLEAFTERRETI command, which must precede the ENABLEDMA command, resets a latch that is set when the Interrupt on Ready first occurred. For non-Z80 CPU environments, the DISABLEINTERRUPTS , ENABLE INTERRUPTS,a n dRESETANDDISABLEINTERRUPTS commands are available. They can simulate the Z80 CPU’s interrupt-acknowledge cycle and return-from-interrupt instruction, both of which the DMA needs to perform and return from interrupts. Byte Matching (Searches) In stopping, or stopping and interrupting on match (WR3, WR4), to perform additional operations with the DMA, the following sequence of commands are written: LOAD or CONTINUE. 2. REINITIALIZE STATUSBYTE. 3. ENABLE DMA. Another command (with the exception of ENABLEDMA ) must precede the REINITIALIZESTATUSBYTE command. Table 11 on page 76 describes the contents of various counters when stopping on byte match.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G14/G17 End-of-Block After a stop or stop and interrupt on end-of-block (WR4 or WR5), where it is necessary to perform additional operations with the DMA, write the same sequence of commands listed immediately under “Byte Matching (Searches)” on page 124. Table 12 on page 76 describes the contents of various counters when stopping on end-of-block. Auto Restart To obtain a repetitive transfer or search using the same block length and starting addresses originally entered, initialize the DMA including WR% bit 5 = 1. Loading of addresses and clearing of the byte counter is auto- matic. When in Byte mode (or Burst mode where the Ready line is occasionally released), it is possible to alter the starting addresses during a transfer (for example, between bus requests) without disturbing that transfer. At the end of this transfer, the DMA automatically loads the new addresses to the counter and continues without interruption. Force Ready Condition The FORCEREADY command is provided for operations such as memory-to- memory transfer or memory search-only where no Ready line from an I/O device is used. However, several DMA commands unforce the Ready condition after the FORCEREADY command is written. The sequence of command entry is therefore important. This sequence is described in the FORCEREADY command in “Write Register 6 Group” on page 105. Pulse Generation To obtain pulses at 256-byte intervals, after a variable offset period, consider only the WR4 group. The INT line is used for these pulses.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G14/G18 Variable Timing The timing on the RD,W R,M R E Q,a n dI O R Qlines can be varied indepen- dently for either port by programming the WR1 and/or WR2 register groups. When programming memory-to-I/O, I/O-to-memory, or I/O-to-I/O sequential transfers or transfer/searches, the IORQ line must be programmed in a specific way. See “Variable Cycle (Port A)” on page 96. Enabling the DMA The last command written to the DMA before an operation occurs must be the ENABLEDMA command, or WR3 bit 6 = 1, which is equivalent. Only this command makes the DMA operate. If all other conditions for operation are satisfied at the time of enabling (for example, the Ready line is active) the DMA begins immediately. In an interrupt service routine, the ENABLE DMAcommand must be the last DMA command written before the return from-interrupt instruction. Other instructions usually follow theENABLE DMAcommand in the service routine before theRETI instruction is executed, but none of these commands affect the DMA. Reading Status These two commands allow the CPU to read DMA status: READ STATUS BYTE Causes the next CPU read of the DMA to access the status byte. Every time the status byte is to be read, theREADSTATUSBYTE command must first be written. INITIATE READ SEQUENCE Causes the next CPU read of the DMA to access the first status register specified as readable by the read mask. Subsequent reads of the DMA, which must complete the sequence of all designated readable registers, do not require write commands. Reading of the sequence of registers must be

instruction such as the Z80 CPU’s OTIR instruction. Table 16. Sample DMA Program

01 C 5

Table 16. Sample DMA Program (Continued)

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G14/G1b Note: The actual number of bytes transferred is one more than specified by the block length. * These entries are necessary only in the case of a fixed destination address. Z80 DMA and CPU As a member of the Z80 Family, the Z80 DMA’s signals and timing are compatible with those of the Z80 CPU. As bus master, the DMA has read- and write-cycle characteristics identical to those of the Z80 CPU, thereby simplifying system design. In addition, variable timing features allow the system designer to interface memories and I/O devices more easily with non-standard capabilities or requirements. The DMA can shorten its read- or write-cycle timings for higher performance or lengthen and tailor control signals to accommodate slower devices. Because these features are under programmed control, the hardware configuration is not affected by changes in cycle and control signal timings. Interconnection In small systems, or where the Z80 DMA shares a board with the CPU, most of the pins on the DMA may be connected directly to the corre- sponding CPU pins. These pins include the address bus (A15-A0), the data bus (D7-D0), and the control signals MREQ ,I O R Q,R D,a n dW R.T h e interrupt request and bus request signals, INT and BUSREQ, may also be connected directly to the CPU, in common with corresponding open-drain outputs from other devices. The priority daisy-chains for these functions are described in an earlier chapter and are illustrated in Figure 31 and Figure 37. Power, ground, and clock signals are also common to the CPU and DMA, but extra care must be taken to provide low impedance paths and adequate decoupling. A 300 Ohms pull-up from a TTL clock driver output may be adequate for small systems operating at the 2.5 MHz rate, but the increased loadings and speeds in larger high-performance systems require active pull-

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G15/G13 Figure 49c depicts a one-of-eight TTL decoder which provides chip enable signals for eight different peripheral devices. Address bits A0 and A1 are often used directly by peripherals such as the Z80 SIO, PIO, and CTC, and so are not decoded here. Additional decoders can be added when more peripheral devices are present. IORQ and M1 are internally gated with CE in Z80 peripheral devices and need not be terms in CE. However, gating chip-enable signals with these control lines do no harm and may produce less-ambiguous logic sequences for circuit-level debugging, as seen in Figure 49c.

Figure 49. Chip Enable Decoding with Z80 CPU

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G15/G15 CPU has relinquished the bus. Therefore, if this DMA is bus master, it samples the WAIT signal for these requests. A simple 2-input multiplexer steers the CE/WAIT s i g n a l sa sd e p i c t e di nF i g u r e5 0 .U s i n gB U S A C K assumes that there is only one DMA. In systems with three or more possible bus masters, BAl active and BAO inactive identify the master. Simultaneous Transfers The highest-speed DMA transfer method is the simultaneous transfer method, or flyby method. This requires some external hardware to generate simultaneous read- and write-control signals to the source and destination ports. Because the address bus is used for memory address, only transfers between I/O and memory can be accomplished directly when the I/O port selection is performed by hard wiring. The DMA is put into search mode, and a circuit, such as that illustrated in Figure 51, generates separate simul- taneous read- and write-control signals, which may be ORed into the read- and write-control paths at memory and I/O. Figure 52 depicts such an arrangement. This arrangement allows both the CPU and DMA access to the I/O peripheral. (If the peripheral communicates only through DMA, it only needs to use the IORD and IOWR signals.) Pay careful attention to access, setup, and hold times in this mode. Because the DMA is programmed to do searching, the MWRand IOWR signals are derived from the DMA RDsignal and mimic its timing. This does not cause a problem for write operations, which are trailing edge activated. To make MWR appear more like a CPU or DMA write cycle signal, the circuit of Figure 50 may be used to delay the leading edge of MWR until after the falling edge in T2. The programmable variable timing features of the DMA may be useful, too.

Figure 52. Simultaneous Transfer

Figure 53. Delaying the Leading Edge of MWR bility and noise margin and to decrease delay times. each card’s bus interfaces require buffering.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G15/G19 (floated) in a manner similar to the CPU and DMA address pins. For example, in a system with one CPU and one DMA, the BUSACK signal can disable CPU buffers and enable DMA buffers when it is active. Where there are three or more potential bus masters, only those buffers associated with the actual bus master must be active at any time. Therefore, each DMA, if its BAI signal is active (Low) and its BAO signal is inactive (High), has control of the bus and can enable its drivers. Data bus lines are bidirectional, making their buffer control more compli- cated. Any device from which the CPU can read drives the data bus when it is selected and the RD control signal is active. In this sense, the RD signal is the principal directional control. Non-CPU devices also drive the data bus during interrupt-acknowledge cycles in which the device puts its vector on the bus and during DMA write cycles. Figure 54 illustrates a bidirectional data bus buffer and its control. Here, Z80 SIC, PIO, CTC, and DMA peripherals share a circuit card. Their common on-card data bus is buffered to and from the system (motherboard or backplane) bus. Each of the three conditions mentioned causes the buffers to drive data out onto the system bus; otherwise, data is buffered into the card. Suitable devices for bidirectional buffering include the 74LS241 (tristate bus drivers) and 74LS245 (transceivers). The control signals MREQ ,I O R Q,R D,a n dW Rshould be unidirectionally buffered in large- or multi-card systems. These signal buffers are, again, enabled when their associated device or card has bus control and are forced into high-impedance states when another master takes control of these bus lines. Because there are short intervals during transfer of the bus (when the bus is not driven by any master), MREQ ,I O R Q,R D,a n dW Rshould be pulled up to + 5V with 2.7 Kohms to 4.7 Kohms resistors so that they remain inactive. Other control signals on CPU and DMA may be perma- nently driven. This usually includes M1, RFSH,a n dH A L Tfrom the CPU, and BAO from a DMA. The BUSREQ line is bidirectional and cannot easily be externally buffered. However, the DMA can sink 3.2 mA on BUSREQ,m o r et h a no no t h e r

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G15/G1a signals. To maximize current, the system’s BUSREQpull-up resistor can be as low as 1.8 Kohms. TTL buffers and drive capacitive loads While the DC output ratings of standard buffers such as the 74LS367 are usually ample, propagation times through these buffers are rated at capac- itive loadings of only 30 pF, a value easily exceeded in practice. Capacitive loading thus usually dominates bus driving requirements. Z80 Family parts are specified over ranges of capacitive loading. The load seen by a device driving a bus line has components due to wiring and printed circuit land capacitance, connector capacitance, and capaci- tances of inputs and outputs connected to the signal. A standard low-power Schottky (LS) TTL input presents about 6 pF of capacitive load, an LS output of about 8 pF. Most other input and output capacitances can be esti- mated from device data sheets, but capacitance associated with intercon- nection may vary markedly. Sometimes, propagation delays and allowable capacitive loading for buffered lines must be determined by measurement or by trial and error.

Figure 54. Data Bus Buffer Control Example is busy transmitting or receiving message bits and requires no service. to the DMA, which is programmed for active-Low RDYin Byte mode.

Table 17. Receive Event Sequence Table 18. Transmit Event Sequence

whenever it has received a character or needs another character to transmit. below.The numbers in parentheses are clock periods per instruction. activity by permanently occupying the alternate register set. Table 18. Transmit Event Sequence (Continued)

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G16/G14 represent the fractional reductions in CPU throughput per Kbaud trans- ferred. The DMA has a shorter and more predictable latency period and decreases system overhead by at least a factor of five in this conservative example. A diagram of a typical Z80 system using a Z80 CPU, a Z80 CTC for asyn- chronous baud rate generation, both channels of a Z80 SIO, and two Z80 DMAs (one for each serial channel) appears in Figure 55. The diagram omits the system memory (ROM and RAM), bus buffers (as required), and chip enable decoders, which are described above. Z80 (2.5 MHz) Z80A (4 MHz) DMA sequential transfer 0.065% 0.041% DMA sequential transfer/search Interrupt-driven transfer 0.340% 0.213%

Figure 55. DMA-SIO Environment

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G16/G16 the Z80 bus, to function. These functions are described in the following sections, and design solutions are offered:  Bus request/release mechanisms  Bus characteristics  Interrupt request, acknowledge, and return Bus Request/Release Mechanisms The most fundamental characteristic that distinguishes the Z80 DMA from other monolithic DMACs is its full control of the system bus during its active state. Therefore, processors using the DMA must be able to give up control of the system bus, including address, data, and the control lines MREQ ,I O R Q,R D,a n dW R(or their equivalents). Some processors have no mechanism for freeing the bus. Others, including the 6800, have rudi- mentary bus control facilities, but because of their internal dynamic logic implementations, cannot relinquish control for indefinite periods of time. This makes them difficult to interface to the DMA. Many popular microprocessor CPUs, however, do have adequate bus control facilities, and some are very similar to the Z80 BUSREQ and BUSACK signals. For instance, the 8080, 8085, and 8086 signals HOLD and HLDA are very close approximations. The active levels of HOLD and HLDA are positive rather than negative, and variations exist in timing. But the use of HOLD and HLDA allows the address and data bus drivers to be put into their high-impedance states. In 8080 systems using an 8238 to demultiplex commands, the MEMW MEMR,I O W ,and IOR control lines can be floated using the BUSEN input. With the 8085, a tristate decoder allows decode or disable corre- sponding signals. The 8086 and its support chips also tristate their control signals when HLDA is active.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G16/G17 Bus Characteristics Similar to the Z80, the 8080 and 8085 have 8-bit data paths and 16-bit addresses. The DMA is matched well to these numbers; it can search whole data words and directly address any byte in the memory. The 8086 and the Z8000 CPUs have 16-bit data paths and larger address spaces, thus making it somewhat harder to use the Z80 DMA. Searching can be done for match bytes in either half of the data word, but not for a whole unique word. Often this is not a problem because byte matches suffice, for example, in detecting special ASCII characters in a data block. The problem of larger address spaces can be resolved by using an external segment or page register, latched to the appropriate high-order addresses before the DMA becomes bus master, or by other schemes such as indexing. This requires some external hardware. To conserve pins, the 8085, 8086, Z8001, and Z8002 multiplex addresses and data. Strobes allowing demultiplexing then become part of the bus structure and must be accounted for in DMA interface. In such cases, the DMA should be connected to the demultiplexed address and data lines rather than closer to the processor. Figure 56 is a simplified diagram of this concept.

Figure 56. Connecting DMA to Demultiplexed Address/Data Buses decoders to float the outputs when the DMA is master. the DMA may well reduce the hardware costs incurred. responding to, and returning from interrupts.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G16/G19 Non-Z80 interrupt environments do not use the IEI and IEO signals, and often they use separate interrupt controllers to generate vectors, and handle acknowledgement and return in different ways, or not at all. Interrupt request is usually easy: active levels typically are low voltage, and there may be one or more separate interrupt request pins. Timing require- ments for interrupt requests are varied and may including pulse widths, latching, and more, and must be carefully examined. Priority of simultaneous or overlapping requests is handled in several ways: some processors (for example, the 8085) have multiple interrupt-request pins, some use daisy-chained priority schemes (as in the Z80), and several types of interrupt control ICs are available. Acknowledgement and identification methods vary too. Sometimes, several fixed memory locations correspond to different interrupt pins’ service routines. In other cases, the interrupting device identifies itself by putting a vector or instruction on the data bus for the CPU to read. Interrupt controllers often provide appropriate vectors to the CPU and distinguish between and prioritize multiple requests. The DMA has the built-in capa- bility of supplying an arbitrary vector byte when it detects a Z80 interrupt acknowledge (IORQ and M1 both active) and its IEI input is active (no higher-priority device is interrupting). Often, then, gating the M1,I O R Q, and IEI pins appropriately can rule out using a separate interrupt controller. IORQ serves another function, too, therefore it must appear during CPU- DMA transfers and be available to signal I/O reads or writes in the active state. At the end of its service routine, the DMA anticipates the CPU fetching the RETI instruction (ED, 4D present on the data bus accompanied by M1) The DMA command RESET AND DISABLE INTERRUPTS is designed for this purpose in non-Z80 CPU environments. Alternatively, the RETI i n s t r u c t i o nm i g h tb es i m u l a t e db yr e - g a t i n gM 1and programming the CPU to write to a phantom peripheral the bytes ED, 4D. The chip select for this nonexistent peripheral is used to simulate M1. S e eF i g u r e5 7 .

Figure 57. Z8000/Z80 Peripheral Interface

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G16/G1b PERFORMANCE LIMITATIONS Bus Contention Using the Direct Memory Access (DMA) as bus master can negatively effect CPU activity by preventing the CPU from fetching and executing instructions. This method of bringing the CPU to a halt creates problems, including:  No interrupt servicing (including nonmaskable CPU interrupts)  No refresh of dynamic memory (if performed by the CPU)  No polling The CPU’s time-critical functions are affected by which operating mode the DMA is using. These modes are Byte, Burst, and Continuous. Byte Mode When bus contention occurs, using Byte Mode allows interleaving of CPU functions and DMA functions for each byte of data transferred. The disadvantage to using this mode is slower transfer speed. Burst Mode Burst mode is useful when transferring data in short segments over a longer period of time. This mode has the advantage of using the bus only when needed. During those times, transfer speeds are maximized. However, this mode may not be suitable for extended bursts of data (long periods when the Ready line is active). Burst mode allows the DMA to release the bus back to the CPU before other CPU-dependent functions are compromised.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G17/G13 System throughput is decreased for applications requiring frequent DMA reprogramming or extensive interrupt service of data-independent DMA functions. It is more efficient to transfer large blocks of repetitive data. TIMING The CPU As Bus Master When the CPU is the bus master, control bytes can program the Direct Memory Access (DMA). Writing Control Bytes Table 13 illustrates the disabled, enabled/inactive, or enabled/stopped states. The enabled/inactive and enabled/stopped states are equivalent. The DMA is programmed by being addressed as an I/O peripheral in a CPU output instruction. The DMA can be addressed in the full 64K I/O space. To accomplish this, three lines must be simultaneously active-Low on the ris- ing edge of the clock: CE Chip Enable IORQ Input/Output Request WR Write Figure 59 illustrates the timing required for this process. In a Z80 CPU environment, this timing occurs automatically when the CPU and DMA are on the same board and have no buffers, drivers, or other external gates in series with the common CPU and DMA pins. This timing applies to the sequential transfer, sequential transfer/search, and search-only classes of operation. It may or may not apply to the simultaneous transfer or simulta- neous transfer/search operations, depending on the speed of the external devices used (see the Applications chapter).

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G17/G16 Simultaneous Transfers The timing for simultaneous transfers and simultaneous transfer/searches is the same. The DMA is programmed in the Search-Only mode, and both read and write cycles occur simultaneously in the time that a source-port read would occur in search-only. Only one address is generated on the address bus; the I/O port is hardwire-selected during this operation as shown in the Applications chapter. The IORQ ,M R E Q,R D ,and WR lines are gated into two new signals by external logic. These signals are either: MEMWR (Memory write) IORD (I/O read) or: MEMRD (Memory read) IOWR (I/O write)

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G17/G17 Figure 61.Sequential Memory-to-I/O Transfer, Standard Timing (Searching is Optional) CE /WAIT D7–D0 Memory Drive DMA DMA Drives Data Bus WR IORQ RD MREQ READ WRITE A15–A0 CLK Memory Read I/O Write T1 T2 T3 T2 TW T3T1

Figure 62. Sequential I/O-to-Memory Transfer, Standard Timing

Figure 63. Simultaneous Memory-to-I/O Transfer (Burst and Continuous

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G17/G1b inactive, are caused by the activity on the BUSREQand BAI lines, which is explained later. Search-Only The standard timing for search-only operations is identical to the read cycles of Figure 61 and Figure 62. Search-only is equivalent to read-only. Data is read to a DMA register for comparison with the match byte. Bus Requests Figure 65 illustrates the bus request and acceptance timing. The RDY line, which may be programmed active High or Low, is sampled on every rising edge of CLK. If the RDY line is active, and if the bus is not in use by any other device, the following rising edge of CLK drives BUSREQ Low. After receiving BUS- REQ the CPU acknowledges on its BUSACK, which is connected to the DMA’s BAIinput either directly or through a multiple-DMA daisy-chain. The CPU checks its BUSREQ input one clock cycle before the end of each CPU machine cycle. If the CPU detects a request, it releases the bus at the end of that same machine cycle. The maximum time delay between the CPU receiving BUSREQ and the response on its BUSACK line is one machine cycle plus slightly less than one clock cycle. The CPU tristates all its bus control lines when it acknowledges on the BUSACK line. M1 is not tristated. The RDY line, which has a specified setup time with respect to a rising edge of CLK, must remain active until after the DMA becomes bus master in Byte or Burst modes.

Figure 65. Bus Request and Acceptance Timing but does not begin operations. CLK, the DMA begins transferring data on the next rising edge of CLK. occur between each byte transferred. because the CPU cannot begin an operation until the following clock cycle. clock-cycle less time needed for a byte transfer.

Figure 66. Bus Release in Byte Mode cycle after BUSREQ returns High. Bus Release on End-of-Block.

sequential transfer or transfer/searches (Figure 68). Figure 68. Bus Release on Match (Burst and Continuous Modes) transferred in any class or mode.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G18/G15 search (Figure 69). The action on BUSREQis thus somewhat delayed from action on the RDY line. The DMA always completes the current byte oper- ation in an orderly fashion before releasing the bus.Figure 69. Bus Release on Not Ready (Burst Mode) By contrast, BUSREQ is not released in Continuous mode when RDY goes inactive. Instead, the DMA idles after completing the current byte opera- tion, awaiting an active RDY again. Figure 70, Figure 71, and Figure 72 review the relationship between the Ready line going inactive and the state of the other lines for each mode of operation, assuming a search-only of memory using standard Z80 timing. The timing for Ready coming active is discussed under Bus Request. RDY is sampled on the rising edge of CLK in the last clock cycle of each read or write cycle. It is a level-sample, not an edge-sample. RDY can go inactive prior to the completion of the last byte operation without disturbing that operation. At the end of that operation, the BUSREQ and BAI lines go High in Byte or Burst mode according to Figure 68 and Figure 71. The bus control lines MREQ,I O R Q,R D,a n dW R ,also remain High in Byte and Burst mode during an inactive RDY, with both the address and data buses tristated. The Continuous mode (Figure 72) is different because the address bus holds the pre incremented address for the next byte throughout the time that RDY is inactive. This address is immediately available when RDY comes active again. BUSREQ RDY DMA Inactive Active Inactive CLK Current Byte Operation

Figure 70. RDY Line in Byte Mode

Figure 71. RDY Line in Burst Mode

Figure 72. RDY Line in Continuous Mode (read) port and destination (write) port, can be independently programmed. independently terminated one-half cycle early. See Figure 73 .

RDY line before stopping on end-of-block or byte match. Figure 74. WAIT Line Sampling in Variable-Cycle Timing for the ripple signals to stabilize and identify what I/O device must respond. Refer to the Z80 CPU User’s Manual for more details.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Direct Memory Access /G13/G18/G1b Interrupt on RDY (interrupt before requesting the bus) does not directly affect the BUSREQ line. Instead, the interrupt service routine may handle this by issuing the following commands to WR6:  Enable after Return From Interrupt (RETI) Command — B7H  An RETI instruction that resets the Interrupt Under Service (IUS) latch in the Z80 DMA — EDH, 4DH. Pulse Generation When the pulse generation option is selected, the INT line is driven Low every 256 bytes after the offset value. The line goes Low during the DMA cycle in which the pulse-control byte matches the lower byte of the byte counter, and it remains Low for one complete transfer cycle. A transfer cycle is defined as either a read cycle (search-only or simultaneous transfer operations) or a read plus a write cycle, where read and write cycles can be independently programmed for length through the variable-cycle option.

Figure 75. Interrupt Acknowledge

Figure 80. Write Register 4 Group

Figure 83. Read Register 0 through 6 Bit Functions

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Direct Memory Access /G13/G19/G18

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G13/G19/G17 Parallel Input/Output OVERVIEW The Z80 Parallel Input/Output (PIO) Circuit is a programmable, two-port device that provides a TTL-compatible interface between peripheral devices and the Z80 CPU. The CPU configures the Z80 PIO to interface with a wide range of peripheral devices with no other external logic required. Typical peripheral devices that are fully compatible with the Z80 PIO include most keyboards, paper tape readers and punches, printers, and PROM programmers. The Z80 PIO package is available in 40-pin DIP, 44- pin PLCC, or 44-pin QFP . The CMOS version is available in all three pack- age configurations. The NMOS version is available in 40-pin DIP and 44- pin PLCC. One unique feature that separates the Z80 PIO from other interface control- lers is that all data transfers between the peripheral device and the CPU is under total interrupt control. The PIO interrupt logic allows full use of the efficient interrupt capabilities of the Z80 CPU during I/O transfers. All logic necessary to implement a fully nested interrupt structure is included in the PIO, requiring no additional circuits. Another unique feature is that the PIO can be programmed to interrupt the CPU on the occurrence of speci- fied status conditions in the peripheral device. For example, the PIO can be programmed to interrupt when any specified peripheral alarm conditions occur. This interrupt capability reduces the amount of time spent by the pro- cessor polling peripheral status.  Two independent 8-Bit bidirectional peripheral interface ports with handshake data transfer control  Interrupt-driven handshake for fast response

Figure 1. PIO Block Diagram

8 Data or Control

Figure 2. Port I/O Block Diagram fied state (either High or Low).

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G13/G19/G1b The interrupt control logic section handles all CPU interrupt protocol for nested priority interrupt structures. The priority of any device is determined by its physical location in a daisy-chain configuration. Two lines are provided in each PIO to form this daisy-chain. The device closest to the CPU has the highest priority. Within a PIO, Port A interrupts have higher priority than those of Port B. In the byte input, byte output or bidirectional modes, an interrupt can be generated whenever a new byte transfer is requested by the peripheral. In the bit control mode an interrupt can be generated when the peripheral status matches a programmed value. The PIO provides for complete control of nested interrupts. That is, lower priority devices may not interrupt higher priority devices that have not had their interrupt service routine completed by the CPU. Higher priority devices may interrupt the servicing of lower priority devices. When an interrupt is accepted by the CPU in Mode 2, the interrupting device must provide an 8-bit interrupt vector for the CPU. This vector is used to form a pointer to a location in the computer memory where the address of the interrupt service routine is located. The 8-bit vector from the interrupting device forms the least-significant eight bits of the indirect pointer while the I Register in the CPU provides the most-significant eight bits of the pointer. Each port (A and B) has an independent interrupt vector. The least-significant bit of the vector is automatically set to a 0 within the PIO because the pointer must point to two adjacent memory locations for a complete 16-bit address. The PIO decodes the RETI (Return from interrupt) instruction directly from the CPU data bus so that each PIO in the system knows at all times whether it is being serviced by the CPU interrupt service routine without any other communication with the CPU.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G13/G1a/G12 PIN DESCRIPTION Figure 3 illustrates a diagram of the Z80 PIO pin configuration. This section describes the function of each pin. D7-D0 Z80 CPU Data Bus (bidirectional, tristate). This bus is used to transfer all data and commands between the Z80 CPU and the Z80 PIO. D0 is the least-significant bit of the bus. B/A Sel Port B or A Select (input, active High). This pin defines which port is accessed during a data transfer between the Z80 CPU and the Z80 PIO. A Low level on this pin selects Port A while a High level selects Port B. Often, Address bit A0 from the CPU is used for this selection function. C/D Sel Control or Data Select (input, active High). This pin defines the type of data transfer to be performed between the CPU and the PIO. A High level on this pin during a CPU write to the PIO causes the Z80 data bus to be interpreted as a command for the port selected by the B/A Select line. A L o wl e v e lo nt h i sp i nm e a n st h a tt h eZ 8 0d a t ab u si sb e i n gu s e dt ot r a n s f e r data between the CPU and the PIO. Often, Address bit Al from the CPU is used for this function. CE Chip Enable (input, active Low). A Low level on this pin enables the PIO to accept command or data inputs from the CPU during a write cycle or to transmit data to the CPU during a read cycle. This signal is generally a decode of four I/O port numbers that encompass Ports A and B, data, and control.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G13/G1a/G13 Φ System Clock (input). The Z80 PIO uses the standard Z80 system clock to synchronize certain signals internally. This is a single phase clock. Machine Cycle One Signal from CPU (input, active Low). This signal from the CPU is used as a sync pulse to control several internal PIO opera- tions. When M1 is active and the RD signal is active, the Z80 CPU is fetching an instruction from memory. Conversely, when M1is active and IORQ is active, the CPU is acknowledging an interrupt. In addition, the M1 signal has two other functions within the Z80 PIO. 1. M1 synchronizes the PIO interrupt logic. 2. When M1 occurs without an active RD or IORQ signal, the PIO logic enters a reset state. IORQ Input/Output Request from Z80 CPU ( i n p u t ,a c t i v eL o w ) .T h eI O R Q signal is used in conjunction with the B/ A Select, C/D Select, CE ,a n d RD signals to transfer commands and data between the Z80 CPU and the Z 8 0P I O .W h e nC E,R D,a n dI O R Qare active, the port addressed by B/A transfers data to the CPU (a read operation). Conversely, when CE and IORQ a r ea c t i v eb u tR Dis not active, then the port addressed by B/A is written to from the CPU with either data or control information as speci- fied by the C/D Select signal. Also, if IORQ and M1 are active simulta- neously, the CPU is acknowledging an interrupt and the interrupting port automatically places its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. RD Read Cycle Status from the Z80 CPU (input, active Low). If RD is active, a MEMORY READ or I/O READ operation is in progress. The RD signal is used with B/A Select, C/D Select, CE,a n dI O R Qsignals to transfer data from the Z80 PIO to the Z80 CPU.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G13/G1a/G14 IEI Interrupt Enable In (input, active High). This signal is used to form a priority interrupt daisy-chain when more than one interrupt driven device is being used. A high level on this pin indicates that no other devices of higher priority are being serviced by a CPU interrupt service routine. IEO Interrupt Enable Out (output, active High). The IEO signal is the other signal required to form a daisy-chain priority scheme. It is High only if IEI is High and the CPU is not servicing an interrupt from this PIO. Thus, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT Interrupt Request (output, open-drain, active Low). When INT is active, the Z80 PIO is requesting an interrupt from the Z80 CPU. A7-A0 Port A Bus (bidirectional, tristate). This 8-bit bus is used to transfer data and/or status or control information between Port A of the Z80 PIO and a peripheral device. A0 is the least-significant bit of the Port A data bus. ASTB Port A Strobe Pulse from Peripheral Device(input, active Low). The meaning of this signal depends on the mode of operation selected for Port A as follows: 1. Output mode: The positive edge of this strobe is issued by the peripheral to acknowledge the receipt of data made available by the PIO. 2. Input mode: The strobe is issued by the peripheral to load data from the peripheral into the Port A input register. Data is loaded into the PIO when this signal is active.

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G13/G1a/G15 3. Bidirectional mode: When this signal is active, data from the Port A output register is gated onto Port A bidirectional data bus. The positive edge of the strobe acknowledges the receipt of the data. 4. Control mode: The strobe is inhibited internally. ARDY Register A Ready (output, active High). The meaning of this signal depends on the mode of operation selected for Port A as follows: 1. Output mode: This signal goes active to indicate that the Port A output register has been loaded and the peripheral data bus is stable and ready for transfer to the peripheral device. 2. Input mode: This signal is active when the Port A input register is empty and is ready to accept data from the peripheral device. 3. Bidirectional mode: This signal is active when data is available in the Port A output register for transfer to the peripheral device. In this mode, data is not placed on the Port A data bus unless ASTB is active. 4. Control mode: This signal is disabled and forced to a Low state. B7-B0 Port B Bus (bidirectional, tristate). This 8-bit bus is used to transfer data and/or status or control information between Port B of the PIO and a peripheral device. The Port B data bus is capable of supplying 1.5 mA @ 1.5V to drive Darlington transistors. B0 is the least significant bit of the bus. BSTB Port B Strobe Pulse from Peripheral Device (input, active Low). The meaning of this signal is similar to that of ASTB with the following exception: In the Port A bidirectional mode, this signal strobes data from the peripheral device into the Port A input register.

and ready to accept data from the peripheral device. Figure 3. PIO Pin Functions

Figure 4. 44-Pin PLCC Pin Assignments

Figure 5. 44-Pin QFP Pin Assignments

Figure 6. 40-Pin DIP Pin Assignments

1. Both port mask registers are reset to inhibit all port data bits.
2. Port data bus lines are set to a high-impedance state and the Ready

handshake signals are inactive (Low). Mode 1 is automatically selected.

1. The vector address registers are not reset.
2. Both port interrupt enable flip-flops are reset.
3. Both port output registers are reset.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G13/G1a/G1a In addition to the automatic power-on reset, the PIO can be reset by applying an M1 signal without the presence of a RD or IORQ signal. If no RD or IORQ is detected during M1, the PIO enters the reset state immedi- ately after the M1 signal goes inactive. This reset allows a single external gate to generate a reset without a power-down sequence. The 40-pin pack- aging requires this routine. When the PIO enters the internal reset state, it is held there until the PIO receives a control word from the CPU. Loading The Interrupt Vector The PIO is designed to operate with the Z80 CPU using the Mode 2 inter- rupt response. This mode requires that an interrupt vector be supplied by the interrupting device. This vector is used by the CPU to form the address for the interrupt service routine of that port. This vector is placed on the Z80 data bus during an interrupt acknowledge cycle by the highest priority device requesting service at that time. (Refer to the Z80 CPU User’s Manual Section for details on how an interrupt is serviced by the CPU). The interrupt vector is loaded to the PIO by writing a control word to the appropriate PIO port using the following format: D0 functions as a flag bit, which when Low, loads V7 through V1 to the vector register. At interrupt acknowledge, the vector of the interrupting port appears on the Z80 data bus exactly as illustrated in the diagram above. Signifies this Control Word is an Interrupt Vector V7 V6 V5 V4 D7 D6 D5 D4 D3 D0 D2 D1 V3 V2 V1 0

(input mode), Mode 2 (bidirectional mode), and Mode 3 (control mode). 1 = In, 2 = Bidirectional. Port B cannot operate in Mode 2. executing an input instruction. Table 1. PIO Mode Selection

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G13/G1b/G12 data is available. This signal remains High until a strobe is received from the peripheral. The rising edge of the strobe generates an interrupt (if it has been enabled) and causes the Ready line to go inactive. This hand- s h a k ei ss i m i l a rt ot h o s eu s e db ym a n yp e r i p h e r a ld e v i c e s . By selecting Mode 1, the port enters input mode. To initiate a handshake, the CPU performs an input read from the port. This activates the Ready line, which signals the peripheral that data can be loaded to the empty input register. The peripheral device then strobes data to the port input register through the strobe line. Again, the rising edge of the strobe causes an inter- rupt request (if it has been enabled) and deactivates the Ready signal. Data may be strobed to the input register regardless of the state of the Ready signal if care is taken to prevent a data overrun condition. Mode 2 is a bidirectional data transfer mode, utilizing all four handshake lines. Therefore, only Port A is used for Mode 2 operation. Mode 2 opera- tion uses the Port A handshake signals for output control, and uses the Port B handshake signals for input control. Thus, both ARDY and BRDY may be active simultaneously. The only operational difference between Mode 0 and the output portion of Mode 2 is: Data from the Port A output register is allowed on the port data bus when ASTB is active. Bidirectional capability is achieved only when ASTB is active. Mode 3 operation is used for status and control applications and does not utilize the handshake signals. When Mode 3 is selected, the next control word sent to the PIO must define which port data bus lines are inputs and which are outputs. The format of the control word is depicted below: If any bit is set to a one, then the corresponding data bus line is used as an input. Conversely, if the bit is reset, the line is used as an output. During Mode 3 operation, the strobe signal is ignored and the Ready line is held Low. Data may be written to a port or read from a port by the Z80 CPU at any time during Mode 3 operation. The data returned from a port to the I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 D7 D6 D5 D4 D3 D0 D2 D1

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G13/G1b/G13 CPU is composed of input data, which comes from port data bus lines assigned as inputs, and port output register data, which comes from lines assigned as outputs. Setting The Interrupt Control Word The interrupt control word for each port has the following format: If bit D7 = 1, the interrupt enable flip-flop of the port is set and the port may generate an interrupt. If bit D7 = 0, the enable flag is reset and inter- rupts may not be generated. If an interrupt is pending when the enable flag is set, the interrupt is then enabled to the CPU interrupt request line. Bits D6, D5, and D4 are used only with Mode 3 operation. However, setting bit D4 of the interrupt control word in any mode of operation causes a pending interrupt to be reset. These three bits allow interrupts in Mode 3, but only when specific I/O lines go to defined states. Bit D6 (AND/OR) defines the logical operation to be performed in port moni- toring. If bit D6 = 1, an AND function is specified and if D6 = 0, an OR function is specified. For example, if the AND function is specified, all bits must go to a specified state before an interrupt is generated. Conversely, the OR function generates an interrupt if any specified bit goes to the active state. Bit D5 defines the active polarity of the port data bus line to be monitored. If bit D5 = 1, the port data lines are monitored for a high state. When bit D5 = 0, the port data lines are monitored for a low state. If bit D4 = 1, the next control word sent to the PIO must define a mask as follows: Used in Signifies Interrupt D7 D6 D5 D4 D3 D0 Enable Int. AND/ OR High Low Masks Follows D2 D1 Mode 3 Only 01 11 Control Word MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 D7 D6 D5 D4 D3 D0 D2 D1

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G13/G1b/G14 Only port lines whose mask bit is zero are monitored for generating an interrupt. When IORQ is high, the forced state of Ready prevents input register data from changing while the CPU is reading the PIO. Ready goes High again after the trailing edge of the IORQ, as previously described TIMING Output Mode (Mode 0) Figure 7 illustrates the timing associated with Mode 0 operation. An output cycle is always started by the execution of an output instruction by the CPU. A WR* pulse is generated by the PIO during a CPU I/O write opera- tion and is used to latch the data from the CPU data bus to the addressed ports (A or B) output register. The rising edge of the WR * pulse then raises the Ready flag after the next falling edge of Φ, indicating that data is avail- able for the peripheral device. In most systems, the rising edge of the Ready signal can be used as a latching signal in the peripheral device. The Ready signal remains active until: (1) a positive edge is received from the strobe line, indicating that the peripheral has taken the data, or (2) if already active, Ready is forced low for one and one-half Φ cycles after the leading edge of IORQ, but only if the port’s output register is written to. Ready returns High on the first falling edge of Φ after the trailing edge of IORQ. This guarantees that Ready is low when port data is changing. The Ready signal does not go inactive until a falling edge occurs on the clock (Φ) line. The purpose of delaying the negative transition of the Ready signal until after a negative clock transition is to allow a simple generation scheme for the strobe pulse. By connecting the Ready line to the Strobe line, a strobe with a duration of one clock period is generated with no other logic required. The positive edge of the strobe pulse automatically generates an INT request when the interrupt enable flip-flop has been set and this device is the highest priority device requesting an interrupt.

enabled to achieve an interrupt-driven, bidirectional transfer. input data onto the bus. The PIO uses the BSTBlow level to latch this data. can be used by the peripheral. Figure 9. Port A, Mode 2 (Bidirectional) Timing latter case, the state of BRDY is not affected.

change in the result of the Mode 3 logical operation has not occurred. Figure 10. Control Mode (Mode 3) Timing

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G13/G1b/G1b Figure 13. Daisy-Chain Interrupt Servicing

APPLICATIONS

Extending The Interrupt Daisy-chain Without external logic, a maximum of four Z80 PIO devices may be daisy- chained into a priority interrupt structure. This limitation allows the inter- rupt enable status (IEO) to ripple through the entire daisy-chain between the beginning of M1 and the beginning of IORQ during an interrupt acknowledge cycle. The interrupt enable status cannot change during M1, therefore, the vector address returned to the CPU is assured to be from the highest priority device that requested an interrupt. IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOHIIEI IEOHI IEI IEOHI IEI IEOHI IEI IEOLO IEI IEOHI IEI IEOHI IEI IEOHI IEI IEOLO IEI IEOLO IEI IEOLO IEI IEOHI HI LO LO LO HI Port 2BPort 1BPort 2A Under Service Service Suspended Service Resumed Service Complete 5. Second‘RETI’instruction issued on completion of Port 2A service routine. 4. Port 1B service routine complete,‘RETI’issued, Port 2A service resumed. 3. Port 1B1 interrupts, suspends servicing of Port 2A. 2. Port 2A requests an interrupt and is Acknowledged. 1. Priority interrupt daisy chain before any interrupt occurs. Service Complete Under Service Port 1A HighestPriorityCh annel

following the setting of the mask. timing for this transfer is as described in “Timing” on page 192. Figure 15. Example of I/O Interface

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G14/G12/G14 Control Interface A typical control mode application is illustrated in Figure 16. In this example, an industrial process is to be monitored. The occurrence of any abnormal operating condition is to be reported to a Z80 CPU-based control system. The process control and status word has the following format: The PIO may be used as follows. First, Port A is set for Mode 3 operation by writing the following control word to Port A. Whenever Mode 3 is selected, the next control word sent to the port must be an I/O select word. In this example, port data lines A5, A3, and A0 are selected as inputs, and the following control word is written: Next, the appropriate interrupt vector must be loaded (refer to the Z80 CPU User’s Manual for details): An interrupt control word is next sent to the port: The mask word following the interrupt mode word is: D7 D6 D5 D4 D3 D0 Halt Processing D2 D1 Special Test Turn On Power Power Failure Alarm Tem p. Alarm Turn On Heaters Pressurize System Pressure Alarm 11XX D7 D6 D5 D4 D3 D0 D2 D1 11 11 00 1 0 D7 D6 D5 D4 D3 D0 D2 D1 10 01 V5 V4 D7 D6 D5 D4 D3 D0 D2 D1 V3 V2 V1 0V1 V6 Interrupt Control D7 D6 D5 D4 D3 D0 D2 D1 01 1110 Enable Interrupts OR Logic Active High Mask Follows

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G14/G12/G15 If a sensor puts a High level on lines A5, A3, or A0, an interrupt request is generated. The mask word may select any combination of inputs or outputs to cause an interrupt. For example, if the mask word above is: then an interrupt request would also occur if bit A7 (Special Test) of the output register was set. Assume that the following port assignments are to be used: E0H = Port A Data E1H = Port B Data E2H = Port A Control E3H = Port B Control All port numbers are in hexadecimal notation. This particular assignment of port numbers is convenient because A0 of the address bus can be used as the Port B/A Select and A1 of the address bus can be used as the Control/ Data Select. The Chip Enable is the decode of CPU address bits A7 through A2 ( 111000). Note: When only a few peripheral devices are being used, a Chip Enable decode may not be required because a higher order address bit may be used directly. Selects A5, A3, and A0 to be Monitored D7 D6 D5 D4 D3 D0 D2 D1 01 1011 D7 D6 D5 D4 D3 D0 D2 D1 01 1001

Figure 16. Control Mode Application

/G3c /G1a /G12 /G2 /G25 /G32/G37/G2 /G32 /G47 /G54/G4b /G52/G4a/G47 /G54/G43 /G4e /G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43/G4e UM008101-0601 Parallel Input/Output /G14/G12/G17 PROGRAMMING SUMMARY Overview This section discusses the Load Interrupt Vector, Set Mode, Set Interrupt control registers. Load Interrupt Vector Set Mode When selecting Mode 3, the next word must set the I/O Register: M1 M0 Mode 00O u t p u t 0 1 Input 1 0 Bidirectional 1 1 Bit Control V5 V4 D7 D6 D5 D4 D3 D0 D2 D1 V3 V2 V1 0V1 V6 M1 M0 X X D7 D6 D5 D4 D3 D0 D2 D1 11 11

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Parallel Input/Output /G14/G12/G18 Set Interrupt Control If the mask follows bit is high, the next control word written to the port must be the mask: In addition, the interrupt enable flip-flop of a port may be set or reset without modifying the remainder of the interrupt control word. This is accomplished by issuing the following command: Used in Enable Int. AND/ OR High Low Masks Follows M o d e3O n l y 01 11 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 XX 00 11X Enable Int.

UM008101-0601 Serial Input/Output 207 Serial Input/Output OVERVIEW The Z80 Serial Input/Output (SIO) is a dual-channel multi-function peripheral component designed to satisfy a wide variety of serial data communications requirements in microcomputer systems. The Z80 SIO functions as a serial-to-parallel, parallel-to-serial converter/controller, and is systems-software configurable to allow optimization for a given serial data communications application. The Z80 SIO is capable of handling asynchronous and synchronous byte- oriented protocols such as IBM Bisync and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device also supports virtually any other serial protocol for applications other than data communications, such as cassette or floppy disk interfaces. The Z80 SIO can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The device also has features for modem controls in both channels. In applica- tions where these controls are not needed, the modem controls can be used for general-purpose I/O.  CMOS and NMOS V ersion  40-Pin DIP , 44-Pin PLCC/QFP Packages  Single 5V Power Supply  Single-Phase 5V Clock

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 208  TTL-Compatible Inputs and Outputs  Two Independent Full-Duplex Channels  Data Rates in Synchronous or Isosynchronous Modes: – 0-800K Bits/Second with 4 MHz System Clock Rate – 0-1.2M Bits/Second with 6 MHz System Clock Rate – 0-2.5M Bits/Second with 10 MHz System Clock Rate  Receiver Data Registers Quadruply Buffered; Transmitter Doubly Buffered  Asynchronous Features: – 5, 6, 7, or 8 Bits per Character – 1, 1 1/2, or 2 Stop Bits – Even, Odd, or No Parity – x1, x16, x32, and x64 Clock Modes – Break Generation and Detection – Parity, Overrun, and Framing Error Detection  Binary Synchronous Features: – Internal or External Character Synchronization – One or Two Sync Characters in Separate Registers – Automatic Sync Character Insertion – CRC Generation and Checking  HDLC and IBM SDLC Features: – Abort Sequence Generation and Detection – Automatic Zero Insertion and Deletion – Automatic Flag insertion Between Messages – Address Field Recognition – 1-Field Residue Handling – Valid Receive Messages Protected from Overrun

Figure 100. Z80 SIO Block Diagram

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 210 PIN DESCRIPTION Pin Functions D7-D0 System Data Bus (bidirectional, tristate). The system data bus transfers data and commands between the CPU and the Z80 SIO. D0 is the least-significant bit. B/A Channel A or B Select (input, High selects Channel B). This input defines which channel is accessed during a data transfer between the CPU and the Z80 SIO. Address bit A0 from the CPU is often used for the selec- tion function. C/D Control Or Data Select (input, High selects Control). This input defines the type of information transfer performed between the CPU and the Z80 SIO. A High at this input during a CPU write to the Z80 SIO causes the information on the data bus to be interpreted as a command for the channel selected by B/A .AL o wa tC / Dindicates that the information on the data bus is data. Address bit A1 is often used for this function. CE Chip Enable (input, active Low). A Low level at this input enables the Z80 SIO to accept command or data inputs from the CPU during a write cycle, or to transmit data to the CPU during a read cycle. Φ System Clock (input). The Z80 SIO uses the standard Z80A System Clock to synchronize internal signals. This is a single-phase clock. M1 Machine Cycle One (input from Z80 CPU, active Low). When M1 is active and RD is also active, the Z80 CPU is fetching an instruction from memory; when M1 is active while IORQ is active, the Z80 SIO accepts M1 and IORQ as an interrupt acknowledge if the Z80 SIO is the highest priority device that has interrupted the Z80 CPU. IORQ input/Output Request (input from CPU, active Low). IORQ is used in conjunction with B/A,C / D,C E,a n dR Dto transfer commands and data between the CPU and the Z80 SIO. When CE,R D,a n dI O R Qare all active, the channel selected by B/A transfers data to the CPU (a read operation).

UM008101-0601 Serial Input/Output 211 When CE and IORQ are active, but RD is inactive, the channel selected by B/A is written to by the CPU with either data or control information as specified by C/D. As mentioned previously, if IORQand M1 are active simultaneously, the CPU is acknowledging an interrupt and the Z80 SIO automatically places its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. RD Read Cycle Status (input from CPU, active Low). If RD is active, a memory or I/O read operation is in progress. RD is used with B/A ,C E, and IORQ to transfer data from the Z80 SIO to the CPU. RESET Reset (input, active Low). A Low /RESET disables both /RESET and transmitters, forces TxDA and TxDB marking, forces the modem controls High and disables all interrupts. The control registers must be rewritten after the Z80 SIO is reset and before data is transmitted or received. IEI Interrupt Enable In (input, active High). This signal is used with IEO to form a priority daisy-chain when there is more than one interrupt- driven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. IEO Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the CPU is not servicing an interrupt from this Z80 SIO. There- fore, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT Interrupt Request (output, open-drain, active Low). When the Z80 SIO is requesting an interrupt, it pulls INT Low. W/RDYA,W / R D Y BWait/Ready A, Wait/Ready B (outputs, open-drain when programmed for Wait function, driven High and Low when programmed for Ready function). These dual-purpose outputs may be programmed as Ready lines for a DMA controller or as Wait lines that synchronize the CPU to the Z80 SIO data rate. The reset state is open-drain. CSTA ,C S T BClear To Send (inputs, active Low). When programmed as Auto Enables, a Low on these inputs enables the respective transmitter. If not programmed as Auto Enables, these inputs may be programmed as

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 212 general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow-risetime inputs. The Z80 SIO detects pulses on these inputs and interrupts the CPU on both logic level transitions. The Schmitt-trigger inputs do not guarantee a specified noise-level margin. DCDA , DCDB Data Carrier Detect (inputs, active Low). These signals are similar to the CTS inputs, except they can be used as receiver enables. RxDA, RxDB Receive Data (inputs, active High). TxDA, TxDB Transmit Data (outputs, active High). RxCA, RxCB* Receiver Clocks (inputs). See the following section on bonding options. The Receive Clocks may be 1, 16, 32, or 64 times the data rate in asynchronous modes. Receive data is sampled on the rising edge of RxC. TxCA,T x C B* Transmitter Clocks (inputs). See section on bonding options. In asynchronous modes, the Transmitter clocks may be 1, 16, 32, or 64 times the data rate. The multiplier for the transmitter and the receiver must be the same. Both the TxC and RxC inputs are Schmitt-trigger buff- ered for relaxed rise- and fall-time requirements (no noise margin is speci- fied). TxD Changes on the falling edge of TxC These clocks may be directly driven by the Z80 CTC (Counter Timer Circuit) for fully programmable baud rate generation. RTSA,R T S BRequest To Send(outputs, active Low). When the /RTSbit is set, the RTS output goes Low. When the RTSbit is reset in the Asynchro- nous mode, the output goes High after the transmitter is empty. In Synchro- nous modes, the RTSpin strictly follows the state of the RTSbit. Both pins can be used as general-purpose outputs. DTRA,D T R BData Terminal, Ready (outputs, active Low). See note on bonding options. These outputs follow the state programmed into the DTR bit. They can also be programmed as general-purpose outputs. SYNCA, SYNCB Synchronization (inputs/outputs, active Low). These pins can act either as inputs or outputs. In the Asynchronous Receive mode,

UM008101-0601 Serial Input/Output 213 they are inputs similar to CTS and DCD. In this mode, the transitions on these lines affect the state of the Sync/Hunt status bits in RR0. In the External Sync mode, these lines also act as inputs. When external synchro- nization is achieved, SYNC must be driven Low on the second rising edge of RxC after that rising edge of RxC on which the last bit of the sync char- acter was received. In other logic must wait for two full Receive Clock cycles to activate the SYNC input. When SYNC is forced Low, keep it Low until the CPU notifies the external sync logic that synchronization has been lost or that a new message is about to start. Character assembly begins on the rising edge of RxC that immediately precedes the falling edge of SYNC in the External Sync mode. In the Internal Synchronization mode (Monosync and Bisync), these pins function as outputs that are active during the part of the receive clock (RxC) cycle in which sync characters are recognized. The sync condition is not latched, therefore, these outputs are active each time a sync pattern is recog- nized, regardless of character boundaries. Bonding Options T h ec o n s t r a i n t so fa4 0 - p i np a c k a g em a k ei ti m p o s s i b l et ob r i n go u tt h e Receive Clock, Transmit Clock, Data Terminal Ready, and Sync signals for both channels. Therefore, Channel B must sacrifice a signal or have two signals bonded together. Because user requirements vary, three bonding options are offered:  Z80 SIO/0 contains all four signals, but TxCB and RxCD are bonded together (Figure 101).  Z80 SIO/1 sacrifices DTRB and keeps TxCB,R x C Dand SYNCB (Figure 103).  Z80 SIO/2 sacrifices SYNCB and keeps TxCB,R x C Band DTRB (Figure 105).  The 44-pin package version SIO/3 (QFP) and SIO/4 (PLCC) have all signals (Figure 107 and Figure 108).

Figure 101. Z80 SIO/0 Functions

Figure 102. Z80 SIO/0 Pin Assignments

Figure 103. Z80 SIO/1 Pin Functions

Figure 104. Z80 SIO/1 Pin Assignments

Figure 105. Z80 SIO/2 Pin Functions

Figure 106. Z80 SIO/2 Pin Assignments

Figure 107. Z80 SIO/3 Pin Assignments

Figure 108. Z80 SIO/4 Pin Assignments

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 222 ARCHITECTURE Overview The device internal structure includes a Z80 CPU interface, internal control and interrupt logic, and two full-duplex channels. Associated with each channel are read and write registers, and discrete control and status logic that provides the interface to modems or other external devices. The read and write register group includes five 8-bit control registers, two sync-character registers, and two status registers. The interrupt vector is written into an additional 8-bit register (Write Register 2) in Channel B that may be read through Read Register 2 in Channel B. The registers for both channels are designated as follows: WR7–WR0 — Write Registers 0 through 7 RR2–RR0 — Read Registers 0 through 2 The bit assignment and functional grouping of each register is configured to simplify and organize the programming process. Table 1 and Table 2 illus- trate the functions assigned to each read or write register. The logic for both channels provides formats, synchronization, and valida- tion for data transferred to and from the channel interface. The modem control inputs Clear to Send (CTS ) and Data Carrier Detect (DCD)a r e monitored by the discrete control logic under program control. All the modem control signals are general purpose and can be used for functions other than modem control. For automatic interrupt vectoring, the interrupt control logic determines which channel and which device within the channel has the highest priority. Priority is fixed with Channel A assigned a higher priority than Channel B; Receive, Transmit and External/Status interrupts are prioritized in that order within each channel.

Figure 109. The receiver contains three 8-bit buffer registers in a FIFO for each of the three bytes in the receive data FIFO. Table 1. Write Register Functions Table 2. Read Register Functions

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 224 entered in the 3-bit buffer if the data has a character length of seven or eight bits, or is entered in the 8-bit receive shift register if the data has a length of five or six bits. In the Synchronous mode, the data path is determined by the phase of the receive process currently in operation. A Synchronous Receive operation begins with the receiver in the Hunt phase, during which the receiver searches the incoming data stream for a bit pattern that matches the prepro- grammed sync characters for flags in the SDLC mode. If the device is programmed for Monosync Hunt, a match is made with a single sync char- acter stored in WR7. In Bisync Hunt, a match is made with dual sync char- acters stored in WR6 and WR7. In either case, the incoming data passes through the receive sync register, and is compared against the programmed sync character in WR6 or WR7. In the Monosync mode, a match between the sync character programmed to WR7 and the character assembled in the receive sync register establishes synchronization. In the Bisync mode, however, incoming data is shifted to the receive shift register while the next eight bits of the message are assembled in the receive sync register. The match between the assembled character in the receive sync registers with the programmed sync character in WR6 and WR7 establishes synchronization. When synchronization is established, incoming data bypasses the receive sync register and directly enters the 3-bit buffer. In the SDLC mode, incoming data first passes through the receive sync register, which continuously monitors the receive data stream and performs zero deletion when indicated. Upon receiving five contiguous 1s, the sixth bit is inspected. If the sixth bit is a 0, it is deleted from the data stream. If the sixth bit is a 1, the seventh bit is inspected. If the seventh bit is a 0, a Flag sequence has been received; if it is a 1, an Abort sequence has been received. The reformatted data enters the 3-bit buffer and is transferred to the receive shift register. The SDLC receive operation also begins in the Hunt phase,

UM008101-0601 Serial Input/Output 225 during which the Z80 SIO tries to match the assembled character in the receive shift register with the nag pattern in WR7. When the first flag char- acter is recognized, all subsequent data is routed through the same path, regardless of character length. Although the same CRC checker is used for both SDLC and synchronous data, the data path taken for each mode is different. In Bisync protocol, a byte-oriented operation requires that the CPU decide to include the data character in CRC. To allow the CPU ample time to make this decision, the Z80 SIO provides an 8-bit delay for synchronous data. In the SDLC mode, no delay is provided because the Z80 SIO contains logic that determines the bytes on which CRC is calculated. The transmitter has an 8-bit transmit data register that is loaded from the internal data bus and a 20-bit transmit shift register that can be loaded from WR6, WR7, and the transmit data register. WR6 and WR7 contain sync characters in the Monosync or Bisync modes, or address field (one char- acter long) and flag respectively in the SDLC mode. During Synchronous modes, information contained in WR6 and WR7 is loaded to the transmit shift register at the beginning of the message and, as a time filler, in the middle of the message if a Transmit Underrun condition occurs. In the SDLC mode, the flags are loaded to the transmit shift register at the begin- ning and end of message. Asynchronous data in the transmit shift register is formatted with start and stop bits and is shifted out to the transmit multiplexer at the selected clock rate. Synchronous (Monosync or Bisync) data is shifted out to the transmit multiplexer and also to the CRC generator at the x1 clock rate. SDLC/HDLC data is shifted out through the zero insertion logic, which is disabled while the flags are sent. For all other fields (address, control, and frame check) a 0 is inserted following five contiguous 1s in the data stream. The CRC generator result for SDLC data is also routed through the zero insertion logic.

Figure 109. Transmit and Receive Data Path data communications device, and as a Z80 family peripheral.

UM008101-0601 Serial Input/Output 227 busses, as well as being a part of the Z80 interrupt structure. As a peripheral to other microprocessors, the Z80 SIO offers valuable features such as non- vectored interrupts, polling and simple handshake capabilities. The first part of the following functional description describes the interac- tion between the CPU and Z80 SIO. The second part introduces its data communications capabilities. I/O Capabilities The Z80 SIO offers the choice of Polling, Interrupt (vectored or non- vectored), and Block Transfer modes to transfer data, status, and control information to and from the CPU. The Block Transfer mode can be imple- mented under CPU or DMA control. Polling The Polled mode avoids interrupts. Status registers RR0 and RR1 are updated at appropriate times for each function being performed, for example, CRC Error status valid at the end of the message. All the Z80 SIO interrupt modes must be disabled to operate the device in a polled environment. While in Polling sequence, the CPU examines the status contained in RR0 for each channel. The RR0 status bits serve as an acknowledge to the Poll inquiry. The two RR0 status bits D0 and D2 indicate that a receive or transmit data transfer is needed. The status also indicates Error or other special status conditions (see “ Programming” on page 272). The Special Receive Condition status contained in RR1 does not have to be read in a Polling sequence because the status bits in RR1 are accompanied by a Receive Character Available status in RR0 Interrupts The Z80 SIO offers an elaborate interrupt scheme to provide fast interrupt response in real-time applications. As covered earlier, Channel B registers WR2 and RR2 contain the interrupt vector that points to an interrupt service

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 228 routine in the memory. To service operations in both channels and to elimi- nate the necessity of writing a status analysis routine, the Z80 SIO can modify the interrupt vector in RR2 so that it points directly to one of eight interrupt service routines. This is done under program control by setting a program bit (WR1, D2) in Channel B called “Status Affects Vector.” when this bit is set, the interrupt vector in WR2 is modified according to the assigned priority of the various interrupting conditions. The table in“ Write Register 1” on page 279 lists the modification details. Transmit interrupts, Receive interrupts, and External/ Status interrupts are the main sources of interrupts ( Figure 110). Each interrupt source is enabled under program control with Channel A having a higher priority than Channel B, and with Receiver, Transmit, and External/Status inter- rupts prioritized in that order within each channel. When the Transmit interrupt is enabled, the CPU is interrupted by the transmit buffer becoming empty. This implies that the transmitter had a data character written into it so it can become empty. When enabled, the receiver can interrupt the CPU in one of three ways:  Interrupt on first receive character  Interrupt on all receive characters  Interrupt on a Special Receive condition Interrupt On First Character is typically used with the Block Transfer mode. Interrupt On All Receive Characters has the option of modifying the inter- rupt vector in the event of a parity error. The Special Receive Condition interrupt can occur on a character or message basis, for example, End-of- Frame interrupt in SDLC. The Special Receive condition can cause an interrupt only if the Interrupt On First Receive Character or Interrupt On All Receive Characters mode is selected. In Interrupt On First Receive Character, an interrupt can occur from Special Receive conditions (except Parity Error) after the first receive character interrupt, for example, Receive Overrun interrupt. The main function of the External/Status interrupt is to monitor the signal transitions of the CTS ,D C D,a n dS Y N Cpins; however, an External/Status

UM008101-0601 Serial Input/Output 229 interrupt is also caused by a Transmit Underrun condition or by the detec- tion of a Break (Asynchronous mode) or Abort (SDLC mode) sequence in the data stream. The interrupt caused by the Break/Abort sequence has a special feature that allows the Z80 SIO to interrupt when the Break/Abort sequence is detected or terminated. This feature facilitates the proper termi- nation of the current message, correct initialization of the next message, and the accurate timing of the Break/Abort condition in external logic. CPU/DMA Block Transfer The Z80 SIO provides a Block Transfer mode to accommodate CPU block transfer functions and DMA controllers (Z80-DMA or other designs). The Block Transfer mode uses the WAIT /READY output in conjunction with the Wait/Ready bits of Write Register 1. The WAIT/READY output can be defined under software control as a WAITline in the CPU Block Transfer mode or as a READY line in the DMA Block Transfer mode. To a DMA controller, the Z80 SIO READYoutput indicates that the Z80 SIO is ready to transfer data to or from memory. To the CPU, the WAIT output indicates that the Z80 SIO is not ready to transfer data, thereby requesting the CPU to extend the I/O cycle. The programming of bits 5, 6, and 7 of Write Register 1 and the logic states of the WAIT /READY line are defined in “Write Register 1” on page 279. Data Communications Capabilities In addition to the I/O capabilities previously discussed, the Z80 SIO provides two independent full-duplex channels as well as Asynchronous, Synchronous, and SDLC (HDLG) operational modes. These modes facili- tate the implementation of commonly used data communications protocols. The specific features of these modes are described in the following sections. To preserve the independence and completeness of each section, s o m ei n f o r m a t i o nc o m m o nt oa l lm o d e si sr e p e a t e d .

Figure 110. Interrupt Structure

description (Z80 SIO Programming section) for the data format. shifted out on the falling edge of TxC. Table 3. Contents of Write Registers 3, 4, and 5 in Asynchronous Modes

Table 4. Asynchronous Mode Table 3. Contents of Write Registers 3, 4, and 5 in Asynchronous Modes (Continued)

no transmit interrupts occur. 4) Special receive condition.

• Transfer data character to CPU
• Update pointers and parameters
• Return from Interrupt If transmitter buffer is empty: Program control is transferred to one of the eight Interrupt Service routines.
• Transfer data character to SIO
• Update pointers and parameters
• Return from interrupt

Table 4. Asynchronous Mode (Continued)

rejection when noise spikes exist on an otherwise marking line. plished externally. Receive data is sampled on the rising edge of RxC.

• Transfer RRD to CPU
• Perform Error routines (include Break detection)
• Return from Interrupt If special receive condition occurs:
• T r a n s f e rR R 1t oC P U
• D6 Special Error (such as framing error) routine
• Return from Interrupt Termination Redefine Receive/Transmit Interrupt modes Disable Transmit/Receive modes When Transmit or Receive Data transfer is complete. Update modem control outputs (such as RTS off) In Transmit, the all sent status bit indicates transmission is complete.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 236 used. If parity is enabled, the parity bit is not stripped from the assembled character for character lengths other than eight bits. For lengths other than eight bits, the receiver assembles a character length of the required number of data bits, plus a parity bit and Is for any unused bits. For example, the receiver assembles a 5-bit character with the following format: 11 P D4 D3 D2 D1 D0. Because the receiver is buffered by three 8-bit registers in addition to the receive shift register, the CPU has enough time to service an interrupt and to accept the data character assembled by the Z80 SIO. The receiver also has three buffers that store error flags for each data character in the receive buffer. These error flags are loaded at the same time as the data characters. After a character is received, it is checked for the following error conditions:  When parity is enabled, the Parity Error bit (RR1, D4) is set whenever the parity bit of the character does not match with the programmed parity. Once this bit is set, it remains set until the Error Reset Command (WR0) is given.  The Framing Error bit (RR1, D6) is set if the character is assembled without any stop bits (that is, a Low level detected for a stop bit). Unlike the Parity Error bit, this bit is set (and not latched) only for the character on which it occurred. Detection of framing error adds an additional one-half of a bit time to the character time so the framing error is not interpreted as a new start bit.  If the CPU fails to read a data character while more than three characters have been received, the Receive Overrun bit RR1 D5) is set. When this occurs, the fourth character assembled replaces the third character in the receive buffers. With this arrangement, only the character that has been written over is flagged with the Receive Overrun Error bit. Like Parity Error, this bit can only be reset by the Error Reset command from the CPU. Both the Framing Error and Receive Overrun Error cause an interrupt with the interrupt vector indicating a Special Receive condition (if Status Affects Vector is selected).

UM008101-0601 Serial Input/Output 237 After the Parity Error and Receive Overrun Error flags are latched, the error status that is read indicates an error in the current word in the receive buffer plus any Parity or Overrun Errors received after the last Error Reset command. To keep correspondence between the state of the error buffers and the contents of the receive data buffers, the error status register must be read before the data. This is easily accomplished if vectored interrupts are used, because a special interrupt vector is generated for these conditions. While the External/Status interrupt is enabled, break detection causes an interrupt and the Break Detected status bit (RR0, D7) is set. The Break Detected interrupt should be responded to by issuing the Reset External/ Status Interrupt command to the Z80 SIO in response to the first Break Detected interrupt that has a Break status of 1 (RR0, D7). The Z80 SIO monitors the Receive Data input and waits for the Break sequence to terminate, at which time the Z80 SIO interrupts the CPU with the Break status set to 0. The CPU must again issue the Reset External/Status Inter- rupt command in its interrupt service routine to reinitialize the break detection logic. The External/Status interrupt also monitors the status of DCD .I ft h eD C D pin becomes inactive for a period greater than the minimum specified pulse width, an interrupt is generated with the DCD status bit (RR0, D3) set to 1. The DCD input is inverted in the RR0, status register. If the status is read after the data, the error data for the next word is also included if it has been stacked in the buffer. If operations are performed rapidly enough so the next character is not yet received, the status register remains valid. An exception occurs when the Interrupt On First Character Only mode is selected. A special interrupt in this mode holds the error data and the character itself (even if read from the buffer) until the Error Reset command is issued. This interrupt prevents further data from becoming available in the receiver until the Reset command is issued, and allows CPU intervention on the character with the error even if DMA or block transfer techniques are in use. If Interrupt On Every Character is selected, the interrupt vector is different an error status occurs in RR1. If a Receiver Overrun occurs, the most recent

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 238 character received is loaded into the buffer; the character preceding it is lost. When the character that has been written over the other characters is read, the Receive Overrun bit is set and the Special Receive. Condition vector is returned if Status Affects Vector is enabled. In a polled environment, the Receive Character Available bit (RR0, D0) must be monitored so that the Z80 CPU knows when to read a character. This bit is automatically reset when the receive buffers are read. To prevent overwriting data in polled operations, the transmit buffer status must be cheeked before writing to the transmitter. The Transmit Buffer Empty bit is set to 1 whenever the transmit buffer is empty. SYNCHRONOUS OPERATION Overview Before describing synchronous transmission and reception, the three types of character synchronization, Monosync, Bisync, and External Sync, require explanation. These modes use the x1 clock for both Transmit and Receive operations. Data is sampled on the rising edge of the Receive Clock input (RxC ). Transmitter data transitions occur on the falling edge of the Transmit Clock input (TxC). The differences between Monosync, Bisync, and External Sync are in the form in which initial character synchronization is achieved. The mode of operation must be selected before sync characters are loaded, because the registers are used differently in the various modes.Figure 112 depicts the formats for all three of these synchronous modes.

Figure 112. Synchronous Formats

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 240 Synchronous Modes Of Operation Monosync In a Receive operation, matching a single sync character (8-bit sync mode) with the programmed sync character stored in WR7 implies char- acter synchronization and enables data transfer. Bisync Matching two contiguous sync characters (16-bit sync mode) with the programmed sync characters stored in WR6 and WR7 implies character synchronization. In both the Monosync and Bisync modes, SYNC is used as an output, and is active for the part of the receive clock that detects the sync character. External Sync In this mode, character synchronization is established externally. SYNC is an input that indicates external character synchronization has been achieved. After the sync pattern is detected, the external logic must wait for two full Receive Clock cycles to activate the SYNC input. The SYNC input must be held Low until character synchronization is lost. Character assembly begins on the rising edge of RxC that precedes the falling edge of SYNC. In all cases after a reset, the receiver is in the Hunt phase, during which the Z80 SIO looks for character synchronization. The hunt can begin only when the receiver is enabled, and data transfer can begin only when char- acter synchronization has been achieved. If character synchronization is lost, the Hunt phase can be re-entered by writing a control word with the Enter Hunt Phase bit set (WR3, D4). In the Transmit mode, the trans- mitter always sends the programmed number of sync bits (8 or 16). In the

ified in the following text. Table 5. Contents of Write Registers 3, 4, and 6 In Synchronous Modes

0 Sync char

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 242 T a b l e6 .B i s y n cT r a n s m i tM o d e Function Typical Program Steps Comments Register Information loaded Initialize WR0 Channel Reset, Reset Transmit CRC Generator Reset SIO, Initialize CRC Generator WR0 Pointer 2 WR2 Interrupt V ector Channel B only WR0 Pointer 3 WR3 Auto Enables Transmission begins only after CTS is detected WR0 Pointer 4 WR4 Parity Information, Sync Modes Information, X1Clock Mode Issue transmit parameters WR0 Pointer 6 WR6 Sync Character 1 WR0 Pointer 7, Reset External/Status Interrupts WR7 Sync Character 2 WR0 Pointer 1, Reset External/Status Interrupts WR1 Status Affects Vector, External Interrupt Enable, Transmit Interrupt Enable or WAIT/READY Mode Enable External Interrupt Mode monitors the status of CTS and DCD input pins as well as the status of Tx Underrun/EOM Latch. Transmit Interrupt Enable interrupts when the transmit buffer becomes empty; the W A I T / R E A D YM o d ec a nb eu s e dt o transfer data using DMA or CPU block transfer.

READY output to transfer data. block transfer from memory to SIO. characters), and interrupt CPU.

• Include/Exclude data byte from CRC Accumulation (in SIO)
• Transfer data byte from CPU (or memory) to SIO
• Detect and set appropriate flags for control characters (in CPU)
• Reset Tx Underrun/EOM Latch WR0 if last character of message is detected
• Update pointers and parameters (CPU) Return from Interrupt If Error Condition Or Status Change Occurs: Tx Underrun/EOM indicates either Transmit Underrun (sync character being sent) or end of message (CRC- 16 being sent).
• Transfer RR0 to CPU
• Execute Error Routine
• Return From Interrupt Termination Redefine Interrupt Modes, Update Modem Control outputs (for example, turn off RTS Program should gracefully terminate message Disable Transmit Mode

Table 6. Bisync Transmit Mode (Continued)

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 244 Synchronous Transmit Initialization The system program must initialize the transmitter with the following parameters: odd or even parity, x1 clock mode, 8-bit or 16-bit sync char- acter(s), CRC polynomial, Transmitter Enables, Request To Send, Data Terminal Ready, interrupt modes, and transmit character length. WR4 parameters must be issued before WR1, WR3, WR5, WR6, and WR7 parameters or commands. One of two polynomials, CRC -16(X 16 +X 15 +X 2 +1 )o rS D L C( X16 + X12 +X 5 + 1), may be used with synchronous modes. In either case (SDLC mode not selected), the CRC generator and checker are reset to all 0s. In the transmit initialization process, the CRC generator is initialized by setting the Reset Transmit CRC Generator command bits (WR0). Both the trans- mitter and the receiver use the same polynomial. Transmit Interrupt Enable or Wait/Ready Enable can be selected to transfer the data. The External/Status interrupt mode is used to monitor the status of the CLEAR TO SEND (CTS ) input as well as the Transmit Underrun/EOM latch. Optionally, the Auto Enables feature can be used to enable the trans- mitter when CTSis active. The first data transfer to the Z80 SIO can begin when the External/Status interrupt occurs (CTSstatus bit set) or immediately following the Transmit Enable command (if the Auto Enables modes is set). Transmit data is held marking after reset or if the transmitter is not enabled. Break may be programmed to generate a spacing line that begins as soon as the Send Break bit is set. With the transmitter fully initialized and enabled, the default condition is continuous transmission of the 8-bit or 16-bit sync character. Data Transfer and Status Monitoring

UM008101-0601 Serial Input/Output 245 In this phase, there are several combinations of data transfers using inter- rupts and Wait/Ready status. Data Transfer Using Interrupts If the Transmit Interrupt Enable bit (WR1, D1) is Set, an interrupt is gener- ated each time the transmit buffer becomes empty. The interrupt can be satisfied either by writing another character to the transmitter or by reset- ting the Transmitter Interrupt Pending latch with a Reset Transmitter Pending command (WR0, CMD5). If the interrupt is satisfied with this command and nothing more is written to the transmitter, there can be no further Transmit Buffer Empty interrupts, because it is the process of the buffer becoming empty that causes the interrupts and the buffer cannot become empty when it is already empty. This situation does cause a Transmit Underrun condition, which is explained in the““ Bisync Transmit Underrun” on page 245” section. Data Transfer Using WAIT/READY To the CPU, the activation of WAITindicates that the Z80 SIO is not ready to accept data and that the CPU must extend the output cycle. To a DMA controller, READY indicates that the transmit buffer is empty and that the Z80 SIO is ready to accept the next data character. If the data character is not loaded to the Z80 SIO by the time the transmit shift register is empty, the Z80 SIO enters the Transmit Underrun condition. Bisync Transmit Underrun In Bisync protocol, filler characters are inserted to maintain synchroniza- tion when the transmitter has no data to send (Transmit Underrun condi- tion). The Z80 SIO has two programmable options for resolving this situation: it can insert sync characters, or it can send the CRC characters generated so far, followed by sync characters. These options are under the control of tile Reset Transmit Underrun/EOM Command in WR0. Following a chip or channel reset, the Transmit Underrun/EOM status bit (RR0, D6) is in a set condition and allows the

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 246 insertion of sync characters when there is no data to send. CRC is not calculated on the automatically inserted sync characters. When the CPU detects the end of message, a Reset Transmit Underrun/EOM command can be issued. This action allows CRC to be sent when the transmitter has no data. In this case, the Z80 SIO sends CRC, followed by sync charac- ters, to terminate the message. There is no restriction as to when in the message the Transmit Underrun/ EOM bit can be reset. If Reset is issued after the first data character has been loaded, the 16-bit CRC is Sent and followed by sync characters the first time the transmitter has no data to send. Because of the Transmit Underrun condition, an External/Status interrupt is generated whenever the Transmit Underrun/EOM bit becomes set. In the case of sync insertion, an interrupt is generated only after the first automatically inserted sync character has been loaded. The status indicates the Transmit Underrun/ EOM bit and the Transmit Buffer Empty bit are set. In the case of CRC insertion, the Transmit Underrun/EOM bit is set and the Transmit Buffer Empty bit is reset while CRC is being sent. When CRC has been completely sent, the Transmit Buffer Empty status bit is set and an interrupt is generated to indicate to the CPU that another message can begin (this interrupt occurs because CRC has been sent and sync has been loaded). If no more messages are to be sent, the program can terminate transmission by resetting RTS, and disabling the transmitter (WR5, D3). Pad characters may be sent by setting the Z80 SIO to eight bits/transmit character and writing FF to the transmitter while sending CRC. Alterna- tively, the sync characters can be redefined as pad characters during this time. The following example clarifies this point. 1. The Z80 SIO interrupts with the Transmit Buffer Empty bit set. 2. The CPU recognizes that the last character (ETX) of the message has already been sent to the Z80 SIO by examining the internal program status.

UM008101-0601 Serial Input/Output 247 3 . T of o r c et h eZ 8 0S I Ot os e n dC R C ,t h eC P Ui s s u e st h eR e s e t Transmit Underrun/EOM Latch command (WR0) and satisfies the interrupt with the Reset Transmit Interrupt Pending command. (This command prevents the Z80 SIO from requesting more data.) Because of the transmit underrun caused by this command, the Z80 SIO starts sending CRC. The Z80 SIO also causes an External/Status interrupt with the Transmit Underrun/EOM latch set. 4. The CPU satisfies this interrupt by loading pad characters to the transmit buffer and issuing the Reset External/Status Interrupt command. 5. With this sequence, CRC is followed by a pad character instead of a sync character. The Z80 SIO interrupts with a Transmit Buffer Empty interrupt when CRC is completely sent and that the pad character is loaded to the transmit shift register. 6. From this point on the CPU can send more pad characters or sync characters. Bisync CRC Generation Setting the Transmit CRC enable bit (WR5, D0) initiates CRC accumula- tion when the program sends the first data character to the Z80 SIO. Although the Z80 SIO automatically transmits up to two sync characters (18-bit sync), it is recommended to send a few more sync characters ahead of the message (before enabling Transmit CRC) to ensure synchronization at the receiving end. The transmit CRC Enable bit can be changed at any time in the message to include or exclude a particular data character from CRC accumulation. The Transmit CRC Enable bit should be in the suitable state when the data char- acter is loaded from the transmit data buffer to the transmit shift register. To ensure this bit is in a suitable state, the Transmit CRC Enable bit must be issued before sending the data character to the Z80 SIO.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 248 Transmit Transparent Mode Transparent mode (Bisync protocol) operation is made possible by the ability to change Transmit CRC Enable on the fly and by the additional capability of inserting 16-bit sync characters. Exclusion of IDLE characters from CRC calculation can be achieved by disabling CRC calculation immediately preceding the IDLE character transfer to the Z80 SIO. In the case of a Transmit Underrun condition in the Transparent mode, a pair of DLE-SYN characters are sent. The Z80 SIO can be programmed to send the DLE-SYN sequence by loading a IDLE character to WR6 and a sync character to WR7. Transmit Termination The Z80 SIO is equipped with a special termination feature that maintains data integrity and validity. If the transmitter is disabled while a data or sync character is being sent, that character is sent as usual, but is followed by a marking line rather than CRC or sync characters. When the transmitter is disabled, a character in the buffer remains in the buffer. If the transmitter is disabled while CRC is being sent, the 16-bit transmission is completed, but sync is sent instead of CRC. A programmed break is effective as soon as it is written to the control register; therefore, characters in the transmit buffer and shift register are lost. In all modes, characters are sent with the least-significant bits first. This requires right justification of transmitted data if the word length is less than eight bits. If the word length is five bits or less, the special technique described in the Write Register 5 discussion (Z80 SIO Programming section) must be used for the data format. The states of any unused bits in a data character are irrelevant except when in the Five Bits Or Less mode. If the External/Status Interrupt Enable bit is set, transmitter conditions such as “starting to send CRC characters,”“starting to send sync characters,” and CTS changing state cause interrupts that have a unique vector if Status Affects Vector is set. This interrupt mode may be used during block transfers.

UM008101-0601 Serial Input/Output 249 All interrupts may be disabled for operation in a Polled mode or to avoid interrupts at inappropriate tunes during the execution of a program. Synchronous Receive Initialization The system program initiates the Synchronous Receive operation with the following parameters: odd or even parity, 8-bit or 16-bit sync characters, x1 clock mode, CRC polynomial, receive character length, and more. Sync characters must be loaded to registers WR6 and WR7. The receivers can be enabled only after all receive parameters are set. WR4 parameters must be issued before WR1, WR3, WR5, WR6, and WR7 parameters or commands. After these condititons are met, the receiver is in the Hunt phase. It remains in this phase until character synchronization is achieved. Under program control, all the leading sync characters of the message can be inhibited from loading the receive buffers by setting the Sync Character Load Inhibit bit in WR3. Data Transfer and Status Monitoring After character synchronization is achieved, the assembled characters are transferred to the receive data FIFO. The following four interrupt modes are available to transfer the data and its associated status to the CPU. No Interrupts Enabled This mode is used for a purely polled operation or for off-line conditions. Interrupt On First Character Only This mode is normally used to start a polling loop or a Block Transfer instruction using WAIT /READY to synchronize the CPU or the DMA device to the incoming data rate. In this mode, the Z80 SIO interrupts on the first character and thereafter interrupts only if Special Receive condi-

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 250 tions are detected. The mode is reinitialized with the Enable Interrupt On Next Receive Character command to allow the next character received to generate an interrupt. Parity errors do not cause interrupts in this mode, but End-of-Frame (SDLC mode) and Receive Overrun do. If External/Status interrupts are enabled, they may interrupt any time DCD changes state. Interrupt On Every Character Whenever a character enters the receive buffer, an interrupt is generated. Error and Special Receive conditions generate a special vector if Status Affects Vector is selected. Optionally, a Parity Error may be directed not to generate the special interrupt vector. Special Receive Condition Interrupts The Special Receive Condition interrupt can occur only if either the Receive Interrupt On First Character Only or Interrupt On Every Receive Character modes is also set. The Special Receive Condition interrupt is caused by the Receive Overrun error condition. Since the Receive Overrun and Parity error status bits are latched, the error status-when read-reflects an error in the current word in the receive buffer in addition to any Parity or Overrun errors received after the last Error Reset command. These status bits can only be reset by the Error reset command. CRC Error Checking and Termination A CRC error check on the receive message can be performed on a per char- acter basis under program control. The Receive CRC Enable bit (WR3, D3) must be set/reset by the program before the next character is transferred from the receive shift register to the receive buffer register. This ensures proper inclusion or exclusion of data characters in the CRC check. To allow the CPU ample time to enable or disable the CRC check on a particular character, the Z80 SIO calculates CRC eight bit times after the character has been transferred to the receive buffer. If CRC is enabled

UM008101-0601 Serial Input/Output 251 before the next character is transferred, CRC is calculated on the transferred character. If CRC is disabled before the time of the next transfer, calcula- tion proceeds on the word in progress, but the word just transferred to the buffer is not included. When these requirements are satisfied, the 3-byte receive data buffer is, in effect, unusable in Bisync operation. CRC may be enabled and disabled as many times as necessary for a given calculation. In the Monosync, Bisync, and External Sync modes, theCRC/Framing Error bit (RR1, D6) contains the comparison result of the CRC checker 16-bit times (eight bits delay and eight shifts for CRC) after the character has been transferred from the receive shift register to the buffer. The result should be zero, indicating an error-free transmission. The result is valid only at the end of CRC calculation. If the result is examined before this time, it usually indicates an error. The comparison is made with each transfer and is valid only as long as the character remains in the receive FIFO. Following is an example of the CRC checking operation when four charac- ters (A, B, C, and D) are received in that order.  Character A loaded to buffer  Character B loaded to buffer If CRC is disabled before C is in the buffer, CRC is not calculated on B.  Character C loaded to buffer After C is loaded, the CRC/Framing Error bit shows the result of the comparison through character A.  Character D loaded to buffer After D is in the buffer, the CRC Error bit shows the result of the comparison through character B whether or not B was included in the CRC calculations. Due to the serial nature of CRC calculation, the Receive Clock (RxC ) must cycle 16 times (8-bit delay plus 8-bit CRC shift) after the second Note:

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 252 CRC character has been loaded to the receive buffer, or 20 times (the previous 16 plus 3-bit buffer delay and 1-bit input delay) after the last bit is at the RxD input, before CRC calculation is complete. A faster external clock can be gated to the Receive Clock input to supply the required 16 cycles. The Transmit and Receive Data Path diagram (Figure 109) illus- trates the various points of delay in the CRC path. The typical program steps that implement a half-duplex Bisync Receive mode are illustrated in Table 7. The complete set of command and status bit definitions are explained under “ Programming” on page 272. T a b l e7 .B i s y n cR e c e i v eM o d e Function Typical Program Steps Comments Register Information Loaded Initialize WR0 Channel Reset, Reset Receive CRC Checker Reset SIO; initialize receive CRC checker WR0 Pointer 2 WR2 Interrupt V ector Channel B only WR0 Pointer 4 WR4 Parity Information, Sync Modes Information, Clock Mode Issue Receive Parameters WR0 Pointer 5, Reset External Status Interrupt WR5 Bisync CRC-16, Data Terminal Ready WR0 Pointer 3 WR3 Sync Character Load Inhibit, Receive CRC Enable; Enter Hunt Mode, Auto Enables, Receive Character Length Sync Character Load Inhibit strips all the leading sync characters at the beginning of the message. Auto Enables enables the receiver to accept data only after the DCD input is active. WR0 Pointer 6 WR6 Sync Character 1 WR0 Pointer 7 WR7 Sync Character 2

receiving SOH or STX character. Table 7. Bisync Receive Mode (Continued)

• Transfers data byte to CPU
• Detects and sets appropriate flags for control characters (in CPU)
• Includes/Excludes data byte in CRC checker
• Updates pointers and other parameters
• Enables Wait/Ready for DMA operation
• Enables DMA controller
• Returns from Interrupt When Wait/Ready becomes active, the DMA controller performs the following:
• Transfers Data Byte to memory
• Interrupts CPU if a special character is captured by the DMA controller
• Interrupts the CPU if the last character of the message is detected For Message Termination, the CPU performs the following: The SIO interrupts the CPU for error condition, and the error routine aborts the present message, clears the error condition, and repeats the operation.
• Transfers RR1 to the CPU
• Sets Ack/Nak Reply Flag based on CRC result
• Updates pointers and parameters
• Returns from Interrupt

covered because of the similarity between SDLC and HDLC. allowing it to accept or reject the frame.

and Transmit modes. WR0 points to other registers and issues commands. stores the flag character and WR6 the secondary address. Figure 113. Transmit/Receive SDLC/HDLC Message Format

UM008101-0601 Serial Input/Output 257 “Synchronous Operation ” on page 238 section for more details on the interrupt modes. After reset, or when the transmitter is not enabled, the Transmit Data output is held marking. Break may be programmed to generate a spacing line. With the transmitter fully initialized and enabled, continuous flags are transmitted on the Transmit Data output. An abort sequence may be sent by issuing the Send Abort command WR0 CMD1). The Send Abort command causes at least 8, but less than 14, 1s to be sent before the line reverts to continuous flags. It is possible that the Abort sequence (eight 1s) could follow up to five continuous 1 bits (allowed by the zero insertion logic) and thus cause up to thirteen 1s to be sent. Any data being transmitted and any data in the transmit buffer is lost when an abort is issued. When required, an extra 0 is automatically inserted when five contiguous 1s occur in the data stream. Automatic insertion does not apply to flags or aborts. Data Transfer and Status Monitoring SDLC mode allows several combinations of interrupts and Wait/Ready functions. Data Transfer Using Interrupts If the Transmit Interrupt Enable bit is set, an interrupt is generated when the buffer becomes empty. The interrupt may be satisfied either by writing another character to the transmitter or by resetting the Transmit Interrupt Pending latch with a Reset Transmitter Pending command (WR0, CMD5). If the interrupt is satisfied with this command and no more is written to the transmitter, then no more transmitter interrupts occur. The result is a Transmit Underrun condition. When another character is written and sent, the transmitter can again become empty and interrupt the CPU. Following the flags in an SDLC operation, the 8-bit address field, control field and

until after the first data character is written. Table 8. Contents of Write Registers 3, 4, and 5 in SDLC Modes

0 Tx Enable 0

UM008101-0601 Serial Input/Output 259 the Z80 SIO with this mode using the Wait/Ready function. The Z80 SIO transmits the Frame Check sequence using the Transmit Underrun feature. SDLC Transmit Underrun/End of Message SDLC-like protocols do not have provisions for fill characters within a message. The Z80 SIO therefore automatically terminates an SDLC frame when the transmit data buffer and output shift register have no more bits to send. It does this by first sending the two bytes of CRC followed by one or more flags. This technique allows very high-speed transmissions under DMA or CPU block I/O control without requiring the CPU to respond quickly to the end of message condition. The Z80 SIO response to the underrun condition depends on the state of the Transmit Underrun/EOM command. Following a reset, the Transmit Underrun/EOM status bit is in the set state and prevents the insertion of CRC characters while there is no data to send. Consequently, flag charac- ters are sent. The Z80 SIO starts sending the frame while data is written to t h et r a n s m i tb u f f e r .B e t w e e nt h et i m et h ef i r s td a t ab y t ei sw r i t t e na n dt h e end of the message, the Reset Transmit Underrun/EOM Command must be issued. Thus the Transmit Underrun/EOM status bit is in the reset state at the end of the message (when underrun occurs), which automatically sends the CRC characters. The sending of CRC again sets the Transmit/Underrun/ EOM status bit. Although there is no restriction about when the Transmit Underrun/EOM bit can be reset within a message, the reset usually occurs after the first data character (secondary address) is sent to the Z80 SIO. Resetting this bit allows CRC and flags to be sent when there is no data to send, allowing additional time for the CPU to recognize the fault and respond with an abort command. By resetting this bit early in the message, the entire message is allotted the maximum amount of CPU response time in an unintentional transmit underrun situation. When the External/Status interrupt is set and while CRC is sent, the Transmit Underrun/EOM bit is set and the Transmit Buffer Empty bit is reset to indicate that the transmit register is full of CRC data. When CRC

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 260 has been completely sent, the Transmit Buffer Empty status bit is set and an interrupt is generated to indicate to the CPU that another message can begin. This interrupt occurs because CRC is sent and the flag is loaded. If no more messages are to be sent, the program can terminate transmission by resetting RTS , disabling the transmitter. In the SDLC mode, reset the Transmit Underrun/EOM status bit immedi- ately after the first character is sent to the Z80 SIO. When the Transmit Underrun is detected, this ensures that the transmission time is filled by CRC characters, giving the CPU enough time to issue the Send Abort command. This procedure also stops the flags from going on the line prematurely and eliminates the possibility of the receiver accepting the frame as valid data. For example, the data pattern, immediately preceding the automatic flag insertion, could match the CRC checker, thereby giving a false CRC check result. The External/Status interrupt is generated when- ever the Transmit Underrun/EOM bit is set as a result of the Transmit Underrun condition. The transmit underrun logic provides additional protection from premature flag insertion if the proper response is given to the Z80 SIO by the CPU interrupt service routine. The following example illustrates this point: 1. The Z80 SIO interrupts with the Transmit Buffer Empty status bit set. 2. The CPU does not respond in a timely manner, which causes a Transmit Underrun condition. 3. The Z80 SIO starts sending CRC characters (two bytes). 4. The CPU eventually satisfies the Transmit Buffer Empty interrupt with a data character that follows the CRC character being transmitted. 5. The Z80 SIO sets the External/Status interrupt with the Transmit Underrun/EOM status bit set 6. The CPU recognizes the Transmit Underrun/EOM status and determines from its internal program status that the interrupt is not “end of message”.

UM008101-0601 Serial Input/Output 261 7. The CPU immediately issues a Send Abort Command WR0 to the Z80 SIO. 8. The Z80 SIO sends the Abort sequence by destroying whatever data (CRC, data, or flag) is being sent. As this sequence describes, the CPU has a protection of 22 minimum and 30 maximum transmit clock cycles. SDLC CRC Generation Reset the CRC generator to all 1s at the beginning of each frame before CRC accumulation begins. Actual accumulation begins when the program sends the address field (eight bits) to the Z80 SIO. Although the Z80 SIO automatically transmits one flag character following the Transmit Enable, send a few more flag characters ahead of the message to ensure that char- acter synchronization occurs at the receiving end. Synchronization is accomplished by externally timing out after enabling the transmitter, and before loading the first character. The Transmit CRC Enable (WR5, D0) must be enabled before sending the address field. In the SDLC mode, all the characters between the opening and closing flags are included in CRC accumulation, and the CRC gener- ated in the Z80 SIO transmitter is inverted before it is sent on the line. Transmit Termination If the transmitter is disabled while a character is being sent, that Character (data or flag) is sent, but is followed by a marking line rather than CRC or flag characters. A character in the buffer while the transmitter is disabled, remains in the buffer; however, a programmed Abort sequence executes when it is written to the control register. Characters being transmitted, if any, are lost. In the case of CRC, the 16-bit transmission is completed if the transmitter is disabled; however, flags are sent in place of CRC.

Write Register 5” on page 289. is loaded from the transmit buffer to the transmitter. Vector is set. All interrupts can be disabled for operation in a polled mode. Table 9. SDLC Transmit Mode

the status of Tx Underrun/EOM Latch. Table 9. SDLC Transmit Mode (Continued)

changed on-the-fly for variable I-Field length.

• Changes Transmit Word Length (if necessary)
• Transfers Data Byte from CPU (memory) to SIO
• Resets Tx Underrun/EOM Latch WR0 If the last character of the I- Field is sent, the SIO performs the following:
• Sends CRC
• Sends Closing Flag
• Interrupts CPU with Buffer Empty status The CPU performs the following:
• Issues Reset Tx Interrupt Pending Command to the Z80 SIO
• Updates NS count
• Repeats the process for next message, and more. If the Vector Indicates an error, the CPU performs the following:
• Sends Abort
• Executes Error Routine
• Updates Parameters, Modes, and more

WR3, WR5, WR6, and WR7 parameters. field matches either address, data transfer begins. suspends reception and searches for a new message headed by a flag.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 266 Because the control field of the frame is transparent to the Z80 SIO, it is transferred to the CPU as a data character. Extra zeros inserted in the data stream are automatically deleted; flags are not transferred to the CPU. Data Transfer and Status Monitoring After receipt of a valid flag, the assembled characters are transferred to the receive data FIFO. The following four interrupt modes are available to transfer this data and its associated status. No Interrupts Enabled This mode is used for purely polled operations or for off-line conditions. Interrupt On First Character Only Use this mode to start a software polling loop or a Block Transfer instruc- tion using WAIT /READY to synchronize the CPU or FNMA device to the incoming data rate. In this mode, the Z80 SIO interrupts on the first char- acter and thereafter only interrupts if Special Receive conditions are detected. The mode is reinitialized by the Enable Interrupt On Next Receive Character Command. The first character received after this command is issued causes an inter- rupt. If External/Status interrupts are enabled, they may interrupt any time the DCD input changes state. Special Receive conditions such as End-of- Frame and Receiver overrun also cause interrupts. The End-of-Frame inter- rupt can be used to exit the Block Transfer mode. Interrupt On Every Character An interrupt is generated whenever the receive FIFO contains a character. Error and Special Receive conditions generate a special vector if Status Affects vector is selected.

UM008101-0601 Serial Input/Output 267 Special Receive Condition Interrupts The Special Receive Condition interrupt is not, as such, a separate interrupt mode. Before the Special Receive condition can cause an interrupt, either Interrupt On First Receive Character only or Interrupt On Every Character must be selected. The Special Receive Condition interrupt is caused by a Receive Overrun or End-of-Frame detection. When the Receive Overrun status bit is latched, the error status read indicates that an error occurred in the current word in the receive buffer in addition to any errors received after the last Error Reset command. The Receive overrun status bit can only be reset by the Error Reset command. The End-of-Frame status bit indicates that a valid ending flag has been received and that the CRC Error and Residue codes are also valid. Character length may be changed on-the-fly. If the address and control bytes are processed as 8-bit characters, the receiver may be switched to a shorter character length while the first information character is being assembled. This change must be made fast enough so that it is effective before the number of bits specified for the character length have been assembled. For example, if the change is to be from the 8-bit control field to a 7-bit information field, the change must be made before the first seven bits of the I-Field are assembled. SDLC Receive CRC Checking Control of the receive CRC checker is automatic. It is reset by the leading flag and CRC is calculated up to the final flag. The byte that has the End-of- Frame bit set is the byte that contains the result of the CRC check. If the CRC/Framing Error bit is not set, the CRC indicates a valid message. A special check sequence is used for the SDLC check because the transmitted CRC check is inverted. The final check must be 0001110100001111 . The 2-byte CRC check characters must be read by the CPU and discarded because the Z80 SIO, while using them for CRC checking, treats them as ordinary data.

If enabled, a special vector is generated when the closing flag is received. This signals that the byte with the End-of-Frame bit set has been received. guish between the Abort and Idle line conditions. 8-bit delay because all the characters are included in CRC calculation. Table 10. SDLC Receive Mode

Affects Vector in Channel B only. entry point for next transaction. WR3 reissued to enable receiver. Table 10. SDLC Receive Mode (Continued)

address field to interrupt the CPU. address matches the message address.

• Transfers Data Byte (address byte) to CPU
• Detects And Sets appropriate Flag for Extended Address Field
• Updates pointers and parameters
• Enables DMA Controller
• E n a b l e sW a i t / R e a d yf u n c t i o ni nS I O
• Returns from Interrupt When the Ready Output becomes active, the DMA Controller performs the following: During the DMA operation, the SIO monitors the DCD Input and the Abort sequence in the data stream to interrupt the CPU with external status error. The special receive condition interrupt is caused by the Receive Overrun Error.
• Transfers the Data Byte to memory
• Updates the pointers

transferred to memory under DMA.

• Exits DMA Mode (disables Wait/ Ready)
• Transfers RR1 to the CPU
• Checks the CRC error bit status and residue codes
• Updates NR count
• Issues Error Reset Command to SIO When Abort Sequence Detected Interrupt occurs, the CPU performs the following:
• Transfers RR0 to the CPU
• Exits DMA Mode
• Issues the Reset External Status Interrupt Command to the SIO
• Enters the Idle Mode CPU is waiting for Abort Sequence to terminate. Termination clears the Break/Abort status bit and causes interrupt. at this point, the program proceeds to terminate this message. When the second Abort Sequence Interrupt occurs, the CPU performs the following:
• Issues the Reset External Status Interrupt Command to the SIO Termination Redefine Interrupt Modes, Sync Mode and SDLC Modes, Disable Receive Mode

parameters are issued in the initialization routine. system program prior to operation. Table 11. Channel Select Functions

UM008101-0601 Serial Input/Output 273 characteristics of the channels. With the exception of WR0, programming the write registers requires two bytes. The first byte contains three bits (D2- D0) that point to the selected register; the second byte is the actual control word that is written into the register to configure the Z80 SIO. After pointing to the selected register, a programmer can either read to test the read register or write to initialize the write register. The Z80 SIO software can be initialized in either a modular or structured mode, allowing the programmer to use powerful block I/O instructions. WR0 functions as a unique register because all the basic commands (CM02-CMDO) can be accessed with a single byte. Reset (internal or external) initializes the pointer bits D0-D2 to point to WR0. The basic commands (CMD2-CMD0) and the CRC controls (CRC0, CRC1) are contained in the first byte of any write register access. This allows maximum flexibility and system control. Each channel contains the following control registers. These registers are addressed as commands, not data. Write Register 0 WR0, (Figure 114) is the command register; however, it is also used for CRC reset codes and points to the other registers. T a b l e1 2 .W r i t eR e g i s t e r0 D7 D6 D5 D4 D3 D2 D1 DO CRC CRC CMD CMD CMD PTR PTR PTR R e s e t R e s e t 210210 Code Code

Figure 114. Write Register 0

generate a sequence of eight to thirteen 1s. CPU has time to read the change. be rewritten after a Channel Reset command. same amount of time that is used by the CPU to fetch the next Op Code. Table 13. Z80 SIO Commands

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 276 Command 4 (Enable Interrupt On Next Receive Character). If the Interrupt On First Receive Character mode is selected, command 4 reactivates the Enable Interrupt On Next Receive Character mode after receiving each complete message. This sequence prepares the Z80 SIO for the next message. Command 5 (Reset Transmitter Interrupt Pending). A transmitter interrupt occurs when the transmit buffer becomes empty. This interrupt happens only when the Transmit Interrupt Enable mode is selected. When there are no more characters to be sent for example, at the end of message, issuing this command prevents further transmitter interrupts until after the next character is loaded to the transmit buffer or until CRC is completely sent. Command 6 (Error Reset). This command resets the error latches. Parity and Overrun errors are latched in RR1 until they are reset with this command. Using this method, parity errors occurring in block transfers can be examined at the end of the block. Command 7 (Return From Interrupt). This command must be issued in Channel A and is interpreted by the Z80 SIO in the same way it interprets an RETI command on the data bus. This command resets the interrupt under-service latch of the highest priority internal device under service. This reset allows lower-priority devices to interrupt through the daisy- chain. This command also allows use of the internal daisy-chain even in systems with no external daisy-chain or RETI command. CRC Reset Codes 0 and 1 (D6 and D7). Used together, these bits select one of the three following reset commands, described in Table 14

Table 14. Reset Commands

transmission when the Transmit Underrun/EOM latch sets. If enabled, interrupts occur whenever the transmitter buffer becomes empty. programmed in WR2 is returned from an interrupt acknowledge sequence. can cause an interrupt that modifies the interrupt vector. Table 16. Vector Results

Figure 115. Write Register 1 Table 17. Receive Interrupt Modes

WAIT/READY output is in the open-drain state and goes Low when active. responds to the condition of the transmit buffer (empty or full). Table 18. Wait/Ready Functions

UM008101-0601 Serial Input/Output 281 IORQ and the corresponding S/A and C/D inputs to the Z80 SIO to transfer data. The READY output becomes inactive when IORQ and CS become active. The Ready function can occur internally in the Z80 SIO, whether it is addressed or not. Therefore, the READY output becomes inactive when any CPU data or command transfer occurs. Because the DMA controller is not enabled when the CPU transfer occurs, the system continues to function normally. The Wait function is active only when the CPU attempts to read Z80 SIO data that has not yet been received, which occurs frequently when block transfer instructions are used. The Wait function can also become active (under program control) if the CPU tries to write data while the transmit buffer is still full. The WAIT output for either channel becomes active when the opposite channel is addressed. This active state occurs because the Z80 SIO is addressed and does not affect software loops or block move instructions. Write Register 2 WR2 (Figure 116) is the interrupt vector register and occurs in Channel B only. V7-V4 and V0 are always returned exactly as written; V3-V1 are returned as written if the Status Affects V ector (WR1, D2) control bit is 0. If this bit is 1, they are modified as explained in “ Write Register 1” on page 277. T a b l e1 9 .W r i t eR e g i s t e r2I n t e r r u p tV e c t o r D7 D6 D5 D4 D3 D2 D1 D0 V7 V6 V5 V4 V3 V2 V1 V0

Figure 116. Write Register 2 WR3 (Figure 117) contains receiver logic control bits and parameters. Table 20. Write Register 3 Logic Control

UM008101-0601 Serial Input/Output 283 Sync Character Load Inhibit (D1) Sync characters preceding the message (leading sync characters) are not loaded into the receive buffers if this option is selected. Because CRC calculations are not stopped by sync character stripping, this feature should be enabled only at the beginning of the message. Address Search Mode (D2) If SDLC is selected, no receive interrupts can occur in the Address Search mode without an address match. Therefore, messages containing addresses that do not match the programmed address in WR6 or the global ( 1111 1111) are rejected. Receiver CRC Enable (D3) If this bit is set, CRC calculation starts or restarts at the beginning of the last character transferred from the receive shift register to the buffer stack. This start or restart occurs regardless of the number of characters in the stack. For more information about setting this bit, see “SDLC Receive CRC Checking” (SDLC Receive section) and “CRC Error Checking” (Synchronous Receive section). Enter Hunt Phase (D4) The Z80 SIO automatically enters the Hunt phase after a reset. However, it can be re-entered if character synchronization is lost (Synchronous mode) or if the contents of an incoming message are not needed (SDLC mode). The Hunt phase is reentered by writing a 1 to bit D4. This sets the Sync/ Hunt bit (D4) in RR0. Auto Enables(D5) If this mode is selected, DCD and CTS become the receiver and transmitter enables, respectively. If this bit is not set, DCDand CTS are simply inputs to their corresponding status bits in RR0.

Figure 117. Write Register 3 currently programmed number of bits is reached. WR4 contains the control bits that affect both the receiver and transmitter. Table 21. Serial Bits/Character

(00) designates that a synchronous mode is to be selected. Table 22. Write Register 4 Rx and Tx Control Table 23. Stop Bits

These bits select various options for character synchronization. Figure 118. Write Register 4 Table 24. Sync Modes

1 Stop Bit/Character

2 Stop Bits/Character

bit synchronization must be performed externally. exception of D2, which affects the transmitter and receiver. Table 25. Clock Rate

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 288 Request To Send (D1) This is the control bit for The RTS pin. When the RTS bit is set, the RTS pin goes Low; when reset, RTS goes High. In the Asynchronous mode, RTS goes High only after all the bits of the character are transmitted and the transmitter buffer is empty. In Synchronous modes, the pin directly follows the state of the bit. CRC-16/SDLC (D2) This bit selects the CRC polynomial used by both the transmitter and receiver. When set, the CRC-16 polynomial (X 16 +X15 +X 2 +1 )i su s e d ; when reset, the SDLC polynomial (X16 +X 12 +X 5 +1 )i su s e d .I ft h eS D L C mode is selected, the CRC generator and checker are preset to 1s and a special check sequence is used. The SDLC CRC polynomial must be selected when the SDLC mode is selected. If the SDLC mode is not selected, the CRC generator and checker are preset to 0s for both polynomials. Transmit Enable (D3) Data is not transmitted until this bit is set, and the Transmit Data output is held marking. Data or sync characters in the process of being transmitted are completely sent if this bit is reset after transmission is started. If the transmitter is disabled during the transmission of a CRC character, sync, or flag characters are sent instead of CRC. Send Break (D4) When set, this bit immediately forces the Transmit Data output to the spacing condition, regardless of any data being transmitted. When reset, TxD returns to marking.

Figure 119. Write Register 5 Table 27. Transmit Bits

when reset, DTR is inactive (High). used to compare against the address field of the SDLC frame. Figure 120. Write Register 6 Table 28. Data Character Format

is not used in the External Sync mode. Figure 121. Write Register 7

conditions, interrupt vector, and standard communications-interface signals. contents of the addressed read register can be read by the CPU. read from a single register (RR1). it is reset when the receive FIFO is empty. Table 31. Read Register 0 Rx and Tx Buffers

UM008101-0601 Serial Input/Output 293 Interrupt Pending (D1) A n yi n t e r r u p t i n gc o n d i t i o ni nt h eZ 8 0S I Oc a u s e st h i sb i tt os e t ;h o w e v e r ,i t is readable only in Channel A. This bit is primarily used in applications not having vectored interrupts available. During the interrupt service routine in these applications, this bit indicates if any interrupt conditions are present in the Z80 SIO. This eliminates the need for analyzing all the bits of RR0 in both Channels A and B. Bit D1 is reset when all the interrupting conditions are satisfied. This bit is always 0 in Channel B. Transmit Buffer Empty (D2) This bit is set whenever the transmit buffer becomes empty, except when a CRC character is being sent in a synchronous or SDLC mode. The bit is reset when a character is loaded into the transmit buffer. This bit is in the set condition after a reset. Data Carrier Detect (D3) The DCD bit indicates the state of the DCD input at the time of the last change of any of the five External/Status bits (DCD,C T S,S y n c / H u n t , Break/ Abort, or Transmit Underrun/EOM). Any transition of the DCD input causes the DCD bit to latch and causes an External/Status interrupt. To read the current state of the DCDbit, this bit must be read immediately following a Reset External/Status Interrupt command. Sync/Hunt (D4) Because this bit is controlled differently in the Asynchronous, Synchronous, and SDLC modes, its operation is somewhat more complex than that of the other bits and therefore requires more explanation. In asynchronous modes, the operation of this bit is similar to the DCD status bit, except that Sync/Hunt shows the state of the SYNCinput. Any High-to-Low transition on the SYNC pin sets this bit and causes an External/Status interrupt (if enabled). The Reset External/Status Interrupt command is issued to clear the interrupt. A Low-to-High transition clears

command to read the current state of tile SYNC input. Figure 122. Read Register 0 holds the Sync/Hunt status bit in the reset condition. that a new message is about to start. Refer to Figure 122 for timing details. interrupt by issuing the Reset External/Status Interrupt command.

UM008101-0601 Serial Input/Output 295 When the SYNC input goes High again, another External/ Status interrupt is generated that must also be cleared. The Enter Hunt Mode control bit is set whenever character synchronization is lost or the end of message is detected. In this case, the Z80 SIO again looks for a High-to-Low transition of the SYNC input and the operation repeats as explained previously. This implies the CPU should also inform the external logic that character synchronization has been lost and that the Z80 SIO is wailing for SYNC to become active. In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to 1 by the Enter Hunt Mode bit. The Sync/Hunt bit is reset when the Z80 SIO establishes character synchronization. The High-to-Low transition of the Sync/Hunt bit causes an External/Status interrupt that must be cleared by the CPU issuing the Reset External/ Status Interrupt command. This enables the Z80 SIO to detect the next transition of other External/Status bits. When the CPU detects the end of message or loss of character synchroniza- tion, it sets the Enter Hunt Mode control bit, which-in turn-sets the Sync/ Hunt bit to 1. The Low-to-High transition of the Sync/Hunt fit sets the External/Status interrupt, which must also be cleared by the Reset External/ Status Interrupt command. The SYNC pin functions as an output in this mode and goes Low when a sync pattern is detected in the data stream. In the SDLC mode, the Sync/Hunt bit is initially set by the Enter Hunt mode bit, or when the receiver is disabled. It is reset to 0 when the opening flag of the first frame is detected by the Z80 SIO. The External/Status inter- rupt is also generated, and should be handled as discussed previously. Unlike the Monosync and Bisync modes, when the Sync/Hunt bit is reset in the SDLC mode, it does not need to be set when the end of message is detected. The Z80 SIO automatically maintains synchronization. The Sync/ Hunt bit can only be set again by the Enter Hunt Mode bit or by disabling the receiver.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 296 Clear To Send, (D5). This bit is similar to the DCDbit, except that it shows the inverted state of the CTS pin. Transmit Underrun/End of Message (D6) This bit is in a set condition following a reset, either internal or external. The only the Reset Transmit Underrun/EOM Latch command (WR0, D6 and D7) can reset this bit. When the Transmit Underrun condition occurs, this bit is set; causing the External/Status interrupt, which is reset by issuing the Reset External/Status Interrupt command bits (WR0). This status bit, along with other control bits, has an important function in controlling a transmit operation. For more information, see“Bisync Transmit Underrun” and “SDLC Transmit Underrun”. Break/Abort (D7) In the Asynchronous Receive mode, this bit is set when a Break sequence (null character plus framing error) is detected in the data stream. The External/Status interrupt, if enabled, is set when Break is detected. The interrupt service routine must issue the Reset External/Status Interrupt command (WR0, CMD2) to the break detection logic, enabling the Break sequence termination to be recognized. The Break/Abort bit is reset when the termination of the Break sequence is detected in the incoming data stream. The termination of the Break sequence also causes the External/Status interrupt to set. The Reset External/Status Interrupt command must be issued to enable the break detection logic to look for the next Break sequence. When a single extra- neous null character is present in the receiver after the termination of a break; it should be read and discarded. In the SDLC Receive mode, this status bit is set by the detection of an Abort sequence (seven or more 1s). The External/Status interrupt is handled the same way as a Break. The Break/Abort bit is not used in the Synchro- nous Receive mode.

codes for the I-Field in the SDLC Receive Mode. rupts and it is always set in synchronous modes. Table 32. Read Register 1 Special Receive Condition Status

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 298 I-Field bits are always right justified. If a receive character length is different from eight bits is used for the I- field, a table similar to the previous one may be constructed for each different character length. For no residue, that is, when the last character boundary coincides with the boundary of the I-field and CRC field, the Residue codes are: 01108 11118 00028 T a b l e3 4 .R e c e i v eC h a r a c t e rL e n g t h Bits per Character Residue Code 2 Residue Code 1 Residue Code 0

8 Bits per Character 0 1 1

7 Bits per Character 0 0 0

6 Bits per Character 0 1 0

5 Bits per Character 0 0 1

T a b l e3 3 .R e s i d u eC o d e s Residue Code Residue Code Residue Code I-Field Bits in Previous Byte I-Field Bits in Second Previous Byte

Figure 123. Read Register 1 error occurs, the bit remains set until given the Error Reset command (WR0).

latched) for the receive character in which the Framing Error occurred. in a non-zero CRC except for a correctly completed message. updated by the first character of the following frame. V1 = 1. This register is read only through Channel B. Table 35. Interrupt Vector

UM008101-0601 Serial Input/Output 303 The Z80 DMA controller circuit is used with Z80 SIO/2 to transmit the reformatted data at high speed with the required protocol. The high-speed modem provides the transmit clock for this channel. The Z80 CTC counter- timer circuit supplies the transmit and receive clocks for the low-speed lines and is also used as a time-out counter for various functions. Z80 SIO/1 controls local or remote terminals. A single intelligent terminal is placed within the dashed lines. The terminal employs a Z80 SIO to communicate to the data concentrator on one channel while providing the interface to a line printer over its second channel. The intelligent terminal could be designed to operate interactively with the operator. Depending on the software and hardware capabilities built into this system, the data concentrator can employ store-and-forward or hold-and-forward methods for regulating information traffic between slow terminals and the high-speed remote processor. If the high-speed channel is provided with a dial-out option, the channel can be connected to a number of remote processors over a switched line.

Figure 127. Data Concentrator

Figure 129. Write Cycle Timing requestor. The IEI of the highest priority peripheral is terminated High. service, forces its IEO Low.

Figure 130. Interrupt Acknowledge Cycle Timing c h a i ni nt h ef o l l o w i n gw a y . the interrupt-underservice latch is reset. See Figure 131.

Figure 132. Typical Interrupt Service

1. Channel B Transmitter Service Routine Complete, Second RETI Issued.
2. Channel A External/Status Routine Complete, RETI Issued, Channel B Transmitter Service Resumed.
3. External/Status Channel A Interrupts Suspending Service of Channel B Transmitter.
4. Channel B Transmitter Interrupts and is Acknowledged.
5. Priority Interrupt Daisy Chain before Any Interrupt Occurs.

/G3c /G1a/G12/G2/G25/G32/G37 /G2/G32 /G47/G54 /G4b/G52/G4a /G47 /G54/G43/G4e/G55 /G37/G55/G47 /G54/G2 /G2f /G43/G50 /G57/G43 /G4e UM008101-0601 Serial Input/Output 310