Z5380

Z5380 ZILOG | Alldatasheet

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FEATURES

n Pin Compatible with the Industry Standard 5380 n 40-Pin DIP or 44-Pin PLCC Package Styles n Low-Power CMOS n Asynchronous Interface (Supports 1.5 MB/s) n Direct SCSI Bus Interface with On-Board 48 mA Drivers n Supports Target and Initiator Roles n Arbitration Support n DMA or Programmed I/O Data Transfers n Supports Normal or Block Mode DMA n Memory or I/O Mapped CPU Interface The Z5380 SCSI (Small Computer System Interface) con- troller is designed to implement the SCSI protocol as defined by the ANSI X3.131-1986 standard, and is fully compatible with the industry standard 5380. It is capable of operating both as a Target and as an Initiator. Special high-current open-drain outputs enable the Z5380 to di- rectly interface to, and drive, the SCSI bus. The Z5380 has the necessary interface hook-ups which allows the system CPU to communicate with it like any other peripheral device. The CPU can read from, or write to, the SCSI registers which are addressed as standard or memory- mapped I/Os (Figure 1). The Z5380 increases the system performance by minimiz- ing the CPU intervention in DMA operations which the SCSI controls. The CPU is interrupted by the SCSI when it detects a bus condition that requires attention. It also supports arbitration and reselection. The Z5380 has the proper hand-shake signals to support normal and block mode DMA operations with most DMA controllers avail- able (Figure 2). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power V CC VDD Ground GND V SS GENERAL DESCRIPTION Z5380 SCSI SMALL COMPUTER SYSTEM INTERFACE (SCSI)

/DB7-/DB0, /DBP Data Bus Bits, Data Bus Parity Bit (Bi- directional, Open-drain). These eight data bits (/DB7-/ DB0), plus a parity bit (/DBP) form the data bus. /DB7 is the most significant bit (MSB) and has the highest priority during the Arbitration phase. Data parity is odd. Parity is always generated and optionally checked. Parity is not valid during Arbitration. I//O Input/Output (Bi-directional, Open-drain). I/O is a signal driven by a Target which controls the direction of data movement on the SCSI bus. True indicates input to the Initiator. This signal is also used to distinguish between Selection and Reselection phases. /MSG Message (Bi-directional, Open-drain, Active Low). This signal is driven by the Target during the Message phase. This signal is received by the Initiator. /REQ Request (Bi-directional, Open-drain, Active Low). Driven by the Target and received by the Initiator, this signal indicates a request for a /REQ//ACK data-transfer handshake. /RST SCSI Bus Reset (Bi-directional, Open-drain, Active Low). This signal indicates a SCSI bus Reset condition. /SEL Select (Bi-directional, Open-drain, Active Low). This signal is used by an Initiator to select a Target, or by a Target to reselect an Initiator. PIN DESCRIPTION (Continued) IRQ Interrupt Request (Output, Active High). IRQ alerts a microprocessor of an error condition or an event comple- tion. READY Ready (Output, Active High). Ready is used to control the speed of Block Mode DMA transfers. This signal goes active to indicate the chip is ready to send/ receive data and remains Low after a transfer until the last byte is sent or until the DMA Mode bit is reset. /RESET Reset (Input, Active Low). /RESET clears all reg- isters. It has no effect upon the SCSI /RST signal. SCSI Bus The following signals are all bi-directional, active Low, open-drain, with 48 mA sink capability. All pins interface directly with the SCSI bus. /ACK Acknowledge (Bi-directional, Open-drain, Active Low). Driven by an Initiator, /ACK indicates an acknowl- edgment for a /REQ//ACK data-transfer handshake. In the Target role, /ACK is received as a response to the /REQ signal. /ATN Attention (Bi-directional, Open-drain, Active Low). Driven by an Initiator, received by the Target, /ATN indi- cates an Attention condition. /BSY Busy (Bi-directional, Open-drain, Active Low). This signal indicates that the SCSI bus is being used and can be driven by both the Initiator and the Target device. C//D Control/Data (Bi-directional, Open-drain). Driven by the Target and received by the Initiator, C//D indicates whether Control or Data information is on the Data Bus. True indicates Control. FUNCTIONAL DESCRIPTION implement all or any of the SCSI protocol in software. These registers are read (written) by activating /CS with an address on A2-A0 and then issuing an /IOR (/IOW) pulse. This section describes the operation of the internal regis- ters (Table 1). The Z5380 Small Computer System Interface (SCSI) has a set of eight registers that are controlled by the CPU. By reading and writing the appropriate registers, the CPU may initiate any SCSI Bus activity or may sample and assert any signal on the SCSI Bus. This allows the user to

the value of these internal control bits (Figure 8). /CS and /DACK to be active simultaneously. reset (0), the Z5380 operates as a SCSI Bus Initiator. the characteristics of the DMA DRQ-/DACK handshake. used to request the next transfer. Figure 8. Mode Register Register should contain the proper SCSI device ID value. Only one data bit should be active for SCSI Bus Arbitration. (Initiator Command Register, bits 5 and 6, respectively).

FUNCTIONAL DESCRIPTION (Continued) DMA Registers Three write-only registers are used to initiate all DMA activity. They are: Start DMA Send, Start DMA Target Receive, and Start DMA Initiator Receive. Performing a write operation into one of these registers starts the de- sired type of DMA transfer. Data presented to the Z5380 on signals D7-D0 during the register write is meaningless and has no effect on the operation. Prior to writing these registers, the Block Mode DMA bit (bit 7), the DMA Mode bit (bit 1), and the Target Mode bit (bit 6) in the Mode Register must be appropriately set. The individual regis- ters are briefly described as follows: Start DMA Send. Address 5 (Write Only). This register is written to initiate a DMA send, from the DMA to the SCSI Bus, for either Initiator or Target role operations. The DMA Mode bit (Mode Register, bit 1) is set prior to writing this register. Start DMA Target Receive. Address 6 (Write Only). This register is written to initiate a DMA receive - from the SCSI Bus to the DMA, for Target operation only. The DMA Mode bit (bit 1) and the Target Mode bit (bit 6) in the Mode Register must both be set (1) prior to writing this register. Start DMA Initiator Receive. Address 7 (Write Only). This register is written to initiate a DMA receive - from the SCSI Bus to the DMA, for Initiator operation only. The DMA Mode bit (bit 6) must be False (0) in the Mode Register prior to writing this register. Reset Parity/Interrupt. Address 7 (Read Only). Reading this register resets the Parity Error bit (bit 5), the Interrupt Request bit (bit 4), and the Busy Error bit (bit 2) in the Bus and Status Register. On-Chip SCSI Hardware Support The Z5380 is easy to use because of its simple architec- ture. The chip allows direct control and monitoring of the SCSI Bus by providing a latch for each signal. However, portions of the protocol define timings which are much too quick for traditional microprocessors to control. Therefore, hardware support has been provided for DMA transfers, bus arbitration, phase change monitoring, bus disconnec- tion, bus reset, parity generation, parity checking, and device selection/reselection. Arbitration is accomplished using a bus-free filter to con- tinuously monitor /BSY. If /BSY remains inactive for at least 1.2 µs, the SCSI Bus is considered free and Arbitration may begin. Arbitration will begin if the bus is free, /SEL is inactive, and the Arbitrate bit (Mode Register, bit 0) is active. Once arbitration has begun (/BSY asserted), an arbitration delay of 2.2 µs must elapse before the Data Bus can be examined to determine if Arbitration is enabled. This delay is implemented in the controlling software driver. The Z5380 is a clockwise device. Delays such as bus-free delay, bus-set delay, and bus-settle delay are imple- mented using gate delays. These delays may differ be- tween devices because of inherent process variations, but are well within the proposed ANSI X3.131 - 1986 specifica- tion. Interrupts The Z5380 provides an interrupt output (IRQ) to indicate a task completion or an abnormal bus occurrence. The use of interrupts is optional and may be disabled by resetting the appropriate bits in the Mode Register or the Select Enable Register. When an interrupt occurs, the Bus and Status Register and the Current SCSI Bus Status Register (Figures 12 and 10) must be read to determine which condition created the interrupt. IRQ can be reset simply by reading the Reset Parity/Interrupt Register or by an external chip reset /RESET active for 200 ns. Assuming the Z5380 has been properly initialized, an interrupt is generated if the chip is selected or reselected; if an /EOP signal occurs during a DMA transfer; if a SCSI Bus reset occurs; if a parity error occurs during a data transfer; if a bus phase mismatch occurs; or if a SCSI Bus disconnection occurs. Selection/Reselection Interrupt The Z5380 generates a select interrupt if /SEL is active (0), its device ID is True and /BSY is False for at least a bus- settle delay. If I//O is active, this is considered a reselect interrupt. The correct ID bit is determined by a match in the Select Enable Register. Only a single bit match is required to generate an interrupt. This interrupt may be disabled by writing zeros into all bits of the Select Enable Register. If parity is supported, parity should be good during the selection phase. Therefore, if the Enable Parity bit (Mode Register, bit 5) is active, the Parity Error bit is checked to ensure that a proper selection has occurred. The Enable Parity Interrupt bit need not be set for this interrupt to be generated.

DRQ signal to generate /DACK and an /IOR or an /IOW pulse to the Z5380. DRQ goes inactive when /DACK is asserted and /DACK goes inactive some time after the minimum read or write pulse width. This process is re- peated for every byte. For this mode, /DACK should not be allowed to cycle unless a transfer is taking place. Block Mode DMA Some popular DMA Controllers, such as the 9517A, pro- vide a Block Mode DMA transfer. This type of transfer allows the DMA controller to transfer blocks of data without relinquishing the use of the Data Bus to the CPU after each byte is transferred; thus, faster transfer rates are achieved by eliminating the repetitive access and release of the CPU Bus. If the Block Mode DMA bit (Mode Register, bit 7) is active, the Z5380 begins the transfer by asserting DRQ. The DMA controller then asserts /DACK for the remainder of the block transfer. DRQ goes inactive for the duration of the transfer. The Ready output is used to control the transfer rate. Non-Block Mode DMA transfers end when /DACK goes False, whereas Block Mode DMA transfers end when /IOR or /IOW becomes inactive. Since this is the case, DMA transfers may be started sooner in a Block Mode transfer. To obtain optimum performance in Block Mode operation, the DMA logic optionally uses the normal DMA mode interlocking handshake. Ready is still available to throttle the DMA transfer, but DRQ is 30 to 40 ns faster than Ready and is used to start the cycle sooner. The methods described under “Halting a DMA Operation” apply for all DMA operations. Pseudo DMA Mode To avoid the tedium of monitoring and asserting the re- quest/acknowledgment handshake signals for pro- grammed I/O transfers, the system can be designed to implement a pseudo DMA mode. This mode is imple- mented by programming the Z5380 to operate in the DMA mode, but using the CPU to emulate the DMA handshake. DRQ may be detected by polling the DMA Request bit (bit 6) in the Bus and Status Register, by sampling the signal through an external port, or by using it to generate a CPU interrupt. Once DRQ is detected, the CPU can perform a read or write data transfer. This CPU read/write is exter- nally decoded to generate the appropriate /DACK and /IOR or /IOW signals. Often, external decoding logic is necessary to generate the Z5380 /CS signal. This same logic may be used to generate /DACK at no extra cost and provide an increased performance in programmed I/O transfers. Halting a DMA Operation The /EOP signal is not the only way to halt a DMA transfer. A bus phase mismatch or a reset of the DMA Mode bit (Mode Register, bit 1) can also terminate a DMA cycle for the current bus phase. Using the /EOP Signal If /EOP is used, it should be asserted for at least 100 ns while /DACK and /IOR or /IOW are simultaneously active. Note, however, that if /IOR or /IOW is not active, an interrupt is generated, but the DMA activity continues. The /EOP signal does not reset the DMA Mode bit. Since the /EOP signal can occur during the last byte sent to the Output Data Register, the /REQ and /ACK signals are monitored to ensure that the last byte has transferred. Bus Phase Mismatch Interrupt A bus phase mismatch interrupt is used to halt the transfer if operating as an Initiator. Using this method frees the host from maintaining a data length counter and frees the DMA logic from providing the /EOP signal. If performing an Initiator send operation, the Z5380 requires /DACK to cycle before /ACK goes inactive. Since phase changes cannot occur if /ACK is active, either /DACK must be cycled after the last byte is sent or the DMA Mode bit must be reset in order to receive the phase mismatch interrupt. Resetting the DMA Mode Bit A DMA operation may be halted at any time simply by resetting the DMA Mode bit. It is recommended that the DMA Mode bit be reset after receiving an /EOP or bus phase-mismatch interrupt. The DMA Mode bit must then be set before writing any of the start DMA registers for subsequent bus phases. If resetting the DMA Mode bit is used instead of /EOP for Target role operation, then care must be taken to reset this bit at the proper time. If receiving data as a Target device, the DMA Mode bit must be reset once the last DRQ is received and before /DACK is asserted to prevent an additional /REQ from occurring. Resetting this bit causes DRQ to go inactive. However, the last byte received remains in the Input Data Register and may be obtained either by performing a normal CPU read or by cycling /DACK and /IOR. In most cases, /EOP is easier to use when operating as a Target device.

Figure 44. CPU Write Cycle

1 Address Setup to Write Enable [1] 20 ns

2 Address Hold from End Write Enable [1] 20 ns

3 Write Enable Width [1] 70 ns

4 Chip Select Hold from End of /IOW 0 ns

5 Data Setup to end of Write Enable

6 Data Hold Time form End of /IOW 30 ns

[1] Write Enable is the occurrence of /IOW and /CS.

Figure 45. CPU Read Cycle

1 Address Setup to Read Enable [1] 20 ns

2 Address Hold from End Read Enable [1] 20 ns

3 Chip Select Hold from End of /IOR 0 ns

4 Data Access Time from Read Enable

5 Data Hold Time from End of Read Enable [1] 20 ns

[1] Read Enable is the occurrence of /IOR and /CS.

Figure 46. DMA Write (Non-Block Mode) Target Send Cycle

DMA Write (Non-Block Mode) Target Send Cycle Table No Description Min Max Units

1 DRQ Low from /DACK Low 130 ns

2 /DACK High to DRQ High 30 ns

3 Write Enable Width

[1] 100 ns 4 /DACK Hold from /IOW High 0 ns

5 Data Setup to End of Write Enable [1] 50 ns

6 Data Hold Time from End of /IOW 40 ns

7 Width of /EOP Pulse

[2] 100 ns 8 /ACK Low to /REQ High 25 125 ns 9 /REQ from End of /DACK (/ACK High) 30 150 ns 10 /ACK Low to DRQ High (Target) 15 110 ns 11 /ACK High to /REQ Low (/DACK High) 20 150 ns

12 Data Hold from Write Enable 15 ns

13 Data Setup to /REQ Low (Target) 60 ns

Notes: [1] Write Enable is the occurrence of /IOW and /DACK. [2] /EOP, /IOW, and /DACK must be concurrently Low for at least T7 for proper recognition of the /EOP pulse.

Figure 47. DMA Write (Non-Block Mode) Initiator Send Cycle

DMA Write (Non-Block Mode) Initiator Send Cycle Table No Description Min Max Units 2 /DACK High to DRQ High 30 ns [1] 100 ns 4 /DACK Hold from End of /IOW 0 ns [2] 100 ns 8 /REQ Low to /ACK Low 20 160 ns 9 /REQ High to DRQ High 20 110 ns 10 /DACK High to /ACK High 25 150 ns 11 /IOW High to Valid SCSI Data 100 ns

12 Data Hold from Write Enable [1] 15 ns

Notes: [1] Write Enable is the occurrence of /IOW and /DACK. [2] /EOP, /IOW, and /DACK must be concurrently Low for at least T7 for proper recognition of the /EOP pulse.

Figure 48. DMA Read (Non-Block Mode) Target Receive Cycle

DMA Read (Non-Block Mode) Target Receive Cycle Table No Description Min Max Units 2 /DACK High to DRQ High 30 ns 3 /DACK Hold Time from End of /IOR 0 ns [1] 115 ns

5 Data Hold Time from End of /IOR 20 ns

6 Width of /EOP Pulse

[2] 100 ns 7 /ACK Low to DRQ High 15 110 ns 8 /DACK High to /REQ Low (/ACK High) 30 150 ns 9 /ACK Low to /REQ High 25 125 ns 10 /ACK High to /REQ Low (/DACK High) 20 150 ns

11 Data Setup Time to /ACK 20 ns

12 Data Hold Time from /ACK 50 ns

Notes: [1] Read Enable is the occurrence of /IOR and /DACK. [2] /EOP, /IOR, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.

Figure 49. DMA Read (Non-Block Mode) Initiator Receive Cycle

DMA Read (Non-Block Mode) Initiator Receive Cycle Table No Description Min Max Units 2 /DACK High to DRQ High 30 ns 3 /DACK Hold Time from End of /IOR 0 ns [1] 115 ns [2] 100 ns 7 /REQ Low to DRQ High 20 ns 8 /DACK High to /ACK High (/REQ High) 25 160 ns 9 /REQ Low to /ACK Low 20 160 ns 10 /REQ High to /ACK High (/DACK High) 15 140 ns

11 Data Setup Time to /REQ 20 ns

12 Data Hold Time from /REQ 50 ns

Notes: [1] Read Enable is the occurrence of /IOR and /DACK. [2] /EOP, /IOR, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.

Figure 50. DMA Write (Block Mode) Target Send Cycle

DMA Write (Block Mode) Target Send Cycle Table No Description Min Max Units

2 Write Enable Width [1] 100 ns

3 Write Recovery Time 120 ns

4 Data Setup to End of Write Enable

[1] 50 ns

5 Data Hold Time from End of /IOW 40 ns

[2] 100 ns 7 /ACK Low to /REQ High 25 125 ns 8 /REQ from End of /IOW (/ACK High) 40 180 ns 9 /REQ from End of /ACK (/IOW High) 20 170 ns 10 /ACK Low to READY High 20 140 ns

11 READY High to /IOW High 70 ns

12 /IOW High to READY Low 20 140 ns

13 Data Hold from /ACK Low 40 ns

14 Data Setup to /REQ Low 60 ns

Notes: [1] Write Enable is the occurrence of /IOW and /DACK. [2] /EOP, /IOW, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.

Figure 51. DMA Read (Block Mode) Target Receive Cycle

DMA Read (Block Mode) Target Receive Cycle Table No Description Min Max Units 2 /IOR Recovery Time 120 ns

3 Data Access Time from Read Enable

[1] 110 ns

4 Data Hold Time from End of /IOR 20 ns

5 Width of /EOP Pulse [2] 100 ns

6 /IOR High to /REQ Low 30 190 ns 7 /ACK Low to /REQ High 25 125 ns 8 /ACK High to /REQ Low (/IOR High) 20 170 ns 9 /ACK Low to READY High 20 140 ns

10 READY High to Valid Data 50 ns

11 /IOR High to READY Low 20 140 ns

12 Data Setup Time to /ACK 20 ns

13 Data Hold Time from /ACK 50 ns

Notes: [1] Read Enable is the occurrence of /IOR and /DACK. [2] /EOP, /IOR, and /DACK must be concurrently Low for at least T5 for proper recognition of the /EOP pulse.

Figure 52. Arbitration

1 Bus Clear from /SEL Low 600 ns

2 Arbitrate Start from /BSY High 1200 2200 ns

Figure 53. Reset

1 Minimum Width of /RESET 200 ns

1. Edge-triggered /RST Interrupt. If the SCSI Bus is not terminated, the /RST interrupt is continually gener- ated. 2. True End of DMA Interrupt. The Z5380 generates an interrupt when it receives the last byte from the DMA, not when the last byte is transferred to the SCSI Bus. 3. Return to Ready after /EOP Interrupt. When operat- ing in Block Mode DMA, the Z5380 does not return the Ready signal to a Ready condition. This locks up the bus and prevents the CPU from executing. 4. SCSI handshake after /EOP occurs. If an EOP oc- curs when receiving data, a subsequent request will cause /ACK to be asserted even though no DRQ is issued. 5. Reselection Interrupt. During reselection, if the Tar- get Command Register does not reflect the current bus phase (most likely Data Out), the reselection interrupt may get reset. 6. Phase Mismatch Interrupt. A phase mismatch inter- rupt is not guaranteed after a reselection for the following reasons: – DMA Mode bit must be set in order to receive a phase mismatch interrupt. – DMA Mode bit can not be set unless /BSY is active. – /BSY can not be asserted until after the reselection has occurred. – Once /BSY is asserted, the Target may assert /REQ in less than 500 ns. – The phase mismatch interrupt is generated on the active edge of /REQ. If the DMA Mode bit is not set before the /REQ goes active, the phase mismatch interrupt will not occur.

PACKAGE INFORMATION

40-Pin DIP Package Diagram 44-Pin PLCC Package Diagram

ORDERING INFORMATION

P = Plastic DIP V = Plastic Leadless Chip Carrier Temperature S = 0°C to +70°C E = –40°C to +85°C Speed

1.5 MB/s

C = Plastic Standard Example: Z 5380 01 V S C Environmental Flow T emperature Package Speed Product Number Zilog Prefix is a Z5380, 1.5 MB/s, PLCC, 0°C to +70°C, Plastic Standard Flow Zilog’s products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of mer- chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.