Z16C3510FEE

Z16C35 ZILOG | Alldatasheet

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EEE, MASTER — @ AN . PRODUCT SPECIFICATION A Zil4 SG CMOS ISCC e INTEGRATED SERIAL COMMUNICATIONS ® CONTROLLER gece @ | Ry Ae ee I 02/90 Ry

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CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER

FEATURES

™ Low power CMOS technology Supports ail Zilog CMOS SCC features: ™ Two general-purpose SCC channels, four DMA # Two independent, 0 to 4.0 M bit/second, full-duplex channels; and Universal Bus Interface Unit channels, each with a separate crystal oscillator, baud rate generator, and digital phase-locked loop Circuit for clock recovery. = Software compatible to the Zilog CMOS SCC ™ Multi-protocol operation under program control; = ~4DMAchannels; twotransmit and two receive channels programmable for NRZ, NRZI, or FM data encoding. to and from the SCC ™ Asynchronous mode with five to eight bits and one, ™ 4 gigabyte address range per DMA channel one and one-half, or two stop bits per character; programmable clock factor; break detection and ™ Flyby DMA transfer mode generation; parity, overrun, and framing error detection. ™ Programmable DMA channel priorities @ ™ Synchronous mode with internal or external character ™ Independent DMA register set synchronization on one or two synchronous characters and CRC generation and checking with CRC-16 or = AUniversal Bus Interface Unit providing simple interface CRC-CCITT preset to either 1's or O's. to most CPUs multiplexed or non-multiplexed bus; compatible with 680x0 and 8x86 CPUs ™ ~SDLC/HDLC mode with comprehensive frame-level control, automatic zero insertion and deletion, ™ 32-bit addresses multiplexed to 16-pin address/data \\-field residue handling, abort generation and lines detection, CRC generation and checking, and SDLC Loop mode operation. ® 8-bit data supporting highfow byte swapping ™ Local Loopback and Auto Echo modes ® 10 MHz timing = Supports T1 digital trunk ® 16 MHz timing planned ™ Enhanced SDLC 10x19 Status FIFO for DMA support ® 68-pin PLCC ® Full CMOS SCC register set GENERAL DESCRIPTION The Z16C35 ISCC™ is a CMOS superintegrated device The ISCCis a dual-channel, multi-protocol data communi- with a flexible Bus Interface Unit (BIU) connecting a built- cations peripheral which easily interfaces to CPU's with in Direct Memory Access (DMA) cell to the CMOS Serial _ either multiplexed or non-multiplexed address and data rf) Communications Control (SCC) cell. buses. The advanced CMOS process offers lower power oe

isters allow the ISCC to be configured for a wide variety of higher interrupt priority than the DMA cell. status FIFO, are added to support high speed SDLC _ between DMA transfers. transfers using on-chip DMA controllers. multiplexed addresses. does not support memory-to-memory transfer. This versatile device supports virtually any serial data system DMA's should be handled outside the ISCC. synchronous mode and can be programmed to check _ implemented. Figure 1. Block Diagram @

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Abs CI f] ADi4 a7 [5 apis eno F) exo Ve FH vee @ ~ 5 te | EU CUP ugg g ooo S36 g2¢e g SUf080 92 SE0EE598 r ) Figure 2. Pin Assignments a PIN DESCRIPTION | The following section describes the Z16C35 pin functions. /OTRA, /DTRB. Data Terminal Ready (outputs, active Figures 1 and 2 detail the respective pin functions and pin Low). These outputs follow the state programmegd into the assignments. All references to DMA are internal. DTR bit. /CTSA, /CTSB. Clear To Send(inputs, active Low). Ifthese —_IEI. Interrupt Enable In(input, active High). |El is used with pins are programmed as AutoEnables, aLowontheinputs —_1EO to form an interrupt daisy chain when there is more enables the respective transmitters. Ifnotprogrammedas than one interrupt driven device. A high {EI indicates that Auto Enables, they may be used as general-purpose _no other higher priority device has an interrupt under inputs. Both inputs are Schmitt-trigger buffered toaccom- __ service or is requesting an interrupt. The SCC cell has a modate slow rise-time inputs. The SCC cell detects pulses —_ higher interrupt priority than the DMA cell. on these inputs and can interrupt the CPU on both logic level transitions. IEO. Interrupt Enable Out(output, active High). !EO is High only if IEl is High and the CPU is not servicing the ISCC /DCDA, /OCDB. Data Carrier Detect (inputs, active Low). (SCC or DMA) interrupt, or the ISCC is not requesting an These pins function as receiver enables if they are pro- _ interrupt (Interrupt Acknowledge cycle only). IEO is con- grammed for Auto Enables; otherwise they are used as __nected to the next lower priority device's IEl input and thus general-purpose input pins. Both pins are Schmitt-trigger _ inhibits interrupts from lower priority devices. buffered to accommodate slow rise time signals. The SCC cell detects pulses on these pins and can interrupt the CPU @ on both logic level transitions. SSS

P# DESCRIPTION (Continued) In External Synchronization mode with the crystal oscilla- tor not selected, these lines also act as inputs. In this e@ AMT. interrupt(output, active Low). This signal is activated + mode, SYNC must be driven Low to receive clock cycles when the SCC or DMA requestsan interrupt. Note that/(NT _atter the last bit in the synchronous character is received. ‘s milled high and is not an open-drain output. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of MBTACK. Interrupt Acknowledge (input, active Low). This SYNC. 's zstrobe which indicates that an interrupt acknowledge cyte is in progress. During this cycle, the SCC andDMA in the Internal Synchronization mode (Monosync and interupt daisy chain is resolved. The device is capable of. Bisync) with the crystal oscillator not selected, these pins retuning an interrupt vector that may be encoded with the —_act as outputs and are active only during the part of the j ype of interrupt pending during this acknowledge cycle _receive clock cycle in which synchronous condition is not ' ‘whe RD or DS become high. INTACK may be pro- _ latched. These outputs are active each time a synchroni- yyanmed to accept a status acknowledge, asingle pulse —_zation pattern is recognized (regardless of character | ackowledge, or a double pulse acknowledge. This is boundaries). In SDLC mode, the pins act as outputs and progammedin the Bus Configuration Register(BCR). The _ are valid on receipt of a flag. dowle pulse acknowledge is compatible with 8x86 family fwcoprocessors. TxDA, TxDB. Transmit Data (outputs, active high). These output signals transmit serial data at standard TTL levels. PCI. Clock (input). This is the master SCC and DMA om used to synchronize internal signals. PCLK isaTTL — /TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or out- eve signal. PCLK is not required to have any phase puts, active Low). These pins can be programmed in @ tetaionship with the master system clock. several different modes of operation. TRxC may supply the receive clock or the transmit clock in the input mode or Reda, RxDB. Receive Data (inputs, active High). These —_ supply the output of the Digital Phase-Locked Loop. the fou signals receive serial data at standard TTL levels. Crystal oscillator, the baud rate generator, or the transmit clock in the output mode. RICA, (RTxCB. Receive/Transmit Clocks(inputs, active tow, These pins can be programmed toseveralmodesof /CE. Chip Enable (input, active Low). This signal selects spention. In each channel, RTxC may supply the receive —_ the ISCC for a Peripheral read or write operation. This i400, the transmit clock, the clock for the baud rate signal is not used when the ISCC is bus master. enzator, or the clock for the Digital Phase-Locked Loop. “hee pins can also be programmed for use with the AD15-ADO0. Data bus (bidirectional, 3-state). These lines fesractive SYNC pins as a Crystal oscillator. The receive carry data and commands to and from the ISCC. Oa may be 1, 16, 32, or 64 times the data rate in 4s8yichronous modes. JAD. Read (bidirectional, active Low). When the ISCC is a Peripheral (i.e. bus slave), this signal indicates a read / RTA, (ATSB. Request To Send (outputs, active Low). operation and when the ISCC is selected, enables the ‘Wher the Request To Send (ATS) bitin Write Register5 is ISCC’sbusdrivers. Asan input, /RD indicates that the CPU t #1. he RTS signal goes Low. When the RTS bitis reset in wants to read from the {SCC read registers. During the he Asynchronous mode and Auto Enable is on, the signal _ Interrupt. ‘Acknowedge cycle, /RD gates the interruptvector a qoec-tigh after the transmitter is empty. In Synchronous onto the bus if the ISCC is the highest priority device oe frodr or in Asynchronous mode with Auto Enable off, the requesting an interrupt. When the ISCCis the bus master, a £7S.mn strictly follows the state of the RTS bit. Both pins this signal is used to read data. As an Output, after the 3 i3n 1e used as general-purpose outputs. ISCC has taken control of the system buses, /RD indicates fa aDMA-controlled read from amemory or I/O port address. SYA, SYNCB. Synchronization (inputs or outputs, ; active Low). These pins can act either as inputs, outputs, — /WR. Write (bidirectional, active Low). When the ISCC is 4 &patof the crystal oscillator circuit. Inthe Asynchronous _ selected, this signal indicates a write operation. As an feceve mode (crystal oscillator option not selected), —_ input, this indicates that the CPU wants to write control or q feseains are inputs similar toCTSand DCD. Inthismode, — command bytes to the ISCC write registers. As an output, tansaions on these lines affect the state of the Synchro- _ after the ISCC has taken control of the system buses /WR rvusHunt status bits in Read Register O buthave noother _ indicates a DMA-controlled write to a memory or I/O port tncton. address, { a eeeeeEeEeeeeeSSSSSSSSSSSSSSSSSSSMSMmmHHsee ae SE SSSR a

—=eoer NN Ke IDS. Data Strobe (bidirectional, active Low). A Lowon this _in the multiplexed bus modes to latch the address on the r ) signal indicates that the AD15-ADO bus is used for data. ADlines. The /AS signalis not used in the non-multiplexed transfer. When the ISCC is notin control of the system bus bus modes and should be tied to Vcc in these cases. and the extemal system is transferring information to or from the ISCC, /DS is a timing input used by the ISCC to. WAIT//RDY. Wail/Ready (bidirectional, active Low). It move data to or from the ADO-AD15 bus. Data is written may be programmed to function either as a Wait signal or into the ISCC by the external system on the Low to High —_ Ready signal during the BCR write. When the BCR is i JOS transition. Data is read from the ISCC by the external _—_ written to Channel A (A1/A//B High during the BCR write), ° system while /DSis Low. There are notiming requirements —_ this signal functions as a WAIT and thus supports the between /DS as an input and ISCC clock; this allows use — READY function of 8X86 microprocessors family. When of the ISCC with a system bus which does not have a _ the BCR writes to Channel B (A1/A//B Low), this signal bussed clock. functions as a READY and supports the DTACK function of the 680X0 microprocessor family. During a DMA operation when the ISCC is in control of the system, DS is an output generated by the SCC and used _This signal is an output when the ISCC in not bus master. by the system to move data to or from the ADO-AD15 bus. _In this case, the Wail/RDY signal indicates when the data When the ISCC has bus control, it writes to the external _ is available during a read cycle; when the device is ready system by placing data on the AD15-ADO bus before the to receive data during a write cycle; and when a valid High-to-Low DS transition and holds the data stable until —_ vector is available during an interrupt acknowledge cycle after the Low-to-High DS transition; while reading from the external system, the Low-to-High transition of DS inputs — When the ISCC is the bus master (the DMA cell has taken data from the AD15-ADO bus into the ISCC. Control of the bus), the /Wait//RDY signal functions as a WAIT or READY input. Slow memories and peripheral RIM. Read/Write (bidirectional). Read polarityisHighand —_ devices can assert WAIT to extend /DS during bus trans- write polarity is Low. When the ISCC is bus master, R/MW _ fers. Similarly, memories and peripherals use READY toin- indicates the data direction of the current bus transaction, _ dicate that its output is valid or that it is ready to latch input andis stable from when ASis High until the bus transaction —_ data. ends. When the ISCC is not in control of the system bus and the external system is transferring information to or /BUSACK. Bus Acknowledge (input, active Low). Signals from the ISCC, R//Wis a status input used by the ISCC to _ the bus has been released to the DMA. If the /BUSACK is determine if data is entering or leaving on the ADO-AD15 _ inactive before the DMA transfer is completed, the current bus during /DS time. insuch acase, Read (High) indicates — DMA transfer is aborted. that the system is requesting data from the ISCC and Write (Low) indicates that the system is presenting data to the + /BUSREQ. Bus Request(output, active Low). This signal is ISCC. The only timing requirements for R/W as an input —_used by the DMA to obtain the bus from the CPU. are defined relative to DS. When the {SCC is in control of the system bus, R//Wis an output generated by the ISCC, AO/SCC//DMA. DMA Channel/SCC Selec/DMA Select with Read indicating that data is being requested from the (bidirectional). When this pin is used as input, a high addressed location or device, and Write indicating that _ selects the SCC cell and alow selects the DMA cell. When data is being presented to the addressed location or this pin is used as output, the signal on this pin is used in device. conjunction with A1/A//B pin output to identify which DMA channel is active. This information can be used by the user TUAS. Upper Address Strobe (Output, active Low). This to determine whether to issue a DMA abort command. signal is used if the addressis more than 16-bit. Theupper — AO/SCC//DMA and A1/A//B output encoding is shown address, A31-A16, can be latched externally by the rising —_ below: edge of this signal. /UASis active first before AS becomes_—_§ —— AAA active. This signal and AS are used by the DMA cell. AVAB AO/SCC//DMA DMA channel JAS. Lower Address Strobe (Bidirectional, active Low). 1 1 RxA When the ISCC is bus master, this signal when an output, 1 (e) TxA is used as a lower address strobe for AD15-ADO. Itis used 0 1 RxB in conjunction with UAS since the address is 32-bits. This (0) 0 TxB @ master. When ISCC is not bus master, this signal is used eee

Note that AO/SCC//DMA pin must be held high toselectthis device. access, the A1/A//B pin is ignored. three blocks: the SCC cell, the DMA cell, and the Bus __ tions outlined here. Figure 3. Block Diagram of ISCC Architecture channels for use in any common asynchronous or syn- data.

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transmitters can supply one, one-and-a-half, or two stop _mits the implementation of protocols such as IBM Bisync. Reception is protected from spikes by a transient spike- _ polynomial may be selected in all Synchronous modes. occur. Vectored interrupts allow fast servicing or error — programmed character length. data at a rate supplied to the receive and transmit clock _ing condition. { 6-bit or 8-bit synchronous character (wonosync), and 12- _ture in the information field of a frame. } bit synchronization pattern (Bisync), or with an external . Figure 5. Detecting © or 7et Synchronous SDLC mode, the ISCC must be programmed to use the

NNN OO TO—sOsO—C!CTSss LTTE. SDLC Loop mode is a programmable option in the ISCC. Parity options available in Asynchronous modes are avail- mode. Comte) byte receive data FIFO. the byte counter in the FIFO enhancment is not reset. Figure 6. An SDLC Loop frame has a byte count which includes the byte countof the Sages to send merely echo the incoming message andare generator may be echoed out via the TRxC pin.

The following formula relates the time constanttothe baud += FM mode and programming the receiver for NRZ data. rate where PCLK or RTxC is the baud rate generator input + Manchester encoding always produces a transition at the g frequency in Hertz. The clock mode is 1, 16, 32, or 64,as center of the bit cell. If the transition is 0 to 1, the bitis a0. selected in Write Register 4, bits D6 and D7. Synchronous __If the transition is 1 to 0, the bit is a 1. operation modes should select 1 and Asynchronous should select 16, 32 or 64 ' ' ° ° ' ° Oete a Cry A One PCLK or RTxC Frequency 2(Baud Rate)(Clock Mode) Lied Digital Phase-Locked Loop. The ISCC contains a Digital saz LIVI SJ ‘VS Phase-Locked Loop (DPLL) to recover clock information from a data stream with NRZI or FM encoding. The DPLL pat nn A OO On is driven by a clock that is nominally 32 (NRZ!) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream. to construct a clock for the data This, ® \\/ \\_S\\/ \\_/- clock is then used as the ISCC receive Clock, the transmit Clock, oF both. Figure 7. Data Encoding Methods For NRZI encoding, the DPLL counts the 32x clock to A create nominal bit times. As the 32x clock is counted, the Saipathassled and Local Loopback. The ‘SCC is capable of OPLL is searching the incoming data stream for edges automatically echoing everything it receives. This feature (either 1 to0, orto 1). Whenever anedgeis detected, the _ ‘S useful mainly in ayncnronous modes, pe works a DPLL makes acount adjustment (during the next counting Synchronous. and ’ ILC modes as well. In , ute ie no cycle), producing a terminal count closer to the center of mode. TxDis| xD. io Echomode can beusedwi the bit cell. or FM encoding with no additional delay because the data stream is not decoded before retransmission. In Auto i i Echo mode, the /CTS input is ignored as a transmitter @ For FM he in mm " rath a eae ning stil counts rom ° ven ron enable (although transitions on this input can still cause DPLLis locked, the clock edges in the data stream should interrupts if programmed to do so) In this mode, the occur between counts 15 and 16 and between counts 31 transmitter is actually bypassed and the programmer is and 0. The DPLL looks for edges only during a time responsible for disabling transmitter interrupts and Centered on the 15 to 16 counting transition. MAITHREQUEST on transmit. The ISCC is also capable of local oopback. In this mode The 32x clock for the DPLL can be programmed to come ; from either the RTxC input or the Sutpat of the baud rate TxD is RxD is just like Auto Echo mode. However, in Local generator. The DPLL output may be programmed to be Loopback mode the internal transmit data is tied to the echoed out of the ISCC via the TRxC pin (if this pin is not internal receive data and RxD is ignored (except to be being used as an input) echoed out via TxD). The /CTS and /DCD inputs are also ° ignored as transmit and receive enables. However, tran- i itions on these inputs can still cause interrupts. Local Data Encoding. The ISCC may be programmed toencode | and decode the serial data in four different ways (Figure 7). Loopback Neca anal yusecha alerted InNRZ encoding, a 1 is represented by a High level anda odes will . or ing of the data str Ois represented by a Low level. In NRZI encoding, a 1 is " i represented by no change in level and a Ois represented pwa core ne 'scc conning 1 eee eby ; . by a change in level. In FM1 (more properly, bi-phase Tode DI ‘ babs s Ae on e's st i van : mark), a transition occurs at the beginning of every bit cell eove a i oar 7 om cl othe DMs A is ele are if A 1is represented by an additional transition at the center Tove Gala to-ane }emiry. ea th Of the bit cell and 2 0 is represented by no additional Iedicated to the transmit and receive FIFO'S, and tl oa transition at the center of the bit cell. in FMO (bi-phase (ore. Oe. he ar used tor device inializalion. Een DMA space), a transition occurs at the beginning of every bit PARA Be nebo a gor Ore on ied providin cell. AQ is represented by an additional transition at the ft bility ie be Nock tea fos lecrem| pr 9 center of the bit cell, and a 1 is represented by no "lexibility in doing block transfers. aa se. the eee adaiton See the I/O Interface Capabilities Section for more details Manchester (bi-phase level) data by using the DPLL inthe 07 the DMA lealures. i :

BUS INTERFACE UNIT (BIU) DESCRIPTION tegister selection and the SCC channel /DMA selection. e Refer to the AO/SCC//DMA and A 1/A//B pin descriptions for The ISCC contains a flexible bus interface that is compat- _ the encoding of these signals. ible with a variety of microprocessors and microcon- fl trollers. The device is designed to work with 8- or 16-bit The Shift Left/ Shift Right modes for the address decoding | bus systems and may be used with address/data multi-_for the internal registers (multiplexed bus) are separately plexed busses or non-multiplexed busses. The multi- programmable for the SCC cell and for the DMA cell. For plexed bus is selected for the ISCC if there is an Address __ the SCC cell the programming and operation is identical to Strobe prior to or during the transaction which writes the _ that in the SCC; programming is accomplished through BCR. Ifno Address Strobe is present prior toor during the Write Register 0 (WRO), bits 1 and 0 (Figure 9-1). . transaction which writes the BCR, a non-multiplexed bus is selected. The programming of the Shift Left / Shift Right modes for . the DMA cell is accomplished in the BCR, bit 0. In this . When the ISCC is initialized for non-multiplexed operation, _case, the shift functionis similar to that for the SCC cell; with register addressing for the ISCC cell is (with the exception _Shift left, the internal register addresses are decoded from 4 . of WRO and RRO), accomplished as follows. Programming bits ADS through AD1 and with Shift Right, the internal {| . the write registers requires two write operations andread- —_register addresses are decoded from bits AD4 through ing the read registers requires both a write and aread —_ ADO. 4 operation. The first write is to WRO which contains four bits i that point to the selected register (note point high com- —_ When the multiplexed bus mode is selected, Write Regis- ‘ mand). The second write is the actual control word forthe ter 0 (WRO) takes on the form of WRO in the Z8030 G q selected register. If the second operation is a read, the —_( Figure 9). i selected register is accessed. When in the non-multi- plexed mode, all of the registers in the SCC cell of the —_Alll data transfers to and from the ISCC are done in bytes ISCC, including the data registers, are accessed in this even though the data can, at special times, occupy the fashion. The pointer register is automatically cleared after _ lower or upper byte of the 16-bit bus. When accessed as the second read or write operation so that WRO(orRRO)is —_ aperipheral device (i.e., when the ISCCis not a bus master addressed again. Note that when the DMA is notusedto —_ performing DMA transfers), all bus transactions are on the L address the data, the data registersmustbe accessed by —_ lower 8 bits of the bus with the following exception: When Pointing to Register 8. This is in contrast to the 28530 _the ISCC registers are read, the byte data is present on which allows directaddressing of the dataregistersthrough —_ both the lower 8 bits of the bus and the upper 8 bits of the the C/D pin. bus. Data is accepted only on the lower 8 bits of the bus q except in certain DMA transfers. When the ISCC is initialized for non-multiplexed operation, register addressing for the DMA cell (with the exceptionof — During DMA transfers, data may be transferred to or from CSAR) is accomplished as follows and is completely the ISCC on the upper8 bits of the bus for odd or even byte independent of the SCC cell register addressing. Pro- transfers. During DMA transfers tomemory from the ISCC, gramming the write registers requires two write operations —_ byte data only is transferred and the data appears on both and reading the read registers requires both awrite anda _ the lower 8 bits and is replicated on the upper 8 bits of the read operation. The first write is to the Command Status __ bus. 4 Address Register (CSAR) which contains five bits that 4 point to the selected register (CSAR bits 4-0). Thesecond —_ During DMA transfers to the ISCC from memory, byte data t write is the actual control word for the selected register. If only is transferred and normally data is accepted only on ar the second operation is a read, the selected register is _ the lower 8 bits of the bus. However, the byte swapping . wd accessed. When in the non-multiplexed mode, all of the feature may be used to elect on which byte of the bus the & registers in the DMA cell of the ISCC may be accessed in —_ datais accepted. The byte swapping feature is enabled i og this fashion. The pointer bits are automatically cleared — by programming the Byte Swap Enable bit to a 1 in the | jh ¢ after the second read or write operation so that CSAR is BCR. The odd/even byte transfer selection is made by i ee addressed again. programming the Byte Swap Select bit in the BCR. if Byte 4 sage Swap Select is a 1, then even address bytes (transfers : bee. When the ISCC is initialized for multiplexed bus operation, — where the DMA addresshas AO equal 0) are transferred on g fe 4 all registers in the SCC cell are directly addressable with —_ the lower 8 bits of the bus and odd address bytes (transfers | ie BS a the register address occupying ADS through AD1,orAD4 —_ where the DMA address has AO equal 1)are transferred on . eee through ADO(Shift Left/ Shift Rightmodes). Twoadditional _the upper 8 bits of the bus. If Byte Swap Selectis a0, then Ce eee D pins, AO/SCC//DMA and A1/A//B control the channel A/B_—_ evenaddress bytes (transfers where the DMA address has Be pier I Be. ia ss ag

AO equal 0) are transferred on the upper 8 bits of the bus _In the ISCC, the IP bit signals a need for interrupt servicing. and odd address bytes(transfers where the DMA address = When an IP bitis 1 and the IEI input is High, the /INT signal 6 has AO equal 1) are transferred on the lower 8 bits of the _is activated, requesting an interrupt. In the SCC, if the IE bus. bit is not set, then the IP for that source can never be set. The IP bits in the DMA are set independent of the IE bit. V/O INTERFACE CAPABILITIES The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower The ISCC offers the choice of Polling, interrupt (vectored _ priority in the ISCC and external to the ISCC are prevented or non-vectored), and DMA Transfer modes to transfer from requesting interrupts. The internal interrupt sources data, status, and control information to and from the CPU. _ are inhibited by the state of the intemal daisy chain, while lower priority devices are inhibited by the IEO output of the Polling. In this mode all interrupts and the DMA's are _ISCC being pulled Low and propagated to subsequent disabled. Three status registers in the SCC are automati- _ peripherals. internaily, the SCC is higher priority than the cally updated whenever any function is performed. For DMA. An IUS bit is set during an Interrupt Acknowledge example, end-of-frame in SDLC mode sets a bit in one of cycle if there are no higher priority devices requesting these status registers. With polling, the CPU must periodi- _ interrupts. Cally read a status register until the register contents indicate the need for some CPU action to be taken. Only —_ Within the SCC portion of the ISCC there are three types of one register in the SCC needs to be read; depending on _ interrupts: Transmit, Receive, and External/Status. Each the contents of the register, the CPU either reads data, _ interrupt type is enabled under program control with writes data, or satisfies an error condition. Two bits inthe — Channel A having higher priority than Channel B, and with register indicate the need for data transfer. Analternative Receive, Transmit, and External/Status interrupts priori- is to poll the Interrupt Pending register to determine the _ tized in that order within each channel. When the Transmit source of an interrupt. The status for both SCC channels _ interrupt is enabled, the CPU is interrupted when the resides in one register. transmit buffer becomes empty. This implies that the transmitter had a data character written into it to make it Interrupts. When the ISCC responds to an Interrupt Ac- empty. When enabled, the receiver interrupts the CPU in knowledge signal (INTACK) from the CPU, an interrupt —_ one of three ways: vector is placed on the data bus. Both the SCC and the DMA contain vector registers. Depending on the source of 1. Interrupt on First Receive Character or Special interrupt, one of these vectors is returned. either unmodi- Receive Condition fied or modified by the interrupt status to indicate the exact cause of the interrupt. 2. Interrupt on All Receive Characters or Special Receive Condition Each of the six sources in interrupts in the SCC (Transmit, Receive, and External/Status interrupts in both channels) 3. Interrupt on Special Condition Only and each DMA channel has three bits associated with the interrupt source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). If the IE bitis set Interrupt on First Character or Special Condition, and for any given source of interrupt, then that source can _ Interrupt on Special Condition Only, are typically used request interrupts. The only exception to this rule is when — when doing block transfers with the DMA. A Special the associate Master Interrupt Enable (MIE) bit is reset, Receive Condition is one of the following: receiver overrun, then no interrupts are requested. Both the SCC and the _ framing error in Asynchronous mode, end-of-frame in OMA have an associated MIE bit. The lEbitsinthe SCC are | SDLC mode and, optionally, a parity error. The Special write only, but the IE bits in the DMA are read write. Receive Condition interrupt is different from an Ordinary Receive Character Available interrupt only by the status The ISCC provides for nesting of interrupt sources with an _ placed in the vector during the Interrupt Acknowledge interrupt daisy chain using the IEI, EO, and INTACK pins. cycle. In Interrupt on First Receive Character, an interrupt As amicroprocessor peripheral, the ISCC mayrequestan —_ occurs from Special Receive Conditions any time after the interrupt only when no higher priority device is requesting _ First Receive Character interrupt. ‘one, e.g., when IE! is High. If the device in question requests an interrupt, it enabies the /INT signal. The CPU then responds with /INTACK, and the interrupting device places the vector on the data bus. @ SSeS

detected or terminated. This feature facilitates the proper be serviced before the bus is released. Each OMA . the next message, and the accurate timing of the Abort . Each DMA in the ISCC has two sources of interrupt, which ISCC to virtually any type of bus. The SCC directly -. decremented with a 16-bit transfer length. Whenever a _ bus mastership upon receipt of a /BUSACK signal. Figure 8. Bus Configuration Register (BCR) Bee:

a SCC Cell. The SCC core contains 13 write registers (14 Table 1. SCC Write Registers counting the transmit buffer) and ten read registers 10 — 6 counting the receive buffer) in each channel. Two of the Bit Description write registers are shared (WR2 and WR9) and are aCe cessed by both channels. WR2 contains the interrupt WRO_ Register Pointers, various initialization commands vector for both channels, while WR9 contains the interrupt. WR1 — Transmit and Receive interrupt enables, control bits. Table 1 is a list of the SCC write registers and WAIT/DMA commands Table 2 is a list of the SCC read registers. Figures 9 and WR2_ Interrupt Vector 10 show the write and read register formats. Read Regis- | WR3_ Receive parameters and control modes ters 6 and 7 are only accessible when the SDLC FIFO is enabled. When the SDLC FIFO is not enabled, Read WR4 Transmit and Receive modes and parameters Registers 6 and 7 are images of Read Registers 2 and 3, WR5__ Transmit parameters and control modes respectively. WR6_— Sync Character or SDLC address WR7 Sync Character or SDLC flag DMA Gell. The DMA cell contains 17 registers (counting. ©, $$ A the BCR). All of the registers are write/read except the = WR8 Transmit buffer BCR, CCAR and ICSR. The ISCC also has two status © WR9 Master Interrupt control and reset commands registers, the DMA status register (DSR) and the Interrupt WR10. Miscellaneous transmit and receive control bits Status Register (ISR), which are addressed by reading the = WR11 Clock mode controls for receive and transmit CCAR and ICSR. The DMA also reserves two addresses J for future use and should not be addressed or should be | WR12_ Lower byte of baud rate generator written with all zeros to prevent unexpected operationand = WR13_ Upper byte of baud rate generator maintain compatibility with future products. Each DMA = WR14_ Miscellaneous control bits channel has a 32-bit wide address register providing an WR15_ External status interrupt enable control addressing range of 4 gigabytes. Each channel also has a 16-bit count register for up to 64K byte data packet sizes. enn ? : ___ ed

1 1 0 Register é 01. Re iIntOn Fett Character or Special Condon .

11 Select Shit Right Mode

11 Reset Tx UnderrunvEOM Latch

Figure 9. Write Register Bit Functions ik

Figure 9. Write Register Bit Functions (Continued)

ee OO, io we @ acca or ]os[os]onTo= [os] i | ‘SyncT Sync& SyncS Syne Sync3. Sync Synet SyncO Monosyne, 8 Bks gry gist grat Set yet Set Set So eee te ‘Synci5 Synet4 Synct3 Synct2 Synet1 Syncl0 Syncd Sync8 Bisyne, 16 Bits | | Sigh Sess Sis Sea Sar See Ss Set geo wang wt oro fos] |=] >To or[ososfosJooJo=]osToo | I | vs © 0 /TRKC Out = Xtal Output NV © 1 ARC Out = Tranemit Clock a | a ¢ | mee teint @ 1 2 mec mens \\ ME ATRxC On ‘Status Highv/Status Low : 2 Tammie « CP 0 «1 Transmit Clock = /TRxC Pin ¢ | fee mee 0 © NoReset 1 1 Transmit Clock = DPLL Output ( ae \\ 13 Foca et eo tenet Amore 1 0 Recelve Clock = BR Generator Output 1} See sr aan or os]os] oes] a=]: [oo] inti — or [os ooo] > [>] La Mt | Li ww (AbortiiFlag On Underrun: Te1 Mark//Flag kite 102 Go Active On Pot Tos Lower Byte of © © NAZ cioy Time Constant oe amen res

11 FMO(Tranekion = 0) Tes |

\\ | | Figure 9. Write Register Bit Functions (Continued) | | \\®@ | yr

Table 2. SCC Read Registers

‘Tx Butler Empty (Channel B Rx IP . Figure 10. Read Register Bit Functions See &

Figure 10. Read Register Bit Functions (Continued)

00000 CCAR Channel Command/Address Register (Write) '

00000 DSR DMA Status Register (Read)

00001 ICR Interrupt Controt Register

00010 IVR Interrupt Vector Register tt

00011 ICSR Interrupt Command Register (Write) H .

00011 ISR Interrupt Status Register (Read) '

00100 DER DMA Enablie/Disable Register

00101 DCR DMA Control Register

00110 Reserved Address

Figure 12. DMA Status Register Figure 11. Channel Command/Address Register :

Figure 13. Interrupt Control Register Figure 16. Interrupt Status Register Figure 17. DMA Enable Register Figure 14. Interrupt Vector Register

01 RRB BR ATKA

Figure 15. Interrupt Command/Register |

7 L_ Pe A AES LL PRA Add24

Figure 23. Receive DMA Address Register Channel A

Figure 24. Transmit DMA Address Register Channel A

2 | ( i) ‘Address: 11000 (Bits 0-7) ‘Adkéroes: 11010 (Bhs 16-23) | [or ]oe]9s]>«[os oe [0% Too] [or] [os] 04 Joe ee [00] | L_ RB Addo LL Rx B Addt6 ' Rx B Addet Rx B Adir17 J Px B Adda RKB Add18 y Rr Badia Px B Adiet9 i Px B Added Rx B Adde20 yy ' RRB Adds Rx B Add2t Rx B Addeé Rx B Addr22 \\ Rx B Addr? Rx B Addr23, : | (A) (c) : ‘Address: 11001 (Bits 8-15) ‘Addross: 11011 (Bks 24-31) i | [>7 Jos] [o« [os [oe Jor Joo} [o7 [>= os] «== 02 [os [oo] ( ) L_ FxB adds Le Re B Adde26 Rx BAGO Rx B Add25 Pe B Add10 Rx B Add28 Rx B Add Rx B AdS27 Px B Adde2 Ax B Add28 ( meaara fbn Re B Ad Fx B Add30 xB Add5 Re B Addr3t (B) (D) A Figure 25. Receive DMA Address Register Channel B F i a i 27 ‘ es eee “

Figure 26. Transmit DMA Address Register Channel B

' f ABSOLUTE MAXIMUM RATINGS ‘ Voltages on all pins, with respect Stresses greater than those listed under Absolute Maxi- Operating Ambient vice. This is a stress rating only; operation of the device at Temperature 0... S€@ Ordering Information any condition above those indicated in the operational Voltages on all inputs, with respect absolute maximum rating conditions for extended periods STANDARD TEST CONDITIONS wv The DC Characteristics and Capacitance section below 1 apply for the following standard test conditions, unless 20Ka otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Standard Conditions are as follows: bi sien +4.75 Vs Vecs5.25V } GND = 0V on alaad ( ) T,as specified in Ordering Information | | ( a Figure 27. Standard Test Load CAPACITANCE ! Symbol — Parameter Min Max Unit Condition Cy Input Capacitance 10 pF Unmeasured Pins Cour Output Capacitance 15 pF Returned to Ground Cy Bidirectional Capacitance 20 pF Unmeasured pins retumed to ground Miscellaneous: Transistor Count 52,047 Z16C35 DC CHARACTERISTICS Symbol Parameter Min Typ Max Unit Condition Vee Input High Voltage 2.2 Vog +0.3 v Va Input Low Voltage 0.3 08 Vv Ven Output High Voltage 2.4 v Igy = 1.6 mA Voge Oulput High Voltage V,, -0.8 v log, = -250 pA Vo Output Low Voltage 0.4 Vv ly = +2.0 mA in Input Leakage + 10.00 pA 04<V,,<+24V leg Output Leakage + 10.00 pA 0.4 < Vogy < +2.4V | 6) loos Vee Supply Current 7 50 MA Veg = SV. Vy = 4.8 V, Vy = 0.2V Vee = 5 V # 5% unless otherwise specified, over specified temperature range. i f , ° nee: L ae

Oe Eo ee: if I SSS i AC CHARACTERISTICS 0 if SSS | 10MHz * ‘ No Symbol Parameter Min Max Notes : mee amt Mex Nts in 1 Teyc Bus Cycle Time 4TcPC i 2 TwASI JAS Low Width 40 , i 3. TwASh JAS High Width 90 \\ | 4 TwDSI /DS Low Width 70 ' 5 TwOSh 1S High Width 60 d

6 TdAS(DS) JAST to /DSL Delay Time 5

7 TdDS(AS) IDST to /ASL Delay Time 5

i 8 TdDS(DRa) /DS1 to Data Active Delay 0

9 TdDS(DRv) /DS to Data Valid Delay 85 :

10 TdDS(DRn) JDST to Data Not Valid Delay te)

i i W TdDS(DRz) /DST to Data Float Delay 20 ‘ 12 TsCS(AS) ICS to /AST Setup Time 15 13. ThCS(AS) ICS to /AST Hold Time 0

14 TsADD(AS) Direct Address to /AST Setup Time 15 a)

15 ThADD(AS) Direct Address to /AST Hold Time 5 Q) ©

16 TsSIA(AS) Status /INTACK to /AST Setup Time 15

17 ThSIA(AS) Status /INTACK to /AST Hold Time 5

18 TsAD(AS) Adress to /AST Setup Time 15

19 ThAD(AS) Address to /AST Hold Time 5

20 TsRW(DS) RIM to (DSL Setup Time 0 ©

21 ThRW(DS) R/M to DSL Hold Time 25

22 TADSK(RDY) /DS1 to /READYJ Delay 50

1. TdDSr(RDY) /DST to /READYT Delay 40

24 TsDW(DS) Write Data to /DSLSetup Time oO

25 ThDW(DS) Write Data to /DSLHold Time 25

26 TARDY(DRv) /READY4 to Data Valid Delay 40

28 TwRDI /RD Low Width 70

29° TwRDh IRD High Width 60

30 TdAS(RD) /AST to /RDL Delay Time 5

31 TdRD(AS) IRDTto /ASL Delay Time 5

32 TdRD(DRa) /RDL to Data Active Delay 0

33 TdRO(DRv) /RD to Data Valid Delay 85 ?

34 TdRD(DRn) /ROT to Data Not Valid Delay 0 \\

35 TdRO(DRz) /RDTto Data Float Delay 20

36 TdRD‘(RDY) IRDLto (READY! Delay 50

37 TARDA(RDY) IROT to /(READYT Delay 40

. 38 Twwrl MAR Low Width 70 ‘ 39 TWWRh MMR High Width 60

40 TdAS(WR) JAST to WR4 Delay Time 5

4 TdWR(AS) MpTto ASI Delay Time 5

• Units in nanoseconds. @ aE

r) AC CHARACTERISTICS (Continued) | $$ SSSSSSSSSSSSSSSSSSsSSSSSSSSSS : 10MHz * | | No Symbol Parameter Min Max Notes ql $$ eee i

42 TsDW(WR) Write Data to WR Setup Time ty) |

{ 43 ThDW(WR) Write Data to /WRL Hold Time 25 i

44 TAWRI(RDY) Jat to READY Delay 50

45 TdWRr(RDY) MRT to /READYLDelay 40 i

d 46 TsCS(DS) ICS to /DSt Setup Time 0 (2) ' ee

47 ThCS(DS) ICS to (DSL Hold Time 25 [2]

48 TsADD(DS) Direct Address to /DSL Setup Time 0 (1.2) \\ 49 ThADD(DS) Direct Address to /DS1. Hold Time 25 (1.2) :

50 TsSIA(DS) Status /INTACK to /DSL Setup Time te) (2] {

51‘ THSIA(DS) Status /INTACK to /DSL Hold Time 25 (2) | ee

52 TsCS(RD) ICS to /RDJ Setup Time () (2)

53 ThCS(RD) ICS to [ROL Hold Time 25 {2] |

54 TsADD(RD) Direct Address to /RDLSetup Time 0 [1.2] 55 ThADO(RD) Direct Address to /RDL Hold Time 25 1.2} ') 56 TsSIA(RD) Status /INTACK to /RDJ Setup Time 0 (2) | SET T<777—< ITI eI i

57 ThSIA(RD) Status /INTACK to /RDJ Hold Time 25 (2) |

58 TsCS(WR) ICS to WRI Setup Time 0 {2]

59 ThCS(WR) ICS to WRI Hold Time 25 [2]

60 TsADD(WR) Direct Address to (WRI Setup Time 0 {1,2}

. ) 61 ThADD(WR) Direct Address to (WRI Hold Time 25 (1.2) ‘ ee 62 —-TsSIA(WR) Status /INTACK to RL Setup Time 0 (2) |

63 ThSIA(WR) Status /INTACK to WRI Hold Time 25 {2}

78 — TADSIRDY) /DS1 (Intack) to READY! Delay 300 [4]

81 TsIEI(DSI) IEI to OSL (Intack) Setup Time 60

82 ThIEK(DSI) IEI to /DST (Intack) Hold Time 0

a

83 TdIEKIEO) IEI to IEO Delay 60

84 TdAS(IEO) JAST or Status Intack to [EO Delay 60 |

85 TdDSK(INT) /DS4 (Intack) to ANT Inactive Delay 200 |

86 —_ TdDSI(W1) JDS+ (Intack) to WAITS Delay 40 H

87 TADS) /DSI (Intack) to WAITT Delay 300 (4) |

, 88 TdW(ORy) MAITT to Data Valid Delay 40 A \\ 89 TdROK(RDY) IRD (Intack) to READY Delay 300 [4] i

91 TsIEK(RDI) IEI to (RDI (Intack) Setup Time 60

{ 92 ThIEK(RD!) EI to (ROT (Intack) Hold Time 0 . 93 TAROI(INT) /RD4 (Intack) to ANT Inactive Delay 200 ee 94 TARDI(W!) IROL (Intack) to WAITL Delay 40 95 — TARDI(Wr) IRD& (Intack) to WAITT Detay 300 (4)

96 TwPIAI Pulsed /INTACK Low Width 70

97 TWPIAh Pulsed /INTACK High Width 60

98 — TAAS(PIA) JAST to Pulsed /INTACK/ Delay Time 5 : 9 "Unitsinnanoseconds SS SSSSFSSSSSSS | 3t i

EE Eee: AC CHARACTERISTICS (Continued) 0 10MHz * | No Symbol Parameter Min Max Notes > Notes

99 TAPIA(AS) Pulsed /INTACKT to /ASL Delay Time 5

i 100 TdPIA(DRa) Pulsed /INTACK to Data Active Delay 0 | | 101 TdPEA(DRn) Pulsed /INTACKT to Data Not Valid Delay 0 i 102 TdPIA(DRz) Pulsed /INTACKT to Data Float Delay 20 if 103 TSIEI(PIA) IEI to Pulsed /INTACKL Setup Time 60 ! 104 THIEK(PIA) 1El to Pulsed /INTACKT Hold Time 0

105 TAPIA(IEO) Pulsed /INTACKL to IEO Delay 60

i 106 TPIA(INT) Pulsed /INTACK4 to /INT Inactive Delay 200 i 107 TdPIAKRDY) Pulsed /INTACK to /READYJ Delay 300 (4]

108 TdPIAr(RDY) Pulsed /INTACKT to /READYT Delay 40

: 109 TAPIA(Wr) Pulsed /INTACK4 to WAIT! Delay 40 i 110 TAPIA(Wr) Pulsed /INTACK4 to /WAITT Delay 300 (4) : qt TdSIA(INT) Status /INTACK4 to /INT inactive Delay 200 (2) i 113 TwRESI /RESET Low Width 170 ! 114 TwRESh IRESET High Width 60 ®)

115 TdRES(STB) IRESETT to /Strobel 60 (3]

116 TdPC(BUSa) PCLKT to Bus Active Delay 40 (5]

117 TdPC(BRQ) PCLKT to /BUSREQ Delay 40

118 TsBAK(PC) IBUSACK to PCLKT Setup Time 10

119 TRBAK(PC) IBUSACK to PCLKTHold Time 30 ©

120 TwPCI PCLK Low Width 35

121 TwPCh PCLK High Width 35

122 TePC PCLK Cycle Time 100

1. TIPC PCLK Fall Time 10

124 TPC PCLK Rise Time 10

125 TdPCr(UAS) PCLKT to /UAS Delay 30 {5}

126 TwUASI JUAS Low Width 30 (5.6)

127 TdPCKUAS) PCLK4 to /UAS Delay 30 {5}

128 TdPCr(AS) PCLKTto /AS Delay Ke) [5]

129 TWAS! /AS Low Width 30 [5.6] eee 130 TdPCI(AS) PCLK! to /AS Delay 30 (5) ; 131 TAAS(DSr) /AST to (DSL (Read) Delay 30 [5.7]

132 TdDS(PCr) PCLKT to /DS Delay 30 {5}

133 TwOSir /DS Low Width (Read) 136 (5,8)

134 TdPCK(DS) PCLK! to /DS Delay 30 (5) ' 135. TsDR(DS) Read Data to /DST Setup Time 30 {5} . 136 ThDR(DS) Read Data to /DST Hold Time 0 [5] ‘ 137 TdPC(RW) PCLKT to RW Delay 30 [5] i 138 TdAS(RD) JAST to /RDL Detay 30 [5.7]

139 TdPCr(RD) PCLKT to /RD Delay 30 [5]

• Units in nanoseconds. eS 32 |

—SSeeSSeSeSSeSSSSSSSSSSSSSSSSOseseFesFSSSSSSSSSSSS e AC CHARACTERISTICS (Continued) | SSS | 10MHz * |) ! No Symbol Parameter Min Max Notes ee 140 TwRDI JRD Low Width 135 (5.8) |

141 TdPCI(RD) PCLK4 to (RD Delay 30 5] 1)

142 TsDR(RD) Read Data to /RDT Setup Time 30 [5]

1. ThDR(RD) Read Data to /ROT Hold Time (o) {5}

144 TdPC(ADD) PCLKT to Direct Address Delay 30 1,5]

145 TdPC(AD) PCLKT to Address Delay 40 (5) |

146 TRAD(PC) Address to PCLKT Hold Time () (5) j

147 TdPC(ADz) PCLKT to Address Float Delay 50 (5)

148 — TdPC(ADa) PCLKT to Address Active Delay 40 {5}

149 TsAD(UAS) Address to /UAST Setup Time 20 5]

150 ThAD(UAS) Address to /UAST Hold Time 20 (5]

151 TsAD(AS) Address to /AST Setup Time 20 {5]

152 TRAD(AS) Address to /ASTHold Time 20 [5]

153 TsW(PC) MAIT to PCLK¢ Setup Time 10 {5]

) 154 THW(PC) MATT to PCLKL Hold Time 30 (5)

155 TsRDY(PC) IREADY to PCLK¢ Setup Time 10 (5] |

156 THRDY(PC) IREADY to PCLKL Hold Time Re) (5]

157 ThOW(PC) Write Data to PCLKT Hold Time 0 (5)

158 TdAS(DSw) JAST to /DSL (Write) Delay 85 (5.9) r) 159 TsDW(DS) Write Data to /DSL Setup Time 30 (5.6] . eee

160 TwOSIw /DS Low Width (Write) 90 {5,10]

161 ThDW(DS) Write Data to /DST Hold Time 30 (5. 7] 162 TdAS(WR) /AST to WRI Delay 85 [5.9] 163 TsDW(WR) Write Data to (WRI Setup Time 30 [5.6] 164 TWWRI WR Low Width 90 (5.10} eee | 165 ThOW(WR) Write Data to WRT Hold Time 30 (5.7) | 166 TdPC(WR) PCLK4 to WR Delay 30 [5] !

167 TdPC(BUSz) PCLKT to Bus Float Delay 50 (5) |

[1] Direct address is A1/A//B or AQSCC//DMA. i [2] The parameter applies onty when /AS is not present. i [3] /Strobe is any of /DS, /RD, WR or Pulsed /INTACK. I [4] Clock-cycle dependent, 2TcPC + TwPCI + TIPC + 55. [5] Parameter applies only while ISCC is bus master. [6] Clock-cycle dependent, TwPCh + TIPC - 15. [7] Clock-cycle dependent, TwPC1 + TrPC - 15. [8] Clock-cycle dependent, TePC + TwPCh + TrPC - 10. [9] Clock-cycle dependent, TcPC - 15. [10] Clock-cycle dependent, TcPC - 10. * Units in nanoseconds. if li 33 !

Figure 28. Multiplexed /DS Read Cycle

oe ~ a @ ol @ | | ofttle I]. INTACK | | | | (Status) ALL IAS (i | | | H i © ’ , as ila | IWAITI/RDY (Wak) . Game) a (Ready) /| : @) @ | Figure 29. Multiplexed /DS Write Cycle i

Figure 30. Multiplexed /RD Read Cycle

Figure 31. Multiplexed /WR Write Cycle

Figure 32. Non-multiplexed /DS Read Cycle |

| ® ap © if ANTACK 7 : { eo | © © i RW @ lm ® )o _— | Het 7 r ) IWATTIIRDY 1} (Wak) | WATTURDY | (Ready) /| | @) @) | Figure 33. Non-multiplexed /DS Write Cycle | | | | q fF 39 |

Figure 34. Non-multiplexed /RD Read Cycle

) ( is ‘ b | a x | | cai an = - Fe, | Figure 35. Non-multiplexed /WR Write Cycle | | A » @ |

Figure 36. Multiplexed /DS Status INTACK Cycle |

Figure 37. Multiplexed /RD Status INTACK Cycle

Figure 38. Multiplexed Pulsed INTACK Cycle

Figure 39. Non-multiplexed /DS INTACK Cycle

a ANTACK @) (Status) . F ° — — | ® cr ADO-AD15 { “| B Pe (Wait) |_| 0 l opt | Ico J ps i , ANT /| j i Lo j t Figure 40. Non-multiplexed /RD Status INTACK Cycle | |

Figure 41. Non-multiplexed Pulsed INTACK Cycle |

A, ® a4 ~ 4 etl lem Si fe LG ly NX | Late . yf pbed , Oo | al Hi + wi R Ie] pe at : g a A aj a a g Es CF) BO t 48

—_ OL SSS eee \\ © ' — © | Ur ele | , 2 @ 4 $ | i nner z { z \\é 3 e ; i 3 | 3 | g O Z z ® g 4 z | J at “z Ps ss > ; gs Fy ey as ey g 5 Ee g ee g za 8 ge g z z eee 49 |

Figure 44. Reset

y .) TR Tso Ts1 To ui “ nm . m ps \\ . im a) P| : ™ a , AAO q j AD15-0 rs \\ /BUSREQ | /BUSACK @-] Le ) @ Figure 45. Z16C35 Start-up st |

Figure 46. Z16C35 Memory Read

a r ) 1 T2 mT 1% | re ! “te C1 i ps i @ ®@ i [PS IIrHhs yl ! eT) Ae UT Tike © aad LT DRT iP Salesiietl van @ i @ f ‘MWaki/ROY “ 3 Pe tts | eblhle r+) Figure 47. Z16C35 Memory Write -__—eoO

Figure 48. Wait and Ready Timing

Figure 49. BUS Release

AC CHARACTERISTICS a) a SSSSeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSeeeeeeSSee 10MHz * No Symbol Parameter Min Max Notes IS

1 TsRXD(RXCr) RxD to /RxCT Setup Time (x1 mode) (0) (]

2 ThRXD(RXCr) RxD to /RxCT Hold Time (x1 mode) 150 u] ! 3 TsRXD(RXCf) RxD to /AxCL Setup Time (x1 mode) ( [1.5]

4 ThRXD(RXCI) RxD to /RxCL Hold Time (xt mode) 150 (1,5}

5 TsSY(RXC) ISYNC to /RxCT Setup Time -200 ty

6 ThSY(RXC) ISYNC to RxCT Hold Time 5TcPc (1) |

7 TsTXC(PC) [TxC to PCLK Setup Time 0 [2.4]

8 TATXCK(TXD) [TxCL to TxD Delay (x1 mode) 150 [2]

9 TdTxCr(TXD) ITxCT to TxD Delay (x1 mode) 150 [2.5]

10 TaTXD(TRX) TxD to /TRXC Delay (Send Clock Echo) 200

11 TwRTXh /RTxC High Width 150 (6)

12 TwRTXI IRTxC Low Width 150 (6)

13 TcRTX IRTxC Cycle Time (RxD, TxD) 400 {6,7}

14 TCRTXX Crystal Oscillator Period 100 1000 {3}

15 TwIRXh /TRxC High Width 150 (6) € )

16 TwIRXI /TRxC Low Width 150 (6) |

17 TeTRX /TRXC Cycle Time (RxD, TxD) 400 (6.7] ! 18 = TwEXT IDCD or /CTS Pulse Width 200 |

19 TwSY ISYNC Pulse Width 200

• Units in Is. Notes: [1] /RKC is (RTXC or /TRxC, whichever is supplying the receive clock. {2] /TxC is /TRxC or (ATXC, whichever is supplying the transmit clock. [3] Both /ATxC and /SYNC have 30 pf capacitors to ground connected to them. [4] Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between /RxC and PCLK or/TxC and PCLK is required. (5) Parameter applies only to FM encoding/decoding. [6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator requirements are identical to case PCLK requirements. [7] The maximum receive or transmit data rate is one-fourth PCLK. eee i

Figure 50. Z16C35 General Timing

ee ee, —. SS AC CHARACTERISTICS System Timing oo SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSSSsSSsessssssseese 10MHz No Symbol Parameter Min Max Notes ¢ SSeS

1 TdRXC(SY) IRxCT to SYNC 4 7 1 |

2 TARXC(INT) RxCT to /INT Valid Delay 10 16 1 }

See '

3 TdTXC(INT) /TxCl to /INT Valid Delay 6 10 }

4 TdSY(INT) SYNC Transition to /INT Valid Delay 2 6

5 TdEXT(INT) DCD or /CTS Transition to /INT Valid Delay 2 6

+ Units equal to TePe. Notes: 1. (RxC is IRTXC or /TRXC, whichever is supplying the receive clock. 2. [IxC is /TRKC or /RTxC, whichever is supplying the transmit clock. E | Cc i 4 58

Figure 51. Z16C35 System Timing i

PACKAGE INFORMATION

G —,050 2.001 O45 X 45° MAX | T'S do h 4 des b ii aed dar B i ds NR BB - —+9904.010 (

045 K a5¢ -

. ‘5° NOMINAL pie fo , peed TTT) ‘ Ls eee alle dee 2.002 Fi) Le 4 i} i i 68-Lead Plastic Chip Carrier

i ——

ORDERING INFORMATION

¢ 4 ..' Z16C35 ISCC 10 MHz 68-Pin PLCC 216C3510VSC CODES PACKAGE ENVIRONMENTAL Preferred Preferred V = Plastic Chip Carrier C = Plastic Standard E = Hermetic Standard Longer Lead Time F = Plastic Quad Flat Pack Longer Lead Time G = Ceramic PGA (Pin Grid Array) D = Plastic Stressed L = Ceramic LCC Q = Ceramic Quad-in-Line TEMPERATURE Preferred S$ =0°C to +70°C € x Longer Lead Time . E = -40°C to +85°C Example: Z16C3510VSC 16C35, 10MHz, Plastic PLCC, 0°C to 70°C, Plastic Standard Flow Z 16035 10 V S C (L——. Environmental Flow Temperature Package Speed Product Number Zilog Prefix

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q SING APOLE oo... ese ecccsesssseseeeesssescssesenseeeseeseseese 65-2357 155, z NEW HAMPSHIRE § NASHUA oo... cesoseesseseescssneesesnssteeeessenessnsesessse 603-888-8590 TAIWAN - ; NEW JERSEY Fs NORTH CAROLINA OHIO “ SEVEN Hills ...cssssssssssessssssesseersneeceeeseeeesseeessee 216-447-1480 PENNSYLVANIA [ ADIGE... eeeces see escesecccestereesesseecceeseseneeereeeeeeee 215-653-0230 : TEXAS i DAN AS 02... eccseeeeeseeeensseesccessetesensueeressunessssess 214-987-9987 i WASHINGTON % Seattle oo. eeceeesesesscosneesensnneecceeneees 206-523-3591 H i 4 ui d é i © 1990 by Zilog, Inc. All rights reserved. No part of this publica- Zilog will not be responsible for any damage to the user that may | tion may be reproduced, stored in a retrieval system, or transmit- result from accidents or any other reasons during operations of ted, in any form or by any means, electronic, mechanical, photo- __ the products described herein. copying, recording, or otherwise, without the prior written permis- q sion of Zilog. All specifications (parameters) are subject to change without notice. Zilog will not be responsible for any such changes. Zilog + The information contained herein is subject to change without _will not be responsible for notifying any user of changes. The ap- f notice. Zilog will not be responsible for any such changes. Zilog _ plicable Zilog test documentation will specity which parameters H will not be responsible for notifying any user of changes. Zilog _are tested. ¢ 3 assumes no responsibility for the use of any circuitry or other technology embodied in a Zilog product. No patent licenses, _Zilog, Inc. 210 Hacienda Ave., Campbell, CA 95008-6609 Telephone. industrial property rights, or other rights are implied. (408) 370-8000 TWX 910-338-7621 SSeS H 00-2515-03 i