X40430 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Renesas
  • PDF pages: 26

Technical content

FN8251 Rev 1.00 Page 1 of 26 May 24, 2006 FN8251 Rev 1.00 May 24, 2006 X40430, X40431, X40434, X40435 4Kbit EEPROM Triple Voltage Monitor with Integrated CPU Supervisor DATASHEET

FEATURES

  • Monitoring voltages: 5V to 9V
  • Independent core voltage monitor
  • Triple voltage detection and reset assertion —Standard reset threshold settings. See selec- tion table on page 2. —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to V CC = 1V —Monitor three separate voltages
  • Fault detection register
  • Selectable power-on reset timeout
  • Selectable watchdog timer interval (25ms, 200ms, 1.4s or off)
  • Debounced manual reset input
  • Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off
  • Memory security
  • 4Kbits of EEPROM —16 byte page write mode —5ms write cycle time (typical)
  • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block lock protect 0, or 1/2, of EEPROM
  • 400kHz 2-wire interface
  • 2.7V to 5.5V power supply operation
  • Available packages —14 Ld SOIC, TSSOP
  • Pb-free plus anneal available (RoHS compliant)

APPLICATIONS

  • Communication equipment —Routers, hubs, switches —Disk arrays, network storage
  • Industrial systems —Process control —Intelligent instrumentation
  • Computer systems —Computers —Network servers

DESCRIPTION

The X40430, X40431, X40434, X40435 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, manual reset, and Block Lock ™ protect serial EEPROM in one package. This combin ation lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to V CC activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscilla- tor to stabilize before the processor can execute code. Low V CC detection circuitry protects the user’s system from low voltage condit ions, resetting the system when V CC falls below the minimum V TRIP1 point. RESET/RESET is active until V CC returns to proper operating level and stabilizes. A second and third volt- age monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available. However, Intersil’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet specific system level requirements or to fine-tune the threshold for applica- tions requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with In tersil’s Block Lock protection. The array is internally organized as x 8. The device features a 2-wire interface and software protocol allowing operation on an I 2C bus. The device utilizes Intersil’s proprietary Direct Write ™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 2 of 26 May 24, 2006 BLOCK DIAGRAM *Voltage monitor requires Vcc to operate. Others are independent of Vcc. V3FAIL V2FAIL WDO MR LOWLINE RESET RESET X40430/34 X40431/35 V3 MonitorLogic V2 MonitorLogic Fault Detection Register Status Register EEPROM Array Data Register Command Decode Test & Control Logic Power-on, Manual Reset Low Voltage Reset GenerationVCC Monitor Logic V3MON V2MON SDA WP SCL VCC (V1MON) Watchdog and Reset Logic VTRIP3 VTRIP2 VTRIP1 *X40430, X40431= VCC or V2MON* V2MON X40434, X40435 =VCC Device Expected System Voltages Vtrip1(V) V trip2(V) Vtrip3(V) POR (system) X40430, X40431 5V; 3V or 3.3V; 1.8V 5V; 3V; 1.8V 3.3V; 2.5V; 1.8V 2.0–4.75* 4.55–4.65* 4.35–4.45* 2.95–3.05* 1.70–4.75 2.85–2.95 2.55–2.65 2.15–2.25 1.70–4.75 1.65–1.75 1.65–1.75 1.65–1.75 RESET = X40430 RESET = X40431 X40434, X40435 5V; 3.3V; 1.5V 5V; 3V or 3.3V; 1.5V 5V; 3 or 3.3V; 1.2V 2.0–4.75* 4.55–4.65* 4.55–4.65* 4.55–4.65* 0.90–3.50* 1.25–1.35* 1.25–1.35* 0.95–1.05* 1.70–4.75 3.05–3.15 2.85–2.95 2.85–2.95 RESET = X40434 RESET = X40435

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 3 of 26 May 24, 2006

Ordering Information

PART NUMBER* PART MARKING MONITORED VCC RANGE VTRIP1 RANGE VTRIP2 RANGE VTRIP3 RANGE TEMP. RANGE (°C) PACKAGE PKG. DWG. # PART NUMBER WITH RESET X40430S14I-C X40430S IC -40 to +85 14 Ld SOIC (150 mil) M14.15 X40430V14-C X4043 0VC 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40430V14I-C X4043 0VIC -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40430S14Z-B (Note) X40430S ZB 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40430S14I-B X40430S IB -40 to +85 14 Ld SOIC (150 mil) M14.15 X40430S14IZ-B (Note) X40430S ZIB -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40430V14-B X4043 0VB 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40430V14Z-B (Note) X40430V ZB 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40430V14I-B X4043 0VIB -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40430V14IZ-B (Note) X40430V ZIB -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40434S14I-C X40434S IC -40 to +85 14 Ld SOIC (150 mil) M14.15 X40434V14-C X40434V C 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40434V14I-C X40434V IC -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40434S14-B X40434S B 1.3 to 5.5 1.3V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15 X40434S14Z-B (Note) X40434S ZB 1.3 to 5.5 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40434S14I-B X40434S IB 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil) M 14.15 X40434S14IZ-B (Note) X40434S ZIB 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40434V14-B X40434V B 1.3 to 5.5 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40434V14Z-B (Note) X40434V ZB 1.3 to 5.5 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40434V14I-B X40434V IB 1.3 to 5.5 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40434V14IZ-B (Note) X4043 4V ZIB 1.3 to 5.5 -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40434S14-A X40434S A 1.3 to 5.5 3.1V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15 X40434S14Z-A (Note) X40434S ZA 1.3 to 5.5 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40434S14I-A X40434S IA 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil) M 14.15 X40434S14IZ-A (Note) X40434S ZIA 1.3 to 5.5 -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 4 of 26 May 24, 2006 (4.4mm) M14.173 X40434V14Z-A (Note) X40434V ZA 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40434V14I-A X40434V IA -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40434V14IZ-A (Note) X40434VZIA -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40430S14Z-A (Note) X40430S ZA 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40430S14I-A X40430S IA -40 to +85 14 Ld SOIC (150 mil) M14.15 X40430S14IZ-A (Note) X40430S ZIA -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40430V14-A X4043 0VA 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40430V14Z-A (Note) X40430V ZA 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40430V14I-A X4043 0VIA -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40430V14IZ-AT1 (Note) X4043 0VZIA -40 to +85 14 Ld TSSOP Tape and Reel (4.4mm) (Pb-free) M14.173 PART NUMBER WITH RESET X40431S14I-C X40431S IC -40 to +85 14 Ld SOIC (150 mil) M14.15 X40431V14-C X40431V C 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40431V14I-C X40431 IC -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40431S14Z-B (Note) X40431S ZB 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40431S14I-B X40431S IB -40 to +85 14 Ld SOIC (150 mil) M14.15 X40431S14IZ-B (Note) X40431S ZIB -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40431V14-B X40431V B 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40431V14Z-B (Note) X40431V ZB 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40431V14I-B X40431V IB -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40431V14IZ-B (Note) X40431V ZIB -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40435S14I-C X40435 IC -40 to +85 14 Ld SOIC (150 mil) M14.15 X40435V14-C X40435 C 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40435V14I-C X40435 IC -40 to +85 14 Ld TSSOP (4.4mm) M14.173 Ordering Information (Continued) PART NUMBER* PART MARKING MONITORED VCC RANGE VTRIP1 RANGE VTRIP2 RANGE VTRIP3 RANGE TEMP. RANGE (°C) PACKAGE PKG. DWG. #

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 5 of 26 May 24, 2006 X40435S14Z-B (Note) X40435S ZB 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40435S14I-B X40435 IB -40 to +85 14 Ld SOIC (150 mil) M14.15 X40435S14IZ-B (Note) X40435S ZIB -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40435V14-B X40435 B 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40435V14Z-B (Note) X40435V ZB 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40435V14I-B X40435 IB -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40435V14IZ-B (Note) X40435V ZIB -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40435S14-A X40435 A 3.1V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15 X40435S14Z-A (Note) X40435S ZA 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40435S14I-A X40435 IA -40 to +85 14 Ld SOIC (150 mil) M14.15 X40435S14IZ-A (Note) X40435S ZIA -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40435V14-A X40435 A 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40435V14Z-A (Note) X40435V ZA 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40435V14I-A X40435 IA -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40435V14IZ-A (Note) X40435V ZIA -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40431S14Z-A (Note) X40431S ZA 0 to 70 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40431S14I-A X40431S IA -40 to +85 14 Ld SOIC (150 mil) M14.15 X40431S14IZ-A (Note) X40431S ZIA -40 to +85 14 Ld SOIC (150 mil) (Pb-free) M14.15 X40431V14-A X40431V A 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40431V14Z-A (Note) X40431V ZA 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40431V14I-A X40431V IA -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X40431V14IZ-A (Note) X40431V ZIA -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER* PART MARKING MONITORED VCC RANGE VTRIP1 RANGE VTRIP2 RANGE VTRIP3 RANGE TEMP. RANGE (°C) PACKAGE PKG. DWG. #

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 6 of 26 May 24, 2006 PIN CONFIGURATION V3MON VSS VCC SDA SCL LOWLINE NC RESET V2MON MR WP V3FAIL WDO V2FAIL V3MON VCC SDA SCL WP V3FAIL WDO VSS LOWLINE NC RESET V2MON MR V2FAIL X40430, X40434 X40431, X40435

14 Ld SOIC, TSSOP 14 Ld SOIC, TSSOP

1V 2 F A I L V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 2V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435). 3L O W L I N EEarly Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4N C No connect. 5M R Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re- main HIGH/LOW until the pin is released and for the tPURST thereafter.

6 RESET /

RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when- ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when- ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. 7V SS Ground 8S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. 9S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull down resistor (>10M typical). 11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external components. Connect V3MON to VSS or VCC when not used. The V3MON comparator is supplied by the V3MON input. 12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin. 13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog timer goes active.

14 V CC Supply Voltage

operate with insufficient voltage. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power-up. allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button ton is released and for tPURST thereafter. and exceeds VTRIP1 for tPURST. active until the V2MON drops below 1V (V2MON falling). active until the V3MON drops below 1V (V3MON falling).

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 9 of 26 May 24, 2006 Setting a VTRIPx Voltage (x = 1, 2, 3) There are two procedures used to set the threshold volt- ages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present V TRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the V TRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to “reset” the V TRIPx voltage before setting the new value. Setting a Higher VTRIPx Voltage (x = 1, 2, 3) To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired V TRIPx threshold voltage to the corresponding input pin Vcc(V1MON), V2MON or V3MON. Then, a programming voltage (Vp) must be applied to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for V TRIP1, 09h for VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to com- plete the operation. To check if the VTRIPX has been set, set VXMON to a value slightly greater than V TRIPX (that was previously set). Slowly ramp down VXMON and observe when the corresponding outputs (LOWLINE V2FAIL and V3FAIL ) switch. The voltage at which this occurs is the VTRIPX (actual). CASE A Now if the desired V TRIPX is greater than the V TRIPX (actual), then add the difference between V TRIPX (desired) – VTRIPX (actual) to the original VTRIPX desired. This is your new V TRIPX that should be applied to VXMON and the whole sequence should be repeated again (see Figure 5). C ASE B Now if the V TRIPX (actual), is higher than the V TRIPX (desired), perform the reset sequence as described in the next section. The new V TRIPX voltage to be applied to VXMON will now be: V TRIPX (desired) – (V TRIPX (actual) – VTRIPX (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIPx Voltage (x = 1, 2, 3) In order to set VTRIPx to a lower voltage than the present value, then V TRIPx must first be “reset” according to the procedure described below. Once V TRIPx has been “reset”, then VTRIPx can be set to the desired voltage using the procedure described in “Setting a Higher V TRIPx Voltage”. Resetting the VTRIPx Voltage To reset a V TRIPx voltage, apply the programming volt- age (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for V TRIP1, 0Bh for V TRIP2, and 0Fh for V TRIP3, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the program- ming sequence. Pin WDO must then be brought LOW to complete the operation. After being reset, the value of V TRIPx becomes a nomi- nal value of 1.7V or lesser. Notes: 1. This operation does not corrupt the memory array. 2. Set V CC  1.5(V2MON or V3MON), when setting VTRIP2 or VTRIP3 respectively. CONTROL REGISTER The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each regi ster write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. S ee "Writing to the Control Registers" on page 11. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, and BP. The X40430, X40431, X40434, X40435 will not ack nowledge any data bytes written after the first byte is entered. The state of the Control Register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. 76543210 PUP1 WD1 WD0 BP 0 RWEL WEL PUP0

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 11 of 26 May 24, 2006 Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. BP: Block Protect Bits (Nonvolatile) The Block Protect Bit BP, determines which blocks of the array are write protected. A write to a protected block of memory is ignored. Th e block protect bit will prevent write operations to half or none of the array. PUP1, PUP0: Power-up Bits (Nonvolatile) The Power-up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power-up times are shown in the following table. WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watch- dog Timer. The options are shown below. Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write one byte value to the Control Register that has all the control bits set to the desired state. The Control regis- ter can be represented as qxys 001r in binary, where xy are the WD bits, s is the BP bit and qr are the power-up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write oper- ation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write pro- tected block. To illustrate, a sequence of wr ites to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolat ile bits unchanged and the RWEL bit remains set. Notes: 1. t PURST is set to 200ms as factory default. 2. Watch Dog Timer bits are shipped disabled. FAULT DETECTION REGISTER The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this FDR. BP Protected Addresses (Size) Memory Array Lock

0 None None

1 100h – 1FFh (256 bytes) Upper Half of Memory Array PUP1 PUP0 Power-on Reset Delay (tPURST) 0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) 7 65432 1 0 LV1F LV2F LV3F WDF MRF 0 0 0

and the last 6 bytes are written to locations 0 through 5. the previous data, one byte at a time. ceed with the read or write operation. See Figure 13. Reads, and Sequential Reads. Figure 11. Page Write Operation Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.

5 Bytes

7 Bytes

acknowledge, and data transfer sequence. Figure 13. Acknowledge Polling Sequence clock cycle and then issue a stop condition. edge, and data transfer sequence. needs to read, but is not ready for the data. acknowledge and then issuing a stop condition. edge and data transfer sequence.

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 18 of 26 May 24, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this spec ification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS *See Ordering Info Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Version Chip Supply Voltage Monitored* Voltages X40430, X40431 2.7V to 5.5V 1.7V to 5.5V X40434, X40435 2.7V to 5.5V 1.0V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min Typ (4) Max Unit Test Conditions ICC1(1) Active Supply Current (VCC) Read 1.5 mA V IL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz ICC2(1) Active Supply Current (VCC) Write 3.0 mA ISB1(1)(6) Standby Current (VCC) AC (WDT off) 6 10 µA V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz ISB2(2)(6) Standby Current (VCC) DC (WDT on) 25 30 µA V SDA = VSCL = VCC Others = GND or VCC ILI Input Leakage Current (SCL, MR, WP) 10 µA V IL = GND to VCC ILO Output Leakage Current (SDA, V2- FAIL, V3FAIL, WDO, RESET) 10 µA V SDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage (SDA, SCL, MR, WP) -0.5 VCC x 0.3 V VIH(3) Input HIGH Voltage (SDA, SCL, MR, WP) VCC x 0.7 VCC + 0.5 V VHYS(6) Schmitt Trigger Input Hysteresis

  • Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage (SDA, RE- SET/RESET, LOWLINE, V2FAIL, V3FAIL, WDO) IOL = 1.8mA (2.7-3.6V) VOH Output (RESET, LOWLINE) HIGH Voltage VCC – 0.8 VCC – 0.4 VI OH = -1.0mA (2.7-5.5V) IOH = -0.4mA (2.7-3.6V)

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 19 of 26 May 24, 2006 Notes: (1) The device enters the Active state after any start, and re mains active until: 9 clock cycl es later if the Device Selec t Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, V CC = 3V (5) See ordering information for standard programming leve ls. For custom programmed levels, contact factory. (6) Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3) CAPACITANCE VCC Supply VTRIP1(5) VCC Trip Point Voltage Range 2.0 4.75 V 4.55 4.6 4.65 V X40430, X40431-A, X40434, X40435 4.35 4.4 4.45 V X40430, X40431-B 2.85 2.9 2.95 V X40430, X40431-C Second Supply Monitor IV2 V2MON Current 15 µA VTRIP2(5) V2MON Trip Point Voltage Range 1.7 0.9 4.75 3.5 V V x40430, X40431 x40434, X40435 2.85 2.9 2.95 V X40430, X40431-A 2.55 2.6 2.65 V X40430, X40431-B 2.15 2.2 2.25 V X40430, X40431-C 1.25 1.3 1.35 V X40434, X40435-A&B 0.95 1.0 1.05 V X40434, X40435-C t RPD2(6) VTRIP2 to V2FAIL 5µ s Third Supply Monitor IV3 V3MON Current 15 µA VTRIP3(5) V3MON Trip Point Voltage Range 1.7 4.75 V 1.65 1.7 1.75 V X40430, X40431 3.05 3.1 3.15 V X40434, X40435-A 2.85 2.9 2.95 V X40434, X40435-B&C tRPD3(6) VTRIP3 to V3FAIL 5µ s D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min Typ (4) Max Unit Test Conditions –VREF tRPDX = 5µs worst case Output Pin VxMON R C V = 100mVV Vref Symbol Parameter Max Unit Test Conditions COUT(1) Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO) 8p F V OUT = 0V CIN(1) Input Capacitance (SCL, WP, MR) 6 pF V IN = 0V Note: (1) This parameter is not 100% tested.

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 20 of 26 May 24, 2006 EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V A.C. TEST CONDITIONS SYMBOL TABLE A.C. CHARACTERISTICS Note: (1) Cb = total capacitance of one bus line in pF. Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load SDA 30pF V2MON, V3MON 4.6k RESET 30pF 2.06k V2FAIL, VCC 4.6k 30pF WDO V3FAIL Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INP UTS OUTPUTS to HIGH Symbol Parameter Min Max Unit fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 21 of 26 May 24, 2006 TIMING DIAGRAMS Bus Timing WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition Symbol Parameter Min Typ Max Unit tWC(1) Write Cycle Time 5 10 ms

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 22 of 26 May 24, 2006 Power Fail Timings RESET/RESET/MR Timings V2MON or V2FAIL or tR tF tRPDX VRVALID V3MON V3FAIL LOWLINE or VCC VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 2, 3 LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Symbol Parameters Min Typ (1) Max Unit tRPD1(2) tRPDL VTRIP1 to RESET/RESET (Power-down only) VTRIP1 to LOWLINE 5µ s t LR LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL] 500 ns tRPDX(2) VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3) 5 µs tPURST Power-on Reset delay: PUP1 = 0, PUP0 = 0 PUP1 = 0, PUP0 = 1 (factory setting) PUP1 = 1, PUP0 = 0 PUP1 = 1, PUP0 = 1 (2) 200 400(2) 800(2) ms ms ms ms t F VCC, V2MON, V3MON, Fall Time 20 mV µs tR VCC, V2MON, V3MON, Rise Time 20 mV µs VRVALID Reset Valid VCC 1V tMD(2) MR to RESET/ RESET delay (activation only) 500 ns VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID MR tMD tIN1

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 23 of 26 May 24, 2006 Notes: (1) V CC = 5V at 25°C. (2) Values based on characterization data only. Watchdog Time Out For 2-Wire Interface tin1 Pulse width for MR 5µ s tWDO Watchdog Timer Period: WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 1, WD0 = 0 WD1 = 1, WD0 = 1 (factory setting) 1.4 (2) 200(2) OFF s ms ms t RST1 Watchdog Reset Time Out Delay WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 100 200 300 ms t RST2 Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 µs LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) (CONTINUED) Symbol Parameters Min Typ (1) Max Unit < tWDO tRST WDO SDA Start tWDO tRST SCL Start tRSP WDT Restart Start SDA SCL Minimum Sequence to Reset WDT Clockin (0 or 1)

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 24 of 26 May 24, 2006 VTRIPX Set/Reset Conditions VTRIP1, VTRIP2, VTRIP3 Programming Specifications: VCC = 2.0 - 5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range – X40430, X40431 1.7 4.75 V VTRAN2A VTRIP2 Set to Voltage Range – X40434, X40435 0.9 3.5 V VTRAN3 VTRIP3 Set Voltage Range 1.7 4.75 V Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 µs SCL SDA VCC/V2MON/V3MON(VTRIPX) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 *0Dh sets VTRIP1 sets VTRIP2 sets VTRIP3 *01h *09h *03h *0Bh *0Fh resets VTRIP3 resets VTRIP2 resets VTRIP1 Start * all others reserved 00h

X40430, X40431, X40434, X40435 FN8251 Rev 1.00 Page 25 of 26 May 24, 2006 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

FN8251 Rev 1.00 Page 26 of 26 May 24, 2006 X40430, X40431, X40434, X40435 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7  0o 8o 0o 8o - Rev. 2 4/06