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FN8118 Rev 3.00 Page 1 of 24 December 9, 2015 FN8118 Rev 3.00 December 9, 2015 X4043, X4045 4k, 512 x 8 Bit CPU Supervisor with 4kbit EEPROM DATASHEET

FEATURES

  • Selectable watchdog timer
  • L o w VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low V CC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V
  • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current
  • 4kbits of EEPROM —16-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
  • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of EEPROM array with Block Lock ™ protection
  • 400kHz 2-wire interface
  • 2.7V to 5.5V power supply operation
  • Available packages —8 Ld SOIC —8 Ld MSOP —8 Ld PDIP
  • Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X4043/45 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one pa ckage. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET /RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V CC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Five industry stan- dard V TRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power-on and GenerationVTRIP RESET (X4043) Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic Block Lock Control 2Kbits 1Kb 1Kb RESET (X4045)

X4043, X4045 FN8118 Rev 3.00 Page 2 of 24 December 9, 2015

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGE X4043S8IZ-4.5A (Note) X4043 Z AM X4045S8IZ-4.5A (Note) X4045 Z AM - 40 to 85 8 Ld SOIC (Pb-free) X4043M8Z-4.5A (Note) DAZ X4045M8Z-4.5A (Note) (No longer available, recommended replacement: X4045S8Z-4.5A) DBH 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ-4.5A (Note) DAU X4045M8IZ-4.5A (Note) (No longer available, recommended replacement: X4045S8IZ-4.5A) DBE -40 to 85 8 Ld MSOP (Pb-free) X4043PZ-4.5A (Note) (No longer available, recommended replacement: X4043M8Z-4.5A) X4043P Z AL X4045PZ-4.5A (Note) (No longer available, recommended replacement: X4045S8Z-4.5A) X4045P Z AL 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ-4.5A (Note) (No longer available, recommended replacement: X4043M8IZ-4.5A) X4043P Z AM X4045PIZ-4.5A (Note) (No longer available, recommended replacement: X4045S8IZ-4.5A) X4045P Z AM -40 to 85 8 Ld PDIP (Pb-free) X4043S8Z* (Note) X4043 Z X4045S8Z* (Note) X4045 Z 4.5-5.5 4.25-4.5 0 to 70 8 Ld SOIC (Pb-free) X4043S8IZ* (Note) X4043 Z I X4045S8IZ (Note) X4045 Z I -40 to 85 8 L d SOIC (Pb-free) X4043M8Z* (Note) DAW X4045M8Z (Note) (No longer available, recommended replacement: X4045S8Z) DBD 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ (Note) DAR X4045M8IZ (Note) (No longer available, recommended replacement: X4045S8IZ) DBA -40 to 85 8 Ld MSOP (Pb-free) X4043PZ (Note) (No longer available, recommended replacement: X4043M8Z) X4043P X4045PZ (Note) (No longer available, recommended replacement: X4045S8Z) X4045P Z 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ (Note) (No longer available, recommended replacement: X4043M8IZ) X4043P Z I X4045PIZ (Note) (No longer available, recommended replacement: X4045S8IZ) X4045P Z I -40 to 85 8 Ld PDIP (Pb-free)

X4043, X4045 FN8118 Rev 3.00 Page 3 of 24 December 9, 2015 X4043S8IZ-2.7A* (Note) X4043 Z AP X4045S8IZ-2.7A (Note) X4045 Z AP -40 to 85 8 Ld SOIC (Pb-free) X4043M8Z-2.7A (Note) DAY X4045M8Z-2.7A (Note) (No longer available, recommended replacement: X4045S8Z-2.7A) DBG 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ-2.7A (Note) DAT X4045M8IZ-2.7A (Note) (No longer available, recommended replacement: X4045S8IZ-2.7A) DBC -40 to 85 8 Ld MSOP (Pb-free) X4043PZ-2.7A (Note) (No longer available, recommended replacement: X4043M8Z-2.7A) X4043P Z AN X4045PZ-2.7A (Note) (No longer available, recommended replacement: X4045S8Z-2.7A) X4045P Z AN 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ-2.7A (Note) (No longer available, recommended replacement: X4043M8IZ-2.7A) X4043P Z AP X4045PIZ-2.7A (Note) (No longer available, recommended replacement: X4045S8IZ-2.7A) X4045P Z AP -40 to 85 8 Ld PDIP (Pb-free) X4043S8IZ-2.7 (Note) X4043 Z G X4045S8IZ-2.7 (Note) X4045 Z G -40 t o 85 8 Ld SOIC (Pb-free) X4043M8Z-2.7 (Note) DAX X4045M8Z-2.7 (Note) (No longer available, recommended replacement: X4045S8Z-2.7) DBF 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ-2.7(Note) DAS X4045M8IZ-2.7 (Note) (No longer available, recommended replacement: X4045S8IZ-2.7) DBB -40 to 85 8 Ld MSOP (Pb-free) X4043PZ-2.7 (Note) (No longer available, recommended replacement: X4043M8Z-2.7) X4043P Z F X4045PZ-2.7 (Note) (No longer available, recommended replacement: X4045S8Z-2.7) X4045P Z F 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ-2.7 (Note) (No longer available, recommended replacement: X4043M8IZ-2.7) X4043P Z G X4045PIZ-2.7 (Note) (No longer available, recommended replacement: X4045S8IZ-2.7) X4045P Z G -40 to 85 8 Ld PDIP (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGE

X4043, X4045 FN8118 Rev 3.00 Page 4 of 24 December 9, 2015 The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing oper- ation on an I 2C bus. The device utilizes Intersil’s proprietary Direct Write ™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION NC VSS VCC SDA SCL3 8NC WP RESET 8-Pin JEDEC SOIC, MSOP (PDIP no longer available or supported) Pin (SOIC/MSOP/DIP) Name Function

1 NC No internal connections

2 NC No internal connections

3 RESET

/RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below VTRIP. It will remain active until VCC rises above the VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. RESET /RESET goes active on power-uppower-up and remains active for 250ms after the power supply stabilizes. RESET is an active high open drain output. An external pull up resistor is required on the RESET /RESET pin. 4V SS Ground 5S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). 6S C L Serial Clock. The Serial Clock input controls the serial bus timing for data input and output. 7W P Write Protect. WP HIGH prevents writes to any location in the device (including the control register). Connect WP pin to V SS when it is not used. 8V CC Supply Voltage

X4043, X4045 FN8118 Rev 3.00 Page 6 of 24 December 9, 2015 Setting a VTRIP Voltage There are two procedures used to set the threshold voltages (VTRIP), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present V TRIP is 2.9 V and the new VTRIP is 3.2 V, the new voltage can be stored directly into the VTRIP cell. If however, the new setting is to be lower than the present setting, then it is necessary to “reset” the V TRIP voltage before setting the new value. Setting a Higher VTRIP Voltage To set a V TRIP threshold to a new voltage which is higher than the present threshold, the user must apply the desired V TRIP threshold voltage to the V CC. Then, a programming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for V TRIP and a 00h Data Byte in order to program V TRIP . The STOP bit following a valid write oper ation initiates the program- ming sequence. WP pin must then be brought LOW to complete the operation. To check if the V TRIP has been set, first power-down the device. Slowly ramp up VCC and observe when the output, RESET (4043) or RESET (4045) switches. The voltage at which this occurs is the V TRIP (actual) (see Figure 2). CASE A Now if the desired V TRIP is greater than the V TRIP (actual), then add t he difference between V TRIP (desired) - VTRIP (actual) to the original V TRIP desired. This is your new V TRIP that should be applied to V CC and the whole sequence should be repeated again (see Figure 5). C ASE B Now if the V TRIP (actual), is higher than the V TRIP (desired), perform the reset sequence as described in the next section. The new VTRIP voltage to be applied to VCC will now be: VTRIP (desired) - (VTRIP ( a c t u a l )-VTRIP (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIP Voltage In order to set V TRIP to a lower voltage than the pres- ent value, then VTRIP must first be “reset” according to the procedure described below. Once V TRIP has been “reset”, then VTRIP can be set to the desired voltage using the procedure described in “Setting a Higher V TRIP Voltage”. Resetting the VTRIP Voltage To reset a VTRIP voltage, apply the programming volt- age (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h fol- lowed by 00h for the Data Byte in order to reset V TRIP. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation. After being reset, the value of V TRIP becomes a nomi- nal value of 1.7V or lesser. Note: This operation does not corrupt the memory array.

Figure 5. VTRIP Programming Sequence changing the block lock and watchdog timer settings. and do not change when power is removed. in the slave byte (1011) and is located at address 1FFh. data byte is allowed for each register write operation.

X4043, X4045 FN8118 Rev 3.00 Page 9 of 24 December 9, 2015 The state of the control regi ster can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be igno red (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part pow- ers up again. Writes to the WEL bit do not cause a non- volatile write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) The block protect bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operat ions to one of eight seg- ments of the array. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 contro l the period of the watch- dog timer. The options are shown below. Writing to the Control Register Changing any of the nonvolatile bits of the control regis- ter requires the following steps: – Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop). – Write a 06H to the control register to set both the reg- ister write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). – Write a value to the control register that has all the control bits set to the desired state. This can be repre- sented as 0xys t01r in binary, where xy are the WD bits, and rst are the BP bits. (Operation preceeded by a start and ended with a stop). Since this is a nonvola- tile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xys t11r) then the RWEL bit is set, but the WD1, WD0, BP2, BP1 and BP0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write oper- ation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write pro- tected block. To illustrate, a sequence of wr ites to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolat ile bits unchanged and the RWEL bit remains set. 76 5 4 3 2 1 0

0 WD1 WD0 BP1 BP0 RWEL WEL BP2BP2

(Size) Array Lock 0 0 0 None (factory setting) None 0 0 1 180h - 1FFh (128 bytes) Upper 1/4 (Q4) 0 1 0 100h - 1FFh (256 bytes) Upper 1/2 (Q3,Q4) 0 1 1 000h - 1FFh (512 bytes) Full Array (All) 1 0 0 000h - 00Fh (16 bytes) First Page (P1) 1 0 1 000h - 01Fh (32 bytes) First 2 pgs (P2) 1 1 0 000h - 03Fh (64 bytes) First 4 pgs (P4) 1 1 1 000h - 07Fh (128 bytes) First 8 pgs (P8) WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 Disabled (factory setting)

Figure 10. Byte Write Sequence over-writes the previous data, one byte at a time. Figure 11. Page Write Operation Figure 12. Writing 12-bytes to a 16-byte page starting at location 10

5 Bytes

7 Bytes

X4043, X4045 FN8118 Rev 3.00 Page 15 of 24 December 9, 2015 Data Protection The following circuitry has been included to prevent inadvertent writes: – The WEL bit must be set to allow write operations. – The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. – A three step sequence is required before writing into the control register to change watchdog timer or block lock settings. – The WP pin, when held HIGH, prevents all writes to the array and the control register. – Communication to the device is inhibited as a result of a low voltage condition (V CC < VTRIP)any in-progress communication is terminated. – Block lock bits can protect sections of the memory array from write operations. Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

X4043, X4045 FN8118 Rev 3.00 Page 16 of 24 December 9, 2015 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Notes: (1) The device enters the active state after any start, and re mains active until: 9 clock cyc les later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t WC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) V IL min. and VIH max. are for reference only and are not tested. Symbol Parameter VCC = 2.7 to 5.5V Unit Test ConditionsMin. Max. ICC1(1) Active supply current read 1.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400kHzICC2(1) Active supply current write 3.0 mA ISB1(2) Standby current AC (WDT off) 1 µA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL= 400kHz, SDA = open VCC = 1.22 x VCC min ISB2(2) Standby current DC (WDT off) 1 µA V SDA = VSCL = VSB Others = GND or VSB ISB3(2) Standby current DC (WDT on) 20 µA V SDA =VSCL = VSB Others = GND or VSB ILI Input leakage current 10 µA V IN = GND to VCC ILO Output leakage current 10 µA V SDA = GND to VCC device is in standby VIL(3) Input LOW voltage -0.5 V CC x 0.3 V VIH(3) Input nonvolatile V CC x 0.7 V CC + 0.5 V VHYS Schmitt trigger input hysteresis Fixed input level V CC related level 0.2 .05 x VCC V V V OL Output LOW voltage 0.4 V I OL = 3.0mA (2.7-5.5V) IOL = 1.8mA (2.0-3.6V) RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Option Supply Voltage Limits -2.7 and -2.7A 2.7V to 5.5V Blank and -4.5A 4.5V to 5.5V

X4043, X4045 FN8118 Rev 3.00 Page 17 of 24 December 9, 2015 CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Notes: (5) Typical values are for T A = 25°C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF. Symbol Parameter Max. Unit Test Conditions COUT(4) Output capacitance (SDA, RESET/RESET) 8 pF V OUT = 0V CIN(4) Input capacitance (SCL, WP) 6 pF V IN = 0V 4.6k RESET 100pF SDA 1533 100pF For VOL= 0.4V and IOL = 3 mA Input pulse levels 0.1 V CC to 0.9 VCC Input rise and fall times 10ns Input and output timing levels 0.5 V CC Output load Standard output load Symbol Parameter 100kHz 400kHz UnitMin. Max. Min. Max. fSCL SCL clock frequency 0 100 0 400 kHz tIN Pulse width suppression time at inputs n/a n/a 50 ns tAA SCL LOW to SDA data out valid 0.1 0.9 0.1 0.9 µs tBUF Time the bus free before start of new transmission 4.7 1.3 µs tLOW Clock LOW time 4.7 1.3 µs tHIGH Clock HIGH time 4.0 0.6 µs tSU:STA Start condition setup time 4.7 0.6 µs tHD:STA Start condition hold time 4.0 0.6 µs tSU:DAT Data in setup time 250 100 ns tHD:DAT Data in hold time 5.0 0 µs tSU:STO Stop condition setup time 0.6 0.6 µs tDH Data output hold time 50 50 ns tR SDA and SCL rise time 1000 20 + .1Cb (6) 300 ns tF SDA and SCL fall time 300 20 + .1Cb (6) 300 ns tSU:WP WP setup time 0.4 0.6 s tHD:WP WP hold time 0 0 s Cb Capacitive load for each bus line 400 400 pF

X4043, X4045 FN8118 Rev 3.00 Page 18 of 24 December 9, 2015 TIMING DIAGRAMS Bus Timing WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Notes: (7) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. Symbol Parameter Min. Typ. (7) Max. Unit tWC(7) Write cycle time 5 10 ms tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition

X4043, X4045 FN8118 Rev 3.00 Page 19 of 24 December 9, 2015 Power-Up and Power-Down Timing RESET Output Timing Notes: (8) This parameter is periodically sampled and not 100% tested. Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X4043/45-4.5A Reset trip point voltage, X4043/45 Reset trip point voltage, X4043/45-2.7A Reset trip point voltage, X4043/45-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V t PURST Power-up reset time out 100 200 400 ms tRPD(8) VCC detect to RESET/RESET 10 20 µs tF(8) VCC fall time 20 mV/µs tR(8) VCC rise time 20 mV/µs VRVALID Reset valid VCC 1V tWDO Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 200 600 1.4 300 800 ms ms sec t RSP Watchdog Time Restart pulse width 1 µs tRST Reset time out 100 200 400 ms VCC tPURST tPURST tR tF tRPD

0 Volts

(X4043) (X4045)

X4043, X4045 FN8118 Rev 3.00 Page 20 of 24 December 9, 2015 Watchdog Time Out For 2-Wire Interface VTRIP Set/Reset Conditions < tWDO tRST (4043) RESET SDA Start tWDO tRST SCL Start tRSP WDT Restart Start SDA SCL Minimum Sequence to Reset WDT Clockin (0 or 1) SCL SDA VCC(VTRIP) WP tTSU tTHD tVPH tVPS VP tWC tVPO 07 70 7 sets VTRIP01h* 03h* resets VTRIP Start * all others reserved A0h 00h

FN8118 Rev 3.00 Page 21 of 24 December 9, 2015 X4043, X4045 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. VTRIP Programming Specifications: VCC = 2.0-5.5V; Temperature = 25°C ABOUT INTERSIL Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support Parameter Description Min. Max. Unit tVPS WP Program Voltage Setup time 10 µs tVPH WP Program Voltage Hold time 10 µs tTSU VTRIP Level Setup time 10 µs tTHD VTRIP Level Hold (stable) time 10 µs tWC VTRIP Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN VTRIP Set Voltage Range 2.0 4.75 V Vtv VTRIP Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WP Program Voltage Setup time 10 µs

REVISION HISTORY

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE December 9, 2015 FN8118.3 Updated Ordering Information Table on page 2. Added Revision History and About Intersil sections.

X4043, X4045 FN8118 Rev 3.00 Page 22 of 24 December 9, 2015 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X4043, X4045 FN8118 Rev 3.00 Page 23 of 24 December 9, 2015 PACKAGING INFORMATION 0.118 ± 0.002 (3.00 ± 0.05) 0.040 ± 0.002 (1.02 ± 0.05) 0.150 (3.81) Ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7° Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 8-Lead Miniature Small Outline Gull Wing Package Type M NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 0.220" 0.0256" Typical 0.025" Typical 0.020" Typical Ref.

X4043, X4045 FN8118 Rev 3.00 Page 24 of 24 December 9, 2015 PACKAGING INFORMATION NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) Ref. Pin 1 Index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) Pin 1 Seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) Typ. 0.010 (0.25) 15° 8-Lead Plastic Dual In-Line Package Type P Half Shoulder Width On All End Pins Optional .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Plane