M37754M6C-XXXGP

M37754M6C-XXXGP RENESAS | Alldatasheet

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The M37754M6C-XXXGP and M37754M6C-XXXHP are single-chip microcomputers designed with high-performance CMOS silicon gate technology. This is housed in a 100-pin plastic molded QFP . This microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing, and the bus interface unit enhances the memory access efficiency to execute instructions fast. In addition to the 7700 Family basic instructions, the M37754M6C- XXXGP and M37754M6C-XXXHP has 6 special instructions which contain instructions for signed multiplication/division; these added in- structions improve the servo arithmetic performance to control hard disk drives and so on. This microcomputer also include the ROM, RAM, multiple-function timers, motor control function, serial I/O, A-D converter, D-A con- verter, and so on. DISTINCTIVE FEATURES (103 basic instructions of 7700 Family + 6 special instructions)

• Instruction execution time (three-phase motor drive waveform or pulse motor control wave- form output)
• 12-bit watchdog timer
• Programmable input/output
• Small package [M37754M6C-XXXHP] APPLICATION Control devices for personal computer peripheral equipment such as CD-ROM drives, hard disk drives, high density FDD, printers Control devices for office equipment such as copiers and facsimiles Control devices for industrial equipment such as communication and measuring instruments Control devices for equipment required for motor control such as in- verter air conditioner and general purpose inverter M37754M6C-XXXGP PIN CONFIGURATION (TOP VIEW) Outline 100P6S-A PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ↔ P00/A0 ↔ P01/A1 ↔ P02/A2 ↔ P03/A3 ↔ P04/A4 ↔ P05/A5 ↔ P06/A6 ↔ P07/A7 ↔ P10/A8 ↔ P11/A9 ↔ P12/A10 ↔ P13/A11 ↔ P14/A12 ↔ P15/A13 ↔ P16/A14 ↔ P17/A15 ↔ P20/A16 ↔ P21/A17 ↔ P22/A18 ↔ P23/A19 ↔ P27/A23 ↔ P100/D0/LA0 ↔ P101/D1/LA1 ↔ P102/D2/LA2 ↔ P103/D3/LA3 ↔ P104/D4/LA4 ↔ P105/D5/LA5 ↔ P106/D6/LA6 ↔ P107/D7/LA7 ↔ P110/D8 ↔ P111/D 9 ↔ P112D 10 ↔ P113/D 11 ↔ P114/D 12 ↔ P115/D 13 ↔ P116/D 14 ↔ P117/D 15 ↔ P30/WR ↔ P31/BHE ↔ P32/ALE ↔ P33/HLDA VCC VSS → E/RD → XOUT ← XIN ← RESET CNV SS ← BYTE ↔ P40/HOLD P87/TXD 1 ↔ P86/RXD 1 ↔ P85/CLK1 ↔ P84/CTS1/RTS1/DA1/INT4 ↔ P83/TXD 0 ↔ P82/RXD 0/CLKS0 ↔ P81/CLK0 ↔ P80/CTS0/RTS0/CLKS1/DA0 ↔ VCC AV CC VREF → AV SS VSS P77/AN7/ADTRG ↔ P76/AN6 ↔ P75/AN5 ↔ P74/AN4 ↔ P73/AN3 ↔ P72/AN2 ↔ P71/AN1 ↔ P70/AN0 ↔ P95/INT3/KI4 ↔ P94/CS4/RTP13 ↔ P93/CS3/A22/RTP12 ↔ P92/CS2/A21/U/RTP11 ↔ P90/CS0 ↔ P67/TB2IN ↔ P66/TB1IN ↔ P65/TB0IN ↔ P64/INT2 ↔ P63/INT1 ↔ P62/INT0 ↔ P61/TA4IN ↔ P60/TA4OUT ↔ P57/TA3IN/KI3 ↔ P56/TA3OUT /KI2 ↔ P55/TA2IN/KI1 ↔ P54/TA2OUT /KI0 ↔ P53/TA1IN/W/RTP0 3 ↔ P52/TA1OUT /U/RTP02 ↔ P51/TA0IN/V/RTP01 ↔ P50/TA0OUT /W/RTP0 0 ↔ P47 ↔ P46 ↔ P45 ↔ P44 ↔ P43 ↔ P42/φ1 ↔ P41/RDY ↔ P91/CS1/A20/V/RTP10 ↔ 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 90 41 91 40 92 39 93 38 94 37 95 36 96 35 M37754M6C-XXXGP 98 33 99 32 100 31

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M37754M6C-XXXHP PIN CONFIGURATION (TOP VIEW) ↔ P43 ↔ P42/φ1 ↔ P41/RDY ↔ P40/HOLD ← BYTE CNVSS ← RESET ← XIN → XOUT → E/RD VSS VCC ↔ P33/HLDA ↔ P32/ALE ↔ P31/BHE ↔ P30/WR ↔ P117/D15 ↔ P116/D14 ↔ P115/D13 ↔ P114/D12 ↔ P113/D11 ↔ P112/D10 ↔ P111/D9 ↔ P110/D8 ↔ P107/D7/LA7 100 P02/A2 ↔ P01/A1 ↔ P00/A0 ↔ P87/TXD 1 ↔ P86/RXD 1 ↔ P85/CLK1 ↔ P84/CTS1/RTS1/DA1/INT4 ↔ P83/TXD 0 ↔ P82/RXD 0/CLKS0 ↔ P81/CLK0 ↔ VCC AV CC VREF → AV SS VSS P77/AN7/ADTRG ↔ M37754M6C-XXXHP P76/AN6 ↔ P75/AN5 ↔ P74/AN4 ↔ P73/AN3 ↔ P72/AN2 ↔ P71/AN1 ↔ P70/AN0 ↔ P95/INT3/KI4 ↔ P80/CTS0/RTS0/CLKS1/DA0 ↔ ↔ P106/D6/LA6 ↔ P105/D5/LA5 ↔ P104/D4/LA4 ↔ P103/D3/LA3 ↔ P102/D2/LA2 ↔ P101/D1/LA1 ↔ P100/D0/LA0 ↔ P27/A23 ↔ P23/A19 ↔ P22/A18 ↔ P21/A17 ↔ P20/A16 ↔ P17/A15 ↔ P16/A14 ↔ P15/A13 ↔ P14/A12 ↔ P13/A11 ↔ P12/A10 ↔ P11/A9 ↔ P10/A8 ↔ P07/A7 ↔ P06/A6 ↔ P05/A5 ↔ P04/A4 ↔ P03/A3 1 P9 4/CS4/RTP13 ↔ P93/CS3/A22/RTP12 ↔ P90/CS0 ↔ P67/TB2IN ↔ P66/TB1IN ↔ P65/TB0IN ↔ P64/INT2 ↔ P61/TA4IN ↔ P60/TA4OUT ↔ P57/TA3IN/KI3 ↔ P56/TA3OUT /KI2 ↔ P55/TA2IN/KI1 ↔ P54/TA2OUT /KI0 ↔ P53/TA1IN/W/RTP0 3 ↔ P52/TA1OUT /U/RTP02 ↔ P51/TA0IN/V/RTP01 ↔ P50/TA0OUT /W/RTP0 0 ↔ P47 ↔ P46 ↔ P45 ↔ P44 ↔ P92/CS2/A21/U/RTP11 ↔ P91/CS1/A20/V/RTP10 ↔ P63/INT1 ↔ P62/INT0 ↔ Outline 100P6Q-A Differences between M37754M6C-XXXGP and M37754M6C-XXXHP Product M37754M6C-XXXGP M37754M6C-XXXHP Package 100-pin QFP (100P6S-A) 100-pin fine pitch QFP (100P6Q-A)

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P2 (5) Input/Output port P2 P1 (8) Input/Output port P1 P0 (8) Input/Output port P0 ROM

48 Kbytes

P3 (4) Input/Output port P3 Input/Output port P4 P11(8) P10 (8) Input/Output port P8 Input/Output port P7 Input/Output port P9 Input/Output port P6 Input/Output port P5 Input/Output port P11 Clock Generating Circuit Instruction Register(8) RAM

2048 Bytes

Timer TA0(16) Timer TA1(16) Timer TA2(16) Timer TA3(16) Timer TB0(16) Timer TB1(16) Timer TB2(16) WatchdogTimer UART 0(9) UART 1(9) A-D Converter(10)D-A0 Converter(8) D-A1 Converter(8) Timer TA4(16) Address Bus Data Bus(Even) Data Buffer DBH (8) Data Buffer DBL(8) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q2(8) Incrementer(24) Program Address Register PA(24) Data Address Register DA(24) Processor Status Register PS(11) Direct Page Register DPR(16) Stack Pointer S(16) Incrementer/Decrementer(24) Program Counter PC(16) Program Bank Register PG(8) Data Bank Register DT(8) Index Register Y(16) Index Register X(16) Accumulator B(16) Accumulator A(16) Arithmetic Logic Unit(16) Input Buffer Register IB(16) Data Bus(Odd) XIN Reset input RESET (5V) VCC CNV SS (0V) AV SS (5V) AV CC Reference voltage input(0V) VSS Clock output XOUT VREF Clock input E Enable output Input/Output port P10 Bus width select input BYTE BLOCK DIAGRAM

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Number of basic machine instructions Instruction execution time Memory size Input/Output ports Multiple-function timers Serial I/O A-D converter D-A converter Watchdog timer Dead-time timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package ROM RAM P0, P1, P4–P8, P10, P11 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 FUNCTIONS OF M37754M6C-XXXGP FunctionsParameter 109 100 ns (the fastest instruction at external clock 40 MHz frequency) 8-bit × 9 5-bit × 1 4-bit × 1 6-bit × 1 16-bit × 5 16-bit × 3 (UART or clock synchronous serial I/O) × 2 10-bit × 1 (8 channels) 8-bit × 2 12-bit × 1 8-bit × 3 5 external types, 16 internal types (Each interrupt can be set to priority levels 0–7.) Built-in (externally connected to a ceramic resonator or quartz crystal resonator)

5 V±10 %

125 mW(at external clock 40 MHz frequency) 5 V 5 mA Maximum 16 Mbytes –20 to 85 °C CMOS high-performance silicon gate process 100-pin plastic molded QFP Input/Output withstand voltage Output current

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN DESCRIPTION (MICROCOMPUTER MODE) Functions Input Input Input Output Output Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input/ OutputNamePin V CC , VSS CNV SS RESET XIN XOUT E BYTE (Note) AVCC , AVSS VREF P00–P07 P10–P17 P20–P23, P27 P30–P33 P40–P47 P50–P57 P60–P67 P70–P77 P80–P87 P90–P95 Supply 5 V±10 % to VCC and 0 V to VSS . This pin controls the processor mode. Connect to VSS for single-chip mode or memory expansion mode. Connect to VCC for microprocessor mode. This is reset input pin. The microcomputer is reset when supplying “L ” level to this pin. These are I/O pins of internal clock generating circuit. Connect a ceramic or quartz- crystal resonator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. This pin outputs enable signal E, which indicates access state of data bus for single-chip mode. This pin outputs RD signal for memory expansion mode or microprocessor mode. This pin determines whether the external data bus is 8-bit width or 16-bit width for memory expansion mode or microprocessor mode. The width is 16 bits when “L ” signal inputs and 8 bits when “H” signal inputs. Power supply for the A-D converter and the D-A converter. Connect AV CC to VCC and AVSS to VSS externally. This is reference voltage input pin for the A-D converter and the D-A converter. In single-chip mode, port P0 is an 8-bit I/O port. This port has an I/O direction register and each pin can be programmed for input or output. These ports are in the input mode when reset. Address (A 0–A7) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. Address (A8– A15) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. Address (A16– A19, A23) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, WR, BHE , ALE, and HLDA signals are output. In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, P4 0, P41, and P42 become HOLD and RDY input pins, and clock φ1 output pin respectively. Functions of other pins are the same as in single-chip mode. In memory expansion mode, P42 can be pro- grammed as I/O port. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for timer A0, timer A1, timer A2, timer A3, output pins for motor drive waveform, and input pins for key input interrupt. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for timer A4, input pins for external interrupt input INT INT1, and INT2, and input pins for timer B0, timer B1, and timer B2. In addition to having the same functions as port P0 in single-chip mode, these pins also function as input pins for A-D converter. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for UART0, UART1, output pins for D-A converter, and input pin for INT In addition to having the same functions as port P0 in single-chip mode, these pins also function as input pin for INT 3, output pins for motor drive waveform. In memory expansion mode and microprocessor mode, these pins can be programmed as address (A 20–A22) or output pins for CS0–CS 4. Power supply CNV SS input Reset input Clock input Clock output Enable output Bus width select input Analog supply input Reference voltage input I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 I/O port P9 Note: It is impossible to change the input level of the BYTE pin in each bus cycle. In other words, bus width cannot be switched dynamically. Fix the input level of the BYTE pin to “H” or “L” according to the bus width used.

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Functions I/O Input/ OutputNamePin P100 – P107 I/O port P10 In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins become data I/O pins and operate as follows: (1) When using 16-bit width as external data bus width:

• Accessing external memory <When reading> Pins’ value is input into low-order internal data bus (DB0 to DB7). <When writing> Value of low-order internal data bus (DB0 to DB7) is output to these pins.
• Accessing internal memory <When reading> These pins become high impedance. <When writing> Value of internal data bus is output to these pins. (2) When using 8-bit width as external data bus width:
• Accessing external memory <When reading> Pins’ value is input into internal data bus. The value is input into low-order internal data bus (DB 0 to DB7) when accessing an even address; it is input into high-order internal data bus (DB8 to DB15) when accessing an odd address. <When writing> Value of internal data bus is output to these pins. The value of low-order internal data bus (DB 0 to DB7) is output when accessing an even address; the value of high-order internal data bus (DB8 to DB15) is output when accessing an odd address.
• Accessing internal memory <When reading> These pins become high impedance. <When writing> Value of internal data bus is output to these pins. When the external bus width is 8 bits, the mode where low-order address (LA 0 to LA7) is output when RD or WR output is “H” and data (D0 to D7) is input/output when RD or WR output is “L ” can be selected in specified external memory area access cycle. In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins operate as follows: (1) When using 16-bit width as external data bus width
• Accessing external memory <When reading> The value is input into high-order internal data bus (DB8 to DB15) when accessing an odd address; these pins enter high impedance state when not accessing an odd address. <When writing> Value of high-order internal data bus (DB 8 to DB15) is output to these pins.
• Accessing internal memory <When reading> These pins enter high impedance state. <When writing> Value of internal data bus is output to these pins. (2) When using 8-bit width as external data bus width These pins become I/O port P11 0 – P117. P110 – P117 I/O port P11 I/O

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS The M37754M6C-XXXGP and M37754M6C-XXXHP has the same functions as the M37754M8C-XXXGP and M37754M8C-XXXHP ex- cept for the following : (1) The ROM size is different. (2) The function of ROM area modification is not available. Therefore, refer to the section on the M37754M8C-XXXGP . MEMORY The memory map is shown in Figure 1. The address space is 16 Mbytes from addresses 0 16 to FFFFFF16. The address space is di- vided into 64-Kbyte units called banks. The banks are numbered from 0 16 to FF16. Internal ROM, internal RAM, and control registers for internal periph- eral devices are assigned to bank 0 16. The 48-Kbyte area from addresses 400016 to FFFF16 is the internal ROM. Addresses FFD2 16 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Refer to the section on interrupts for details. The 2048-byte area from addresses 80 16 to 87F16 contains the inter- nal RAM. In addition to storing data, the RAM is used as stack during a subroutine call, or interrupts. Assigned to addresses 0 16 to 7F16 are peripheral devices such as I/O ports, A-D converter, D-A converter, UART, timer, and interrupt control registers. A 256-byte direct page area can be allocated anywhere in bank 0 using the direct page register DPR. In direct page addressing mode, the memory in the direct page area can be accessed with two words thus reducing program steps. Note: Internal ROM area can be modified. (Refer to the section on ROM area modification function.) 00000016 00000016 00000016 00007F16 00087F16 00FFFF 16 00FFFE 16 00FFD2 16 00008016 00FFFF 16 Bank 016 Bank 116 01000016 01FFFF 16 FF000016 FFFFFF 16 Internal RAM 2048 bytes Peripherai devices control registers Interrupt vector table A-D INT3 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT Watchdog timer BRK instruction Zero divide see Fig. 2 for further information INT1 INT0 DBC RESET Bank FF Internal ROM Fig. 1 Memory map

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 2 Location of peripheral devices and interrupt control registers 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 00000A Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P11 register Port P11 direction register A-D control register 0 A-D control register 1 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register 00000B 00000C 00000D 00000E 00000F 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004A Count start register One-shot start register Up-down register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register Chip select control register Chip select area register Comparator function select register Comparator result register D-A register 0 D-A register 1 Particular function select register 0 Particular function select register 1 INT3 interrupt control register A-D interrupt control register UART0 trasmit interrupt control register UART0 receive interrupt control register UART1 trasmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register 00004B 00004C 00004D 00004E 00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Address (Hexadecimal notation) Address (Hexadecimal notation) Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P10 register Port P10 direction register Waveform output mode register Dead-time timer Pulse output data register 1 Pulse output data register 0 Timer A write register Reserved area (Note) Reserved area (Note) INT4 interrupt control register Note: Do not write to this address.

Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS

The M37754M6C-XXXGP and M37754M6C-XXXHP have the same function as the M37754M8C-XXXGP and M37754M8C-XXXHP in the following : (1) ABSOLUTE MAXIMUM RATINGS (2) RECOMMENDED OPERA TING CONDITIONS (3) ELECTRICAL CHARACTERISTICS (4) PERIPHERAL DEVICE INPUT/OUTPUT TIMING (5) TIMING REQUIREMENTS (6) SWITCHING CHARACTERISTICS Therefore, refer to the correponding section on the M37754M8C- XXXGP . ADDRESSING MODES AND INSTRUCTION SET The M37754M6C-XXXGP and M37754M6C-XXXHP have 29 pow- erful addressing modes; 1 addressing mode is added to the basis of the 7700 series. Refer to the “7751 Series Software Manual” for the details. INSTRUCTION SET The M37754M6C-XXXGP and M37754M6C-XXXHP have the ex- tended instruction set; 6 instructions are added to the instruction set of 7700 series. The object code of this extended instruction set is upwards compatible to that of 7700 series instruction set. Refer to the “7751 Series Software Manual” for the details. SHORTENING NUMBER OF INSTRUCTION EXECUTION CYCLES Shortening number of instruction execution cycles is realized in the M37754M6C-XXXGP and M37754M6C-XXXHP owing to modifica- tions of the instruction execution algorithm and the CPU circuit, and others. Refer to the “7751 Series Software Manual” about the number of instruction execution cycles. DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders: <M37754M6C-XXXGP> (1) M37754M6C-XXXGP mask ROM order confirmation form (2) 100P6S mark specification form (3) ROM data (EPROM 3 sets) <M37754M6C-XXXHP> (1) M37754M6C-XXXHP mask ROM order confirmation form (2) 100P6Q mark specification form (3) ROM data (EPROM 3 sets)

SINGLE-CHIP 16-BIT MICROCOMPUTER M37754M6C-XXXGP Date: Receipt GZZ–SH00–84B<85A0> ( ) Note : Please fill in all items marked Customer SupervisorCompany name Date issued Date: TEL 1. Confirmation Specify the name of the product being ordered. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : (hexadecimal notation) Responsible officer Section head signature Supervisor signature Issuance signatures One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered. Check @ in the appropriate box. STP instruction enable STP instruction disable 2. STP instruction option 0116 0016 Address 1016 Address 1016 3. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 100P6S Mark Specification Form (for M37754M6C-XXXGP), 100P6Q Mark Specification Form (for M37754M6C-XXXHP) and attach to the Mask ROM Order Confirmation Form.

7700 FAMILY MASK ROM ORDER CONFIRMATION FORM

(1) Set “FF16” in the shaded area. (2) Address 016 to 1016 are the area for storing the data on model designation and options.This area must be written with the data shown below. Details for option data are given next in the section describing the STP instruction option. Address and data are written in hexadecimal notation. F A E C B D FF FF FF FF FF FF Option data Address Address Address 27101 1FFFF 00010 00000 14000 48K 4. Comments DATA DATA

Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 14 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, ã,. (periods),, (commas) are usable. 100P6S (100-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark C. Special Mark Required B. Customer’s Parts Number + Mitsubishi catalog name Mitsubishi IC catalog name Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required 1 30 81 50 80 51 100 Mitsubishi lot number (6-digit or 7-digit) 1 30 81 50 80 51 100 1 30 81 50 80 51 100

© 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Apr. 1999. Specifications subject to change without notice. Notes regarding these materials

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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Rev. Rev. No. date

1.0 First Edition 971114

1.01 The following are added: 980528

• MASK ROM ORDER CONFIRMATION FORM
• MARK SPECIFICATION FORM 2.00 (1) For the “timer A write flag (address 4516)”, it’s name is corrected: 990428
• New register name: timer A write register
• Related page: page 8 REVISION DESCRIPTION LIST M37754M6C-XXXGP/HP DATA SHEET (1/1) Revision Description