HD74LS74A RENESAS | Alldatasheet

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Technical content

Features

  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS74AP DILP-14 pin PRDP0014AB-B (DP-14AV) P — HD74LS74AFPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP EL (2,000 pcs/reel) HD74LS74ARPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement (Top view) VCC 2CLR 2CK 2PR 1CLR GND 1CK 1PR PR CKD CLR QQ DCK PR Q Q CLR

Rev.3.00, Jul.22.2005, page 2 of 7 Function Table Input Output Preset Clear Clock D Q Q L H X X H L H L X X L H L L X X H* H* H H ↑ H H L H H ↑ L L H H H L X Q 0 Q0 H; high level, L; low level, X; irrelevant, ↑; transition from low to high level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. *;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level. Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage V CC 7 V Input voltage V IN 7 V Power dissipation P T 400 mW Storage temperature Tstg –65 to +150 °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage V CC 4.75 5.00 5.25 V IOH — — –400 µA Output current IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency f clock 0 — 25 MHz Clock High t w 25 — — Pulse width Clear Preset t w 25 — — ns “H” Data t su 20 ↑ — — Setup time “L” Data t su 20 ↑ — — ns Hold time t h 5 ↑ — — ns Note: ↑; The arrow indicates the rising edge.

Rev.3.00, Jul.22.2005, page 3 of 7

Electrical Characteristics

(Ta = –20 to +75 °C) Item Symbol min. typ.* max. Unit Condition VIH 2.0 — — V Input voltage VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA — — 0.5 I OL = 8 mA Output voltage VOL — — 0.4 V IOL = 4 mA VCC = 4.75 V, VIL = 0.8 V, VIH = 2 V D — — 20 Clear — — 40 Preset — — 40 Clock IIH — — 20 µA V CC = 5.25 V, VI = 2.7 V D — — –0.4 Clear — — –0.8 Preset — — –0.8 Clock IIL — — –0.4 mA V CC = 5.25 V, VI = 0.4 V D — — 0.1 Clear — — 0.2 Preset — — 0.2 Input current Clock II — — 0.1 mA V CC = 5.25 V, VI = 7 V Short-circuit output current IOS –20 — –100 mA V CC = 5.25 V Supply current I CC** — 4 8 mA V CC = 5.25 V Input clamp voltage V IR — — –1.5 V V CC = 4.75 V, IIN = –18 mA Notes: * V CC = 5 V, Ta = 25°C ** With all output open, I CC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol Inputs Outputs min. typ. max. Unit Condition Maximum clock frequency f max 25 33 MHz tPLH — 13 25 ns Propagation delay time tPHL Clear, Clock or Preset Q, Q — 25 40 ns CL = 15 pF, RL = 2 kΩ Timing Definition Data Clock 0 V 3 V 0 V 3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V "H" Data "L" Data tw tsu th tsu th

Rev.3.00, Jul.22.2005, page 4 of 7 Testing Method Test Circuit 1. ƒmax, tPLH, tPHL (Clock→ Q, Q) PR 4.5V VCC Output Q Output Q Input D CK Q Q CLR P.G. Zout = 50Ω Same as Load Circuit 1. RL Load circuit 1 CLInput P.G. Zout = 50Ω Notes: 1. Test is put into the each flip-flop. 2. C L includes probe and jig capacitance. 3. All diodes are 1S2074(H). 2. t PHL, tPLH (Clear or Preset→ Q, Q) PR VCC Output Q Output Q Q Q CLR Same as Load Circuit 1. RL Load circuit 1 CL D Input P.G. Zout = 50Ω Input P.G. Zout = 50Ω CK Notes: 1. Test is put into the each flip-flop. 2. C L includes probe and jig capacitance. 3. All diodes are 1S2074(H).

Rev.3.00, Jul.22.2005, page 5 of 7 Waveforms 1 tw(H) tPHL VOH VOL 0 V 3 V 0 V 3 V VOH VOL tw(L) tPHL tPLH tPLH 10% 90% 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 10% 90% Clock D Q Q tTLH tTHL Note: Clock input pulse; t TLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax, tTLH = tTHL ≤ 2.5 ns Waveforms 2 Clear Preset Q Q VOH VOH VOL VOL 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V tTHL tTLH tw (clear) ≥ 25ns tw (preset) ≥ 25ns tTLH tTHL tPHL tPLH 10%10% 10% 10% 90% 90% 90% 90% 1.3V 1.3V tPLH tPHL Note: Crear and presel input pulse; t TLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz,

Rev.3.00, Jul.22.2005, page 6 of 7 Package Dimensions ( Ni/Pd/Au plating ) 7.62 DP-14AV RENESAS CodeJEITA Package Code Previous Code MaxNomMin Dimension in Millimeters Symbol Reference 19.2 6.3 5.06 MASS[Typ.] A Z b D E A b c θ e L p e 0.51 0.56 1.30 0.19 0.25 0.31 2.29 2.54 2.79 0° 15° PRDP0014AB-BP-DIP14-6.3x19.2-2.54 20.32 7.4 0.40 0.48 2.39 2.54 0.97g 814 p b D E e Z b LA A c e θ 1.42 0.15 1.27 7.50 8.00 0.400.34p A 1 10.5 FP-14DAV RENESAS CodeJEITA Package Code Previous Code MaxNomMin Dimension in Millimeters Symbol Reference 2.20 0.900.700.50 5.50 0.200.100.00 0.46 0.250.200.15 7.80 8°0° 0.12 1.15 10.06 0.23g MASS[Typ.] E L Z H y x θ c b A E D b c e L A P-SOP14-5.5x10.06-1.27 PRSP0014DF-B Index mark E 14 8 F p Mx y D E H Z b A p Terminal cross section ( Ni/Pd/Au plating ) b c Detail F L A θ NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. e

Rev.3.00, Jul.22.2005, page 7 of 7 14 8 F*1 p Mx y E Index mark b A Z H E D Terminal cross section ( Ni/Pd/Au plating ) pb c Detail F L L A θ PRSP0014DE-AP-SOP14-3.95x8.65-1.27 A L e e c b D E A b c θ x y H Z L E MASS[Typ.] 0.13g 8.65 1.08 0.25 0° 8° 6.10 0.15 0.20 0.25 0.46 0.10 0.14 0.25 3.95 0.40 0.60 1.27 1.75 Reference Symbol Dimension in Millimeters Min Nom Max Previous CodeJEITA Package Code RENESAS Code FP-14DNV 9.05 p 0.34 0.40 6.205.80 1.27 0.15 0.635 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.

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