WMS7202 WINBOND | Alldatasheet

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Publication Release Date: January 2003 - 1 - Revision 1.1 WMS7202 256-TAP DUAL-CHANNEL NON-VOLATILE DIGITAL POTENTIOMETER

  • 2 - 1. GENERAL DESCRIPTION The WMS7202 is a 256-tap, dual-channel non-volat ile digital potentiometer available in 10K Ω, 50KΩ and 100KΩ end-to-end resistances. These devices can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications. The output of each potentiometer is determined by t he wiper position, which varies linearly between VA and VB terminal according to the content stored in the volatile Tap Register (TR). The settings of the TR can be provided either dire ctly by the user through the indus try standard SPI interface, or by the non-volatile memory (NVMEM0~3) where the previous settings are stored. When changes are made to the TR to establish a new wiper position, the value of the setting can be saved into any non- volatile memory location (NVMEM0~3) by execut ing a NVMEM save operation. Each channel has its own four non-volatile memory locations (NVMEM0~ 3) that can be directly written to, and read by, users through the SPI interface. Upon powerup the c ontent of the NVMEM0 is automatically loaded to the Tap Register. The WMS7202 contains two independent channels in 14-pin PDIP, SOIC and TSSOP packages and can operate over a wide operating voltage range from 2. 7V to 5.5V. A selectable output buffer is built- in for each channel for those applications where an output buffer is required. 2. FEATURES
  • 256 taps for each potentiometer
  • Dual independent, linear-taper channels in one package
  • End-to-end resistance available in 10K Ω, 50KΩ and 100KΩ
  • Selectable output buffer for each channel
  • SPI Serial Interface for data transfer and potentiometer control
  • Daisy-chain operation for multiple devices
  • Nonvolatile storage of four wiper positions per channel with power-on recall from NVMEM0
  • Low standby current (1 µA Max. with output buffer inactive)
  • Endurance 100K typical stores per bit
  • Register Data Retention 100 years
  • Industrial temperature range: -40 ~ 85 °C
  • Wide operating voltage range: 2.7V ~ 5.5V
  • Package option: ƒ 14-pin TSSOP, 14-pin SOIC, 14-pin PDIP

Publication Release Date: January 2003 - 3 - Revision 1.1 3. BLOCK DIAGRAM Serial Interface Ta p Re gi st er De co de r NV Memory Control SDI CLK VSS VA1 VB1 VW1 Ta p Re gi st er De co de r VA2 VB2 VW2 WP SDO R/B CS VDD NVMEM0 (Non-volatile Memory 0; Power - on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) NVMEM0 (Non-volatile Memory 0; Power- on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) MUX MUX Serial Interface Tap Register Decoder NV Memory Control SDI VSS VA1 VB1 VW1 Tap Register Decoder VA2 VB2 VW2 WP SDO CS VDD VDD NVMEM0 (Non-volatile Memory 0; Power - on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) NVMEM0 (Non-volatile Memory 0; Power - on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) NVMEM0 (Non-volatile Memory 0; Power- on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) NVMEM0 (Non-volatile Memory 0; Power- on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) MUX MUX

  • 4 - 4. TABLE OF CONTENTS

Publication Release Date: January 2003 - 5 - Revision 1.1 5. PIN CONFIGURATION 5 10 CS CLK SDI WP VSS R/B VA2 VDD SDO VA1 VW1 VB1 VB2 VW2 14 13 12 11 9 8 12 3 4 6 75

14 PDIP 14 SOIC 14 TSSOP

V SS R/B VA2

  • 6 - 6. PIN DESCRIPTION TABLE 1 – PIN DESCRIPTION PIN NAME PIN NO I/O DESCRIPTION CLK 2 I Serial Clock pin. Data Shifts in one bit at a time on positive clock (CLK) edges CS 1 I Chip Select pin. When CS is HIGH, WMS7202 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables WMS7202, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. SDI I Serial Data Input pin. All opcodes, byte addresses and data to be written to the registers are input on this pin. Data is latched by the rising edge of the serial clock. SDO O Serial Data Output pin with open-drain output. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock except for the 1st bit , which is clocked out by the falling edge of CS. Also can be used to daisy-chain several parts. R/B O Ready signal with active-LOW, open-drain output, and acknowledges the completion of commands 2, 4, 5, 6, and 7. WP 4 I Hardware Write Protect pin. When active LOW WP prevents any changes to the present contents except retrieving NVMEM contents. VDD 14 - Power Supply VSS 5 - Ground pin, logic ground reference VA1 12 - A terminal of potentiometer ‘1’, equivalent to the HI terminal connection on a mechanical potentiometer VB1 10 - B terminal of potentiometer ‘1’, equivalent to the LO terminal connection on a mechanical potentiometer VW1 11 O Wiper terminal of potentiometer ‘1’, equivalent to the wiper terminal of a mechanical potentiometer VA2 - A terminal of potentiometer ‘2’, equivalent to the HI terminal connection on a mechanical potentiometer. VB2 - B terminal of potentiometer ‘2’, equivalent to the LO terminal connection on a mechanical potentiometer. VW2 O Wiper terminal of potentiometer ‘2’, equivalent to the wiper terminal of a mechanical potentiometer.

Publication Release Date: January 2003 - 7 - Revision 1.1 7. FUNCTIONAL DESCRIPTION The WMS7202 series, a family of 256-tap, nonvolat ile digitally programmable potentiometers is designed to operate as both a potentiometer or a variable resistor depending upon the output configuration selected. The chip can store four 9-bit words in nonvolatile memory (NVMEM0 ~ NVMEM3) and the word stored in the NVMEM0 will be used to set the tap register values when the device is powered up. The WMS7202 is controlled by a serial SPI interface t hat allows setting tap register values as well as storing data in the nonvolatile memory. 7.1. POTENTIOMETER AND RHEOSTAT MODES The WMS7202 can operate as either a rheostat or as a potentiometer (voltage divider). When in the potentiometer configuration there are two possibl e modes. One is without the output buffer and the other mode is with the output buffer. Selecting the mode is done by controlling bit D8 of the data register. D8 = 0 sets the output buffer off and D8 = 1 sets it on. Each channel can be independently set to either buffer On or Off. Note that this bit can only be set by loading the value to the NVMEM with instructions #5 and then loading the TAP register with instruction #6 from NVMEM. This bit cannot be controlled by directly writing the value to the chip when the tap register is set. 7.1.1. Rheostat Configuration The WMS7202 acts as a two terminal resistive element in the rheostat configuration where one terminal is either one of the end point pins of t he resistor (VA and VB) and the other terminal is the wiper (VW) pin. This configur ation controls the resistance between the two terminals and the resistance can be adjusted by sending the corre sponding tap register setting commands to the WMS7202 or loading a pre-set tap register value from nonvolatile memory NVMEM0 ~ MVMEM3. 7.1.2. Potentiometer Configuration In potentiometer configuration an input voltage is connected to one of the end point pins (VA or VB). The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the wiper setting. The resistance cannot be directly measured in this configuration. 7.2. P ROGRAMMING MODES Two program modes are available for the WMS7202:

  • Direct program mode . The tap register setting can be changed either by loading a predetermined value from an external microcont roller or by using the UP/DOWN commands. The UP and DOWN commands change the tap regist er setting incrementally i.e., 1 LSB at a time. The UP and DOWN commands will not wrap around at the ends of the scale.
  • NVMEM restore mode . One of the previously stored settings can be loaded into the TR register from the non-volatile memory. Four 9-bit non-volatile memories, are available for each channel to store tap register settings. The firs t register, NVMEM0, stores the favorite or default tap register setting that will be loaded into the tap register at system power up or software power on reset operation.
  • 8 - 7.3. NON-VOLATILE MEMORY (NVMEM) Each channel has four NVMEM positions availabl e for storing the output buffer operating mode and the potentiometer setting. These NVMEM positions can be directly written through the SPI using a write command (#5) with address and data bytes. Anot her command (#7) is available that stores the current output buffer operating mode and potentiomete r settings into the selected NVMEM position. Bit A3 and A2 in the instruction byte decide which NVMEM position is used. (See Table 5) All potentiometers are loaded with the value stored in the NVMEM position 0 for their respective channel on power up.

7.3.1 Write Protect of NVMEM

Write-protect ( WP ) disables any changes of current cont ent in the NVMEM regardless of the commands, except that NVMEM setting can be re trieved using commands 4, 6 of Table 5 . Therefore, Write-Protect ( WP ) pin provides hardware NVME M protection feature with WP tied to Vss. WP , which is active at logic LOW, should be tied directly to VDD if it is not being used.

7.4 FLOW CONTROL

Reading and writing to NVMEM requires an internal access cycle to complete before the next command can be sent. The following commands have additional flow control using the R/B pin. Read Tap Register (#2) Read NVMEM (#4) Program NVMEM (#5) Load Tap Register(#6) Program NVMEM with Tap Register (#7) The R/B bit will be pulled HIGH when CS goes LOW, and will stay HIGH indicating the chip is ready to accept another command. After sending one of those commands, the R/B pin should be polled to determine when the device is ready to accept the additional data. This flow control can be used on all commands wi thout any performance penalty although it is only needed on the commands listed above.

  • 10 - 7.6. SERIAL DATA INTERFACE The WMS7202 contains a four-wire SPI interface:
  • SDO (Serial Data Output) Used for reading out t he internal register contents and for daisy chaining multiple devices.
  • SDI (Serial Data Input) Used for clocking in commands and potentiometer settings.
  • CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled HIGH to signal the end of the command. This pi n can be used to control multiple devices on the bus.
  • CLK (Clock) The SDI bits are shifted in on the rising edge of the clock and SDO data is shifted out on the falling edge of the clock. The key features of this interface include:
  • Independently programmable Read & Write to all registers
  • Direct parallel refresh of all Tap registers from corresponding internal NVMEM registers
  • Increment and decrement instruction for each Tap register
  • Nonvolatile storage of the present Tap register values into one of the four NVMEM registers available to each channel
  • Configurable output buffer amplifier to allo w both the functions of a potentiometer and a variable resistor
  • Four 9-bit non-volatile registers store four preset wiper positions and the first one will be recalled to set the wiper position during power up. The serial interface uses an SPI compatible uniform 24-bit word format as shown below. This format is used for all members of the WMS720x family. The data is sent MSB first. TABLE 2 – 24-BIT DATA WORD FORMAT M S B L S B C3 C2 C1 C0 A3 A2 A1 A0 X X X X X X X D8 D7 D6 D5 D4 D3 D2 D1 D0 C3-C0 are the command bits that control the operati on of the digital potentiometer according to the command instructions shown in the Instruction Set in Table 5 in Section 7.7. A1 and A0 are the address bits that determine whic h channel is activated, as shown in the table below. For the WMS7202 only the first two codes are used.

Publication Release Date: January 2003 - 11 - Revision 1.1 TABLE 3 – A1 AND A0 ADDRESS BIT DECODE TABLE Channel 0 1 2 3 A3 and A2 are the address bits that decide which NVMEM memory to be accessed, as shown in the table below. TABLE 4 – A3 AND A2 ADDRESS BIT DECODE TABLE NVMEM 0 1 2 3 D7-D0 are the data values to be loaded into the Tap R egister to set the wiper position, while D8 is used to set the output mode. D8 has to be loaded into the NVMEM0~3 first and then the “ Load Tap Register” command (#6) has be executed to load D8 into the output-selection MUX to set the output mode. D8=0 sets the output to Buffer Off mode while D8=1 sets to Buffer On mode. FIGURE 5 – SPI COMMAND WAVEFORMS CS CS is taken LOW before command starts CS is taken HIGH after command is sent R/B Note:

  • A multiple of 24 bits must always be sent or the command will not be valid
  • Bits marked ‘x’ are don’t care bits. R/B goes LOW at completion of commands 2, 4, 5, 6 and 7 to allow NVMEM to program for T SV. For other commands, R/B stays HIGH after command is sent. SDO SDI must be valid on the rising edge of the clock SDO is valid on the falling edge of the clock o r CS C2 C1 C0 A3 A2 A1 A0 x x x x x x x D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1

4 CLK

  • 12 - 7.7. INSTRUCTION SET TABLE 5 – INSTRUCTION SET Inst No. Instruction Byte C3 C2 C1 C0 A3 A2 A1 Data Byte 1 D15 D14 D13 D12 D11 D10 D9 D8 Data Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Operation 1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x No Operation (NOP). Do nothing 2 1 1 0 0 x x A1 A0 x x x x x x x x x x x x x x x x Read Tap Register and output selection MUX register 3 0 1 0 0 x x A 1 A 0 x x x x x x x x D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Write to Tap Register with D7-D0 4 1 0 1 0 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Read NVMEM pointed to by A3-A0 5 0 0 1 0 A 3 A 2 A 1 A 0 x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 Program NVMEM pointed to by A3-A0 with D8-D0 6 1 0 1 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Load Tap Register and output selection MUX register with the contents of NVMEM pointed to by A3-A0 7 0 0 1 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Program NVMEM pointed to by A3-A0 with the contents of Tap Register and output selection MUX register 8 0 1 1 1 x x A1 A0 x x x x x x x x x x x x x x x x Up: Increment setting of TR by one tap 9 1 1 1 1 x x A1 A0 x x x x x x x x x x x x x x x x Down: Decrement setting of TR by one tap 10 1 0 0 0 x x x x x x x x x x x x x x x x x x x x Sleep: Discontinue clock supply to the logic and memories 11 0 0 0 1 x x x x x x x x x x x x x x x x x x x x Wake Up: Clock supply to the logic and memories 12 1 1 0 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Byte-erase NVMEM pointed to by A3-A0 13 1 0 0 1 x x x x x x x x x x x x x x x x x x x x Power On Reset: Software reset the part to the power up state Note: C3-C0 are the command op-code; A3, A2 are the NVMEM address; A1, A0 are the channel address. 7.8. BASIC OPERATION This chapter describes the sequences of comm ands to send to the WMS7202 and how to use the different features.

7.8.1 Sending a Command

  1. Take the chip out of SLEEP mode. 2. Check that the write protect is set correctly if writing to NVMEM. 3. Check that R/B is HI GH before issuing command. 4. Pull the CS pin LOW before sending data to the device.

Publication Release Date: January 2003 - 13 - Revision 1.1 5. 24 clock pulses are sent for each command. SD I must be valid on the rising edge of the clock, SDO is valid on the falling edge of the clock or CS . 6. Take CS HIGH after the command has completed. 7. If command 2, 4, 5, 6 or 7 is sent, wait for the R/B pin to go HIGH before sending the next command.

7.8.2 Wake Up/Sleep/Power Commands

The chip is in SLEEP mode after:

  • VDD is applied
  • A Power on Reset command is sent
  • A SLEEP command is sent Before any operations can be performed the WAKE UP command must be sent. When a SLEEP command is sent, the chip retains its re sistor settings as long as the chip is powered up but cannot accept any other commands than a WAKE UP command. TABLE 6 – POWER RELATED COMMANDS Inst. No. Command Name: Command Byte Data Byte 1 Data Byte 2 Comment

11 Wake Up 0 0 0 1 x x x x x x x x x x x x x x x x x x x x Wake Up entire chip

10 Sleep 1 0 0 0 x x x x x x x x x x x x x x x x x x x x Send chip into power

13 Power on Reset 1 0 0 1 x x x x x x x x x x x x x x x x x x x x Reset Chip

1 NOP 0 0 0 0 x x x x x x x x x x x x x x x x x x x x Dummy instruction

The commands above control the entire chip. T here is no way to independently power on or off individual potentiometers.

7.8.3 Write to Tap Register (TR)

The microcontroller can write a value directly into the tap register or send an increment or decrement command to control the tap register. Alternatively, the contents of an NVME M location can be written to the tap register. The only way to change the output buffer mode is to write the desired value of bit D8 into an NVMEM location and then load the corresponding NVMEM location into the tap register.

  • 14 - TABLE 7 – WRITING TO THE TAP REGISTERS Inst. No. Comman d Name: Command Byte Data Byte 1 Data Byte 2 Comment

3 Write to

0 1 0 0 x x A1 A0 x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 Writes a value to the tap register of the selected channel

8 Up 0 1 1 1 x x A1 A0 x x x x x x x x x x x x x x x x Increment tap

9 Down 1 1 1 1 x x A1 A0 x x x x x x x x x x x x x x x x Decrement tap

6 Load Tap

1 0 1 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Load the selected NVMEM location into the tap register

7.8.4 Programming Non-Volatile Memory (NVMEM)

The value stored in the NVMEM location is 9 bits, the 8 bits (D7-D0) of the tap register plus 1 bit (D8) of the output buffer mode. The NV MEM position must be erased before writing to it. There are two ways to program a value into NVMEM. Write a value directly from the microcontroller Load the current potentiometer setting into NVMEM. TABLE 8 – PROGRAMMING NVMEM Inst. No Command Name Command Byte Data Byte 1 Data Byte 2 Comment

12 Erase

1 1 0 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Erases the 9 bit word pointed to by A3, A2, A1 and A0.

5 Program

0 0 1 0 A3 A2 A1 A0 x x x x x x x D8 D7 D6 D5 D4 D3 D2 D1 D0 Writes a value to the selected NVMEM register of the selected channel

7 Program

0 0 1 1 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Takes the current potentiometer settings and saves in the selected NVMEM location. For programming NVMEM, the following sequence must be followed: 1. Erase word at NVMEM location 2. Program word at NVMEM location

Publication Release Date: January 2003 - 15 - Revision 1.1

7.8.5 Reading Tap Registers and NVMEM Locations

The contents of the tap register for any channel or any NVMEM location can be read back through the SDO pin. When a command is sent, the data is cl ocked out on the falling edge of the clock. Since daisy-chain operation requires data from one co mmand to be clocked out when the next command arrives, any read command must be followed by another command to get the correct data on the SDO pin. TABLE 9 – READING THE TAP REGISTERS Inst. No. Command Name: Command Byte Data Byte 1 Data Byte 2 Comment

4 Read

1 0 1 0 A3 A2 A1 A0 x x x x x x x x x x x x x x x x Read the value of the selected NVMEM location

2 Read Tap

1 1 0 0 x x A1 A0 x x x x x x x x x x x x x x x x Read the value of the selected tap register

1 NOP to

0 0 0 0 x x x x x x x x x x x D8 D7 D6 D5 D4 D3 D2 D1 D0 Output data to SDO pin To read the contents of either t he tap register or a NVMEM loca tion, the following sequence must be followed. 1. Send the desired read command (#2 or #4) to select the register to read 2. Send another command such as NOP and read t he SDO pin on the falling edge of the clock. The other command could be any command, but to make sure that the chip does not change anything, send either another Read command or a NOP command (#1).

  • 16 - 8. TIMING DIAGRAMS FIGURE 6 – WMS7202 TIMING DIAGRAM tLEAD tCYC tWL tWH tLAG tCS tDH tDSU tLAC tPD tLRL tRSU tST tSV CLK CS SDI SDO R/B tWPSU tWPH WP MSB LSB MSB LSB

Publication Release Date: January 2003 - 17 - Revision 1.1 TABLE 10 – TIMING PARAMETERS Note: The interface timing characteristics apply to all parts but are guaranteed by design and not subject to production test. PARAMETER SYMBOL MIN. MAX. UNIT SPI Clock Cycle Time t CYC 100 ns SPI Clock HIGH Time t WH 50 ns SPI Clock LOW Time t WL 50 ns Lead Time t LEAD 100 ns Lag Time t LAG 100 ns SDI Setup Time t DSU 20 ns SDI Hold Time t DH 20 ns CS to SDO – SPI Line Acquire tLAC 5 ns CS to SDO – SPI Line Release tLRL 5 ns CLK to SDO Propagation Delay t PD 1 ns R/B Rise to CS Fall tRSU 500 ns Store to NVMEM Save Time t SV 2 ms CS Deselect Time tCS 600 ns Startup Time t ST 0.1 ms WP Setup Time tWPSU 10 ns WP Hold Time tWPH 10 ns

  • 18 - 9. ABSOLUTE MAXIMUM RATINGS TABLE 11 – ABSOLUTE MAXIMUM RATINGS Condition Value Junction temperature 150ºC Storage temperature -65º to +150ºC Voltage applied to any pad (V ss – 0.3V) to (VDD + 0.3V) Vdd - Vss -0.3 to 7.0V Note: Exposure to conditions beyond those listed under: Absolute Maximum Ratings, may adversely affect the life and reliability of the device.

Publication Release Date: January 2003 - 19 - Revision 1.1 10. ELECTRICAL CHARACTERISTICS TABLE 12 – ELECTRICAL CHARACTERISTICS All Parameters apply across specified operating ranges unless noted (VDD: 2.7V~5.5V; Temp: –40°C~85°C) Typical values: VDD=5V and T=25°C PARAMETER SYMBOL MIN. TYP MAX. UNITS CONDITIONS Rheostat Mode Nominal Resistance R -20 +20 % T=25ºC, V W open Different Non Linearity DNL -1 0.3 +1 LSB Integral Non Linearity INL -1 0.5 +1 LSB Rheostat Tempco1 ∆RAB/∆T 500 ppm/° C Wiper Resistance2 RW 50 100 Ω VDD=5V, I=VDD/RTotal 80 120 Ω VDD=2.7V, I=VDD/RTotal Potentiometer Mode Resolution1 N 8 Bits Different Non Linearity2 DNL -1 +1 LSB Integral Non Linearity2 INL -1 +1 LSB Potentiometer Tempco1 ∆Vw/∆T +20 ppm/° C Code = 80h Full Scale Error V FSE -1 0 LSB Code = Full Scale Zero Scale Error V ZSE 0 1 LSB Code = Zero Scale Resistor Terminal Voltage Range1 VA,VB,VW V SS V DD V Terminal Capacitance1 CA, CB 30 pF Wiper Capacitance1 30 pF Dynamic Characteristics1 BW 10K 1.5 MHz V DD=5V, VB=VSS Code = Full Scale Bandwidth –3dB BW 50K 300 KHz Code = 80h BW 100K 200 KHz CL=30pf Settling Time to 1 LSB T S 80 100 uS V DD=5.5V=VA, VB=VSS Analog Output (Buffer enabled) Amp Output Current2 IOUT 3 mA V O=1/2 scale Amp Output Resistance2 Rout 1 10 Ω Total Harmonic Distortion1 THD 0.08 % VA=2.5V, VDD=5V, f=1kHz, VIN=1VRMS Digital Inputs/Outputs Input High Voltage V IH 0.7V DD V Input Low Voltage V IL 0.3V DD V Output Low Voltage V OL 0.4 V I OL=2mA Input Leakage Current I LI -1 +1 uA CS =VDD,Vin=Vss

  • 20 - ~ VDD Output Leakage Current I Lo -1 +1 uA CS =VDD,Vin=VSS ~ VDD Input Capacitance1 CIN 25 pF VDD=5V, fc = 1Mhz Code = 80h Output Capacitance1 COUT 25 pF VDD=5V, fc = 1Mhz Code = 80h Power Requirements Operating Voltage1 VDD 2.7 5.5 V Operating Current I DDR 1 1.8 mA All ops except NVMEM program Operating Current I DDW 1 2 mA During Non- volatile memory program ISA 0.5 1 mA Buffer is active, , no load Standby Current ISB 2 0.1 1 uA Buffer is inactive, Power Down, No load Power Supply Rejection Ratio PSRR 1 LSB/V VDD=5V±10%, Code=80h noted.

Publication Release Date: January 2003 - 21 - Revision 1.1

10.1 TEST CIRCUITS

FIGURE 7 – TEST CIRCUITS Potentiometer divider nonlinearity error test circuit (INL, DNL) *Assume infinite input impedance V + VMS* V+ = VDD 1LSB= V+/255 WMS7202 VA VB VW Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) *Assume infinite input impedance No Connection V MS * WMS7202 WVA VB VW IW WMS7202 Wiper resistance test circuit *Assume infinite input impedance V MS* WMS7202 VA VB VW IW I W = V DD /R Total R W = V MS /I W Power supply sensitivity test circuit (PSS, PSRR) *Assume infinite input impedance V+ = V DD ± 10% VA VB VW VMS* PSRR(dB) = 20LOG ( ) ∆ VMS ∆ VDD PSS(%/% ) = ∆ V MS ∆ V DD WMS7202 VA VB VW VIN~ +5V 2.5V DC Offset V OUT Capacitance test circuit VA VB WMS7202 VW VIN ~ +5V 2.5V DC VOUT OFFSET GND Gain vs. frequency test circuit

  • 24 - FIGURE 12 – PROGRAMMABLE LOW-PASS FILTER SDI Vout CLK CONTROL Vin CS\\ SDO13 PROGRAMMABLE LOW-PASS FILTER R/B\\ 1/2 WMS7202 1/2 WMS7202 WP\\ VDD

Publication Release Date: January 2003 - 25 - Revision 1.1 11.1. LAYOUT CONSIDERATIONS A 0.1µF bypass capacitor as close as possible to the V DD pin is recommended for best performance. Often this can be done by placing the surface mount capacitor on the bottom side of the PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces. Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals. FIGURE 13 – WMS7202 LAYOUT

  • 26 - 12. PACKAGE DRAWINGS AND DEMINSIONS DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. NOM MAX. MIN. NOM MAX. A1 0.381 0.015 c 0.25 0.010 e1 2.54BSC 0.1 BSC. L 2.2921 0.115 FIGURE 14 – 14L PDIP – 300MIL L B B1 D E eA BASE PLANE SEATING PLANE 14 8 1 7

Publication Release Date: January 2003 - 27 - Revision 1.1 DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. MAX. MIN. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 E 3.80 4.00 0.150 0.157 D 8.55 8.75 0.337 0.344 e 1.27 BSC. 0.050 BSC. HE 5.80 6.20 0.228 0.244 Y 0.10 0.004 L 0.40 1.27 0.016 0.050 0 0 8 0 8 FIGURE 15 – 14L SOIC – 150MIL SEATING PLANE L O c 0.25 GAUGE PLANE E H E 1 8 A e b D Y

  • 28 - DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. NOM MAX MIN NOM MAX A 1.20 0.043 A1 0.05 0.15 0.002 0.006 E 6.40 BSC 0.252 BSC b 0.19 0.30 0.007 0.012 Y 0.076 0.006 e 0.65 BSC 0.026 BSC e1 0 8 0 8 FIGURE 16 – 14L TSSOP – 4.4MM A AA SEATING PLANE Y D E b e

Publication Release Date: January 2003 - 29 - Revision 1.1 13. ORDERING INFORMATION Winbond’s WinPot Part Number Description: For the latest product information, access Winbond’s worldwide website at http://www.winbond-usa.com WMS72 XX XXX X Winbond WinPot Products Features:

  • 01: Single channel with SPI Interface
  • 02: Dual channels with SPI Interface
  • 04: Quad channels with SPI Interface End-to-end Resistance:
  • 010: 10KΩ
  • 050: 50KΩ
  • 100: 100KΩ Package Index:
  • T: TSSOP
  • S: SOIC
  • P: PDIP
  • 30 - 14. VERSION HISTORY VERSION DATE PAGE DESCRIPTION

1.0 June 2002 All Initial issue

1.1 Jan. 2003 Correct typos, add Inst No. to tables, add values to Specification Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai, Science-Based Industrial Park, CA 95134, U.S.A. 200336 China Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999 TEL: 886-3-5770066 FAX: 1-408-5441797 FAX: 86-21-62356998 FAX: 886-3-5665577 http:// www.winbond-usa.com/ http://www.winbond.com.tw/ Taipei Office Winbond Electronics Corporat ion Japan Winbond Electronics (H.K.) Ltd. 9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG. 3-7-18 Unit 9-15, 22F, Millennium City, Neihu District Shinyokohama Kohokuku, No. 378 Kwun Tong Rd., Taipei, 114 Taiwan Yokohama, 222-0033 Kowloon, Hong Kong TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100 FAX: 886-2-87153579 FAX: 81-45-4781800 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. This product incorporates SuperFlash® technology licensed From SST The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy o r completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and produc t descriptions at any time wit hout notice. No license, whethe r express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Wi nbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, author ized or warranted for use as components in systems or equipments intended for surgical impl antation, atomic energy control instruments, airplane or spaceship instruments, transportati on instruments, traffi c signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further, Winbond products are not intended for app lications wherein failure of Winbond products could result or lead to a situation wherei n personal injury, death or severe property o r environmental injury could occur.