27C4096

W27C4096 WINBOND | Alldatasheet

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Technical content

256K × 16 ELECTRICALLY ERASABLE EPROM Publication Release Date: March 1999 - 1 - Revision A1 GENERAL DESCRIPTION The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 16 bits that operates on a single 5 volt power supply. The W27C4096 provides an electrical chip erase function.

FEATURES

• High speed access time: 120/150 nS (max.)
• Read operating current: 30 mA (max.)
• Erase/Programming operating current 30 mA (max.)
• Standby current: 100 µA (max.)
• Single 5V power supply
• +14V erase/+12V programming voltage
• Fully static operation
• All inputs and outp uts directly TTL/CMOS compatible
• Three-state outputs
• Available packages: 40-pin 600 mil DIP, TSOP and 44-pin PLCC PIN CONFIGURATIONS 40-pin DIP Q15 Q14 Q13 Q12 CE GND GND A15 A14 A13 A12 A11 A10 A17 A16 V DD Q11 Q10 OE V PP 232221201918 44-pin PLCC 456 44123 40414243 A13 A12 A11 A10 GND NC Q11 Q10 Q12 GND NC Q4 2827262524 Q Q Q Q O E N C A A A A A C E N C Q Q Q V p p A V C C A A A OE 40-pin TSOP A15 V A13 A12 A11 CC A10 A17 A16 A14 V PP CE Q15 Q14 Q13 Q12 Q11 Q10 GND BLOCK DIAGRAM CE OE Q15 A17 V GND CC V PP CONTROL DECODER CORE ARRAY OUTPUT BUFFER PIN DESCRIPTION SYMBOL DESCRIPTION A0 −A17 Address Inputs Q0 −Q15 Data Inputs/Outputs CE Chip Enable OE Output Enable V PP Program/Erase Supply Voltage V CC Power Supply GND Ground NC No Connection

• 2 - FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C4096 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (T ACC ) is equal to the delay from CE to output (T CE ), and data are available at the outputs T OE after the falling edge of OE , if T ACC and T CE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C4096 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when V PP is raised to V PE (14V), V CC = V CE (5V), CE low, OE high, A9 = V PE (14V), A0 low , and all other address pins low and data input pins high. Erase Verify Mode After an erase operation, all of the words in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if V PP = V PE (14V), CE high, and OE low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when V PP is raised to V PP (12V), V CC = V CP (5V), CE low , OE high, the address pins equal the desired address, and the input pins equal the desired inputs. Program Verify Mode All of the words in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each word is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if V PP = V PP (12V), CE high, OE low and V CC = V CP (5V). Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , V PP = V PP /V PE (12V/14V), and V CC = 5V, erasing or programming of non- target chips is inhibited, so that except for the CE and V PP , and V CC , the W27C4096 may have common inputs.

Publication Release Date: March 1999 - 3 - Revision A1 Standby Mode The standby mode significantly reduces V CC current. This mode is entered when CE high , V PP = 5V, and V CC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE . Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C4096 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (I SB ), active current levels (I CC ), and transient current peaks produced by the falling and rising edges of CE . Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its V CC and GND. This high frequency, low inherent- inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES (V PP = 12V, V PE = 14V, V HH = 12V, V CP = 5V, X = V IH or V IL ) MODE PINS CE OE A0 A9 VCC VPP OUTPUTS Read V IL V IL X X V CC V CC D OUT Output Disable V IL V IH X X V CC V CC High Z Standby (TTL) V IH X X X V CC V CC High Z Standby (CMOS) V CC ±0.3V X X X V CC V CC High Z Program V IL V IH X X V CP V PP D IN Program Verify V IH V IL X X V CP V PP D OUT Program Inhibit V IH X X X V CP V PP High Z Erase V IL V IH V IL V PE V CE V PE D IH Erase Verify V IH V IL X X V CE V PE D OUT Erase Inhibit V IH X X X V CE V PE High Z Product Identifier-manufacturer V IL V IL V IL V HH V CC V CC 00DA (Hex) Product Identifier-device V IL V IL V IH V HH V CC V CC 000D (Hex)

• 4 - DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Ambient Temperature with Power Applied -55 to +125 °C Storage Temperature -65 to +125 °C Voltage on all pins with Respect to Ground Except V PP, A9 and V CC pins -0.5 to V CC +0.5 V Voltage on V PP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Voltage on V CC Pin with Respect to Ground -0.5 to +7 V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current I LI V IN = V IL or V IH -10 - 10 µA V CC Erase Current I CP CE = V IL - - 30 mA V PP Erase Current I PP CE = V IL - - 30 mA Input Low Voltage V IL - -0.3 - 0.8 V Input High Voltage V IH - 2.4 - 5.5 V Output Low Voltage (Verify) V OL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) V OH IOH = -0.4 mA 2.4 - - - A9 Erase Voltage V ID - 13.75 14 14.25 V V PP Erase Voltage V PE - 13.75 14 14.25 V V CC Supply Voltage (Erase) V CE - 4.5 5.0 5.5 V Note: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP . CAPACITANCE (V CC = 5V, T A = 25 ° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT Input Capacitance C IN V IN = 0V 6 pF Output Capacitance C OUT V OUT = 0V 12 pF

Publication Release Date: March 1999 - 5 - Revision A1 AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 0.8V/2.0V Output Load C L = 100 pF, I OH /I OL = -0.4 mA/2.1 mA AC Test Load and Waveform +1.3V 3.3K ohm 100 pF (Including Jig and Scope) D (IN914) OUT Input 2.4V 0.45V 2.0V 0.8V 2.0V 0.8V Test Points Test Points Output

• 6 - READ OPERATION DC CHARACTERISTICS (V CC = 5.0V ±5%, T A = 0 to 50 ° C) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI V IN = 0V to V CC -5 - 5 µA Output Leakage Current ILO V OUT = 0V to V CC -10 - 10 µA V CC Standby Current ISB CE = V IH - - 1.0 mA ISB1 CE = V CC ±0.2V - 5 100 µA V CC Operating Current ICC CE = V IL IOUT = 0 mA, f = 5 MHz - - 30 mA V PP Operating Current IPP V PP = V CC - - 10 µA Input Low Voltage V IL - -0.3 - 0.8 V Input High Voltage V IH - 2.2 - V CC +0.5 V Output Low Voltage V OL IOL = 2.1 mA - - 0.4 V Output High Voltage V OH IOH = -0.4 mA 2.4 - - V V PP Operating Voltage V PP - V CC -0.7 - V CC V READ OPERATION AC CHARACTERISTICS (V CC = 5.0V ±5%, T A = 0 to 50 ° C) PARAMETER SYM. W27C4096-12 W27C4096-15 UNIT MIN. MAX. MIN. MAX. Read Cycle Time T RC 120 - 150 - nS Chip Enable Access Time T CE - 120 - 150 nS Address Access Time T ACC - 120 - 150 nS Output Enable Access Time T OE - 50 - 70 nS OE High to High-Z Output T DF - 30 - 30 nS Output Hold from Address Change T OH 0 - 0 - nS Note: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP .

Publication Release Date: March 1999 - 7 - Revision A1 DC PROGRAMMING CHARACTERISTICS PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current I LI V IN = V IL or V IH -10 - 10 µA V CC Program Current I CP CE = V IL - - 30 mA V PP Program Current I PP CE = V IL - - 30 mA Input Low Voltage V IL - -0.3 - 0.8 V Input High Voltage V IH - 2.4 - 5.5 V Output Low Voltage (Verify) V OL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) V OH IOH = -0.4 mA 2.4 - - V V PP Program Voltage V PP - 11.75 12.0 12.25 V V CC Supply Voltage (Program) V CP - 4.5 5.0 5.5 V AC PROGRAMMING/ERASE CHARACTERISTICS PARAMETER SYM. LIMITS UNIT MIN. TYP. MAX. V PP Setup Time T VPS 2.0 - - µS Address Setup Time T AS 2.0 - - µS Data Setup Time T DS 2.0 - - µS CE Program Pulse Width T PWP 95 100 105 µS CE Erase Pulse Width T PWE 95 100 105 mS Data Hold Time T DH 2.0 - - µS OE Setup Time T OES 2.0 - - µS Data Valid from OE T OEV - - 150 nS OE High to Output High Z T DFP 0 - 130 nS Address Hold Time T AH 0 - - µS Address Hold Time after CE High (Erase) T AHC 2.0 - - µS Note: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP .

• 8 - TIMING WAVEFORMS AC Read Waveform CE Outputs T High Z High Z Valid Output CE T OE T ACC T OH T DF Address Address Valid V IL V IH V IH V IL V IH V IL OE Erase Waveform Address Read SID Device Read SID A9 = 12.0V Others = V IL A0 = V IL Data Chip Erase A9 = 14.0V Erase Verify Address Stable T ACC 00DA 000D Data All One 14.0V 5.0V A0= V IH Read Verify Blank Check Manufacturer Address Stable Address StableOthers = V IL Others = V IL T ACC T AS T ARC T DS T AHC T VPS T DFP D OUT D OUTD OUT T AH T ACC V IH V IL V PP CE OE T CE T OET OE T OES T OEV T OE V IH V IL V IH V IL T PWE

Publication Release Date: March 1999 - 9 - Revision A1 Timing Waveforms, continued Programming Waveform Address Data 12.0V 5.0V CE Address Stable Program Read Verify Address Stable Address Valid Verify Data In Stable Program D OUT T AH D OUTD OUT T DHT DS T VPS T ACC T DFPT AS V IH V IL V IH V IL V PP OE T OES T OEV T OE V IH V IL T PWP

• 10 - SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X = 0 Increment X X = 25? Verify One Word Last Address? Vcc = 5V Vpp = 5V Compare All Words to Original Data Pass Device Increment Address No Fail Yes Pass Fail Fail Fail Device Verify One Word Program One 100 S Pulse µ No Pass Yes Pass

Publication Release Date: March 1999 - 11 - Revision A1 SMART ERASE ALGORITHM Start Vcc = 5V Vpp = 14V Increment X Last Address? Vcc = 5V Vpp = 5V Compare All Words to FFFF (HEX) Pass Device Increment Address No Fail Fail Fail Device X = 0 A9 = 14V; A0 = V Chip Erase 100 mS Pulse Address = First Location Erase Verify X = 20? No Yes Pass Pass Yes IL

• 12 -

ORDERING INFORMATION

PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX. (m A) PACKAGE W27C4096-12 120 30 100 600 mil DIP W27C4096T-12 120 30 100 40-pin TSOP W27C4096P-12 120 30 100 44-pin PLCC W27C4096-15 150 30 100 600 mil DIP W27C4096T-15 150 30 100 40-pin TSOP W27C4096P-15 150 30 100 44-pin PLCC Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

Publication Release Date: March 1999 - 13 - Revision A1 PACKAGE DIMENSIONS 40-pin PDIP 1.371.220.0540.048 Notes: Dimension in inches Dimension in mm A B c D e A L S A A E 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 17.02 B 1 e E 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.29 0.6500.630 16.00 16.51 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 6. General appearance spec. should be based on final visual inspection spec. protrusion/intrusion. 4. Dimension B1 does not include dambar 5. Controlling dimension: Inches. 150 Seating Plane e A a c E Base Plane1A L A S D B 40 21 201 40-pin TSOP A A A L 1 Y c E H D D b eM 0.10(0.004) θ Dimension in mmDimension in Inches Min. Nom. Max. Symbol A D E e L L Y A H D Controlling dimension: Millimeters 0.05 18.3 9.90 19.8 0.50 0.00 18.4 20.0 0.50 0.60 0.8 1.20 0.15 18.5 10.10 20.2 0.70 0.10 0.047 0.006 0.72 0.724 0.728 0.390 0.394 0.398 0.780 0.787 0.795 0.020 0.020 0.024 0.028 0.031 0.000 0.004 0 3 5 0.002 Min. Nom. Max. θ

• 14 - Package Dimensions, continued 44-pin PLCC 44 40 2818 6 1 L c H D D e b E H E y A A 1 Seating Plane DG G E Notes: Dimension in inches Dimension in mm A b c D e H E L y A A E b 1 H D G G D E on final visual inspection spec. 4. General appearance spec. should be based 3. Controlling dimension: Inches protrusion/intrusion. 2. Dimension b1 does not include dambar 1. Dimension D & E do not include interlead flash. 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100

0.050 BSC

0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 BSC θ

Publication Release Date: March 1999 - 15 - Revision A1 VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 Mar. 1999 Initial Issued Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Note: All data and specifications are subject to change without notice.