83627F

W83627HG WINBOND | Alldatasheet

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Date： 2006/06/09 Revision： 2.27

Publication Release Date: June 09, 2006 - i - Revision 2.27 W83627HF/F, W83627HG/G Data Sheet Revision History VERSION DATE PAGE DESCRIPTION 0.50 09/25/98 n.a. Not released For internal use only 0.51 11/10/98 88-93,102,105, 139,151,153 First published. Explanation of H/W Monitor function andregister correction. 0.52 01/11/99 90-93;113-115 Pinout and register correction. 0.53 07/26/99 90,91,113-115, 119-123,133,136, 137,140,141 Typo and data correction. H/W Monitor register explanation. 1.0 11/14/00 All New composition. 2.0 11/01/02 All New composition. 2.1 03/07/03 90 Correct SUSLED mode register 2.2 04/09/03 1. P74 ~ P76 2. P3,P90,P111 3. P6~P7 1. Add Section 4.1 Plug and Pla Configuration. 2. Remove Phoenix MultiKey related. 3. Add Block Digram 2.21 02/03/04 121 Add the top marking of W83627HG and W83627G. 2.22 05/28/04 12,13,21,23,39,4 5,46,82,93,94,98 ~ 100 Typo and data correction. 2.23 07/07/04 20,24,84,100 Data correction. 2.24 10/28/04 48,79 Data correction. 2.25 11/02/04 98 Data correction. 2.26 01/11/05 24, 76,77,120 Add part No.to Section 13 Ordering Instruction and data correction. 2.27 06/09/06 8 ~ 11 Add pin conf iguration of W83627G & W83627HG

• ii - Table of Content-

Publication Release Date: June 09, 2006 - iii - Revision 2.27

Publication Release Date: June 09, 2006 - 1 - Revision 2.27 1. GENERAL DESCRIPTION The W83627HF and W83627F are evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC（Low Pin Count）interface, which will be supported in the next generation Intel chip-set. This interface as it s name suggests is to provide an economical imple- mentation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts ar e saved in LPC I/O comparing to ISA implemen- tation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83627F/HF's integration of Game Port and MIDI Port.It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. The disk drive adapter functions of W83627F/HF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, writ e pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface c ontrol logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627F/HF greatly reduces the number of components re- quired for interfacing with floppy disk drives . The W83627F/HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer ra tes of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83627F/HF provides two high-speed serial communication ports （UARTs）, one of which sup- ports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a program- mable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which s upport higher speed modems. In addition, the W83627F/HF provides IR functions： IrDA 1.0 （SIR for 1.152K bps）and TV remote IR （Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols）. The W83627F/HF supports one PC-compatible printer port （SPP ）, Bi-directional Printer port （BPP） and also Enhanced Parallel Port （EPP） and Extended Capabilities Port（ECP）. Through the printer port interface pins, also available are ： Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selecti on, function enable/disable, and power down function selection. Furthermore, the configurable PnP featur es are compatible with the plug-and-play feature demand of Windows 95/98TM, which makes system resource allocation more efficient than ever. The W83627F/HF provides functions that complies with ACPI （Advanced Configuration and Power Interface ）, which includes support of legac y and ACPI power management through PME# or PSOUT# function pins. For OnNow keyboard Wake -Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up. The W83627F/HF also has auto power management to reduce the power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firm ware are available with optional AMIKEY TM -2, Phoenix MultiKey/42TM, or customer code. The W83627F/HF provides a set of flexible I/O cont rol functions to the system designer through a set of General Purpose I/O ports. Thes e GPIO ports may serve as simple I/O or may be individually con- figured to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode（VCC is off）. The W83627F/HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. Moreover W83627F/HF is made to meet the specification of PC98/PC99's requirement in the power management： ACPI and DPM （Device Power Management）.

• 2 - The W83627F/HF contains a game port and a MIDI port. The game port is designed to support 2 joy- sticks and can be applied to all standard PC game control devices, They are very important for a en- tertainment or consumer computer. Only the W83627HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly.

Publication Release Date: June 09, 2006 - 3 - Revision 2.27 2. FEATURES General

• Meet LPC Spec. 1.0
• Support LDRQ# （LPC DMA）, SERIRQ （serial IRQ）
• Include all the features of Winbond I/O W83977TF and W83977EF
• Integrate Hardware Monitor functions
• Compliant with Microsoft PC98/PC99 Hardware Design Guide
• Support DPM （Device Power Management）, ACPI
• Programmable configuration settings
• Single 24 or 48 MHz clock input FDC
• Compatible with IBM PC AT disk drive systems
• Variable write pre-compensation with track selectable capability
• Support vertical recording format
• DMA enable logic
• 16-byte data FIFOs
• Support floppy disk drives and tape drives
• Detects all overrun and underrun conditions
• Built-in address mark detection circuit to simplify the read electronics
• FDD anti-virus functions with softwar e write protect and FDD write enable signal （write data signal was forced to be inactive）
• Support up to four 3.5-inch or 5.25-inch floppy disk drives
• Completely compatible with industry standard 82077
• 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
• Support 3-mode FDD, and its Win95/98 driver UART
• Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
• MIDI compatible
• Fully programmable serial-interface characteristics ： ─ 5, 6, 7 or 8-bit characters ─ Even, odd or no parity bit generation/detection ─ 1, 1.5 or 2 stop bits generation

• 4 -
• Internal diagnostic capabilities ： ─ Loop-back controls for communications link fault isolation ─ Break, parity, overrun, framing error simulation
• Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to （216-1）
• Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Infrared
• Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Parallel Port
• Compatible with IBM parallel port
• Support PS/2 compatible bi-directional parallel port
• Support Enhanced Parallel Port （EPP）− Compatible with IEEE 1284 specification
• Support Extended Capabilities Port （ECP）− Compatible with IEEE 1284 specification
• Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port
• Enhanced printer port back-drive current protection Keyboard Controller
• 8042 based with optional F/W from AMIKKEY TM-2,or customer code with 2K bytes of program- mable ROM, and 256 bytes of RAM
• Asynchronous Access to Two Data Registers and One status Register
• Software compatibility with the 8042
• Support PS/2 mouse
• Support port 92
• Support both interrupt and polling modes
• Fast Gate A20 and Hardware Keyboard Reset
• 8 Bit Timer/ Counter
• Support binary and BCD arithmetic
• 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency Game Port
• Support two separate Joysticks
• Support every Joystick two axis （X,Y） and two button （A,B） controllers

Publication Release Date: June 09, 2006 - 5 - Revision 2.27 MIDI Port

• The baud rate is 31.25 Kbaud
• 16-byte input FIFO
• 16-byte output FIFO General Purpose I/O Ports
• 22 programmable general purpose I/O ports
• General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watch dog timer output, power LED output, infrared I/O pi ns, KBC control I/O pins, suspend LED output, RSMRST# signal, PWROK signal, Beep output
• Functional in power down mode （GP1 only） OnNow Functions
• Keyboard Wake-Up by programmable keys
• Mouse Wake-Up by programmable buttons
• CIR Wake-Up by programmable keys
• On Now Wake-Up from all of the ACPI sleeping states （S1-S5） Hardware Monitor Functions （ Only for W83627HF）
• 5 VID input pins for CPU Vcore identification
• 3 thermal inputs from optionally remote t hermistors or 2N3904 transistors or PentiumTM II （Deschutes） thermal diode output
• 7 positive voltage inputs （typical for +12V, -12V, +5V, -5V, +3.3V, VcoreA, VcoreB）
• 2 intrinsic voltage monitoring （typical for Vbat, +5VSB）
• 3 fan speed monitoring inputs
• 2 fan speed control
• Build in Case open detection circuit
• WATCHDOG comparison of all monitored values
• Programmable hysteresis and setting points for all monitored items
• Over temperature indicate output
• Automatic Power On voltage detection Beep
• Issue SMI#, IRQ, OVT# to activate system protection
• Intel LDCM TM / Acer ADMTM compatible Package
• 128-pin PQFP

• 6 - 3. BLOCK DIAGRAM FOR W83627F LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface FDC URA, B PRT CIR Game Port MIDI KBC GPIO IR Floppy drive interface signals Serial port A, B interface signals Printer port interface signals IRRX IRTX ACPI CIRRX# Joystick interface signals General-purpose I/O pins MSI MSO Keyboard/Mouse data and clock

Publication Release Date: June 09, 2006 - 7 - Revision 2.27 4. BLOCK DIAGRAM FOR W83627HF LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface FDC URA, B PRTHM CIR Game Port MIDI KBC GPIO IR Floppy drive interface signals Serial port A, B interface signals Printer port interface signals IRRX IRTX ACPI CIRRX# Joystick interface signals General-purpose I/O pins MSI MSO Keyboard/Mouse data and clock Hardware monitor channel and Vref

• 8 - 5. PIN CONFIGURATION Pin configuration of W83627F and W83627G 12345 6 7 89 10 11 12 1 14 15 1 6 1 7 18 9 2 0 21 22 2 3 24 25 2 6 2 8 2 9 30 31 3 3 34 35 36 37 38 V B A T KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VCC GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 102 100 97 96 9 5 9 4 9 3 9 91 90 8 9 8 8 8 85 84 8 3 82 81 8 0 79 7 73 72 71 69 68 67 66 65 GPSB1/P13/GP11 VSS GPSA1/P12/GP10 G P G P I R R X G P I R T X G P R I B D C D B V S S S O U T B S I N B D T R B R T S B D S R B C T S B V C C W D T O G P S L P S X G P P L E D G P P W R C T L G P SUSLED/GP35 R S M R S T G P P W R O K G P C I R R X G P P S I N P S O U T M D A T M C L K S U S C L K I N A V C C A G N D P C I C L K L D R Q S E R I R Q L A D L A D L A D L A D V C C V L F R A M E V C C L R E S E T P M E C L K I N D R V D E N D R V D E N S M I G P I N D E X M O A D S B D S A V S S M O B D I R S T E P W D W E T R A K W P R D A T A H E A D D S K C H G S L C T P E B U S Y A C K P D P D P D P D W83627F MSI/GP20 MSO/IRQIN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC N C N C N C N C N C N C N C N C N C

Publication Release Date: June 09, 2006 - 9 - Revision 2.27 1234 5 6 7 89 10 11 12 1 3 14 15 1 6 1 7 18 1 9 2 0 21 22 2 3 24 25 2 6 2 7 2 8 2 9 30 31 3 2 3 3 34 35 36 37 38 V B A T KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VCC GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 102 101 9 98 97 96 9 5 9 4 9 3 9 2 91 9 0 8 9 8 8 8 7 86 85 84 8 3 82 81 8 0 79 7 8 77 76 7 5 74 73 7 2 71 70 69 6 8 67 66 65 GPSB1/P13/GP11 VSS GPSA1/P12/GP10 G P G P I R R X G P I R T X G P R I B D C D B V S S S O U T B S I N B D T R B R T S B D S R B C T S B V C C W D T O G P S L P S X G P P L E D G P P W R C T L G P SUSLED/GP35 R S M R S T G P P W R O K G P C I R R X G P P S I N P S O U T M D A T M C L K S U S C L K I N A V C C A G N D P C I C L K L D R Q S E R I R Q L A D L A D L A D L A D V C C V L F R A M E V C C L R E S E T P M E C L K I N D R V D E N D R V D E N S M I G P I N D E X M O A D S B D S A V S S M O B D I R S T E P W D W E T R A K W P R D A T A H E A D D S K C H G S L C T P E B U S Y A C K P D P D P D P D W83627G MSI/GP20 MSO/IRQIN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC N C N C N C N C N C N C N C N C N C 1234 5 6 7 89 10 11 12 1 3 14 15 1 6 1 0 11 12 1 3 14 15 1 6 1 7 18 1 9 2 0 21 22 2 3 24 25 2 6 2 7 2 8 1 9 2 0 21 22 2 3 24 25 2 6 2 7 2 8 2 9 30 31 3 2 3 3 34 35 36 29 30 3 1 32 3 3 34 35 36 37 38 V B A T V B A T KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VCC GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 102 101 9 98 97 96 9 5 9 4 9 3 9 2 91 9 0 8 9 8 8 8 7 86 85 84 8 3 82 81 8 0 79 7 8 77 76 75 74 73 72 71 70 69 68 67 66 65102 101 9 98 97 96 9 5 9 4 9 3 9 2 91 9 0 8 9 8 8 8 7 86 85 84 8 3 82 81 8 0 79 7 8 77 76 7 5 74 73 7 2 71 70 69 6 8 67 66 65 GPSB1/P13/GP11 VSS GPSA1/P12/GP10 G P G P G P G P I R R X G P I R R X G P I R T X G P I R T X G P R I B R I B D C D B D C D B V S S V S S S O U T B S O U T B S I N B S I N B D T R B D T R B R T S B R T S B D S R B D S R B C T S B C T S B V C C V C C W D T O G P W D T O G P S L P S X G P P L E D G P P L E D G P P W R C T L G P P W R C T L G P SUSLED/GP35 R S M R S T G P R S M R S T G P P W R O K G P P W R O K G P C I R R X G P C I R R X G P P S I N P S I N P S O U T P S O U T M D A T M D A T M C L K M C L K S U S C L K I N S U S C L K I N A V C C A V C C A G N D A G N D P C I C L K P C I C L K L D R Q L D R Q S E R I R Q S E R I R Q L A D L A D L A D L A D L A D L A D L A D L A D V C C V V C C V L F R A M E L F R A M E V C C V C C L R E S E T L R E S E T P M E P M E C L K I N C L K I N D R V D E N D R V D E N D R V D E N S M I G P I N D E X I N D E X M O A M O A D S B D S B D S A D S A V S S V S S M O B M O B D I R D I R S T E P S T E P W D W D W E W E T R A K T R A K W P W P R D A T A R D A T A H E A D H E A D D S K C H G D S K C H G S L C T S L C T P E P E B U S Y B U S Y A C K A C K P D P D P D P D P D P D P D P D W83627G MSI/GP20 MSO/IRQIN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C

• 10 - PIN CONFIGURATION of W83627HF and W83627HG 12 34 5 6 7 8 9 10 1 1 1 2 1 3 14 1 5 1 6 1 7 1 8 1 9 20 21 22 23 2 4 25 26 2 7 2 8 2 9 3 0 31 32 3 3 34 35 36 37 3 V B A T KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 V R E F V T I N VTIN2 VTIN1 OVT# VID4 VID3 VID2VID1 VID0 VCC GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 101 99 98 97 96 9 5 94 93 9 2 91 9 0 8 9 8 8 8 86 85 84 83 82 81 80 79 7 8 77 76 7 5 74 73 7 2 71 70 69 6 8 67 66 65 GPSB1/P13/GP11 VSS GPSA1/P12/GP10 FANPWM1 FANPWM2 FANIO1 FANIO2 FANIO3 S C L G P S D A G P I R R X G P I R T X G P R I B D C D B V S S S O U T B S I N B D T R B R T S B D S R B C T S B V C C W D T O G P S L P S X G P P L E D G P P W R C T L G P SUSLED/GP35 R S M R S T G P P W R O K G P C I R R X G P P S I N P S O U T C A S E O P E N M D A T M C L K V C O R E A V C O R E B V I N S U S C L K I N A V C C V I N V I N V I N A G N D P C I C L K L D R Q S E R I R Q L A D L A D L A D L A D V C C V L F R A M E V C C L R E S E T P M E C L K I N D R V D E N D R V D E N S M I G P I N D E X M O A D S B D S A V S S M O B D I R S T E P W D W E T R A K W P R D A T A H E A D D S K C H G S L C T P E B U S Y A C K P D P D P D P D W83627HF BEEP MSI/GP20 MSO/IRQIN0

Publication Release Date: June 09, 2006 - 11 - Revision 2.27 12 34 56 7 8 9 10 1 1 1 2 1 3 14 15 1 6 1 7 18 19 20 21 22 23 24 2 5 26 2 7 28 29 30 3 1 32 3 3 34 35 36 37 3 4847 V B A T KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 V R E F V T I N VTIN2 VTIN1 OVT# VID4 VID3 VID2VID1 VID0 VCC GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 102 9 98 9 7 96 9 5 9 4 9 3 9 2 91 90 8 9 8 8 8 7 86 8 5 84 83 82 8 1 8 0 7 9 7 8 77 7 6 75 74 7 3 72 7 1 70 6 9 68 6 7 66 65 GPSB1/P13/GP11 VSS GPSA1/P12/GP10 FANPWM1 FANPWM2 FANIO1 FANIO2 FANIO3 S C L G P S D A G P I R R X G P I R T X G P R I B D C D B V S S S O U T B S I N B D T R B R T S B D S R B C T S B V C C W D T O G P S L P S X G P P L E D G P P W R C T L G P SUSLED/GP35 R S M R S T G P P W R O K G P C I R R X G P P S I N P S O U T C A S E O P E N M D A T M C L K V C O R E A V C O R E B V I N S U S C L K I N A V C C V I N V I N V I N A G N D P C I C L K L D R Q S E R I R Q L A D L A D L A D L A D V C C V L F R A M E V C C L R E S E T P M E C L K I N D R V D E N D R V D E N S M I G P I N D E X M O A D S B D S A V S S M O B D I R S T E P W D W E T R A K W P R D A T A H E A D D S K C H G S L C T P E B U S Y A C K P D P D P D P D W83627HG BEEP MSI/GP20 MSO/IRQIN0 12 34 56 7 8 9 10 1 1 1 2 1 3 14 15 1 6 1 710 1 1 1 2 1 3 14 15 1 6 1 7 18 19 20 21 22 23 24 2 5 26 2 7 2818 19 20 21 22 23 24 2 5 26 2 7 28 29 30 3 1 32 3 3 34 35 3629 3 0 31 32 3 3 34 35 36 37 3 4847 V B A T V B A T KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 V R E F V R E F V T I N V T I N VTIN2 VTIN1 OVT# VID4 VID3 VID2VID1 VID0 VCC GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 102 9 98 9 7 96 9 5 9 4 9 3 9 2 91 90 8 9 8 8 8 7 86 8 5 84 83 8 2 8 1 8 0 7 9 7 77 7 6 75 74 7 3 72 7 1 70 6 9 68 6 7 66 651 101 9 98 9 7 96 9 5 9 4 9 3 9 2 91 90 8 9 8 8 8 7 86 8 5 84 83 8 2 8 1 8 0 7 9 7 8 77 7 6 75 74 7 3 72 7 1 70 6 9 68 6 7 6 6 6 GPSB1/P13/GP11 VSS GPSA1/P12/GP10 FANPWM1 FANPWM2 FANIO1 FANIO2 FANIO3 S C L G P S C L G P S D A G P S D A G P I R R X G P I R R X G P I R T X G P I R T X G P R I B R I B D C D B D C D B V S S V S S S O U T B S O U T B S I N B S I N B D T R B D T R B R T S B R T S B D S R B D S R B C T S B C T S B V C C V C C W D T O G P W D T O G P S L P S X G P P L E D G P P L E D G P P W R C T L G P P W R C T L G P SUSLED/GP35 R S M R S T G P R S M R S T G P P W R O K G P P W R O K G P C I R R X G P C I R R X G P P S I N P S I N P S O U T P S O U T C A S E O P E N C A S E O P E N M D A T M D A T M C L K M C L K V C O R E A V C O R E A V C O R E B V C O R E B V I N V I N S U S C L K I N S U S C L K I N A V C C A V C C V I N V I N V I N V I N V I N V I N A G N D A G N D P C I C L K P C I C L K L D R Q L D R Q S E R I R Q S E R I R Q L A D L A D L A D L A D L A D L A D L A D L A D V C C V V C C V L F R A M E L F R A M E V C C V C C L R E S E T L R E S E T P M E P M E C L K I N C L K I N D R V D E N D R V D E N D R V D E N S M I G P I N D E X I N D E X M O A M O A D S B D S B D S A D S A V S S V S S M O B M O B D I R D I R S T E P S T E P W D W D W E W E T R A K T R A K W P W P R D A T A R D A T A H E A D H E A D D S K C H G D S K C H G S L C T S L C T P E P E B U S Y B U S Y A C K A C K P D P D P D P D P D P D P D P D W83627HG BEEP MSI/GP20 MSO/IRQIN0

• 12 - 6. PIN DESCRIPTION TYPE DESCRIPTION I/O8t TTL level bi-directional pin with 8mA source-sink capability I/O12t TTL level bi-directional pin with 12mA source-sink capability I/O24t TTL level bi-directional pin with 24 mA source-sink capability I/O12tp3 3.3V TTL level bi-directional pin with 12mA source-sink capability I/O12ts TTL level Schmitt-trigger bi-directi onal pin with 12mA source-sink capability I/O24ts TTL level Schmitt-trigger bi-directi onal pin with 24mA source-sink capability I/O24tsp3 3.3V TTL level Schmitt-trigger bi-direc tional pin with 24mA source-sink capability I/OD12t TTL level bi-directional pin and open-dr ain output with 12mA sink capability I/OD24t TTL level bi-directional pin and open-dr ain output with 24mA sink capability I/OD12ts TTL level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink ca- pability I/OD16ts TTL level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink ca- pability I/OD24ts TTL level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink ca- pability I/OD12cs CMOS level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability I/OD16cs CMOS level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability I/OD12csd CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open- drain output with 12mA sink capability I/OD12csu CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open- drain output with 12mA sink capability O4 Output pin with 4 mA source-sink capability O8 Output pin with 8 mA source-sink capability O12 Output pin with 12 mA source-sink capability O16 Output pin with 16 mA source-sink capability O24 Output pin with 24 mA source-sink capability O12p3 3.3V output pin with 12 mA source-sink capability O24p3 3.3V output pin with 24 mA source-sink capability OD12 Open-drain output pin with 12 mA sink capability OD24 Open-drain output pin with 24 mA sink capability OD12p3 3.3V open-drain output pin with 12 mA sink capability

Publication Release Date: June 09, 2006 - 13 - Revision 2.27 PIN DESCRIPTION, continued. TYPE DESCRIPTION INt TTL level input pin INtp3 3.3V TTL level input pin INtd TTL level input pin with internal pull down resistor INtu TTL level input pin with internal pull up resistor INts TTL level Schmitt-trigger input pin INtsp3 3.3V TTL level Schmitt-trigger input pin INc CMOS level input pin INcd CMOS level input pin with internal pull down resistor INcs CMOS level Schmitt-trigger input pin INcsu CMOS level Schmitt-trigger input pin with internal pull up resistor Note： Please refer to Section 11.2 DC CHARACTERISTICS for details.

6.1 LPC Interface

System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz in- put. PME# 19 OD12p3 Generated PME event. PCICLK 21 INtsp3 PCI clock input. LDRQ# 22 O12p3 Encoded DMA Request signal. SERIRQ 23 I/O 12tp3 Serial IRQ input/Output. LAD[3：0] 24-27 I/O12tp3 These signal lines communicate address, control, and data in- formation over the LPC bus between a host and a peripheral. LFRAME# 29 INtsp3 Indicates start of a new cycle or termination of a broken cycle. LRESET# 30 INtsp3 Reset signal. It can connect to PCIRST# signal on the host. SUSCLKIN 75 IN tsp3 32khz clock input, for CIR only.

• 14 -

6.2 FDC Interface

DRVDEN0 1 OD 24 Drive Density Select bit 0. DRVDEN1 2 OD12 Drive Density Select bit 1.（Default） SMI# IRQIN1 GP27 OD12 INt I/OD12t System Management Interrupt Interrupt channel input. General purpose I/O port 2 bit 7. INDEX# 3 IN csu This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 500 ohm resistor. The resist or can be disabled by bit 7 of LD0-CRF0（FIPURDWN）. MOA# 4 OD 24 Motor A On. When set to 0, this pin enables disk drive 0. DSB# FANIN3

5 OD 24

Drive Select B. When set to 0, this pin enables disk drive B. 0V to +5V amplitude fan tachometer input DSA# 6 OD 24 Drive Select A. When set to 0, this pin enables disk drive A. MOB# FANPWM3

7 OD 24

Motor B On. When set to 0, this pin enables disk drive 1. Fan speed control. Use the Pulse Width Modulation （PWM） technical knowledge to control the Fan's RPM. DIR# 8 OD 24 Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion STEP# 9 OD 24 Step output pulses. This active low open drain output produces a pulse to move the head to another track. WD# 10 OD 24 Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. WE# 11 OD 24 Write enable. An open drain output. TRACK0# 13 IN csu Track 0. This Schmitt-triggered input from the disk drive is ac- tive low when the head is positi oned over the outermost track. This input pin is pulled up internally by a 1 K ohm resistor.The resistor can be disabled by bit 7 of L0-CRF0（FIPURDWN）. WP# 14 IN csu Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN）.

Publication Release Date: June 09, 2006 - 15 - Revision 2.27 FDC Interface, continued. SYMBOL PIN I/O FUNCTION RDATA# 15 IN csu The read data input signal from the FDD. This input pin is pulled up internally by a 1 K ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN）. HEAD# 16 OD 24 Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 DSKCHG# 17 IN csu Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up in- ternally by a 1 K ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN）.

6.3 Multi-Mode Parallel Port

The following pins have alternate functions (Pri nter Mode and Extension FDD Mode), which are se- lected by CR28 and LD1-CRF0 setting. SYMBOL PIN I/O FUNCTION SLCT 31 IN ts PRINTER MODE： An active high input on this pin indicates that the printer is se- lected. Refer to the description of the parallel port for defini- tion of this pin in ECP and EPP mode. WE2# OD 12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PE WD2#

32 IN ts

PRINTER MODE： An active high input on this pin indicates that the printer has detected the end of the paper. Refe r to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC.

• 16 - Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION BUSY 33 IN ts PRINTER MODE： An active high input indicates t hat the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. MOB2# OD 12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. ACK# 34 IN ts PRINTER MODE： An active low input on this pin indicates that the printer has received data and is ready to acc ept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DSB2# OD 12 EXTENSION FDD MODE： This pin is for the Extension FDD B; its functions are the same as the DSB# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PD7

35 I/O 12ts PRINTER MODE： PD7

Parallel port data bus bit 7. Refer to the description of the par- allel port for the definition of this pin in ECP and EPP mode. DSA2# OD 12 EXTENSION FDD MODE： This pin is a tri-state output. EXTENSION 2FDD MODE： This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC.

Publication Release Date: June 09, 2006 - 17 - Revision 2.27 Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION PD6 36 I/O 12ts PRINTER MODE： PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. MOA2# OD 12 EXTENSION FDD MODE： This pin is a tri-state output. EXTENSION. 2FDD MODE： MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PD5 37 I/O 12ts PRINTER MODE： PD5 Parallel port data bus bit 5. Refer to the description of the par- allel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE： This pin is a tri-state output. EXTENSION 2FDD MODE： This pin is a tri-state output. PD4 38 I/O 12ts PRINTER MODE： PD4 Parallel port data bus bit 4. Refer to the description of the par- allel port for the definition of this pin in ECP and EPP mode. DSKCHG2# IN ts EXTENSION FDD MODE： This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high in- ternally. PD3 39 I/O 12ts PRINTER MODE： PD3 Parallel port data bus bit 3. Refer to the description of the par- allel port for the definition of this pin in ECP and EPP mode. RDATA2# IN ts EXTENSION FDD MODE： RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE： RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally.

• 18 - Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION PD2 40 I/O 12ts PRINTER MODE： PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. WP2# IN ts EXTENSION FDD MODE： WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE： WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally. PD1 41 I/O 12ts PRINTER MODE： PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. TRAK02# IN ts EXTENSION FDD MODE： TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE： TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. PD0 42 I/O 12ts PRINTER MODE： PD0 Parallel port data bus bit 0. Refer to the description of the par- allel port for the definition of this pin in ECP and EPP mode. INDEX2# IN ts EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally.

Publication Release Date: June 09, 2006 - 19 - Revision 2.27 Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION SLIN# 43 OD 12 PRINTER MODE： SLIN# Output line for detection of prin ter selection. Refer to the de- scription of the parallel port for the definition of this pin in ECP and EPP mode. STEP2# OD 12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. INIT# 44 OD 12 PRINTER MODE： Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DIR2# OD 12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. ERR# 45 IN ts PRINTER MODE： An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. HEAD2# OD 12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the HEAD# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC.

• 20 - Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION AFD# 46 OD 12 PRINTER MODE： An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DRVDEN0 OD 12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. STB# 47 OD 12 PRINTER MODE： An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the defi- nition of this pin in ECP and EPP mode. EXTENSION FDD MODE： This pin is a tri-state output EXTENSION 2FDD MODE： This pin is a tri-state output.

Publication Release Date: June 09, 2006 - 21 - Revision 2.27

6.4 Serial Port Interface

CTSA# CTSB# INt Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. DSRA# DSRB# IN t Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. RTSA# HEFRAS O8C INcd UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is de- fined as HEFRAS, which provides the power-on value for CR26 bit 6 （HEFRAS）. A 4.7 k ohm is recommended if intends to pull up. （select 4EH as configuration I/O port′s address） DTRA# PNPCVS#

52 O 8C

UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is de- fined as PNPCVS# , which provides the power-on value for CR24 bit 0, A 4.7k ohm is recommended if intends to pull up.（This bit is used to clear the default value of FDC, UARTs, and LPT setting） RTSB# 80 O 8C UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. DTRB# 81 O 8C UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. SINA SINB# IN t Serial Input. It is used to receive serial data through the communica- tion link. SOUTA PENKBC O8C INcd UART A Serial Output. It is used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is de- fined as PENKBC, which provides the power-on value for CR24 bit 2 （PENKBC）. A 4.7 k ohm resistor is recommended if intends to pull up. （ enable KBC） SOUTB PEN48 O8C INcd UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power- on value for CR24 bit 6 （EN48）. A 4.7 k ohm resistor is recom- mended if intends to pull up. DCDA# DCDB# IN t Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. RIA# RIB# IN t Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.

• 22 -

6.5 KBC Interface

KBLOCK# 58 IN tu Keyboard inhibits control input. Th is pin is after system reset. In- ternal pull high. （KBC P17） GA20M 59 O 16 Gate A20 output. This pin is high after system reset. （KBC P21） KBRST 60 O 16 Keyboard reset. This pin is high after system reset. （KBC P20） KCLK 62 I/OD 16ts I/OD16cs Keyboard Clock. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. KDAT 63 I/OD 16ts I/OD16cs Keyboard Data. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. MCLK 65 I/OD 16ts I/OD16cs PS2 Mouse Clock. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. MDAT 66 I/OD 16ts I/OD16cs PS2 Mouse Data. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level.

6.6 ACPI Interface

PSOUT# 67 OD12 Panel Switch Output. This signal is used for Wake-Up system from S5cold state. This pin is pulse output, active low. PSIN 68 INcd Panel Switch Input. This pin is high active with an internal pull down resistor. VBAT 74 PWR Battery voltage input.

Publication Release Date: June 09, 2006 - 23 - Revision 2.27

6.7 Hardware Monitor Interface

（For W83627HF only, all these pins in W83627F are NC.） SYMBOL PIN I/O FUNCTION CASEOPEN# 76 INt CASE OPEN. An active low input from an external device when case is opened. This signal can be latched if pin VBAT is con- nect to battery, even W83627HF is power off. -5VIN 94 AIN 0V to 4. 096V FSR Analog Inputs. -12VIN 95 AIN 0V to 4. 096V FSR Analog Inputs. +12VIN 96 AIN 0V to 4. 096V FSR Analog Inputs. +3.3VIN 98 AIN 0V to 4. 096V FSR Analog Inputs. VCOREB 99 AIN 0V to 4.096V FSR Analog Inputs. VCOREA 100 AIN 0V to 4.096V FSR Analog Inputs. VREF 101 PWR Reference Voltage for temperature measuration. VTIN3 102 AIN Temperature sensor 3 input. It is used for temperature measu- ration. VTIN2 103 AIN Temperature sensor 2 input. It is used for CPU1 temperature measuration. VTIN1 104 AIN Temperature sensor 1 input. It is used for system temperature measuration. OVT# 105 OD24 Over temperature Shutdown Output. It indicated the VTIN2 or VTIN3 is over temperature limit. VID[4：0] 106- 110 INt Voltage Supply readouts from Pentium II. FANIO[3：1] 111-

113 I/O12ts

0V to +5V amplitude fan tachometer input. Alternate Function： Fan on-off control output. These multifunctional pins can be programmable input or out- put. FANPWM1 FANPWM2 116 115 O 12 Fan speed control. Use the Pulse Width Modulatuion （PWM） technic knowledge to control the Fan's RPM. BEEP 118 OD 12 Beep function for hardware monitor. This pin is low after sys- tem reset.

• 24 -

6.8 Game Port & MIDI Port

119 INtu

MIDI serial data input .（Default） General purpose I/O port 2 bit 0. MSO IRQIN0

120 O 8C

MIDI serial data output. （Default） Alternate Function input： Interrupt channel input. GPSA2 GP17

121 INcsu

Active-low, Joystick I switch input 2. This pin has an internal pull-up resistor. （Default） General purpose I/O port 1 bit 7. GPSB2 GP16

122 INcsu

Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. （Default） General purpose I/O port 1 bit 6. GPY1 GP15

123 I/OD 12csd

Joystick I timer pin. This pin connects to Y positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 5. GPY2 GP14

124 I/OD 12csd

Joystick II timer pin. This pin connects to Y positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 4. P16 Alternate Function Output： KBC P16 I/O port. GPX2 GP13

125 I/OD 12csd

Joystick II timer pin. This pin connects to X positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 3. P15 Alternate Function Output： KBC P15 I/O port. GPX1 GP12 P14

126 I/OD 12csd

Joystick I timer pin. This pin connects to X positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 2. Alternate Function Output： KBC P14 I/O port. GPSB1 GP11 P13

127 INcsu

Active-low, Joystick II switch input 1. （Default） General purpose I/O port 1 bit 1. Alternate Function Output： KBC P13 I/O port. GPSA1 GP10 P12

128 INcsu

Active-low, Joystick I switch input 1. （Default） General purpose I/O port 1 bit 0. Alternate Function Output： KBC P12 I/O port.

Publication Release Date: June 09, 2006 - 25 - Revision 2.27

6.9 General Purpose I/O Port

6.9.1 General Purpose I/O Port 1 （Power source is Vcc）

See section 7.8

6.9.2 General Purpose I/O Port 2 （Power source is Vcc）

119 I/OD 12t

General purpose I/O port 2 bit 0. MIDI serial data input. Schmitt trigger input with internal pull-up resistor. GP21 SCL

92 I/OD 12t

General purpose I/O port 2 bit 1. Serail Bus Clock.（availiable for W83627HF only） GP22 SDA

91 I/OD 12t

General purpose I/O port 2 bit 2. Serial Bus Data.（availiable for W83627HF only） GP23 PLED

90 I/OD 12t

General purpose I/O port 2 bit 3. Power LED output, this signal will be logical low after system reset. GP24 WDTO

89 I/OD 12t

General purpose I/O port 2 bit 4. Watch Dog Timer Output. High level indicates that Watch Dog Timer time-out occurs. GP25 IRRX

88 I/OD 12t

General purpose I/O port 2 bit 5. Infrared Receiver Input. GP26 IRTX

87 I/OD 12t

General purpose I/O port 2 bit 6. Infrared Transmitter Output. GP27 SMI# ( IRQIN1)

2 I/OD 24t

General purpose I/O port 2 bit 7. System Management Interrupt. (Interrupt channel input. For C version only) DRVDEN1 OD 24 Drive Density Select bit 1.（Default）

• 26 -

6.9.3 General Purpose I/O Port 3 （Power souce is VSB）

GP30 73 I/OD 12t General purpose I/O port 3 bit 0. SLP_SX# IN ts Chipset suspend C status input. GP31 72 I/OD 12t General purpose I/O port 3 bit 1. PWRCTL# O 12 Power On Control . Active low signal that informs sys- tem to turn main power. GP32 71 I/OD 12t General purpose I/O port 3 bit 2. PWROK OD 12 Power OK. Active (High) level indicates VDD is ready. GP33 70 I/OD 12t General purpose I/O port 3 bit 3. RSMRST# OD 12 Resume Reset . Active (High) level indicates VSB is ready. GP34 69 I/OD 12t General purpose I/O port 3 bit 4. CIRRX# IN ts Consumer IR receiving input. This pin can Wake-Up system from S5cold.（Default） GP35 64 I/OD 24t General purpose I/O port 3 bit 5. SUSLED O 24 Suspend LED output, it can program to flash when suspend state.This function can work without VCC. （Default）

6.10 POWER PINS

VCC 12, 48, 77, 114 +5V power supply for the digital circuitry. VSB 61 +5V stand-by power supply for the digital circuitry. Do not leave this pin unconnected. Connect it to VCC if the sys- tem does not provide standby power VCC3V 28 +3.3V power supply for dr iving 3V on host interface. AVCC 97 Analog VCC input. Internally supplier to all analog circuitry. AGND 93 Internally connected to all analog circuitry. The ground ref- erence for all analog inputs.. VSS 20, 55, 86, 117 Ground.

Publication Release Date: June 09, 2006 - 27 - Revision 2.27 7. HARDWARE MONITOR

7.1 General Description

The W83627HF can be used to monitor several critic al hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end com- puter system to work stable and proper ly. W83627HF provides both LPC and I 2CTM serial bus inter- face to access hardware. An 8-bit analog-to-digital converter（ADC）was built inside W83627HF. The W83627HF can simulta- neously monitor 9 analog voltage inputs, 3 fan tachom eter inputs, 3 remote temperature, one case- open detection signal. The remote temperature sens ing can be performed by thermistors, or 2N3904 NPN-type transistors, or directly from Intel TM Deschutes CPU thermal diode output. Also the W83627HF provides： 2 PWM（pulse width modulation）outputs for the fan speed control; beep tone output for warning; SMI#（through serial IRQ）, OVT#, GPO# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be al so activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware Doctor TM, or IntelTM LDCM （LanDesk Client Management ）, or other management application software. Also the users can set up the upper and lower limits （alarm thresholds） of these monitored parameters and to ac- tivate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters are out of the preset range. Additionally, 5 VID inputs are provided to read the VID of CPU （i.e. PentiumTM II） if applicable. This is to provide the Vcore voltage correction autom atically. Also W83627HF uniquely provides an op- tional feature： early stage （before BIOS was loaded ） beep warning. This is to detect if the fatal elements present --- Vcore or +3.3V voltage fail, and the system can not be boomed up.

7.2 Access Interface

The W83627HF provides two interface for microprocessor to read/write hardware monitor internal reg- isters.

7.2.1 LPC interface

The first interface uses LPC Bus to access which the ports of low byte （bit2~bit0） are defined in the port 5h and 6h. The other higher bits of these por ts is set by W83627HF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following： Port 295h： Index port. Port 296h： Data port. The register structure is showed as the Figure 8.1

• 28 - Figure 8.1 ： ISA interface access diagram Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h VID<3:0>/Fan Divisor Register 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID<4>/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Control Register 4Bh~4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Temperature 3 Control/Staus Registers 50h~56h Data Register Port 6h Port 5h Index Register ISA Data Bus ISA Address Bus BANK 4 Additional Control/Staus Registers 50h~5Ch BANK 5 Additional Limit Value & Value RAM 50h~57h Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h VID<3:0>/Fan Divisor Register 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID<4>/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Control Register 4Bh~4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Temperature 3 Control/Staus Registers 50h~56h Data Register Port 6h Port 5h Index Register ISA Data Bus ISA Address Bus BANK 4 Additional Control/Staus Registers 50h~5Ch BANK 5 Additional Limit Value & Value RAM 50h~57h

Publication Release Date: June 09, 2006 - 29 - Revision 2.27

7.2.2 I 2C interface

The second interface uses I2C Serial Bus. W83627HF hardware monitor has three serial bus address. That is, the first address defined at CR[48h] can r ead/write all registers ex cluding Bank 1 and Bank 2 temperature sensor 2/3 registers. The second addr ess defined at CR[4Ah] bit2-0 only read/write tem- perature sensor 2 registers, and the third addr ess defined at CR[4Ah] bit6-4 only can access （read/write）temperature sensor 3 registers.

7.2.2.1 The first serial bus access timing is shown as follow ：

(a) Serial bus write to internal addr ess register followed by the data byte Start By Master 01011 01 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D R/W Ack by 781D SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Stop by Master SCL SDA (Continued) 780 78 Frame 2 Internal Index Register Byte (Continued) Frame 3 Data Byte Frame 1 Serial Bus Address Byte (b) Serial bus write to internal address register only Start By Master 01011 01 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D R/W Ack by 781D SCL SDA 780 78 Frame 2 Internal Index Register Byte Frame 1 Serial Bus Address Byte Stop by Master (c) Serial bus read from a register with the in ternal address register prefer to desired location Start By Master 01011 01 D7 D6 D5 D4 D3 D2 D1 D0 Ack by Master R/W Ack by 781D SCL SDA 780 78 Frame 2 Data Byte Frame 1 Serial Bus Address Byte Stop by Master

• 30 -

7.2.2.2 The serial bus timing of the temperature 2 and 3 are shown as follow ：

(a) Typical 2-byte read from preset pointer location （Temp, TOS, THYST） Start By Master 01011 01 D7 D1 D0 Ack by Master R/W Ack by 782D SCL SDA 780 78 Frame 2 MSB Data Byte Frame 1 Serial Bus Address Byte D7 D1 D0 Stop by Master ... Ack by Master ... Frame 3 LSB Data Byte (b) Typical pointer set followed by immediate read for 2-byte register （Temp, TOS, THYST） Start By Master D7 D1 D0 Ack by Master Ack by 782D SCL SDA 780 78 Frame 4 MSB Data Byte Frame 3 Serial Bus Address Byte D7 D1 D0 Stop by Master ... No Ack by Master ... Frame 5 LSB Data Byte Start By Master 1001A 2 A1 A0 R/W Ack by 782D SCL SDA 780 Frame 1 Serial Bus Address Byte D1 D0 Ack by 782D Frame 2 Pointer Byte 1 0 0 1 A2 A1 A0 R/W 000000 (c) Typical read 1-byte from configur ation register with preset pointer Start By Master D7 D2 Ack by 782D SCL SDA 780 Frame 2 Data Byte Frame 1 Serial Bus Address Byte Stop by Master No Ack by Master 1001A 2 A 1 A 0 R / W D1D5 D4 D3D6

Publication Release Date: June 09, 2006 - 31 - Revision 2.27 (d) Typical pointer set followed by imm ediate read from configuration register Start By Master 01011 01 D7 D1 D0 Ack by Master R/W Ack by 782D SCL SDA 780 78 Frame 2 MSB Data Byte Frame 1 Serial Bus Address By D7 D1 D0 Stop b Maste ... Ack by Master ... Frame 3 LSB Data Byte (e) Temperature 2/3 configuration register Write Start By Master D7 D1 D0 Ack by Master Ack by 782D SCL SDA 780 78 Frame 4 MSB Data Byte Frame 3 Serial Bus Address Byte D7 D1 D0 Stop by Master ... No Ack by Master ... Frame 5 LSB Data Byte Start By Master 1001A 2 A1 A0 R/W Ack by 782D SCL SDA 780 Frame 1 Serial Bus Address Byte D1 D0 Ack by 782D Frame 2 Pointer Byte 1 0 0 1 A2 A1 A0 R/W 000000 (f) Temperature 2/3 TOS and THYST write Start By Master D7 D2 Ack by 782D SCL SDA 780 Frame 2 Data Byte Frame 1 Serial Bus Address Byte Stop by Master No Ack by Master 1001A 2 A 1 A 0 R / W D1D5 D4 D3D6

• 32 -

7.3 Analog Inputs

The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring woul d most often be connected to power suppliers. The CPU V-core voltage, +3.3V, battery and 5VSB volt age can directly connected to these analog inputs. The +12V,-12V and -5V voltage inputs should be reduced a factor with external resistors so as to ob- tain the input range. As Figure 8.2 shows. Pin 100VCOREA VCOREB Pin 99 +3.3VIN +12VIN Pin 98 Pin 96 Pin 97AVCC(+5V) N12VIN VBAT Pin 95 Pin 74 N5VIN Positive Input Negative Input 8-bit ADC with 16mV LSB Typical Thermister Connection 10K, 1% RTHM VREF Pin 101 VTIN3 VTIN2 VTIN1 Pin 102 Pin 103 Pin 104 5VSB Pin 61 Pin 94 Positive Inputs 10K, 25 C **The Connections of VTIN1 and VTIN2 are same as VTIN3 R Figure. 8.2 7.3.1 Monitor over 4.096V voltage ： The input voltage +12VIN can be expressed as following equation. 12 1 VIN V R RR=× + The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun input range of the 8-bit ADC. The Pin 97 is connect ed to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83627HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The values of two serial resist ors are 34K ohms and 50K ohm s so that input voltage to ADC is 2.98V which is less than 4.096V of A DC maximum input voltage. The express equation can represent as follows.

Publication Release Date: June 09, 2006 - 33 - Revision 2.27 VV C C K KK Vin =× + ≅50 50 34 29 8Ω ΩΩ . where VCC is set to 5V. The Pin 61 is connected to 5VSB voltage. W83627HF moni tors this voltage and the internal two serial resistors are 17K Ω and 33K Ω so that input voltage to ADC is 3.3V which less than 4.096V of ADC maximum input voltage.

7.3.2 Monitor negative voltage ：

The negative voltage should be connected two seri es resistors and a positive voltage VREF （is equal to 3.6V ）. In the Figure 8.2, the voltage V2 and V3 are two negative voltage which they are - 12V and -5V respectively. The voltage V2 is connected to two serial resistors then is connected to an- other terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage if the scales of the two serial resirt ors are carefully selected. It is recommanded from Winbond that the scale of two serial resistors are R3=232K ohm and R4=56K ohm. The input voltage of node N12VIN can be calculated by following equation. N VIN VREF V K KK V12 232 232 56 22=+ × + +() ( ) Ω ΩΩ Where VREF is equal 3.6V. If the V2 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative votage and the express equation is shown as follows. V N VIN VREF 1= − × β β Where β is 232K/（232K+56K）. If the N2VIN is 0.567 then the V2 is approximately equal to -12V. The another negative voltage input V3 （approximate -5V ） also can be evaluated by the similar method and the serial resistors can be selected wi th R5=120K ohms and R6=56K ohms by the Win- bond recommended. The expression equation of V3 With -5V voltage is shown as follows. V N VIN VREF 1= − × γ γ Where the γ is set to 120K/ （120K+56K）. If the monitored ADC value in the N5VIN channel is 0.8635, VREF is 3.6V and the parameter γ is 0.6818 then the negative vo ltage of V3 can be evalated to be -5V.

• 34 -

7.3.3 Temperature Measurement Machine

The temperature data format is 8-bit two's-compl ement for sensor 2 and 9-bit two's-complement for sensor 1. The 8-bit temperature data can be obt ained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1 CR[50h] and the LSB from the Bank1 CR[51h] bit 7. The format of the temperature data is show in Table 1. Table 1. TEMPERATURE 8-BIT DIGITAL OUTPUT 9-BIT DIGITAL OUTPUT 8-BIT BINARY 8-BIT HEX 9-BIT BINARY 9-BIT HEX +125°C 0111,1101 7Dh 0,1111,1010 0FAh +25°C 0001,1001 19h 0,0011,0010 032h +1°C 0000,0001 01h 0,0000,0010 002h +0°C 0000,0000 00h 0,0000,0000 000h -1°C 1111,1111 FFh 1,1111,1110 1FFh -25°C 1110,0111 E7h 1,1100,1110 1CEh -55°C 1100,1001 C9h 1,1001,0010 192h

7.3.3.1 Monitor temperature from thermistor ：

The W83627HF can connect three thermistors to measur e three different envirment temperature. The specification of thermistor should be considered to （1） β value is 3435K, （2） resistor value is 10K ohms at 25°C. In the Figure 8.2, the themistor is connect ed by a serial resistor with 10K Ohms, then connect to VREF （Pin 101）.

7.3.3.2 Monitor temperature from Pentium II TM thermal diode or bipolar transistor 2N3904

The W83627HF can alternate the thermistor to Pentium II TM （Deschutes） thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 8.3. The pin of Pentium IITM D- is con- nected to power supply ground （GND） and the pin D+ is connected to pin VTINx in the W83627HF. The resistor R=30K ohms should be connected to VR EF to supply the diode bias current and the by- pass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base （B） and Collector （C） in the 2N3904 should be tied togeter to act as a thermal diode.

Publication Release Date: June 09, 2006 - 35 - Revision 2.27 2N3904 C E B R=30K, 1% C=3300pF Bipolar Transistor Temperature Sensor Pentium II CPU D+ Therminal Diode C=3300pF R=30K, 1% VREF VTINx VTINx OR W83627HF Figure. 8.3

7.4 FAN Speed Count and FAN Speed Control

7.4.1 Fan speed count

Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The norma l circuit and trimming circuits are shown as Figure 8.4. Determine the fan counter according to： Count RPM Divisor= × 135 10 6. In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation. RPM Count Divisor= × 13 5 1 0 6. The default divisor is 2 and defined at CR47.bit7~4 , CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The fol- lowed table is an example for the relation of divisor, PRM, and count.

• 36 - Table 2. DIVISOR NOMINAL PRM TIME PER REVOLUTION COUNTS 70% RPM TIME FOR 70% 1 8800 6.82 ms 153 6160 9.74 ms 2 （default） 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms FAN Connector FAN Out +12V GND Pull-up resister 4.7K Ohms +5V+12V Fan Input Pin 111-113 W83627HF FAN Connector FAN Out +12V GND Pull-up resister 4.7K Ohms +12V Fan Input Pin 111-113 W83627HF 14K~39K 10K Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator Fan with Tach Pull-Up to +5V FAN Connector FAN Out +12V GND Pull-up resister > 1K +12V Fan Input Pin 111-113 W83627HF FAN Connector FAN Out +12V GND Pull-up resister < 1K or totem-pole output +12V Fan Input Pin 111-113 W83627HF > 1K Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Zener ClampFan with Tach Pull-Up to +12V and Zener Clamp 3.9V Zener 3.9V Zener diode diode diodediode Figure. 8.4

Publication Release Date: June 09, 2006 - 37 - Revision 2.27

7.4.2 Fan speed control

The W83627HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be pro- grammed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be repre- sented as follows. Duty cycle Programmed 8- bit Register Value 255−= × (%) 100% The PWM clock frequency also can be program and def ined in the Bank0.CR5C. The application cir- cuit is shown as follows. +12V FAN NMOS PNP Transistor C PWM Clock Input D S G Figure. 8.5

• 38 -

7.5 SMI# interrupt mode

7.5.1 Voltage SMI# mode ：

SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. （See Figure 8.6） Figure. 8.6 SMI# Two-Times Interrupt Mode

7.5.2 Fan SMI# mode ：

SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. （See Figure 8.7） Figure. 8.7 Two-Times Interrupt Mode

Publication Release Date: June 09, 2006 - 39 - Revision 2.27

7.5.3 Temperature 1 SMI# modes

The W83627HF temperature sensor 1 SMI# interrupt has two modes （1）Comparator Interrupt Mode Setting the THYST （Temperature Hysteresis） limit to 127 °C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds T O （Over Temperature） Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an in- terrupt event has occurred by exceeding T O, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding T O and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. （See Figure 8.8 ） Figure. 8.8 Temperature 1 SMI# Comparator Interrupt Mode （2）Two-Times Interrupt Mode Setting the THYST lower than TO will set temperatur e sensor 1 SMI# to the Two-Times Interrupt Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous in terrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the tem- perature remains above the THYST, the interrupt will not occur. （See Figure 8.9） Figure. 8.9 Temperature 1 SMI# Two-Times Interrupt Mode

• 40 -

7.5.4 Temperature 2, 3 SMI# modes ：

The W83627HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is pro- grammed at CR[4Ch] bit 6. （1）Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt ev ent has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the in terrupt will occur again when the next conver- sion has completed. If an interrupt event has o ccurred by exceeding TO and not reset, the inter- rupts will not occur again. The interrupts will cont inue to occur in this manner until the tempera- ture goes below THYST. （ See Figure 8.10 ） Figure. 8.10 Temperature 2, 3 SMI# Comparator Interrupt Mode （2）Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will not occur. （See Figure 8.11 ） Figure. 8.11 Temperature 2, 3 SMI# Two-Times Interrupt Mode

Publication Release Date: June 09, 2006 - 41 - Revision 2.27

7.6 OVT# interrupt mode

The W83627HF OVT# signal is only related to temperature sensor 2 and 3 （VTIN2 / VTIN3）. They have two modes： （1）Comparator Mode： Setting Bank1/2 CR[52h] bit 2 to 0 will set OVT# signal to comparator mode. Temperature ex- ceeding TO causes the OVT# output activat ed until the temperature is less than THYST. （See Figure 8.12） （2）Interrupt Mode： Setting Bank1/2 CR[52h] bit 2 to 1 will set OVT# signal to interrupt mode. Setting Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then tempera- ture going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. On ce the OVT# is activated by exceeding TO, then reset, if the temperature remains above TH YST, the OVT# will not be activated again. （See Fig- ure 8.12） Figure. 8.12 OVT# Interrupt Mode

• 42 -

7.7 REGISTERS AND RAM

Address Register （Port x5h） Data Port： Port x5h Power on Default Value 00h Attribute： B i t 6 ：0 Read/write , Bit 7： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 Data 7 6 5 4 3 2 1 0 Data Bit7： Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With checking this bit, multiple LPC drivers can use W83627HF hardware monitor without interfering with each other or a Serial Bus driver. It is the user's responsibility not to have a Serial Bus and LPC bus operations at the same time. This bit is： Set： with a write to Port x5h or when a Serial Bus transaction is in progress. Reset： with a write or read from Port x6h if it is se t by a write to Port x5h, or when the Serial Bus transaction is finished. Bit 6-0： Read/Write BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Busy Address Pointer （Power On default 00h） （Power On default 0） A6 A5 A4 A3 A2 A1 A0

Publication Release Date: June 09, 2006 - 43 - Revision 2.27 Address Pointer Index （A6-A0） REGISTERS AND RAM A6-A0 IN HEX POWER ON VALUE OF REGISTERS <K7：0> IN BINARY NOTES Configuration Register 40h 00001000 Interrupt Status Register 1 41h 00000000 Auto-increment to the address of Interrupt Status Register 2 af- ter a read or write to Port x6h. Interrupt Status Register 2 42h 00000000 SMI#Ý Mask Register 1 43h 00000000 Auto-increment to the address of SMIÝ Mask Register 2 after a read or write to Port x6h. SMIÝ Mask Register 2 44h 00000000 NMI Mask Register 1 45h 00000000 Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h NMI Mask Register 2 46h 01000000 VID/Fan Divisor Register 47h <7：4> = 0101; <3：0> = VID3-VID0 Serial Bus Address Regis- ter 48h <7> = 0 ; <6：0> = 0101101 VID4 & Device ID Register 49h <7：1> = 0000001; <0> = VID4 Temperature 2 and Tem- perature 3 Serial Bus Ad- dress Register 4Ah <7：0> = 00000001 Pin Control Register 4Bh <7：0> = 01000100 IRQ/OVT# Property Select Register 4Ch <7：0> = 00000000 FAN IN/OUT and BEEP Control Register 4Dh <7：0> = 00010101 Register 50h-5Fh Bank Se- lect Register 4Eh <7> = 1 ; <6：3> = Reserved ; <2：0> = 000

• 44 - Address Pointer Index（A6-A0）, continued REGISTERS AND RAM A6-A0 IN HEX POWER ON VALUE OF REGISTERS <K7：0> IN BINARY NOTES Winbond Vendor ID Regis- ter 4Fh <7：0> = 01011100 （High Byte） <7：0> = 10100011 （LOW BYTE） POST RAM 00-1Fh Auto-increment to the next loca- tion after a read or write to Port x6h and stop at 1Fh. Value RAM 20-3Fh Value RAM 60-7Fh Auto-increment to the next loca- tion after a read or write to Port x6h and stop at 7Fh. Temperature 2 Registers Bank1 50h-56h Temperature 3 Registers Bank2 50h-56h Additional Configuration Registers Bank4 50h-5Dh Data Register （Port x6h） Data Port： Port x6h Power on Default Value： 00h Attribute： Read/write Size： 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0： Data to be read from or to be written to RAM and Register.

Publication Release Date: June 09, 2006 - 45 - Revision 2.27 Configuration Register - Index 40h Register Location： 40h Power on Default Value： 01h Attribute： Read/write Size： 8 bits 7 6 5 4 3 2 1 0 START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION Bit 7： A one restores power on default value to all regi sters except the Serial Bus Address register. This bit clears itself since the power on default is zero. Bit 6： Reserced Bit 5： Reserved Bit 4： Reserved Bit 3： A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2： Reserved Bit 1： A one enables the SMI# Interrupt output. Bit 0： A one enables startup of monitoring operations, a zero puts the part in standby mode. Note： The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. Interrupt Status Register 1 - Index 41h Register Location： 41h Power on Default Value： 00h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2

• 46 - Bit 7： A one indicates the fan count limit of FAN2 has been exceeded. Bit 6： A one indicates the fan count limit of FAN1 has been exceeded. Bit 5： A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2. Bit 4： A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1. Bit 3： A one indicates a High or Low limit of +5VIN has been exceeded. Bit 2： A one indicates a High or Low limit of +3.3VIN has been exceeded. Bit 1： A one indicates a High or Low limit of VCOREB has been exceeded. Bit 0： A one indicates a High or Low limit of VCOREA has been exceeded. Interrupt Status Register 2 - Index 42h Register Location： 42h Power on Default Value： 00h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 +12VIN -12VIN -5VIN FAN3 Chassis Intrusion Temp3 Reserved Reserved Bit 7-6： Reserved.This bit should be set to 0. Bit 5： A “1” indicates a High limit of VTIN3 has been exceeded from temperature sensor 3. Bit 4： A “1” indicates Chassis Intrusion Event Occur. When CASEOPEN# （Pin 76）gone logic low, this bit will be set “1”. Bit 3： A “1” indicates the fan count limit of FAN3 has been exceeded. Bit 2： A “1” indicates a High or Low limit of -5VIN has been exceeded. Bit 1： A “1” indicates a High or Low limit of -12VIN has been exceeded. Bit 0： A “1” indicates a High or Low limit of +12VIN has been exceeded.

Publication Release Date: June 09, 2006 - 47 - Revision 2.27 SMI# Mask Register 1 - Index 43h Register Location： 43h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 Bit 7-0： A one disables the corresponding interrupt status bit for SMI interrupt. SMI# Mask Register 2 - Index 44h Register Location： 44h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 +12VIN -12VIN -5VIN FAN3 Chassis Intrusion TEMP3 Reserved Reserved Bit 7-6： Reserved. This bit should be set to 0. Bit 5-0： A one disables the corresponding interrupt status bit for SMI interrupt.

• 48 - Reserved Register - Index 45h This register is reserved. Chassis Clear Register - Index 46h （Not available for A Version） Register Location： 46h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear Bit 7： Clear Chassis Intrusion Event. Write “1” will make Hardware Monitor Register Index 42, bit 4 cleared to “0”）. This bit self clears after clearing Chassis Intrusion event. For W83627HF A Version, Clear Chassis Intrusion Event has been changed form this bit to LDA CRE6[6]. Bit 6-0：Reserved, and should be set to 0. VID/Fan Divisor Register - Index 47h Register Location： 47h Power on Default Value： <7：4> is 0101, <3：0> is mapped to VID<3：0> Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 VID0 VID1 VID2 VID3 FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 Bit 7-6： FAN2 Speed Control.

Publication Release Date: June 09, 2006 - 49 - Revision 2.27 Bit 5-4： FAN1 Speed Control. Bit 3-0： The VID <3：0> inputs Note: Please refer to Bank0 CR[5Dh] , Fan divisor table. Serial Bus Address Register - Index 48h Register Location： 48h Power on Default Value： 2Dh Size： 8 bits 7 6 5 4 3 2 1 0 Serial Bus Address Reserved Bit 7： Read Only - Reserved. Bit 6-0： Read/Write - Serial Bus address <6：0>. Value RAM ⎯ Index 20h- 3Fh or 60h - 7Fh （auto-increment） ADDRESS A6-A0 ADDRESS A6-A0 WITH AUTO-INCREMENT DESCRIPTION 20h 60h VCOREA reading 21h 61h VCOREB reading 22h 62h +3.3VIN reading 23h 63h +5VIN reading 24h 64h +12VIN reading 25h 65h -12VIN reading 26h 66h -5VIN reading 27h 67h VTIN1 reading 28h 68h FAN1 reading Note： This location stores the number of counts of the internal clock per revolution. 29h 69h FAN2 reading Note： This location stores the number of counts of the internal clock per revolution.

• 50 - Value RAM ⎯ Index 20h- 3Fh or 60h - 7Fh （auto-increment）, continued ADDRESS A6-A0 ADDRESS A6-A0 WITH AUTO-INCREMENT DESCRIPTION 2Ah 6Ah FAN3 reading Note： This location stores the number of counts of the internal clock per revolution. 2Bh 6Bh VCOREA High Limit, default value is defined by Vcore Voltage +0.2v. 2Ch 6Ch VCOREA Low Limit, default value is defined by Vcore Voltage -0.2v. 2Dh 6Dh VCOREB High Limit. 2Eh 6Eh VCOREB Low Limit. 2Fh 6Fh +3.3VIN High Limit 30h 70h +3.3VIN Low Limit 31h 71h +5VIN High Limit 32h 72h +5VIN Low Limit 33h 73h +12VIN High Limit 34h 74h +12VIN Low Limit 35h 75h -12VIN High Limit 36h 76h -12VIN Low Limit 37h 77h -5VIN High Limit 38h 78h -5VIN Low Limit 39h 79h Temperature sensor 1 （VTIN1） High Limit 3Ah 7Ah Temperature sensor 1 （VTIN1） Hysteresis Limit 3Bh 7Bh FAN1 Fan Count Limit Note： It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Ch 7Ch FAN2 Fan Count Limit Note： It is the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh 7Dh FAN3 Fan Count Limit Note： It is the number of counts of the internal clock for the Low Limit of the fan speed. 3E- 3Fh 7E- 7Fh Reserved Setting all ones to the high limits for voltages and fans （0111 1111 binary for temperature ） means interrupts will never be generated except the case when voltages go below the low limits. Voltage ID（VID4）& Device ID Register - Index 49h

Publication Release Date: June 09, 2006 - 51 - Revision 2.27 Register Location： 49h Power on Default Value： <7 ：1> is 000,0001 binary, <0> is mapped to VID <4> Size： 8 bits 7 6 5 4 3 2 1 0 DID<6:0> VID4 Bit 7-1： Read Only - Device ID<6：0> Bit 0 ： Read/Write - The VID4 inputs. Temperature 2 and Temperature 3 Serial Bus Address Register - Index 4Ah Register Location： 4Ah Power on Default Value： 01h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3 Bit 7： Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3. Bit 6-4： Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Bit 3： Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2. Bit 2-0： Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits.

• 52 - Pin Control Register - Index 4Bh Register Location： 4Bh Power on Default Value： 44h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1 Bit 7-6：Fan3 speed divisor. Please refer to Bank0 CR[5Dh] , Fan divisor table. Bit 5-4：Select A/D Converter Clock Input. <5：4> = 00 - default. ADC clock select 22.5 KHz. <5：4> = 01- ADC clock select 5.6 Khz.（22.5K/4） <5：4> = 10 - ADC clock select 1.4Khz.（22.5K/16） <5：4> = 11 - ADC clock select 0.35 Khz.（22.5K/64） Bit 3-2：Clock Input Select. <3：2> = 00 - Pin 3 （CLKIN） select 14.318M Hz clock. <3：2> = 01 - Default. Pin 3 （CLKIN） select 24M Hz clock. <3：2> = 10 - Pin 3 （CLKIN） select 48M Hz clock . <3：2> = 11 - Reserved. Pin3 no clock input. Bit 1-0：Reserved. User defined.

Publication Release Date: June 09, 2006 - 53 - Revision 2.27 IRQ/OVT# Property Select Register - Index 4Ch Register Location： 4Ch Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved OVTPOL DIS_OVT1 DIS_OVT2 Reserved T23_INTMode Reserved Bit 7： Reserved. User Defined. Bit 6： Set to 1, the SMI# output type of Temperature 2 and 3 is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. （default 0） Bit 5： Reserved. User Defined. Bit 4： Disable temperature sensor 3 over-temperature （OVT） output if set to 1. Default 0, enable OVT2 output through pin OVT#. Bit 3： Disable temperature sensor 2 over-temperature （OVT） output if set to 1. Default 0, enable OVT1 output through pin OVT#. Bit 2： Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1： Reserved. Bit 0： Reserved.

• 54 - FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location： 4Dh Power on Default Value： 15h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 RESERVED DIS_ABN Bit 7： Disable power-on abnormal the monitor voltage including V-Core A and +3.3V. If these voltage exceed the limit value, the pin （Open Drain） of BEEP will drives 300Hz and 600Hz frquency signal. Write 1, the frequency will be disabled. Default is 0. After power on, the system should set 1 to this bit to 1 in order to disable BEEP. Bit 6： Reserved. Bit 5： FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high sig- nal. Write 0, pin 18 always generates logic low signal. This bit default 0. Bit 4： FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0, this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. Bit 3： FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high sig- nal. Write 0, pin 19 always generates logic low signal. This bit default 0. Bit 2： FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0, this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1： FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high sig- nal. Write 0, pin 20 always generates logic low signal. This bit default 0. Bit 0： FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1.

Publication Release Date: June 09, 2006 - 55 - Revision 2.27 Register 50h ~ 5Fh Bank Select Register - Index 4Eh （No Auto Increase） Register Location： 4Eh Power on Default Value： 80h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS Bit 7： HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3： Reserved. This bit should be set to 0. Bit 2-0： Index ports 0x50~0x5F Bank select. Winbond Vendor ID Register - Index 4Fh （No Auto Increase） Register Location： 4Fh Power on Default Value： <15 ：0> = 5CA3h Attribute： Read Only Size： 16 bits 15 8 7 0 VIDH VIDL Bit 15-8： Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0： Vendor ID Low Byte if CR4E.bit7=0. Default A3h.

• 56 - Winbond Test Register - Index 50h ~ 55h （Bank 0） These registers are reserved for Winbond internal use. BEEP Control Register 1 - Index 56h （Bank 0） Register Location： 56h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 EN_VCA_BP EN_VCB_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP Bit 7： Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 6： Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 5： Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4： Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 3： Enable BEEP output from VDD （+5V）, Write 1, enable BEEP output if the monitor value ex- ceed the limits value. Default is 0, which is disable BEEP output. Bit 2： Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value. Bit 1： Enable BEEP output from VCOREB. Write 1, enable BEEP output, which is default value. Bit 0： Enable BEEP Output from VCOREA if the monitor value exceed the limits value. Write 1, en- able BEEP output, which is default value

Publication Release Date: June 09, 2006 - 57 - Revision 2.27 BEEP Control Register 2 - Index 57h （Bank 0） Register Location： 57h Power on Default Value： 80h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP EN_T3_BP Reserved EN_GBP Bit 7： Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6： Reserved. This bit should be set to 0. Bit5： Enable BEEP Output from Temperature Sensor 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4： Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Default is 0. Bit 3： Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default is 0. Bit 2： Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output. Bit 1： Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output. Bit 0： Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output.

• 58 - Chip ID Register - Index 58h （Bank 0） Register Location： 58h Power on Default Value： 21h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 CHIPID Bit 7： Winbond Chip ID number. Read this register will return 21h. Reserved Register - Index 59h （Bank 0） Register Location： 59h Power on Default Value： 70h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved Bit 7： Reserved Bit 6： Temperature sensor diode 3. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bi- polar mode. Bit 5： Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bi- polar mode. Bit 4： Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bi- polar mode. Bit 3-0： Reserved

Publication Release Date: June 09, 2006 - 59 - Revision 2.27 PWMOUT1 Control Register - Index 5Ah （Bank 0） Register Location： 5Ah Power on default value： FFh Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 PWM1_DUTY Bit 7： PWMOUT1 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. PWMOUT2 Control Register - Index 5Bh （Bank 0） Register Location： 5Bh Power on default value： FFh Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 PWM2_DUTY Bit 7： PWMOUT2 duty cycle control. Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.

• 60 - PWMOUT1/2 Clock Select Register - Index 5Ch （Bank 0） Register Location： 5Ch Power on Default Value： 11h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 PWM1CLKSEL PWM1CLKSEL PWM1CLKSEL Reserved PWM2CLKSEL PWM2CLKSEL PWM2CLKSEL Reserved Bit 7： Reserved Bit 6-4： PWMOUT2 clock selection. The clock defined frequency is same as PWMOUT1 clock selec- tion. Bit 3： Reserved Bit 2-0： PWMOUT1 clock Selection. <2：0> = 001： 23.43K Hz （Default）

Publication Release Date: June 09, 2006 - 61 - Revision 2.27 VBAT Monitor Control Register - Index 5Dh （Bank 0） Register Location： 5Dh Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 EN_VBAT_MNT DIODES1 DIODES2 DIODES3 RESERVE FANDIV1_B2 FANDIV2_B2 FANDIV3_B2 Bit 7： Fan3 divisor Bit 2. Bit 6： Fan2 divisor Bit 2. Bit 5： Fan1 divisor Bit 2. Bit 4： Reserved. Bit 3： Temperature sensor 3 select into thermal diode such as Pentium II CPU supported. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 2： Sensor 2 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 1： Sensor 1 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 0： Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83627HF hardware monitor. Fan divisor table ： BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR 0 0 0 1 1 0 0 16 0 0 1 2 1 0 1 32 0 1 0 4 1 1 0 64 0 1 1 8 1 1 1 128

• 62 - Reserved Register - Index 5Eh （Bank 0） This register is reserved. Reserved Register - Index 5Fh （Bank 0） This register is reserved. VTIN2 Reading（High Byte） - Index 50h （Bank 1） Register Location： 50h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 TEMP2<8:1> Bit 7： Temperature <8：1> of sensor 2, which is high byte. VTIN2 Reading（Low Byte）- Index 51h （Bank 1） Register Location： 51h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 TEMP2<0> Reserved Bit 7： Temperature <0> of sensor2, which is low byte. Bit 6-0： Reserved.

Publication Release Date: June 09, 2006 - 63 - Revision 2.27 VTIN2 Configuration Register - Index 52h （Bank 1） Register Location： 52h Power on Default Value 00h Size： 8 bits 7 6 5 4 3 2 1 0 STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5： Read - Reserved. This bit should be set to 0. Bit 4-3： Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2： Read - Reserved. This bit should be set to 0. Bit 1： Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0： Read/Write - When set to 1 the sensor will stop monitor. VTIN2 Hysteresis（High Byte）Register - Index 53h （Bank 1） Register Location： 53h Power on Default Value 4Bh Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 THYST2<8:1> Bit 7-0： Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

• 64 - VTIN2 Hysteresis （Low Byte） Register - Index 54h （Bank 1） Register Location： 54h Power on Default Value 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 THYST2<0> Reserved Bit 7： Hysteresis temperature bit 0, which is low Byte. Bit 6-0： Reserved. VTIN2 Over-temperature（High Byte）Register - Index 55h （Bank 1） Register Location： 55h Power on Default Value 50h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 TOVF2<8:1> Bit 7-0： Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

Publication Release Date: June 09, 2006 - 65 - Revision 2.27 VTIN2 Over-temperature（Low Byte）Register - Index 56h （Bank 1） Register Location： 56h Power on Default Value 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 TOVF2<0> Reserved Bit 7： Over-temperature bit 0, which is low Byte. Bit 6-0： Reserved. VTIN3 Reading（High Byte）Register - Index 50h （Bank 2） Register Location： 50h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 TEMP2<8:1> Bit 7-0： Temperature <8：1> of sensor 2, which is high byte.

• 66 - VTIN3 Reading（Low Byte）Register - Index 51h （Bank 2） Register Location： 51h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 TEMP2<0> Reserved Bit 7： Temperature <0> of sensor2, which is low byte. Bit 6-0： Reserved. VTIN3 Configuration Register - Index 52h （Bank 2） Register Location： 52h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5： Read - Reserved. This bit should be set to 0. Bit 4-3： Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2： Read - Reserved. This bit should be set to 0. Bit 1： Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0： Read/Write - When set to 1 the sensor will stop monitor.

Publication Release Date: June 09, 2006 - 67 - Revision 2.27 VTIN3 Hysteresis（High Byte）Register - Index 53h （Bank 2） Register Location： 53h Power on Default Value： 4Bh Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 THYST3<8:1> Bit 7-0： Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. VTIN3 Hysteresis（Low Byte）Register - Index 54h （Bank 2） Register Location： 54h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 THYST3<0> Reserved Bit 7： Hysteresis temperature bit 0, which is low Byte. Bit 6-0： Reserved.

• 68 - VTIN3 Over-temperature（High Byte）Register - Index 55h （Bank 2） Register Location： 55h Power on Default Value： 50h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 TOVF3<8:1> Bit 7-0： Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. VTIN3 Over-temperature（Low Byte）Register - Index 56h（Bank 2） Register Location： 56h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 TOVF3<0> Reserved Bit 7： Over-temperature bit 0, which is low Byte. Bit 6-0： Reserved.

Publication Release Date: June 09, 2006 - 69 - Revision 2.27 Interrupt Status Register 3 - Index 50h （BANK4） Register Location： 50h Power on Default Value： 00h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2： Reserved. Bit 1： A one indicates a High or Low limit of VBAT has been exceeded. Bit 0： A one indicates a High or Low limit of 5VSB has been exceeded. SMI# Mask Register 3 - Index 51h （BANK 4） Register Location： 51h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2： Reserved. Bit 1： A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0： A one disables the corresponding interrupt status bit for SMI interrupt.

• 70 - Reserved Register - Index 52h （Bank 4） This register is reserved for Winbond internal use. BEEP Control Register 3 - Index 53h （Bank 4） Register Location： 53h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Bit 7-6： Reserved. Bit 5： User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. （Default 0） Bit 4-2： Reserved. Bit 1： Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value. Bit 0： Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value. Temperature Sensor 1 Offset Register - Index 54h （Bank 4） Register Location： 54h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 OFFSET1<7:0> Bit 7-0： Temperature 1 base temperature. The tem perature is added by both monitor value and off- set value.

Publication Release Date: June 09, 2006 - 71 - Revision 2.27 Temperature Sensor 2 Offset Register - Index 55h （Bank 4） Register Location： 55h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 OFFSET2<7:0> Bit 7-0：Temperature 2 base temperature. The temperature is added by both monitor value and offset value. Temperature Sensor 3 Offset Register - Index 56h （Bank 4） Register Location： 56h Power on Default Value： 00h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 OFFSET3<7:0> Bit 7-0： Temperature 3 base temperature. The temperature is added by both monitor value and off- set value. Reserved Register - Index 57h ~ 58h These registers are reserved for Winbond internal use.

• 72 - Real Time Hardware Status Register I - Index 59h （Bank 4） Register Location： 59h Power on Default Value： 00h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 VCOREA_STS VCOREB_STS +3.3VIN_STS +5VIN_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS Bit 7： FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6： FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5： Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4： Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 3： +5V Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Bit 2： +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Bit 1： VCOREB Voltage Status. Set 1, the voltage of VCOREB is over the limit value. Set 0, the volt- age of VCOREB is in the limit range. Bit 0： VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the voltage of VCORE A is in the limit range.

Publication Release Date: June 09, 2006 - 73 - Revision 2.27 Real Time Hardware Status Register II - Index 5Ah （Bank 4） Register Location： 5Ah Power on Default Value： 00h Attribute： Read Only Size： 8 bits 7 6 5 4 3 2 1 0 +12VIN_STS -12VIN_STS -5VIN_STS FAN3_STS CASE_STS TEMP3_STS Reserved Reserved Bit 7-6： Reserved Bit 5： Temperature sensor 3 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4： Case Open Status. Acts like Index 42[4], when Chassis Intrusion Event occurs, this bit will be set 1. Until the event is cleared, this bit returns to 0. Bit 3： FAN3 Voltage Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Bit 2： -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Bit 1： -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of - 12V is during the limit range. Bit 0： +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range. Real Time Hardware Status Register III - Index 5Bh （Bank 4） Register Location： 5Bh Power on Default Value： 00h Attribute： Read Only Size： 8 bits

• 74 - 7 6 5 4 3 2 1 0 5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2： Reserved. Bit 1： VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Bit 0： 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range. Reserved Register - Index 5Ch （Bank 4） This register is reserved for Winbond internal use. VID Output Register - Index 5Dh （Bank 4） Register Location： 5Dh Power on Default Value： <7 ：0> = 0000,0000h Attribute： Read/Write Size： 8 bits 7 6 5 4 3 2 1 0 VIDOUT_0 VIDOUT_1 VIDOUT_2 VIDOUT_3 VIDOUT_4 Reserved Reserved VIDOUT_EN Bit 7： VID Output Enable. Set 1, enable VID pins to out put. Set 0, disable VID pins to output. Default is 0. Bit 6-5： Reserved. Bit 4-0： Set 1, VID pins drive a 1 . Set 0, VID pins drive a 0. Default is 0.

Publication Release Date: June 09, 2006 - 75 - Revision 2.27 Value RAM 2⎯ Index 50h - 5Ah （auto-increment） （BANK 5） ADDRESS A6-A0 AUTO-INCREMENT

DESCRIPTION

55h 5VSB Low Limit. 56h VBAT High Limit 57h VBAT Low Limit Winbond Test Register - Index 50h （Bank 6） This register is reserved for Winbond internal use.

• 76 - 8. SERIAL IRQ W83627HF supports a serial IRQ scheme. This allo ws a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock sour ce is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame.

8.1 Start Frame

There are two modes of operation for the IRQSER Start frame： Quiet mode and Continuous mode. In the Quiet mode, the peripheral drives the SER IRQ signal active low for one clock, and then tri- states it. This brings all the states machines of the peripherals from idle to active states. The host con- troller will then take over driving IRQSER signal low in the next clock and will continue driving the IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4 to 8 clock periods. After these clocks, the host cont roller will drive the IRQSER high for one clock and then tri-states it. In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line in- formation. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset, the IRQSER signal is defaulted to the Continuous mode fo r the host controller to initiate the first Start frame.

8.2 IRQ/Data Frame

Once the start frame has been initiated, all the peripherals must start counting frames based on the rsing edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SER IRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. Duri ng the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 8-1.

Publication Release Date: June 09, 2006 - 77 - Revision 2.27 Table 8-1 IRQSER Sampling periods IRQ/DATA FRAME SIGNAL SAMPLED # OF CLOCKS PAST START

1 IRQ0 2

2 IRQ1 5

3 SMI 8

4 IRQ3 11

5 IRQ4 14

6 IRQ5 17

7 IRQ6 20

8 IRQ7 23

9 IRQ8 26

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41

15 IRQ14 44

16 IRQ15 47

17 IOCHCK 50

18 INTA 53

19 INTB 56

20 INTC 59

21 INTD 62

32：22 Unassigned 95

8.3 Stop Frame

After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the next IRQSER cycl e's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode.

• 78 - 9. CONFIGURATION REGISTER

9.1 Plug and Play Configuration

The W83627HF/F uses Compatible PNP protocol to access configuration registers for setting up dif- ferent types of configurations. In W 83627HF/F, there are eleven Logical Devices （from Logical De- vice 0 to Logical Device B with the excepti on of logical device 4 for backward compatibility ）which correspond to eleven individual functions ： FDC （logical device 0 ）, PRT （logical device 1 ）, UART1 （logical device 2 ）, UART2（logical device 3 ）, KBC（logical device 5 ）, CIR（Consumer IR, logical device 6）, GPIO1（logical device 7）, GPIO2（logical device 8）, GPIO3（logical device 9）, ACPI （logical device A）, and hardware monitor （logical device B）. Each Logical Device has its own configuration registers （above CR30）. Host can access those registers by writing an appro- priate logical device number into logical device select register at CR7.

9.1.1 Compatible PnP

9.1.1.1 Extended Function Registers

In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS（CR26 bit 6）can be used to select one out of t hese two methods of entering the Extended Function mode as follows： HEFRAS ADDRESS AND VALUE 0 write 87h to the location 2Eh twice 1 write 87h to the location 4Eh twice After Power-on reset, the value on RTSA （pin 51）is latched by HEFRAS of CR26. In Compatible PnP, a specific value （87h）must be written twice to the Extended Functions Enable Register （I/O port address 2Eh or 4Eh ）. Secondly, an index value （02h, 07h ~ FFh ）must be written to the Ex- tended Functions Index Register （I/O port address 2Eh or 4Eh same as Extended Functions Enable Register）to identify which configuration register is to be accessed. The designer can then access the desired configuration register thr ough the Extended Functions Data Register （I/O port address 2Fh or 4Fh）. After programming of the configuration r egister is finished, an additional value （AAh）should be writ- ten to EFERs to exit the Extended Function mode to prevent unintentional access to those configura-

Publication Release Date: June 09, 2006 - 79 - Revision 2.27 tion registers. The designer can also set bit 5 of CR26 （LOCKREG）to high to protect the configura- tion registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset （pin MR = 1）. A warm reset will not affect the configuration registers.

9.1.1.2 Extended Functions Enable Registers （EFERs）

After a power-on reset, the W83627HF/F enters t he default operating mode. Before the W83627HF /Fenters the extended function mode, a specific va lue must be programmed into the Extended Func- tion Enable Register（EFER）so that the extended function regi ster can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh （as described in previous section）.

9.1.1.3 Extended Function Index Registers （EFIRs）, Extended Function Data Registers

（EFDRs） After the extended function mode is enter ed, the Extended Function Index Register （EFIR）must be loaded with an index value （02h, 07h-FEh） to access Configuration Register 0 （CR0）, Configura- tion Register 7 （CR07）to Configuration Register FE （CRFE）, and so forth through the Extended Function Data Register （EFDR）. The EFIRs are write-only registers with port address 2Eh or 4Eh （as described in section 12.2.1 ）on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh （as described in section 9.2.1） on PC/AT systems.

9.1.2 Configuration Sequence

To program W83627HF/F configuration registers, the following configuration sequence must be followed： （1） Enter the extended function mode （2） Configure the configuration registers （3） Exit the extended function mode

9.1.2.1 Enter the extended function mode

To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers（EFERs, i.e. 2Eh or 4Eh）.

9.1.2.2 Configurate the configuration registers

The chip selects the logical device and activate s the desired logical devices through Extended Func- tion Index Register（EFIR） and Extended Function Data Register （EFDR）. EFIR is located at the same address as EFER, and EFDR is located at address （EFIR+1）. First, write the Logical Device Number （i.e.,0x07）to the EFIR and then write the number of the de- sired logical device to the EFDR. If accessing the Chip （Global）Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write （or read） the desired configuration register through EFDR.

• 80 -

9.1.2.3 Exit the extended function mode

To exit the extended function mode, one write of 0xAA to EFER is requi red. Once the chip exits the extended function mode, it is in the normal runni ng mode and is ready to enter the configuration mode.

9.1.2.4 Software programming example

The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2E h and EFDR is located at 2Fh. If HEFRAS （CR26 bit 6）is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ; Enter the extended function mode ,interruptible double-write | MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ; Configurate logical device 1, configuration register CRF0 | MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ; Exit extended function mode | MOV DX,2EH MOV AL,AAH OUT DX,AL

Publication Release Date: June 09, 2006 - 81 - Revision 2.27

9.2 Chip （Global）Control Register

CR02 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 0 SWRST --> Soft Reset. CR07 Bit 7 - 0 ： Logical Device Number CR20 Bit 7 - 0 ： Device ID = 0x52 （read only）. CR21 Bit 7 - 0 ： Device Rev （read only）. VERSION DEVICE REV G 17 J 3A UD-A 41 CR22 （Default 0xff） BIT DESCRIPTION 7 Reserved.

6 HMPWD

0： Power down 1： No Power down

5 URBPWD

0： Power down 1： No Power down

4 URAPWD

0： Power down 1： No Power down

3 PRTPWD

0： Power down 1： No Power down 2 - 1 Reserved.

0 FDCPWD

0： Power down 1： No Power down

• 82 - CR23 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 0 IPD （Immediate Power Down）. When set to 1, it will put the whole chip into power down mode immediately. CR24 （Default 0b1s000s0s） BIT DESCRIPTION

7 EN16SA

0： 12 bit Address Qualification 1： 16 bit Address Qualification

6 CLKSEL

0： The clock input on Pin 1 should be 24 Mhz. 1： The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB （pin 83）. 5 - 3 Reserved

2 ENKBC（Read Only）

0： KBC is disabled after hardware reset. 1： KBC is enabled after hardware reset. This bit is set/reset by power-on setting pin SOUTA（pin 54）.

1 Reserved

0 PNPCVS

0： The Compatible PnP address select registers have default values. 1： The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCVS must be complemen- tary to the old one to make an effective change. For example, the user must set PNPCVS to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCVS is 1. The corresponding power-on setting pin is NDTRA （pin 52）. CR25 （Default 0x00） BIT DESCRIPTION 7 - 6 Reserved 5 URBTRI. UART2 output pin tri-stated. 4 URATRI. UART1 output pin tri-stated. 3 PRTTRI. Parallel port output pin tri-stated. 2 - 1 Reserved 0 FDCTRI. FDC output pin tri-stated.

Publication Release Date: June 09, 2006 - 83 - Revision 2.27 CR26 （Default 0b0s000000） BIT DESCRIPTION

7 SEL4FDD

0： Select two FDD mode. 1： Select four FDD mode.

6 HEFRAS

These two bits define how to enable Confi guration mode. The corresponding power-on setting pin is NRTSA （pin 51）. HEFRAS Address and Value 0： Write 87h to the location 2E twice. 1： Write 87h to the location 4Etwice.

5 LOCKREG

0： Enable R/W Configuration Registers 1： Disable R/W Configuration Registers.

4 Reserve

3 DSFDLGRQ

0： Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effec- tive on selecting IRQ 1： Disable FDC legacy mode on IRQ and DRQ sele ction, then DO register bit 3 is not effective on selecting IRQ

2 DSPRLGRQ

0： Enable PRT legacy mode on IRQ and DRQ sele ction, then DCR bit 4 is effective on selecting IRQ 1： Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effec- tive on selecting IRQ

1 DSUALGRQ

0： Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on select- ingIRQ 1： Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on se- lecting IRQ

0 DSUBLGRQ

0： Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ 1： Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on se- lecting IRQ

• 84 - CR28 （Default 0x00） BIT DESCRIPTION 7 - 3 Reserved. 2 - 0 PRTMODS2 - PRTMODS0 0xx： Parallel Port Mode 100： Reserved 101： External FDC Mode 110： Reserved 111： External two FDC Mode CR29 （GPIO3 multiplexed pin selection register. VBAT powered. Default 0x00） BIT DESCRIPTION

7 PIN64S

0： SUSLED （SUSLED control bits are in CRF3 of Logical Device 9） 1： GP35

6 PIN69S

0： CIRRX# 1： GP34

5 PIN70S

0： RSMRST# 1： GP33

4 PIN71S

0： PWROK 1： GP32

3 PIN72S

0： PWRCTL# 1： GP31

2 PIN 73S

0： SLP_SX# 1： GP30

0 Reserved

Publication Release Date: June 09, 2006 - 85 - Revision 2.27 CR2A （GPIO multiplexed pin selection register 1. VCC powered. Default 0X7C） BIT DESCRIPTION

7 Port Select（select Game Port or General Purpose I/O Port 1）

0： Game Port 1： General Purpose I/O Port 1（pin121~128 select function GP10~GP17 or KBC Port

6 PIN128S

0： 8042 P12 1： GP10

5 PIN127S

0： 8042 P13 1： GP11

4 PIN126S

0： 8042 P14 1： GP12

3 PIN125S

0： 8042 P15 1： GP13

2 PIN124S

0： 8042 P16 1： GP14

1 PIN120S

0： MSO （MIDI Serial Output） 1： IRQIN0 （select IRQ resource through CRF4 Bit 7-4 of Logical Device 8）

1 PIN119S

0： MS1 （MIDI Serial Input） 1： GP20

• 86 - CR2B（GPIO multiplexed pin selection register 2. VCC powered. Default 0XC0） BIT DESCRIPTION

7 PIN92S

0： SCL 1： GP21

6 PIN91S

0： SDA 1： GP22

5 PIN90S

0： PLED （PLED0 control bits are in CRF5 of Logical Device 8） 1： GP23

4 PIN89S

0： WDTO （Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device 1： GP24

3 PIN88S

0： IRRX 1： GP25

2 PIN87S

0： IRTX 1： GP26 1-0 PIN 2S 00： DRVDEN1 01： SMI# 10： IRQIN1（select IRQ resource through CRF4 Bit 7-4 of Logical Device8） 11： GP27 CR2C （Default 0x00） Reserved CR2E （Default 0x00） Test Modes ： Reserved for Winbond. CR2F （Default 0x00） Test Modes ： Reserved for Winbond.

Publication Release Date: June 09, 2006 - 87 - Revision 2.27

9.3 Logical Device 0 （FDC）

CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 1 Reserved.

0 Logic device activation control

1： Active 0： Inactived CR60, CR 61 （Default 0x03, 0xf0 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select FDC I/O base address [0x100 ：0xFF8] on 8 bytes boundary. CR70 （Default 0x06 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for FDC. CR74 （Default 0x02 if PNPCVS = 0 during POR, default 0x04 otherwise） BIT DESCRIPTION 7 - 3 Reserved. 2 - 0 These bits select DRQ resource for FDC. 000： DMA0 001： DMA1 010： DMA2 011： DMA3 100 ~ 111： No DMA active

• 88 - CRF0 （Default 0x0E） FDD Mode Register BIT DESCRIPTION

7 FIPURDWN

This bit controls the internal pull-up resi stors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. 0： The internal pull-up resistors of FDC are turned on.（Default） 1： The internal pull-up resistors of FDC are turned off.

6 INTVERTZ

This bit determines the polarity of all FDD interface signals. 0： FDD interface signals are active low. 1： FDD interface signals are active high.

5 DRV2EN （PS2 mode only）

When this bit is a logic 0, indicates a second dr ive is installed and is reflected in status register A.

4 Swap Drive 0, 1 Mode

0： No Swap （Default） 1： Drive and Motor sel 0 and 1 are swapped. 3 - 2 Interface Mode 11： AT Mode （Default） 10： Reserved 01： PS/2 00： Model 30

1 FDC DMA Mode

0： Burst Mode is enabled 1： Non-Burst Mode （Default）

0 Floppy Mode

0： Normal Floppy Mode （Default） 1： Enhanced 3-mode FDD

Publication Release Date: June 09, 2006 - 89 - Revision 2.27 CRF1 （Default 0x00） BIT DESCRIPTION 7 - 6 Boot Floppy 00： FDD A 01： FDD B 10： FDD C 11： FDD D 5 - 4 Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 3 - 2 Density Select 00： Normal （Default） 01： Normal 10： 1 （Forced to logic 1） 11： 0 （Forced to logic 0）

1 DISFDDWR

0： Enable FDD write. 1： Disable FDD write（forces pins WE, WD stay high）.

0 SWWP

0： Normal, use WP to determine whether the FDD is write protected or not. 1： FDD is always write-protected. CRF2 （Default 0xFF） BIT DESCRIPTION 7 - 6 FDD D Drive Type 5 - 4 FDD C Drive Type 3 - 2 FDD B Drive Type 1 - 0 FDD A Drive Type

• 90 - CRF4 （Default 0x00） FDD0 Selection： BIT DESCRIPTION 7 Reserved. 6 Precomp. Disable. 1： Disable FDC Precompensation. 0： Enable FDC Precompensation. 5 Reserved. 4 - 3 DRTS1, DRTS0： Data Rate Table select （Refer to TABLE A）. 00： Select Regular drives and 2.88 format 01： 3-mode drive 10： 2 Meg Tape 11： Reserved 2 Reserved. 1 - 0 DTYPE0, DTYPE1： Drive Type select （Refer to TABLE B）. CRF5 （Default 0x00） FDD1 Selection： Same as FDD0 of CRF4. TABLE A DRIVE RATE TABLE SELECT DATA RATE SELECTED DATA RATE SELDEN DRTS1 DRTS0 DRATE1 DRATE0 MFM FM 1 1 1Meg --- 1 0 0 0 0 500K 250K 1 0 1 300K 150K 0 1 0 250K 125K 0 1 1 1Meg --- 1 0 1 0 0 500K 250K 1 0 1 500K 250K 0 1 0 250K 125K 0 1 1 1Meg --- 1 1 0 0 0 500K 250K 1 0 1 2Meg --- 0 1 0 250K 125K 0

Publication Release Date: June 09, 2006 - 91 - Revision 2.27 TABLE B DTYPE0 DTYPE1 DRVDEN0（pin 1） DRVDEN1（pin 2） DRIVE TYPE 0 0 SELDEN DRATE0 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” （3-MODE） 0 1 DRATE1 DRATE0 1 0 SELDEN DRATE0 1 1 DRATE0 DRATE1

9.4 Logical Device 1 （Parallel Port）

CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactived CR60, CR 61 （Default 0x03, 0x78 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select Parallel Port I/O base address. [0x100 ：0xFFC] on 4 byte boundary（EPP not supported）or [0x100：0xFF8] on 8 byte bounda （all modes supported, EPP is only available when the base address is on 8 byte boundary）. CR70 （Default 0x07 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for Parallel Port. CR74 （Default 0x04） BIT DESCRIPTION 7 - 3 Reserved. 2 - 0 These bits select DRQ resource for Parallel Port. 000： DMA0 001： DMA1 010： DMA2 011： DMA3 100 ~ 111： No DMA active

• 92 - CRF0 （Default 0x3F） BIT DESCRIPTION 7 Reserved. 6 - 3 ECP FIFO Threshold. 2 - 0 Parallel Port Mode （CR28 PRTMODS2 = 0） 100：Printer Mode （Default） 000：Standard and Bi-direction（SPP）mode 001：EPP - 1.9 and SPP mode 101：EPP - 1.7 and SPP mode 010：ECP mode 011：ECP and EPP - 1.9 mode 111：ECP and EPP - 1.7 mode

Publication Release Date: June 09, 2006 - 93 - Revision 2.27

9.5 Logical Device 2 （UART A）

CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactived CR60, CR 61 （Default 0x03, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select Serial Port 1 I/O base address [0x100 ：0xFF8] on 8 byte boundary. CR70 （Default 0x04 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for Serial Port 1. CRF0 （Default 0x00） BIT DESCRIPTION 7 - 2 Reserved. 1 - 0 SUACLKB1, SUACLKB0 00： UART A clock source is 1.8462 Mhz （24MHz/13） 01： UART A clock source is 2 Mhz （24MHz/12） 10： UART A clock source is 24 Mhz （24MHz/1） 11： UART A clock source is 14.769 Mhz （24mhz/1.625）

• 94 -

9.6 Logical Device 3 （UART B）

CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactived CR60, CR 61 （Default 0x02, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select Serial Port 2 I/O base address [0x100 ：0xFF8] on 8 byte boundary. CR70 （Default 0x03 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for Serial Port 2. CRF0 （Default 0x00） BIT DESCRIPTION 7 - 4 Reserved.

3 RXW4C

0： No reception delay when IR is changed from TX mode to RX mode. 1： Reception delays 4 characters time （40 bit-time） when SIR is changed from TX mode to RX mode.

2 TXW4C

0： No transmission delay when SIR is changed from RX mode to TX mode. 1： Transmission delays 4 characters time （40 bit-time） when SIR is changed from RX mode to TX mode. 1 - 0 SUBCLKB1, SUBCLKB0 00： UART B clock source is 1.8462 Mhz （24MHz/13） 01： UART B clock source is 2 Mhz （24MHz/12） 10： UART B clock source is 24 Mhz （24MHz/1） 11： UART B clock source is 14.769 Mhz （24mhz/1.625）

Publication Release Date: June 09, 2006 - 95 - Revision 2.27 CRF1 （Default 0x00） BIT DESCRIPTION 7 Reserved. 6 IRLOCSEL. IR I/O pins' location select. 0： Through SINB/SOUTB. 1： Through IRRX/IRTX. 5 IRMODE2. IR function mode selection bit 2. 4 IRMODE1. IR function mode selection bit 1. 3 IRMODE0. IR function mode selection bit 0. IR MODE IR FUNCTION IRTX IRRX 00X Disable tri-state high 010* IrDA Active pulse 1.6 μS Demodulation into SINB/IRRX 011* IrDA Active pulse 3/16 bit time Demodulation into SINB/IRRX

100 ASK-IR Inverting IRTX/SOUTB pin routed to

101 ASK-IR Inverting IRTX/SOUTB & 500 KHZ clock routed to

110 ASK-IR Inverting IRTX/SOUTB Demodulation into

111* ASK-IR Inverting IRTX/SOUTB & 500 KHZ clock Demodulation into SINB/IRRX Note： The notation is normal mode in the IR function. BIT DESCRIPTION 2 HDUPLX. IR half/full duplex function select. 0： The IR function is Full Duplex. 1： The IR function is Half Duplex.

1 TX2INV

0： the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1： inverse the SOUTB pin of UART B function or IRTX pin of IR function. 0 RX2INV. 0： the SINB pin of UART B function or IRRX pin of IR function in normal condition. 1： Inverse the SINB pin of UART B function or IRRX pin of IR function

• 96 -

9.7 Logical Device 5 （KBC）

CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 1 Reserved. 0 Logic device activation control. 1： Active 0： Inactived CR60, CR 61 （Default 0x00, 0x60 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the first KBC I/O base address [0x100 ：0xFFF] on 1 byte boundary. CR62, CR 63 （Default 0x00, 0x64 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the second KBC I/O base address [0x100 ：0xFFF] on 1 byte boundary. CR70 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for KINT （keyboard）. CR72 （Default 0x0C if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for MINT （PS2 Mouse） CRF0 （Default 0x80） BIT DESCRIPTION 7 - 6 KBC clock rate selection 00： Select 6MHz as KBC clock input. 01： Select 8MHz as KBC clock input. 10： Select 12Mhz as KBC clock input. 11： Select 16Mhz as KBC clock input. 5 - 3 Reserved. 2 0： Port 92 disable. 1： Port 92 enable. 1 0： Gate20 software control. 1： Gate20 hardware speed up. 0 0： KBRST software control. 1： KBRST hardware speed up.

Publication Release Date: June 09, 2006 - 97 - Revision 2.27

9.8 Logical Device 6 （CIR）

CR30 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactived CR60, CR 61 （Default 0x00, 0x00） These two registers select CIR I/O base address [0x100 ：0xFF8] on 8 byte boundary. CR70 （Default 0x00） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for CIR.

9.9 Logical Device 7 （Game Port, MIDI Port and GPIO Port 1）

CR30 （Default 0x00） BIT DESCRIPTION 7 - 3 Reserved

2 MIDI Port activation control

1： Enable（MIDI Port will be active individually even though CR30[0] is set “0”） 0： Disbale

1 Game Port activation control

1： Enable（Game Port will be active individually even though CR30[0] is set “0”） 0： Disable 1： Active 0： Inactived CR60, CR 61 （Default 0x02, 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the Game Port base address [0x100 ：0xFFF] on 1 byte boundary. CR62, CR 63 （Default 0x03, 0x30 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select t he MIDI Port base address [0x100：0xFFF] on 2 byte boundary.

• 98 - CR70 （Default 0x09 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for MIDI Port. CRF0 （GP10-GP17 I/O selection register. Default 0xFF） When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 （GP10-GP17 data register. Default 0x00） If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 （GP10-GP17 inversion register. Default 0x00） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 （Reserved） This register is reserved.

9.10 Logical Device 8 （GPIO Port 2 and Watch Dog Timer）

CR30 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactive CRF0 （GP20-GP27 I/O selection register. Default 0xFF） When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 （GP20-GP27 data register. Default 0x00） If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 （GP20-GP27 inversion register. Default 0x00） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.

Publication Release Date: June 09, 2006 - 99 - Revision 2.27 CRF3 （Default 0x00） BIT DESCRIPTION 7 - 4 These bits select IRQ resource for IRQIN1. 3 - 0 These bits select IRQ resource for IRQIN0. CRF4 （Reserved） This register is reserved.. CRF5 （PLED mode register. Default 0x00） BIT DESCRIPTION 7 - 6 PLED mode select 00： Power LED pin is tri-stated. 01： Power LED pin is drived low. 10： Power LED pin is a 1Hz toggle pulse with 50 duty cycle 11： Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. 5 - 4 Reserved

3 WDTO count mode select

0： Second 1： Minute 2 Enable the rising edge of keyboard Reset（P20）to force Time-out event. 0： Disable 1： Enable 1 - 0 Reserved CRF6 （Default 0x00） Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set, any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previ- ously-loaded non-zero value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. BIT DESCRIPTION 7 - 0 0x00 Time-out Disable 0x01 Time-out occurs after 1 sec / min 0x02 Time-out occurs after 2 sec / min 0x03 Time-out occurs after 3 sec / min 0xFF Time-out occurs after 255 sec / min

• 100 - CRF7 （Default 0x00） BIT DESCRIPTION

7 Mouse interrupt reset Enable or Disable

1： Watch Dog Timer is reset upon a Mouse interrupt 0： Watch Dog Timer is not affected by Mouse interrupt

6 Keyboard interrupt reset Enable or Disable

1： Watch Dog Timer is reset upon a Keyboard interrupt 0： Watch Dog Timer is not affected by Keyboard interrupt

5 Force Watch Dog Timer Time-out, Write only

1： Force Watch Dog Timer time-out event; this bit is self-clearing.

4 Watch Dog Timer Status, R/W

1： Watch Dog Timer time-out occurred 0： Watch Dog Timer counting 3 -0 These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.

9.11 Logical Device 9 （GPIO Port 3, VSB powered）

CR30 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved 1： Active 0： Inactived CRF0 （GP30-GP35 I/O selection register. Default 0xFF Bit 7-6： Reserve） When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 （GP30-GP35 data register. Default 0x00 Bit 7-6： Reserve） If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 （GP30-GP35 inversion register. Default 0x00 Bit 7-6： Reserve） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.

Publication Release Date: June 09, 2006 - 101 - Revision 2.27 CRF3 （SUSLED mode register. Default 0x00） BIT DESCRIPTION 7-6 Select Suspend LED mode.（VSB powered） 00： Suspend LED pin is drived low. 01： Suspend LED pin is tri-stated. 10： Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle. 11： Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle. 5 - 0 Reserved.

9.12 Logical Device A （ACPI）

CR30 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactive CR70 （Default 0x00） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resources for PME . CRE0 （Default 0x00） BIT DESCRIPTION 7 DIS-PANSW_IN. Disable panel switch input to turn system power supply on. 0： PANSW_IN is wire-ANDed and connected to PANSW_OUT. 1： PANSW_IN is blocked and can not affect PANSW_OUT. 6 ENKBWAKEUP. Enable Keyboard to wake-up system via PANSW_OUT. 0： Disable Keyboard wake-up function. 1： Enable Keyboard wake-up function. 5 ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT. 0： Disable Mouse wake-up function. 1： Enable Mouse wake-up function. 4 MSRKEY. Select Mouse Left/Right Botton to wake-up system via PANSW_OUT. 0： Select click on Mouse Left-botton to wake the system up. 1： Select click on Mouse right-botton to wake the system up.

• 102 - CRE0 （Default 0x00）, continued BIT DESCRIPTION 3 ENCIRWAKEUP. Enable CIR to wake-up system via PANSW_OUT. 0： Disable CIR wake-up function. 1： Enable CIR wake-up function. 2 KB/MS Swap. Enable Keyboard/Mouse port-swap. 0： Keyboard/Mouse ports are not swapped. 1： Keyboard/Mouse ports are swapped. 1 MSXKEY. Select either single or double click to wake-up the system. 0： Indicates mouse double click can wake the system up. 1： Indicates mouse single click can wake the system up. 0 KBXKEY. Enable any character received from Keyboard to wake-up the system 0： Only predetermined specific key combination can wake up the system. 1： Any character received from Keyboard can wake up the system. CRE1（Default 0x00）Keyboard Password Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or predetermined key Reg- ister is to be read or written via CRE2. CRE2 Keyboard Password Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. W83627HF supports at most 5-key password wake-up function. CRE1 is an index register to indi- cate which byte of key code storage (0X00 ~ 0X0E) is going to be read or written. According to IBM 101/102 keyboard specification, a complete key code contains a 1-byte make code and a 2- byte break code. For example.The make code of Key “0” is 0x45, and the corresponding break code is 0xF0, 0x45. The approach to implement Keyboard Password Wake-up function is to fill key codes into the password storage. Assume that we want to set “012” as the password. The storage must be filled as below. Please note that index 0x09 ~ 0x0e must be filled as 0x00 since the pass- word has only three words. IndexÆ 00 01 02 03 04 05 06 07 08 09 0A 1B 0C 0D 0E DataÆ 1E F0 1E 16 F0 16 45 F0 45 00 00 00 00 00 00 First-pressed key “0” Second-pressed key “1” Third-pressed key “2”

Publication Release Date: June 09, 2006 - 103 - Revision 2.27 CRE3 Keyboard/Mouse Wake-Up Status Register（Read Only） BIT DESCRIPTION 7-6 Reserved. 5 When 1 is VSB Power Loss status. 4 PWRLOSS_STS. This bit is set when power loss occurs. This bit is control by CRE4[7] 3 CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by reading this register. 2 PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by reading this register. 1 MOUSE_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. 0 KB_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. CRE4 （Default 0x00） BIT DESCRIPTION 7 Power loss control bit 2. 0： Indicates that PWRCTL#（Pin 72）outputs logic low after PSOUT# issues a low pluse. 1： Indicates that PWRCTL# will output logic low after resum from AC power loss if SLP_SX（Pin 73）is logic high. 6-5 Power loss control bit <1：0> 00： System always turn off when come back from power loss state. 01： System always turn on when come back from power loss state. 10： System turn on/off when come back from power loss state depend on the state before power loss. 11： Reserved.

4 Suspend clock source select

0： Use internal clock source. 1： Use external suspend clock source（32.768KHz）. 3 Keyboard wake-up type select for wake-up the system from S1/S2. 0： Password or Hot keys programmed in the registers. 1： Any key. 2 Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs. 0： Disable. 1： Enable. 1 - 0 Reserved.

• 104 - CRE5 （Default 0x00） BIT DESCRIPTION

7 Reserved

6 - 0 Compared Code Length. When the compar ed codes are storaged in the data register, these data length should be written to this register. CRE6 （Default 0x00） BIT DESCRIPTION 6 Chassis Status Clear.（availibale for A Version only） 1： Clear CASEOPEN#（Pin 76）event. 0： Disable clear function. Set this bit to “1” will make hardware monitor register index 42, bit 4 cleared unceas- ingly. Therefore, next Case-open Event can not be triggered again until this bit Is cleared to “0”. This bit is available for W83627HF A Version only, please refer to Hard- ware Monitor Register Index 46, bit 7 for other version. 5 - 0 CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz divided by（ CIR Baud Rate Divisor + 1）. CRE7 （Default 0x00） BIT DESCRIPTION 7 Reaerved. 6 Reserved. 5 Reserved. 4 Reserved. 3 SELWDTORST. Watch Dog Timer Reset Control. 0： Indicates that Watch Dog Timer is reset by LPC_RST. 1： Indicates that Watch Dog Timer is reset by PWR_OK. 2 Reset CIR Power-On function. After usi ng CIR power-on, the software should write logical 1 to restart CIR power-on function. 1 Invert RX Data. 1： Inverting RX Data. 0： Not inverting RX Data. 0 Enable Demodulation. 1： Enable received signal to demodulate. 0： Disable received signal to demodulate.

Publication Release Date: June 09, 2006 - 105 - Revision 2.27 CRF0 （Default 0x00） BIT DESCRIPTION 7 CHIPPME. Chip level auto power management enable. 0： Disable the auto power management functions 1： Enable the auto power management functions. 6 CIRPME. Consumer IR port auto power management enable. 0： Disable the auto power management functions 1： Enable the auto power management functions. 5 MIDIPME. MIDI port auto power management enable. 0： Disable the auto power management functions 1： Enable the auto power management functions. 4 Reserved. Return zero when read. 3 PRTPME. Printer port auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. 2 FDCPME. FDC auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. 1 URAPME. UART A auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. 0 URBPME. UART B auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. CRF1 （Default 0x00） BIT DESCRIPTION WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sl eeping/working state machine will transition the system to the working stat e. This bit is only set by hardware and is cleared by writ- ing a 1 to this bit position or by the sl eeping/working state machine automatically when the global standby timer expires. 0： the chip is in the sleeping state. 1： the chip is in the working state. 6 - 5 Devices' trap status. 4 Reserved. Return zero when read. 3 - 0 Devices' trap status.

• 106 - CRF3 （Default 0x00） BIT DESCRIPTION 7 - 6 Reserved. Return zero when read. 5 - 0 Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. 5 MOUIRQSTS. MOUSE IRQ status. 4 KBCIRQSTS. KBC IRQ status. 3 PRTIRQSTS. printer port IRQ status. 2 FDCIRQSTS. FDC IRQ status. 1 URAIRQSTS. UART A IRQ status. 0 URBIRQSTS. UART B IRQ status. CRF4 （Default 0x00） BIT DESCRIPTION 7 - 6 Reserved. Return zero when read. 5 - 0 These bits indicate the IRQ status of the individual GPIO function or logical device re- spectively. The status bit is set by their source function or device and is cleared by writ- ing a1. Writing a 0 has no effect. 5 HMIRQSTS. Hardware monitor IRQ status. 4 WDTIRQSTS. Watch dog timer IRQ status. 3 CIRIRQSTS. Consumer IR IRQ status. 1 IRQIN1STS. IRQIN1 status. 0 IRQIN0STS. IRQIN0 status. CRF6 （Default 0x00） BIT DESCRIPTION 7 - 6 Reserved. Return zero when read. 5 - 0 Enable bits of the SMI / PME generation due to the device's IRQ. These bits enable the generation of a SMI / PME interrupt due to any IRQ of the de- vices. SMI / PME logic output =（MOUIRQEN and MOUIRQSTS）or（KBCIRQEN and KBCIRQSTS）or（PRTIRQEN and PRTIRQSTS）or（FDCIRQEN and FDCIRQSTS） or（URAIRQEN and URAIRQSTS）or（URBIRQEN and URBIRQSTS）or （HMIRQEN and HMIRQSTS）or（WDTIRQEN and WDTIRQSTS）or （IRQIN3EN and IRQIN3STS）or（IRQIN2EN and IRQIN2STS）or （IRQIN1EN and IRQIN1STS）or（IRQIN0EN and IRQIN0STS） 5 MOUIRQEN. 0： Disable the generation of an SMI / PME interrupt due to MOUSE's IRQ. 1： Enable the generation of an SMI / PME interrupt due to MOUSE's IRQ.

Publication Release Date: June 09, 2006 - 107 - Revision 2.27 CRF6 （Default 0x00）, continued. BIT DESCRIPTION 4 KBCIRQEN. 0： Disable the generation of an SMI / PME interrupt due to KBC's IRQ. 1： Enable the generation of an SMI / PME interrupt due to KBC's IRQ. 3 PRTIRQEN. 0： Disable the generation of an SMI / PME interrupt due to printer port's IRQ. 1： Enable the generation of an SMI / PME interrupt due to printer port's IRQ. 2 FDCIRQEN. 0： Disable the generation of an SMI / PME interrupt due to FDC's IRQ. 1： Enable the generation of an SMI / PME interrupt due to FDC's IRQ. 1 URAIRQEN. 0： Disable the generation of an SMI / PME interrupt due to UART A's IRQ. 1： Enable the generation of an SMI / PME interrupt due to UART A's IRQ. 0 URBIRQEN. 0： Disable the generation of an SMI / PME interrupt due to UART B's IRQ. 1： Enable the generation of an SMI / PME interrupt due to UART B's IRQ. CRF7 （Default 0x00） BIT DESCRIPTION 7 - 6 Reserved. Return zero when read 5 - 0 Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. 5 HMIRQEN. 0： Disable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. 1： Enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. 4 WDTIRQEN. 0： Disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. 1： Enable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. 3 CIRIRQEN. 0： Disable the generation of an SMI / PME interrupt due to CIR's IRQ. 1： Enable the generation of an SMI / PME interrupt due to CIR's IRQ 2 MIDIIRQEN. 0： Disable the generation of an SMI / PME interrupt due to MIDI's IRQ. 1： Enable the generation of an SMI / PME interrupt due to MIDI's IRQ.

• 108 - CRF7 （Default 0x00）, continued BIT DESCRIPTION 1 IRQIN1EN. 0： Disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. 1： Enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. 0 IRQIN0EN. 0： Disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. 1： Enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. CRF9 （Default 0x00） BIT DESCRIPTION 7 - 3 Reserved. Return zero when read.

2 PME_EN： Select the power management events to be either an PME or SMI inter-

rupt for the IRQ events. Note that： this bit is valid only when SMIPME_OE = 1. 0： The power management events will generate an SMI event 1： The power management events will generate an PME event. 1 Reserved. 0 SMIPME_OE： This is the SMI and PME output enable bit. 0： Neither SMI nor PME will be generated. Only the IRQ status bit is set. 1： An SMI or PME event will be generated. CRFE, FF （Default 0x00） Reserved for Winbond test.

9.13 Logical Device B （Hardware Monitor）

CR30 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 1： Active 0： Inactived CR60, CR 61 （Default 0x00, 0x00） These two registers select Hardware Monitor base address [0x100 ：0xFFF] on 8-byte boundary.

Publication Release Date: June 09, 2006 - 109 - Revision 2.27 CR70 （Default 0x00） BIT DESCRIPTION 7 - 4 Reserved. 3 - 0 These bits select IRQ resource for Hardware Monitor. CRF0 （Default 0x00） BIT DESCRIPTION 7 - 1 Reserved. 0 Disable initial abnormal beep （VcoreA and +3.3 V） 0： Enable power-on abnormal beep 1： Disable power-on abnormal beep

• 110 - 10. SPECIFICATIONS

10.1 Absolute Maximum Ratings

Power Supply Voltage （5V） -0.5 to 7.0 V Input Voltage -0.5 to V DD+0.5 V RTC Battery Voltage VBAT 2.2 to 4.0 V Operating Temperature 0 to +70 ° C Storage Temperature -55 to +150 ° C Note： Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

10.2 DC CHARACTERISTICS

（Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V） PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS RTC Battery Quiescent Current IBAT 2.4 uA V BAT = 2.5 V ACPI Stand-by Power Supply Quiescent Cur- rent I BAT 2.0 mA V SB = 5.0 V, All ACPI pins are not connected. I/O8t - TTL level bi-directional pin with 8mA source-sink capability Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Output Low Voltage V OL 0.4 V I OL = 8 mA Output High Voltage V OH 2.4 V I OH = - 8 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V I/O12t - TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Output Low Voltage V OL 0.4 V I OL = 12 mA Output High Voltage V OH 2.4 V I OH = -12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V

Publication Release Date: June 09, 2006 - 111 - Revision 2.27 DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS I/O24t - TTL level bi-directional pin with 24mA source-sink capability Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Output Low Voltage V OL 0.4 V I OL = 24 mA Output High Voltage V OH 2.4 V I OH = -24 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V I/O12tp3 – 3.3V TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Output Low Voltage V OL 0.4 V I OL = 12 mA Output High Voltage V OH 2.4 V I OH = -12 mA Input High Leakage I LIH +10 μA VIN = 3.3V Input Low Leakage I LIL -10 μA VIN = 0V I/O12ts - TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V Hystersis V TH 0.5 1.2 V V DD=5V Output Low Voltage V OL 0.4 V I OL = 12 mA Output High Voltage V OH 2.4 V I OH = -12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V I/O24ts - TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage V t- 0.5 0.8 1.1 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V Hystersis V TH 0.5 1.2 V V DD=5V Output Low Voltage V OL 0.4 V I OL = 24 mA Output High Voltage V OH 2.4 V I OH = -24 mA Input High Leakage I LIH +10 μA VIN = 5V

• 112 - DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS Input Low Leakage I LIL -10 μA VIN = 0V I/O24tsp3 – 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V Hystersis V TH 0.5 1.2 V V DD=3.3V Output Low Voltage V OL 0.4 V I OL = 24 mA Output High Voltage V OH 2.4 V I OH = -24 mA Input High Leakage I LIH +10 μA VIN = 3.3V Input Low Leakage I LIL -10 μA VIN = 0V I/OD12t - TTL level bi-directional pin and open-drain output with 12mA sink capability Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Output Low Voltage V OL 0.4 V I OL = 12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V I/OD24t - TTL level bi-directional pin and open-drain output with 24mA sink capability Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Output Low Voltage V OL 0.4 V I OL = 24 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V I/OD12ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage V t- 0.5 0.8 1.1 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V Hystersis V TH 0.5 1.2 V V DD=5V Output Low Voltage V OL 0.4 V I OL = 12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V

Publication Release Date: June 09, 2006 - 113 - Revision 2.27 DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS I/OD24ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V Hystersis V TH 0.5 1.2 V V DD=5V Output Low Voltage V OL 0.4 V I OL = 24 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0V I/OD12cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage V t- 1.3 1.5 1.7 V V DD = 5 V Input High Threshold Voltage V t+ 3.2 3.5 3.8 V V DD = 5 V Hystersis V TH 1.5 2 V V DD = 5 V Output Low Voltage V OL 0.4 V I OL = 12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V I/OD16cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA sink capability Input Low Threshold Voltage V t- 1.3 1.5 1.7 V V DD = 5 V Input High Threshold Voltage V t+ 3.2 3.5 3.8 V V DD = 5 V Hystersis V TH 1.5 2 V V DD = 5 V Output Low Voltage V OL 0.4 V I OL = 16 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V

• 114 - DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS I/OD12csd - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Vt- 1.3 1.5 1.7 V V DD = 5 V Input High Threshold Voltage V t+ 3.2 3.5 3.8 V V DD = 5 V Hystersis V TH 1.5 2 V V DD = 5 V Output Low Voltage V OL 0.4 V I OL = 12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V I/OD12csu - CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open drain output with 12mA sink capability Input Low Threshold Voltage V t- 1.3 1.5 1.7 V V DD = 5 V Input High Threshold Voltage V t+ 3.2 3.5 3.8 V V DD = 5 V Hystersis V TH 1.5 2 V V DD = 5 V Output Low Voltage V OL 0.4 V I OL = 12 mA Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V O4 - Output pin with 4mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 4 mA Output High Voltage V OH 2.4 V I OH = -4 mA O8 - Output pin with 8mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 8 mA Output High Voltage V OH 2.4 V I OH = -8 mA O12 - Output pin with 12mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 12 mA Output High Voltage V OH 2.4 V I OH = -12 mA O16 - Output pin with 16mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 16 mA Output High Voltage V OH 2.4 V I OH = -16 mA

Publication Release Date: June 09, 2006 - 115 - Revision 2.27 DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS O24 - Output pin with 24mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 24 mA Output High Voltage V OH 2.4 V I OH = -24 mA O12p3 - 3.3V output pin with 12mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 12 mA O24p3 - 3.3V output pin with 24mA source-sink capability Output Low Voltage V OL 0.4 V I OL = 24 mA OD12 - Open drain output pin with 12mA sink capability Output Low Voltage V OL 0.4 V I OL = 12 mA OD24 - Open drain output pin with 24mA sink capability Output Low Voltage V OL 0.4 V I OL = 24 mA OD12p3 - 3.3V open drain output pin with 12mA sink capability Output Low Voltage V OL 0.4 V I OL = 12 mA INt - TTL level input pin Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V INtp3 - 3.3V TTL level input pin Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Input High Leakage I LIH +10 μA VIN = 3.3V Input Low Leakage I LIL -10 μA VIN = 0 V INtd - TTL level input pin with internal pull down resistor Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V

• 116 - DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS INtu - TTL level input pin with internal pull up resistor Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.0 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V INts- TTL level Schmitt-trigger input pin Input Low Threshold Volt- age Vt- 0.5 0.8 1.1 V V DD = 5 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V V DD = 5 V Hystersis V TH 0.5 1.2 V V DD = 5 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V INtsp3 - 3.3 V TTL level Schmitt-trigger input pin Input Low Threshold Volt- age V t- 0.5 0.8 1.1 V V DD = 3.3 V Input High Threshold Voltage V t+ 1.6 2.0 2.4 V V DD = 3.3 V Hystersis V TH 0.5 1.2 V V DD = 3.3 V Input High Leakage I LIH +10 μA VIN = 3.3 V Input Low Leakage I LIL -10 μA VIN = 0 V INc- CMOS level input pin Input Low Voltage V IL 1.5 V Input High Voltage V IH 3.5 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V INcd- CMOS level input pin with internal pull down resistor Input Low Voltage V IL 1.5 V Input High Voltage V IH 3.5 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V

Publication Release Date: June 09, 2006 - 117 - Revision 2.27 DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. T YP. MAX. UNIT CONDITIONS INcs- CMOS level Schmitt-trigger input pin Input Low Threshold Volt- age Vt- 1.3 1.5 1.7 V V DD = 5 V Hystersis V TH 1.5 2 V V DD = 5 V Input High Leakage I LIH +10 μA VIN = 5 V Input Low Leakage I LIL -10 μA VIN = 0 V INcsu - CMOS level Schmitt-trigger input pin with internal pull up resistor Input Low Threshold Volt- age V t- 1.3 1.5 1.7 V V DD = 5 V Input High Threshold Voltage V t+ 3.2 3.5 3.8 V V DD = 5 V Hystersis V TH 1.5 2 V V DD = 5 V Input High Leakage I LIH +10 μA VIN = 5V Input Low Leakage I LIL -10 μA VIN = 0 V

• 118 - 11. APPLICATION CIRCUITS

11.1 Parallel Port Extension FDD

Parallel Port Extension FDD Mode Connection Diagram

11.2 Parallel Port Extension 2FDD

Parallel Port Extension 2FDD Connection Diagram DSA2/PD7 MOA2/PD6

Publication Release Date: June 09, 2006 - 119 - Revision 2.27

11.3 Four FDD Mode

• 120 - 12. ORDERING INSTRUCTION PART NO. KBC FIRMWARE REMARKS W83627HF-AW AMIKEY-2TM W83627F-AW AMIKEY-2TM W83627HG-AW AMIKEY-2TM W83627G-AW AMIKEY-2TM 13. HOW TO READ THE TOP MARKING inbond W83627HF-AW 821A2B282012345BC © AM. MEGA. 87-96 inbond W83627HG-AW 821A2B282012345BC ©AM. MEGA. 87-96 inbond W83627F-AW 821A2B282012345BC © AM. MEGA. 87-96 inbond W83627G-AW 821A2B282012345BC ©AM. MEGA. 87-96 1st line： Winbond logo 2nd line： the type number： W83627HF-AW, W83627F-AW, W83627HG-AW, W83627G-AW （the “G” means Pb-free package） 3rd line： the source of KBC F/W -- American Megatrends IncorporatedTM 4th line： the tracking code 821 A 2 C 282012345BC 821： packages made in '98, week 21 2： Winbond internal use. B： IC revision; A means version A, B means version B 282012345： wafer production series lot number BC： Winbond internal use.

Publication Release Date: June 09, 2006 - 121 - Revision 2.27 14. PACKAGE DIMENSIONS （128-pin QFP） L L 1 Detail F c e b 1 38 HDD H E E 102 65 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. Note: Seating Plane See Detail F y A A 128 103 5. PCB layout please use the "mm". Symbol b c D e HD HE L y A A E 0.08 1.60 0.95 17.40 0.80 17.20 0.65 17.00 14.10 0.20 0.30 2.87 14.00 2.72 0.50 13.90 0.10 0.10 2.57 0.25 Min Nom Max Dimension in mm 0.20 0.15 19.90 20.00 20.10 23.00 23.20 23.40 0.35 0.45 0.003 0.063 0.037 0.685 0.031 0.677 0.025 0.669 0.020 0.555 0.008 0.012 0.113 0.551 0.107 0.547 0.004 0.004 0.101 0.010 MaxNomMin Dimension in inch 0.006 0.008 0.783 0.787 0.791 0.905 0.913 0.921 0.014 0.018

• 122 - 15. APPENDIX A ： DEMO CIRCUIT FANIO1 R1 300 DTRA# Printer 5VSB STB# R10 4.7K CIRRX RTSA# connected directly to DSB# AGND KEYLOCK# GND MSI COMB & IR PD1 SMBCLK VCOREA R11 4.7K PWRCTL# Fan Speed Seneing VTIN2 SUSCLK COMA VCC3V GND FDC PWROK 3VSB TRAK0# RDATA# MIDI PORT SOFTRST -12VIN MSO SLCT RSMRST# SUSLED battery) R14 R 4.7K R6 10K DSRB# VCC VCC CAP NP 0.1u LAD3 RIA# DSA# PANSWOUT# VTIN3 PEMOB# DSRA# R2 300 KDAT IRTX VID2 VID0 FANPWM2 VCC3V LDA[0..3] RWC# PD[0..7] VID4 R4 10K VCC3V VTIN1 LAD[0..3] CASEOPEN# HEAD# DTRB# GPSB1 Indicated the VCC is OK. (To monitor battery voltage, DS1# WE# PD[0..7] RIB# -5VIN To Power supply for turn ON VCC. SINB W83627HF + FDC 0.4 W83627HF CIRCUIT (LPC I/O + H/W) Winbond Electronic Corp. B 16Monday, August 05, 2002 Title Size Document Number Rev Date: Sheet of VCC3V PD7 PCICLK FANIO3 3VSB JP1 HEADER 17X2 SERIRQ BEEP GPY1 GAME PORT ACK# OSC1 24/48MHz NC OUTPUT For Wake Up Function IRRX VID1 LAD2 R15 R 4.7K R13 4.7K & Speed Control 3VSB WP# CAP NP 0.1u this input should be MOA# VID3 LAD0 PD2 AFD# MCLK VCC3V DCDA# CAP NP 0.1u DSKCHG# R3 10K OVT# ERR# CTSB# DCDB# GPSA1 RTSB# SOUTB R8 0 PLED PD4 W83627HF 1112 1617 2223 2728 3233 7071 7576 8081 8687 9192 9798 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DRVDEN0 DRVDEN1/IRQIN1/INDEX# MOA# DSB# DSA# MOB# DIR#STEP# WD# WE# VCC TRAK0#WP# RDATA# HEAD# DSKCHG# CLKINPME# VSS PCICLK LDRQ# SERIRQ LAD3LAD2 LAD1 LAD0 VCC3V LFRAME#LRESET# SLCT PE BUSY ACK#PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 SLIN# INIT# ERR# AFD# STB# VCC CTSA# DSRA# RTSA# DTRA# SINA SOUTA VSS DCDA# RIA# KBLOCK# GA20M KBRST VSB KCLK KDAT SUSLED/GP35 MCLK MDAT PSOUT# PSIN#CIRRX/GP34 RSMRST#/GP33 PWROK/GP32 PWRCTL#/GP31 SLP_SX#/GP30VBAT SUSCLKIN CASEOPEN# VCC CTSB#DSRB# RTSB# DTRB# SINB SOUTB DCDB#RIB# VSS IRTX/GP26 IRRX/GP25 WDTO/GP24PLED/GP23 SDA/GP22 SCL/GP21 AGND -5VIN-12VIN +12VIN AVCC +3.3VIN VCOREB VCOREAVREF VTIN3 VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 VCC FANPWM2 FANPWM1 VSS BEEP MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 MDAT +12VIN VCC3V VCC3V LDRQ# LRESET# +3.3VIN C5CAP NP 0.1u PD5 PS2 Mouse. Temperature Sensing GND CAP NP 0.1u From ICH S3 or S5 signal. STEP# GPY2 BAT SLP_SX# CTSA# SOUTA GPX1 VCC FANPWM1 R12 10K PME# INIT# DIR# SMBDATA Keyboard & R7 0 SLIN# VCOREB Voltage SENSING VCC PD6 SINA GPSB2 R5 10K PD3 CAP NP 0.1u PD0 INDEX# WD# KCLK LFRAME# Temperature Sensing LAD1 GPSA2 GPX2 BUSY VREF 5VSB FANIO2 A20M# AVCC PANSWIN

Publication Release Date: June 09, 2006 - 123 - Revision 2.27 IOVSB C10 47P PS2 MOUSE JP5:1-2 Clear CMOS VCC FB KEYBOARD VCC C14 10u FB C12 0.1uF R26 ON, D2,D3 OFF:NO Wake_up fuction R16 47P R28 R 4.7K R23 10K HEADER 5 JP3 HEADER 5 R26 OFF, D2,D3 ON: Wake_up fuction R22 4.7K SUSPEND LED CIRCUIT JP2 HEADER 2 KEYLOCK FB R19 4.7K KDAT VCC R27 R 150 VCC BATTERY CIRCUIT FB PLED 47P R25 R 150 POWER LED CIRCUIT 5VSB MCLK NPN LED C11 47P MDAT R17 IOVSB R21 4.7K R20 4.7K 5817 VBAT 2-3 Enable ONNOW functions 5VSB IOVSB HEADER 6 KEYLOCK# NPN LED KB & PS2 MOUSE & POWER 0.4 W83627HF CIRCUIT (LPC I/O + H/M) WINBOND ELECTRONICS CORP. Custom 26Monday, August 05, 2002 Title Size Document Number Rev Date: Sheet of .1UF PANEL SWITCH BT1 BATTERY FUSE 5817 R18 150 R24 100 SUSLED OnNow or Wake_up function power KCLK IOVSB JP4 HEAD3 3C13 0.1UF PANSWIN IOVSB CIRCUIT

• 124 - RIB# +12V SINB NCTSA PD[0..7] VCC -12V SLCT PD2 VCC DTRA# IRTX NDTRB RPACK1 1 2 3 4 5 6 7 8 GND CN2X5B C22 180 W83778 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V C23 180 NDSRB SINA DSRB# PD[0..7] COMA NDTRA NDSRA NRIB NDTRARTSA# (SOP20) NCTSB RP2 10P9R-4.7K CIRRX COMB NDSRB C16 180 C17 180 PD1 +12V NRIA CN2X5B RPACK3 1 2 3 4 5 6 7 8 C31 180C28 180 DTRB# W83778 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V BUSY PD3 PD6 SOUTA NDCDB AFD# CTSB# DB25 NSOUTA NSOUTB (UARTA) NSINB COM & IR & LPT PORT 0.4 W83627HF CIRCUIT (LPC I/O + H/W) WINBOND ELECTRONICS CORP. Custom 36Monday, August 05, 2002 Title Size Document Number Rev Date: Sheet of NDTRB PD0 RTSB# C18 180 NRTSA NDCDB PRT PORT NRIB NSINB NRTSB NRTSB DSRA# NDCDA INIT# IOVSB THE IOVSB OF PIN 8 IS FOR CIR WAKE-UP FUNCTION. VCC (UARTB) VCC C25 180 CTSA# STB# SLIN# RPACK2 1 2 3 4 5 6 7 8 C15 180 -12V NRIA ACK# C30 180 RP1 10P9R-4.7K PE NDCDA C20 180 NDSRA NSINA NCTSB NSOUTA PD7 DCDA# ERR# C21 180 COM PORT C26 180 RIA# NSINA C27 180 IRRX (SOP20) NRTSA J5 CN2X5 C29 180 PD5 VCC NSOUTB C24 180 DCDB# SOUTB NCTSA GND PD4 IR/CIR CONNECTOR C19 180

Publication Release Date: June 09, 2006 - 125 - Revision 2.27 GPX1 R35 R GPY1 R33 R 2.2K C40 CAP NP 150P R40 R 2.2K R32 R 2.2K VCC GPSB2 VCC GAME & MIDI 0.4 W83627HF CIRCUIT (LPC I/O + H/W) WINBOND ELECTRONICS CORP. Custom 46Monday, August 05, 2002 Title Size Document Number Rev Date: Sheet of C37 CAP NP 0.01U R38 R R36 R MSO C34 CAP NP 0.01U VCC INDUCTOR GPY2 VCC C33 CAP NP 0.01U GPX2 R39 R 2.2K R34 R 2.2K R78 R 100K R30 R 2.2K GPSA2 VCC CONNECTOR DB15 R41 R 2.2K GPSA1 C36 CAP NP 0.01U R42 R 2.2K GAME & MIDI PORT CIRCUIT C32 CAP NP 0.01U GPSB1 R37 R MSI VCC C38 CAP NP 0.01U R31 R 2.2K R29 R 2.2K C35 CAP NP 0.01U C39 CAP NP 0.01U

• 126 - R57 1K R65 10K FANIO3 CPU Voltage ID output (for other) R69 10K R75 56K 1% VCC3V LS1 SPEAKER R66 10K MOSFET N 2N7002 1N4148 PIIVID1 C43 CAPACITOR NON-POL 3300p R73 56K 1% R52 27K R70 10K 3VCC -12VINVREF VCOREA +12V PNP 3906 PNP 3906 R48 510 VBAT +C41 10u R72 10K -5VIN Hardware Monitor circuits Case Open Circuits R50 4.7K R54 10K PIIVID4 R46 R 28K 1% FANIO2 CPUVCOB R74 232K 1% VCC R76 120K 1% JP7 HEADER 3 VID3 R68 10K AGND +12VIN R58 4.7K Voltage Sensing C42 10u AGND PIIVID2 CASEOPEN# 3904 R49 1K CASEOPEN SW VID2 R44 R 10K R64 27K R60 30K TRT1 THERMISTOR 10K 1% JP5 HEADER 3 R71 10K VTIN2 R43 R 10K VCC R47 R 10K 1% PIIVID3 1N4148 VID0 Temperature Sensing TRT2 THERMISTOR 10K 1% FB -12V R77 R VCOREB VTIN1 +12V (from Deschutes) R51 4.7K R62 10K 1% FANIO1 VID1 BEEP Fan Speed Input Circuit R53 10K MOSFET N 2N7002 AVCC AGND -5V VREF (for system) R56 4.7K R55 27K VID4 VTIN3 R45 R 10K PWM Circuit for FAN speed control +12V JP6 HEADER 3 PIIVID0 +3.3VIN Hardware Monitor 0.4 W83627HF CIRCUIT (LPC I/O+ H/W) Winbond Electronic Corp. Custom 56Monday, August 05, 2002 Title Size Document Number Rev Date: Sheet of R59 510 +12V FANPWM2 FB R61 10K 1% 1N4148 R67 100 Beep Circuits R63 4.7K FANPWM1 CPUVCOA

Publication Release Date: June 09, 2006 - 127 - Revision 2.27 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instru- ments, airplane or spaceship instruments, tran sportation instruments, traffic signal instru- ments, combustion control instruments, or for other applications intended to support or sus- tain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.