W25D10 WINBOND | Alldatasheet
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W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 1 - P r e l i m i n a r y - R e v i s i o n A 1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI
W25D10, W25D20, W25D40, W25D80 - 2 - Table of Contents-
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 3 - P r e l i m i n a r y - R e v i s i o n A
W25D10, W25D20, W25D40, W25D80 - 4 - 1. GENERAL DESCRIPTION The W25D10 (1M-bit), W25D20 (2M-bit), W25D40 (4M-bit) and W25D80 (8M-bit) Serial Flash memories provide a storage solution for systems wi th limited space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code download applications as well as storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25D10/20/40/80 array is organized into 512/1024/2048/4096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase). The W25D10/20/40/80 has 32/64/128/256 erasable sectors and 2/4/8/16 erasable blocks respectively. The small 4KB sectors allow for greater flexibilit y in applications that require data and parameter storage. (See figure 2.) The W25D10/20/40/80 supports the standard Serial Peripheral Interface (SPI), and a high performance dual output SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI clock frequencies of up to 75MHz ar e supported allowing equivalent clock rates of 150MHz when using the Fast Read Dual Output inst ruction. These transfer rates are comparable to those of 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable wr ite protect, with top or bottom array control features, provide further control flexibility. Additionally, the devic e supports JEDEC standard manufacturer and device identification. 2. FEATURES
- Family of Serial Flash Memories – W25D10: 1M-bit / 128K-byte (131,072) – W25D20: 2M-bit / 256K-byte (262,144) – W25D40: 4M-bit / 512K-byte (524,288) – W25D80: 8M-bit / 1M-byte (1,048,576) – 256-bytes per programmable page – Uniform 4K-byte Sectors / 64K-byte Blocks
- SPI with Single or Dual Outputs – Clock, Chip Select, Data I/O, Data Out – Optional Hold function for SPI flexibility
- Data Transfer up to 150M-bits / second – Clock operation to 75MHz – Fast Read Dual Output instruction – Auto-increment Read capability
- Flexible Architecture with 4KB sectors – Sector Erase (4K-bytes) – Block Erase (64K-byte) – Page program up to 256 bytes <2ms – Up to 100,000 erase/write cycles – 20-year retention
- Low Power Consumption, Wide Temperature Range – Single 2.7 to 3.6V supply – 5mA active current, 1µA Power-down (typ) – -40° to +85°C operating range
- Software and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin – Top or bottom array protection
- Space Efficient Packaging – 8-pin SOIC 150-mil (W25D10/20/40) – 8-pin SOIC 208-mil (W25D40/80) – 8-pin PDIP 300-mil (W25D10/20/40/80) – 8-pin WSON 6x5-mm (W25D10/20/40/80)
W25D10, W25D20, W25D40, W25D80 - 6 - 6. PIN CONFIGURATION WSON 6X5-MM Figure 1d。W25D10, W25D20, W25D40 and W25D80 Pin Assignments, 8-pin WSON (Package Code ZP) 7. PIN DESCRIPTION SOIC 150-mil, SOIC 208-mil, PDIP 300-mil, and WSON 6x5-mm PAD NO. PAD NAME I/O FUNCTION 1 /CS I Chip Select Input
2 DO O Data Output
3 /WP I Write Protect Input
4 GND Ground
5 DIO I/O Data Input / Output
6 CLK I Serial Clock Input
8 VCC Power Supply
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 7 - P r e l i m i n a r y - R e v i s i o n A
7.1 Package Types
At the time this datasheet was published not all package types had been finalized. Contact Winbond to confirm availability of these packages before designing to this specification. The W25D10, W25D20 and W25D40 are offered in an 8-pin plastic 150-mil width SOIC (package code SN) as shown in figure 1a. The W25D40 and W25D80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) as shown in figure 1b. All parts will be offered in 6x5-mm WSON (package code ZP) and 300-mil DIP (package code DA). Package diagrams and dimensions are illustrated at the end of this datasheet.
7.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices power consumption will be at standby levels unless an in ternal erase, program or status register cycle is in progress. When /CS is brought low the device will be select ed, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new inst ruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Pr otection” and figure 20). If needed a pull-up resister on /CS can be used to accomplish this.
7.3 Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
7.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Pr otect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low.
7.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high im pedance and signals on the DIO and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)
7.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides t he timing for serial input and output operations. ("See SPI "Operations")
7.7 Serial Data Input / Output (DIO)
The SPI Serial Data Input/Output (DIO) pin provi des a means for instructions, addresses and data to be serially written to (shifted in to) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin. The DIO pin is also used as an out put when the Fast Read Dual Output instruction is executed.
Figure 2. W25D10, W25D20, W25D40 and W25D80 Block Diagram
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 9 - P r e l i m i n a r y - R e v i s i o n A 9. FUNCTIONAL DESCRIPTION
9.1 SPI OPERATIONS
9.1.1 SPI Modes
The W25D10/20/40/80 is accessed through an SPI compat ible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are suppor ted. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of the CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.
9.1.2 Dual Output SPI
The W25D10/20/40/80 supports Dual output operation when using the "Fast Read with Dual Output" (3B hex) instruction. This feature allows data to be transferred from t he Serial Flash memory at twice the rate possible with the standard SPI. This inst ruction is ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM for execution. The Dual output f eature simply allows the SPI input pin to also serve as an output during this instruction. All other operations use the standard SPI interface with single output signal.
9.1.3 Hold Function
The /HOLD signal allows the W25D10/20/40/80 operati on to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so progra mming can resume where it left off once the bus is available again. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if t he CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (D O) is high impedance, and Serial Data Input/Output (DIO) and Serial Clock (CLK) are ignor ed. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.
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9.2 WRITE PROTECTION
Applications that use non-volatile memory must ta ke into consideration the possibility of noise and other adverse system conditions that may compromi se data integrity. To address this concern the W25D10/20/40/80 provides several means to protect data from inadvertent writes.
9.2.1 Write Protect Features
- Device resets when VCC is below threshold.
- Time delay write disable after Power-up.
- Write enable/disable instructions.
- Automatic write disable after program and erase.
- Software write protection using Status Register.
- Hardware write protection using Status Register and /WP pin.
- Write Protection using Power-down instruction. Upon power-up or at power-down the W25D10/20/40/80 will maintain a reset condition while VCC is below the threshold value of V WI, (See Power-up Timing and Voltage Levels and Figure 20). While reset, all operations are disabled and no instructi ons are recognized. During power-up and after the VCC voltage exceeds V WI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program , Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note t hat the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and t VSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Stat us Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WE L) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP) and Block Pr otect (TB, BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to t he Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 1 1 - P r e l i m i n a r y - R e v i s i o n A 10. CONTROL AND STATUS REGISTERS The Read Status Register instruction can be used to provide status on the av ailability of the Flash memory array, if the device is write enabled or dis abled, and the state of writ e protection. The Write Status Register instruction can be used to configure the devices write protection features. See Figure 3.
10.1 STATUS REGISTER
10.1.1 BUSY
BUSY is a read only bit in the status register (S0) t hat is set to a 1 state w hen the device is executing a Page Program, Sector Erase, Block Erase, Chip Er ase or Write Status Regi ster instruction. During this time the device will ignore further instructions except for the Read Status Register instruction (see tW, t PP, t SE, TBE , and t CE in AC Characteristics). When the progr am, erase or write status register instruction has completed, the BUSY bit will be clear ed to a 0 state indicating the device is ready for further instructions.
10.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable Instruction. The WE L status bit is cleared to a 0 w hen the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
10.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see t W in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instru ctions (see Status Regi ster Memory Protection table). The factory default setting for the Block Protec tion Bits is 0, none of the array protected. The Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.
10.1.4 Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block Pr otect Bits (BP2, BP1, BP0 ) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB bit is non-volatile and the factory default setti ng is TB=0. The TB bit can be set with the Write Status Register Instruction provided that the Write Enable instruction has been issued. The TB bit can not be written to if the Status Regi ster Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.
10.1.5 Reserved Bits
Status register bit location S6 is reserved for fu ture use. Current devices will read 0 for this bit location. It is recommended to mask out the reserved bi t when testing the Status Register. Doing this will ensure compatibility with future devices.
10.1.6 Status Register Protect (SRP)
/WP pin is high the Write Status Register instruction is allowed. Figure 3. Status Register Bit Locations
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 1 3 - P r e l i m i n a r y - R e v i s i o n A
10.1.7 Status Register Memory Protection
STATUS REGISTER(1) W25D80 (8M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY (KB) PORTION x 0 0 0 NONE NONE NONE NONE 0 0 0 1 15 0F0000h - 0FFFFFh 512K-bit Upper 1/16 0 0 1 0 14 and 15 0E0000h - 0FFFFFh 1M-bit Upper 1/8 0 0 1 1 12 thru 15 0C0000h - 0FFFFFh 2M-bit Upper 1/4 0 1 0 0 8 thru 15 080000h - 0FFFFFh 4M-bit Upper 1/2 1 0 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/16 1 0 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/8 1 0 1 1 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/4 1 1 0 0 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/2 x 1 0 1 0 thru 15 000000h - 0FFFFFh 8M-bit ALL x 1 1 x 0 thru 15 000000h - 0FFFFFh 8M-bit ALL STATUS REGISTER(1) W25D40 (4M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY (KB) PORTION x 0 0 0 NONE NONE NONE NONE 0 0 0 1 7 070000h - 07FFFFh 512K-bit Upper 1/8 0 0 1 0 6 and 7 060000h - 07FFFFh 1M-bit Upper 1/4 0 0 1 1 4 thru 7 040000h - 07FFFFh 2M-bit Upper 1/2 1 0 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/8 1 0 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/4 1 0 1 1 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/2 x 1 x x 0 thru 7 000000h - 07FFFFh 4M-bit ALL STATUS REGISTER(1) W25D20 (2M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY (KB) PORTION x x 0 0 NONE NONE NONE NONE 0 x 0 1 3 030000h - 03FFFFh 512K-bit Upper 1/4 0 x 1 0 2 and 3 020000h - 03FFFFh 1M-bit Upper 1/2 1 x 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/4 1 x 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/2 x x 1 1 0 thru 3 000000h - 03FFFFh 2M-bit ALL STATUS REGISTER(1) W25D10 (1M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY (KB) PORTION x x 0 0 NONE NONE NONE NONE 0 x 0 1 1 010000h - 01FFFFh 512K-bit Upper 1/2 1 x 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/2 x x 1 x 0 and 1 000000h - 01FFFFh 1M-bit ALL Note: 1. x = don’t care
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10.2 INSTRUCTIONS
The instruction set of the W25D 10/20/80/16 consists of fifteen basic instructions that are fully controlled through the SPI bus (see Instruction Set t able). Instructions are initiated with the falling edge of Chip Select (/CS). The firs t byte of data clocked into the DI O input provides the instruction code. Data on the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some ca ses, a combination. Inst ructions are completed with the rising edge of edge /CS. Clock relative ti ming diagrams for each instruction are included in figures 4 through 19. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. This feature further protects the device from inadvertent writes . Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all inst ructions except for Read Status Register will be ignored until the program or erase cycle has completed.
10.2.1 Manufacturer and Device Identification
MANUFACTURER ID (M7-M0) Winbond Serial Flash EFH Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h 9Fh W25D10 10h 3011h W25D20 11h 3012h W25D40 12h 3013h W25D80 13h 3014h
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 1 5 - P r e l i m i n a r y - R e v i s i o n A
10.2.2 Instruction Set (1)
BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 N-BYTES Write Enable 06h Write Disable 04h Read Status Register 05h (S7–S0) (1) (2) Write Status Register 01h S7–S0 Read Data 03h A23–A16 A15–A8 A7–A0 (D7–D0) (Next byte) continuous Fast Read 0Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0) (Next Byte) continuous Fast Read Dual Output 3Bh A23–A16 A15–A8 A7–A0 dummy I/O = (D6,D4,D2,D0) O = (D7,D5,D3,D1) (one byte per 4 clocks, continuous) Page Program 02h A23–A16 A15–A8 A7–A0 (3) (D7–D0) (Next byte) Up to 256 bytes Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0 Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0 Chip Erase C7h Power-down B9h Release Power- down / Device ID ABh dummy dummy dummy (ID7-ID0) (4) Manufacturer/ Device ID (3) 90h dummy dummy 00h (M7-M0) (ID7-ID0) JEDEC ID 9Fh (M7-M0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. See Manufacturer and Device Identification table for Device ID information. 4. The Device ID will repeat continuously until /CS terminates the instruction.
10.2.3 Write Disable (04h)
Figure 4. Write Disable Instruction Sequence Diagram
10.2.4 Write Enable (06h)
Figure 5. Write Enable Instruction Sequence Diagram
10.2.5 Read Status Register (05h)
continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram
10.2.6 Write Status Register (01h)
Status Register instruction. cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. high the Write Status Register instruction is allowed. Figure 7. Write Status Register Instruction Sequence Diagram
10.2.7 Read Data (03h)
fR (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram
10.2.8 Fast Read (0Bh)
data value on the DIO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram
10.2.9 Fast Read Dual Output (3Bh)
applications that cache code-segments to RAM for execution. Figure 10. Fast Read Dual Output Instruction Sequence Diagram
10.2.10 Page Program (02h)
sequence is shown in figure 11. wrap to the beginning of the page and overwrite previously sent data. Figure 11. Page Program Instruction Sequence Diagram
10.2.11 Sector Erase (20h)
2). The Sector Erase instruction sequence is shown in figure 12. BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 12. Sector Erase Instruction Sequence Diagram
10.2.12 Block Erase (D8h)
2). The Block Erase instruction sequence is shown in figure 13. and BP0) bits (see Status Register Memory Protection table). Figure 13. Block Erase Instruction Sequence Diagram
10.2.13 Chip Erase (C7h)
shifting the instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 14. Figure 14. Chip Erase Instruction Sequence Diagram
10.2.14 Power-down (B9h)
“B9h” as shown in figure 15. the normal operation with the standby current of ICC1. Figure 15. Deep Power-down Instruction Sequence Diagram
10.2.15 Release Power-down / Device ID (ABh)
instructions will be accepted. The /CS pin must remain high during the tRES1 time duration. instruction is completed by driving /CS high. device will resume normal operation and other instructions will be accepted. Figure 16. Release Power-down Instruction Sequence
Figure 17. Release Power-down / Device ID Instruction Sequence Diagram
10.2.16 Read Manufacturer / Device ID (90h)
Figure 18. Read Manufacturer / Device ID Diagram
10.2.17 JEDEC ID (9Fh)
standard for SPI compatible serial memories that was adopted in 2003. Device Identification table. Figure 19. Read JEDEC ID
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 3 1 - P r e l i m i n a r y - R e v i s i o n A 11. ELECTRICAL CHARACTERISTICS (PRELIMINARY) (4)
11.1 Absolute Maximum Ratings (1)
PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to +4.0 V Voltage Applied to Any Pin V IO Relative to Ground –0.6 to VCC +0.4 V Storage Temperature T STG –65 to +150 °C Lead Temperature T LEAD See Note (2) °C Electrostatic Discharge Voltage VESD Human Body Model (3) –2000 to +2000 V Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms). 4. See preliminary designation at the end of this datasheet.
11.2 Operating Ranges
SPEC PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Supply Voltage(1) VCC FR = 50MHz, fR = 33MHz FR0 = 70MHz, fR = 33MHz FR1 = 75MHz, fR = 33MHz 2.7 3.0 3.0 3.6 3.6 3.6 V Ambient Temperature, Operating TA Commercial (2) Industrial –40 +70 +85 Note: 1. VCC voltage during Read can operate across the mi n and max range but should not exceed ±10% of the programming (erase/write) voltage. 2. Commercial temperature only applies to Fast Read (F R0 & F R1) and 100K cycles endurance for 4K byte sectors . Industrial temperature applies to all other parameters.
11.3 Endurance and Data Retention
11.4 Power-up Timing and Write Inhibit Threshold
- These parameters are characterized only.
Figure 20. Power-up Timing and Voltage Levels
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11.5 DC Electrical Characteristics
SPEC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input Capacitance C IN(1) V IN = 0V(2) 6 pf Output Capacitance Cout (1) V OUT = 0V(2) 8 pf Input Leakage I LI ±2 µA I/O Leakage I LO ±2 µA Standby Current I CC1 /CS = VCC, VIN = GND or VCC 25 50 µA Power-down Current I CC2 /CS = VCC, VIN = GND or VCC <1 5 µA Current Read Data / Dual Output Read 1MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 5/8 10/12 mA Current Read Data / Dual Output Read 33MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 10/10 15/20 mA Current Read Data / Dual Output Read 50MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 10/15 15/20 mA Current Read Data / Dual Output Read 75MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 15/20 20/25 mA Current Page Program I CC4 /CS = VCC 20 25 mA Current Write Status Register ICC5 /CS = VCC 8 12 mA Current Sector/Block Erase ICC6 /CS = VCC 20 25 mA Current Chip Erase I CC7 /CS = VCC 20 25 mA Input Low Voltage V IL –0.5 VCC x 0.3 V Input High Voltage V IH VCC x0.7 VCC +0.4 V Output Low Voltage V OL I OL = 1.6 mA 0.4 V Output High Voltage V OH I OH = –100 µA VCC –0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V. 2. Checker Board Pattern.
11.6 AC Measurement Conditions
- Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC Measurement I/O Waveform
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 3 5 - P r e l i m i n a r y - R e v i s i o n A
11.7 AC Electrical Characteristics
for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature FR f C D.C. 50 MHz Clock frequency for all instructions, except Read Data (03h) 3.0V-3.6V VCC & Commercial Temperature F R0 (4) f C0 D.C. 70 MHz Clock frequency, for Fast Read (0Bh, 3Bh) only 3.0V-3.6V VCC & Commercial Temperature FR1 (4) f C1 D.C. 75 MHz Clock freq. Read Data instruction 03h f R D.C. 33 MHz Clock High, Low Time, for Fast Read (0Bh, 3Bh) / other instructions except Read Data (03h) tCLH, tCLL(1) 6/7 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak t CLCH(2) 0.1 V/ns Clock Fall Time peak to peak t CHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK t SLCH t CSS 5 ns /CS Not Active Hold Time relative to CLK t CHSL 5 ns Data In Setup Time t DVCH t DSU 2 ns Data In Hold Time t CHDX t DH 5 ns /CS Active Hold Time relative to CLK t CHSH 10 ns /CS Not Active Setup Time relative to CLK t SHCH 0 ns /CS Deselect Time t SHSL t CSH 100 ns Output Disable Time t SHQZ(2) t DIS 7 ns Clock Low to Output Valid t CLQV t V 7.5 / 6.5 ns Output Hold Time t CLQX t HO 0 ns Continued – next page
W25D10, W25D20, W25D40, W25D80 - 36 -
11.8 AC Electrical Characteristics ( cont’d)
/HOLD Active Setup Time relative to CLK t HLCH 5 ns /HOLD Active Hold Time relative to CLK t CHHH 5 ns /HOLD Not Active Setup Time relative to CLK t HHCH 5 ns /HOLD Not Active Hold Time relative to CLK t CHHL 5 ns /HOLD to Output Low-Z t HHQX(2) t LZ 7 ns /HOLD to Output High-Z t HLQZ(2) t HZ 12 ns Write Protect Setup Time Before /CS Low t WHSL(3) 20 ns Write Protect Hold Time After /CS High t SHWL(3) 100 ns /CS High to Power-down Mode t DP(2) 3 µs /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 µs /CS High to Standby Mode with Electronic Signature Read tRES2(2) 1.8 µs Write Status Register Time t W 10 15 ms Byte Program Time (First Byte) (5) t BP1 100 150 µs Additional Byte Program Time (After First Byte) (5) t BP2 6 12 µs Page Program Time t PP 1.5 3 ms Sector Erase Time (4KB) t SE 150 300 ms Block Erase Time (64KB) t BE 1 2 s Chip Erase Time W25D10 / W25D20 Chip Erase Time W25D40 Chip Erase Time W25D80 t CE 3 s s s Notes: 1. Clock high + Clock low must be less than or equal to 1/f C. 2. Value guaranteed by design and/or characte rization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1. 4. Commercial temperature only applies to Fast Read (F R0 & FR1). Industrial temperature applies to all other parameters. 5. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed.
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 3 7 - P r e l i m i n a r y - R e v i s i o n A
11.9 Serial Output Timing
11.10 Input Timing
11.11 Hold Timing
W25D10, W25D20, W25D40, W25D80 - 38 - 12. PACKAGE SPECIFICATION 12.1 8-Pin SOIC 150-mil (Package Code SN) MILLIMETERS INCHES SYMBOL MIN TYP. MAX MIN TYP. MAX e(2) 1.27 BSC 0.050 BSC θ 0o --- 8 o 0 o --- 8 o Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 3 9 - P r e l i m i n a r y - R e v i s i o n A 12.2 8-Pin SOIC 208-mil (Package Code SS) MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 1.75 2.16 0.069 0.085 A1 0.05 0.25 0.002 0.010 A2 1.70 1.91 0.067 0.075 b 0.35 0.48 0.014 0.019 C 0.19 0.25 0.007 0.010 D 5.18 5.38 0.204 0.212 E 7.70 8.10 0.303 0.319 E1 5.18 5.38 0.204 0.212 e 1.27 BSC 0.050 BSC L 0.50 0.80 0.020 0.031 θ 0o 8 o 0 o 8 o Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.
W25D10, W25D20, W25D40, W25D80 - 40 - 12.3 8-Pin PDIP 300-mil (Package Code DA) 1.631.470.0640.058 Symbol Min Nom Max Max NomMin Dimension in inch Dimension in mm A B c D e A L S A A E 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 9.53 e 0.360 0.380 9.14 9.65 01 5 0.045 1.14 0.3550.335 8.51 9.02 150 Seating Plane eA c E Base Plane1A L A S D B 8 5 1 4 α α
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 4 1 - P r e l i m i n a r y - R e v i s i o n A 12.4 8-contact 6x5 WSON
W25D10, W25D20, W25D40, W25D80 - 42 - 12.5 8-contact 6x5 WSON Cont’d.
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 4 3 - P r e l i m i n a r y - R e v i s i o n A 13. ORDERING INFORMATION (1) Notes: 1. The Winbond W25D20, W25D40 and W25D80 are fully compat ible with the previous Nexflash NX25X20, NX25X40 and NX25X80 Serial Flash Memories. 2. Please check with Winbond for availability. 3. Only the 2 nd letter is used for the part marking.
W25D10, W25D20, W25D40, W25D80 - 44 - 14. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 07/15/06 New Create
W25D10, W25D20, W25D40, W25D80 Publication Release Date: July 15, 2006 - 4 5 - P r e l i m i n a r y - R e v i s i o n A Preliminary Designation The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not g uaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. Trademarks Winbond and spiFlash are trademarks of Winbond Electronics Corporation All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Taipei Office TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (H.K.) Ltd. No. 378 Kwun Tong Rd., Kowloon, Hong Kong FAX: 852-27552064 Unit 9-15, 22F, Millennium City, TEL: 852-27513100 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998 27F, 2299 Yan An W. Rd. Shanghai, TEL: 86-21-62365999 Winbond Electronics Corporation Japan Shinyokohama Kohoku-ku, Yokohama, 222-0033 FAX: 81-45-4781800 7F Daini-ueno BLDG, 3-7-18 TEL: 81-45-4781881 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C.