DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 133
Technical content
AC’97 Audio and Touchpanel Codec http://www.cirrus.com Copyright Cirrus Logic, Inc., 2008–2016 (All Rights Reserved) Rev 4.0 DEC ‘16 WM9713L
DESCRIPTION
The WM9713L is a highly integrated input/output device designed for mobile computing and communications. The chip is architected for dual CODEC operation, supporting hi-fi stereo CODEC functions via the AC link interface, and additionally supporting voice CODEC functions via a PCM type Synchronous Serial Port (SSP). A third , auxiliary DAC is provided which may be used to support generation of supervisory tones, or ring -tones at different sample rates to the main CODEC. The device can connect d irectly to a 4 -wire or 5 -wire touch - panel, mono or stereo microphones, stereo headphones and a stereo speaker, reducing total component count in the system. Cap-less connections to the headphones, speakers, and earpiece may be used, saving cost and board a rea. Additionally, multiple analog ue input and output pins are provided for seamless integration with analog ue connected wireless communication devices. All device functions are accessed and controlled through a single AC-Link interface compliant with the AC’97 standard. The 24.576MHz master clock can be input directly or generated internally from a 13MHz (or other frequency) clock by an on-chip PLL. The PLL supports a wide range of input clock from 2.048MHz to 78.6MHz. The WM9713L operates at supply volt ages from 1.8 V to 3.6V. Each section of the chip can be powered down under software control to save power. The device is available in a small leadless 7x7mm QFN package, ideal for use in hand -held portable systems.
FEATURES
AC’97 Rev 2.2 compatible stereo CODEC - DAC SNR 94dB, THD –85dB - ADC SNR 87dB, THD –86dB - Variable Rate Audio, supports all WinCE sample rates - Tone Control, Bass Boost and 3D Enhancement On-chip 45mW headphone driver On-chip 400mW mono or stereo speaker drivers Stereo, mono or differential microphone input - Automatic Level Control (ALC) - Mic insert and mic button press detection Auxiliary mono DAC (ring tone or DC level generation) Seamless interface to wireless chipset Resistive touchpanel interface - Supports 4-wire and 5-wire panels - 12-bit resolution, INL 2 LSBs (<0.5 pixels) - X, Y and touch-pressure (Z) measurement - Pen-down detection supported in Sleep Mode Additional PCM/I2S interface to support voice CODEC PLL derived audio clocks. Supports input clock ranging from 2.048MHz to 78.6MHz 1.8V to 3.6V supplies (digital down to 1.62V, speaker up to 4.2V) 7x7mm 48-lead QFN package
APPLICATIONS
Smartphones Personal Digital Assistants (PDA) Handheld and Tablet Computers BLOCK DIAGRAM MONO ALC / NOISE GATE TONE / BASS BOOST MIC2A/COMP1/AUX1 MIC2B/COMP2/AUX2 LINER LINEL PCBEEP SDATAIN SYNC BITCLK RESETB/GPIO7/PENDOWN SDATAOUT X+ WIPER/ AUX4/ GPIO8/ (SPDIF) MCLKA MCLKB/GPIO6/(ADA/MASK) 4-wire or 5-wire resistive touchpanel ADCSEL TPGND TPVDD TOUCH PANEL MATRIX DCVDD DBVDDDGND2 HPVDDHPGND AC'97 INTERFACE AUX DAC MONOIN ADC L ADC R MICBIAS VREFAVDDAGND CAP2 50K50K VREF DAC L DAC R HEADPHONE MIXER SPEAKER MIXER MONO MIXER AUX ADC INPUT PGAs RECORD SELECT RECORD VOLUME DGND1 SPKVDDSPKGNDAGND2 MICCM MIC1 DIFFERENTIAL STEREO or MONO MICS GPIO2/IRQ GPIO1/PCMCLK GPIO3/PENDOWN/PCMFS GPIO4/ADA/MASK/PCMDAC GPIO5/SPDIF/PCMADC PLL PCM/I2S INTERFACE VOICE DAC DEAD BAT LOW BAT VREF / AUX4 Stereo Speaker (R) Stereo Speaker (L) HP 16/32R Ear Speaker 32R Hands-free 32R HPL HPR SPKL SPKR OUT3 OUT4 SPKVDD / 3 WM9713L PORAVDD DCVDD RESETB (pin 11) rb
2 Rev 4.0 TABLE OF CONTENTS
Rev 4.0 3
4 Rev 4.0 PIN CONFIGURATION WM9713L 47 46 4548 44 43 42 41 40 39 38 37 14 15 1613 17 18 19 20 21 22 23 24 SPKRDBVDD SPKL SPKGND OUT3 CAP2 OUT4 MIC2B / COMP2 / AUX2 MIC2A / COMP1 / AUX1 MICBIAS VREF AGND AVDD MCLKB / GPIO6 / (ADA / MASK) MCLKA DGND1 SDATAOUT BITCLK DGND2 SDATAIN DCVDD SYNC RESETB / GPIO7 / (PENDOWN) WIPER / AUX4 / GPIO8 / (SPDIF) GPIO4 / ADA / MASK / PCMDAC GPIO5 / SPDIF / PCMADC GPIO2 / IRQ GPIO3 / PENDOWN / PCMFS HPL HPGND SPKVDD GPIO1 / PCMCLK HPR AGND2 X+ / BR TPVDD X- / TL Y+ / TR TPGND Y- / BL MONOIN PCBEEP MICCM MIC1 LINER LINEL HPVDD MONO
ORDERING INFORMATION
RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM9713CLGEFL/V -25 to +85oC 48-lead QFN (Pb-free) MSL3 260oC WM9713CLGEFL/RV -25 to +85oC 48-lead QFN (Pb-free, tape and reel) MSL3 260oC Note: Reel quantity = 2,200 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION
1 DBVDD Supply Digital I/O Buffer Supply
2 MCLKA Digital Input Master Clock A Input
3 MCLKB / GPIO6 / (ADA / MASK) Digital In/Out Master Clock B Input / GPIO6 / (ADA output / MASK input)
4 DGND1 Supply Digital Ground (return path for both DCVDD and DBVDD)
5 SDATAOUT Digital Input Serial Data Output from Controller / Input to WM9713L
6 BITCLK Digital Output Serial Interface Clock Output to Controller
Rev 4.0 5 PIN NAME TYPE DESCRIPTION
7 DGND2 Supply Digital Ground (return path for both DCVDD and DBVDD)
8 SDATAIN Digital Output Serial Data Input to Controller / Output from WM9713L
9 DCVDD Supply Digital Core Supply
10 SYNC Digital Input Serial Interface Synchronisation Pulse from Controller
11 RESETB / GPIO7 / (PENDOWN) Digital In / Out Reset (asynchronous, active Low, resets all registers to their default) / GPIO7 / (pen down output) 12 WIPER / AUX4 / GPIO8 / (S/PDIF) Analogue In / Out Top Sheet Connection for 5-wire Touchpanels / Auxiliary ADC input / GPIO8 / (S/PDIF digital audio output)
13 TPVDD Supply Touchpanel Driver Supply
14 X+/ BR Analogue Input Touchpanel Connection: X+ (Right) for 4-wire / bottom right for 5-
15 Y+/TR Analogue Input Touchpanel Connection: Y+ (Top) for 4-wire / top right for 5-wire
16 X-/TL Analogue Input Touchpanel Connection: X- (Left) for 4-wire / top left for 5-wire
17 Y-/BL Analogue Input Touchpanel Connection: Y- (Bottom) for 4-wire / bottom left for 5-
18 TPGND Supply Touchpanel Driver Ground
19 PCBEEP Analogue Input Line Input to analogue audio mixers, typically used for beeps
20 MONOIN Analogue Input Mono Input (RX)
21 MIC1 Analogue Input Microphone preamp A input 1
22 MICCM Analogue Input Microphone common mode input
23 LINEL Analogue Input Left Line Input
24 LINER Analogue Input Right Line Input
25 AVDD Supply Analogue Supply (audio DACs, ADCs, PGAs, mic amps, mixers)
26 AGND Supply Analogue Ground
27 VREF Analogue Output Internal Reference Voltage (buffered CAP2)
28 MICBIAS Analogue Output Bias Voltage for Microphones (buffered CAP2 1.8)
29 MIC2A / COMP1 / AUX1 Analogue Input Microphone preamp A input 2 / COMP1 input / Auxiliary ADC input
30 MIC2B / COMP2 / AUX2 Analogue Input Microphone preamp B input / COMP2 input / Auxiliary ADC input
31 MONO Analogue output Mono output driver (line or headphone)
32 CAP2 Analogue In / Out Internal Reference Voltage (normally AVDD/2, if not overdriven)
33 OUT4 Analogue Output Auxiliary output driver (speaker, line or headphone)
34 SPKGND Supply Speaker ground (feeds output buffers on pins 33, 35, 36 and 37)
35 SPKL Analogue Output Left speaker driver (speaker, line or headphone)
36 SPKR Analogue Output Right speaker driver (speaker, line or headphone)
37 OUT3 Analogue Output Auxiliary output driver (speaker, line or headphone)
38 SPKVDD Supply Speaker supply (feeds output buffers on pins 33, 35, 36 and 37)
39 HPL Analogue Output Headphone left driver (line or headphone)
40 HPGND Supply Headphone ground (feeds output buffers on pins 39 and 41)
41 HPR Analogue Output Headphone right driver (line or headphone)
42 AGND2 Supply Analogue ground, chip substrate
43 HPVDD Supply Headphone supply (feeds output buffers on pins 39 and 41)
44 GPIO1 / PCMCLK Digital In / Out GPIO Pin 1 / PCM interface clock
45 GPIO2 / IRQ Digital In / Out GPIO Pin 2 / IRQ (Interrupt Request) output
46 GPIO3 / PENDOWN / PCMFS Digital In / Out GPIO Pin 3 / pen down output or PCM frame signal
47 GPIO4 / ADA / MASK / PCMDAC Digital In / Out GPIO Pin 4 / ADA (ADC data available) output or Mask input / PCM input (DAC) data 48 GPIO5 / S/PDIF / PCMADC Digital In / Out GPIO Pin 5 / S/PDIF digital audio output / PCM output (ADC) data
49 GND_PADDLE Die Paddle (Note 1)
Note: 1. It is recommended that the GND_PADDLE is connected to analogue ground. Refer to “Recommended External Components” and “Package Dimensions” for further information.
6 Rev 4.0 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed perfor mance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus Logic tests its package types according to IPC/JEDEC J -STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Digital supply voltages (DCVDD, DBVDD) -0.3V +3.63V Analogue supply voltages (AVDD, HPVDD, TPVDD) -0.3V +3.63V Speaker supply voltage (SPKVDD) -0.3V +4.2V Touchpanel supply voltage (TPVDD) AVDD +0.3V Voltage range digital inputs DGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Voltage range touchpanel Inputs X+, X-, Y+ and Y- TPVDD +0.3V Voltage range touchpanel Inputs X+, X-, Y+ and Y- AVDD +0.3V Operating temperature range, TA -25oC +85oC RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital input/output buffer supply range DBVDD 1.71 3.3 3.6 V Digital core supply range DCVDD 1.71 1.8 3.6 V Analogue supply range AVDD, HPVDD, TPVDD 1.8 3.3 3.6 V Speaker supply range SPKVDD 1.8 3.3 4.2 V Digital ground DGND1, DGND2 0 V Analogue ground AGND, HPGND, SPKGND, TPGND 0 V Difference AGND to DGND Note 1 -0.3 0 +0.3 V Notes: 1. AGND is normally the same as DGND1/DGND2 2. DCVDD <= DBVDD and DCVDD <= AVDD 3. DCVDD should be >=2V when using the PLL
Rev 4.0 7
ELECTRICAL CHARACTERISTICS
DBVDD=3.3V, DCVDD = 3.3V, AVDD=HPVDD=SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Line-Out (HPL/R, SPKL/R or MONO with 10k / 50pF load) Full-scale output (0dBFS) AVDD = 3.3V, PGA gains set to 0dB
1 V rms
(A-weighted) SNR 85 94 dB Total Harmonic Distortion THD -3dB output -85 -74 dB Power Supply Rejection PSRR 100mV, 20Hz to 20kHz signal on AVDD 50 dB Speaker Output (SPKL/SPKR with 8 bridge tied load, INV=1) Output Power at 1% THD PO THD = 1% 400 mW (rms) Abs. max output power POmax 500 mW (rms) Total Harmonic Distortion THD PO = 200mW -66 0.05 dB Signal to Noise Ratio (A-weighted) SNR 90 dB Stereo Speaker Output (SPKL/OUT4 and SPKR/OUT3 with 8 bridge tied load, INV=1) Output Power at 1% THD PO THD = 1% 400 mW (rms) Abs. max output power POmax 500 mW (rms) Total Harmonic Distortion THD PO = 200mW -66 0.05 dB Signal to Noise Ratio (A-weighted) SNR 90 dB Headphone Output (HPL/R, OUT3/4 or SPKL/SPKR with 16 or 32 load) Output Power per channel PO Output power is very closely correlated with THD; see below. Total Harmonic Distortion THD PO=10mW, RL=16 -80 dB PO=10mW, RL=32 -80 PO=20mW, RL=16 -78 PO=20mW, RL=32 -79 Signal to Noise Ratio (A-weighted) SNR 90 dB Note: 1. All THD values are valid for the output power level quoted above – for example, at HPVDD=3.3V and RL=16, THD is –80dB when output power is 10mW. Higher output power is possible, but will result in deterioration in THD.
8 Rev 4.0 AUDIO INPUTS Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT LINEL/R, MIC1/2A/2B, MONOIN and PCBEEP pins Full Scale Input Signal Level (0dBFS) VINFS AVDD = 3.3V 1.0 Vrms AVDD = 1.8V 0.545 differential input mode (MS = 01) AVDD = 3.3V 0.5 differential input mode (MS = 01) AVDD = 1.8V 0.273 Input Resistance RIN 0dB PGA gain 25.6 32 38.4 k 12dB PGA gain 10.4 13 15.6 Input Capacitance 5 pF Line input to ADC (LINEL, LINER, MONOIN) Signal to Noise Ratio (A-weighted) SNR 80 87 dB Total Harmonic Distortion THD -3dBFS input -86 -80 dB Power Supply Rejection PSRR 20Hz to 20kHz 50 dB Microphone input to ADC (MIC1/2A/2B pins) Signal to Noise Ratio (A-weighted) SNR 20dB boost enabled 80 dB Total Harmonic Distortion THD 20dB boost enabled -80 dB AUXILIARY MONO DAC (AUXDAC) Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 8kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 bits Full scale output voltage AVDD=3.3V 1 Vrms Signal to Noise Ratio (A-weighted) SNR 65 71 dB Total Harmonic Distortion THD 0dBFS input 50 63 dB PCM VOICE DAC (VXDAC) Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 8kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Resolution 16 bits Sample rates 8 16 Ks/s Full scale output voltage AVDD=3.3V 1 Vrms Signal to Noise Ratio (A-weighted) SNR 80 dB Total Harmonic Distortion THD 74 dB
Rev 4.0 9 TOUCHPANEL AND AUXILIARY ADC Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Input Pins X+, X-, Y+, Y-, WIPER/AUX4, COMP1/AUX1, COMP2/AUX2 Input Voltage AGND AVDD V Input leakage current AUX pin not selected as AUX ADC input <10 nA ADC Resolution 12 bits Differential Non-Linearity Error DNL 0.25 1 LSB Integral Non-Linearity Error INL 2 LSB Offset Error 4 LSB Gain Error 6 LSB Power Supply Rejection PSRR 50 dB Channel-to-channel isolation 80 dB Throughput Rate DEL = 1111 (zero settling time) 48 kHz Settling Time (programmable) MCLK = 24.576MHz 0 6 ms Switch matrix resistance 20 Programmable Pull-up resistor RPU RPU = 000001 1 63 k Pen down detector threshold VDD/2 V Pressure measurement current IP PIL = 1 400 A PIL = 0 200 COMPARATORS Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT COMP1/AUX1 and COMP2/AUX2 (pins 29, 30 – when not used as mic inputs) Input Voltage AGND AVDD V Input leakage current pin not selected as AUX ADC input <10 nA Comparator Input Offset (COMP1, COMP2 only) -50 +50 mV COMP2 delay (COMP2 only) MCLK = 24.576MHz 0 10.9 s REFERENCE VOLTAGES Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio ADCs, DACs, Mixers Reference Input/Output CAP2 pin 1.63 1.65 1.66 V Buffered Reference Output VREF pin 1.64 1.65 1.67 V Microphone Bias Bias Voltage VMICBIAS 2.92 2.97 3.00 V Bias Current Source IMICBIAS 3 mA Output Noise Voltage Vn 1K to 20kHz 15 nV/Hz
10 Rev 4.0 DIGITAL INTERFACE CHARACTERISTICS Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (all digital input or output pins) – CMOS Levels Input HIGH level VIH DBVDD0.7 V Input LOW level VIL DBVDD0.3 V Output HIGH level VOH source current = 2mA DBVDD0.9 Output LOW level VOL sink current = 2mA DBVDD0.1 Clock Frequency Master clock (MCLKA pin) 24.576 MHz AC’97 bit clock (BIT_CLK pin) 12.288 MHz AC’97 sync pulse (SYNC pin) 48 kHz Notes: 1. All audio and non-audio sample rates and other timing scales proportionately with the master clock. 2. For signal timing on the AC-Link, please refer to the AC’97 specification (Revision 2.2) POWER CONSUMPTION The power consumption of the WM9713L depends on the following factors: Supply voltages: Reducing the supply voltages also reduces digital supply currents, and therefore results in significant power savings especially in the digital sections of the WM9713L. Operating mode: Significant power savings can be achieved by always disabling parts of the WM9713L that are not used (e.g. audio ADC, DAC, touchpanel digitiser). Sample rates: Running at lower sample rates will reduce power consumption significantly. The figures below are for 48kHz (unless otherwise specified), but in many scenarios it is not necessary to run at this frequency, e.g. 8kHz PCM voice call scenario uses only 11.4mW (see below). MODE DESCRIPTION AVDD Supply Current V / mA DCVDD Supply Current V / mA DBVDD Supply Current V / mA Total Power (mW) Off (lowest possible power) Clocks stopped. This is the default configuration after power-up. LPS (Low Power Standby) VREF maintained using 1MOhm string Stereo DAC Playback (AC link to headphone) PLL running with 13MHz input to MCLKB Table 1 Supply Current Consumption Notes: 1. Unless otherwise specified, all figures are at TA = +25C, audio sample rate fs = 48kHz, with zero signal (quiescent), and voltage references settled. 2. The power dissipated in the headphone, speaker and touchpanel is not included in the above table.
Rev 4.0 11 SIGNAL TIMING REQUIREMENTS AC97 INTERFACE TIMING CLOCK SPECIFICATIONS BITCLK SYNC tCLK_HIGH tCLK_LOW tCLK_PERIOD tSYNC_HIGH tSYNC_LOW tSYNC_PERIOD Figure 1 Clock Specifications (50pF External Load) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT BITCLK frequency 12.288 MHz BITCLK period tCLK_PERIOD 81.4 ns BITCLK output jitter 750 ps BITCLK high pulse width (Note 1) tCLK_HIGH 36 40.7 45 ns BITCLK low pulse width (Note 1) tCLK_LOW 36 40.7 45 ns SYNC frequency 48 kHz SYNC period tSYNC_PERIOD 20.8 s SYNC high pulse width tSYNC_HIGH 1.3 s SYNC low pulse width tSYNC_LOW 19.5 s Note: 1. Worst case duty cycle restricted to 45/55
12 Rev 4.0 DATA SETUP AND HOLD BITCLK SDATAIN SDATAOUT SYNC V V V tHOLD V tSETUPtCO OL OH IH IL Figure 2 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9713L. Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Setup to falling edge of BITCLK tSETUP 10 ns Hold from falling edge of BITCLK tHOLD 10 ns Output valid delay from rising edge of BITCLK tCO 15 ns
Rev 4.0 15 PCM AUDIO INTERFACE TIMING – SLAVE MODE PCMCLK PCMFS tCLKH tCLKL tCLKY PCMDAC PCMADC tFSSUtDS tFSH tDHtDD Figure 7 Digital Audio Data Timing – Slave Mode Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information PCMCLK cycle time tPCMY 50 ns PCMCLK pulse width high tPCMH 20 ns PCMCLK pulse width low tPCML 20 ns PCMFS set-up time to PCMCLK rising edge tFSSU 10 ns PCMFS hold time from PCMCLK rising edge tFSH 10 ns PCMDAC set-up time from PCMCLK rising edge tDS 10 ns PCMDAC hold time from PCMCLK rising edge tDH 10 ns PCMADC propagation delay from PCMCLK falling edge tDD 10 ns Note: 1. PCMCLK period should always be greater than or equal to Voice CLK period.
16 Rev 4.0 PCM AUDIO INTERFACE TIMING – MASTER MODE PCMCLK (Output) PCMADC PCMFS (Output) tDL PCMDAC tDDA tDHTtDST Figure 8 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information PCMFS propagation delay from PCMCLK falling edge tDL 10 ns PCMADC propagation delay from PCMCLK falling edge tDDA 10 ns PCMDAC setup time to PCMCLK rising edge tDST 10 ns PCMDAC hold time from PCMCLK rising edge tDHT 10 ns
Rev 4.0 17 DEVICE DESCRIPTION INTRODUCTION The WM9713L is a largely pin-compatible upgrade to WM9712, with a PCM voice CODEC added. This CODEC is interface d via a PCM type audio interface which makes use of GPIO pins for connection. It is designed to meet the mixed -signal requirements of portable and wireless smartphone systems. It includes audio recording and playback, touchpanel digitisation, battery monitoring, auxiliary ADC and GPIO functions, all controlled through a single 5 -wire A C-Link interface. Additionally, PCM voice CODEC functions are supported through provision of an additional voice DAC and a PCM audio serial interface. A PLL is included to allow unrelated reference clocks to be used for generation of the AC link system clock. Typically 13MHz or 2.048MHz clock sources might be used as a reference. SOFTWARE SUPPORT The basic audio features of the WM9713L are software compatible with standard AC’97 device drivers. However, to better support the touchpanel and other additional functions, Cirrus Logic supplies custom device drivers for selected CPUs and operating systems. Please contact your local Cirrus Logic representative for more information. AC’97 COMPATIBILITY The WM9713L uses an AC’97 interface to communicate with a micr oprocessor or controller. The audio and GPIO functions are largely compliant with AC’97 Revision 2.2. The following differences from the AC’97 standard are noted: Pinout: The function of some pins has been changed to support device specific features. The PHONE and PCBEEP pins have been moved to different locations on the device package. Package: The default package for the WM9713L is a 77mm leadless QFN package. Audio mixing: The WM9713L handles all the audio functions of a smartphone, including audio playback, voice recording, phone calls, phone call recording, ring tones, as well as simultaneous use of these features. The AC’97 mixer architecture does not fully support this. The WM9713L therefore uses a modified AC’97 mixer architecture with three separate mixers. Tone Control, Bass Boost and 3D Enhancement: These functions are implemented in the digital domain and therefore affect only signals being played through the audio DACs, not all output signals as stipulated in AC’97. Some other functions are additional to AC’97: On-chip BTL loudspeaker driver for mono or stereo speakers On-chip BTL driver for ear speaker (phone receiver) Auxiliary mono DAC for ring tones, system alerts etc. Touchpanel controller Auxiliary ADC Inputs 2 Analogue Comparators for Battery Alarm Programmable Filter Characteristics for Tone Control and 3D Enhancement PCM interface to additional Voice DAC and existing audio ADCs PLL to create AC’97 system clock from unrelated reference clock input
18 Rev 4.0 PCM CODEC The PCM voice CODEC functions typically required by mobile telephony devices are provided by an extra voice DAC on the WM9713L, which is interfaced via a standard PCM type data interface, which is constructed through optional use of 4 of the GPIO pins on WM9713L. The audio output data from one or both of the audio ADCs can also be output over this PCM interface, allowing a full voice CODEC function to be implemented. This PCM interface supports sample rates from 8 to 48ks/s using the standard AC’97 master clock.
Rev 4.0 19 AUDIO PATHS OVERVIEW WM9713 Analogue LINEL
12 Bit Resistor
Note: all PGAs and summers are inverting DACR DACL LINER LINEL PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC PCBEEP MONOIN 08h:12-8 00000 = +12dB 11111 = -34.5dB 0Eh:12-8 00000 = +12dB 11111 = -34.5dB 0Ah:12-8 00000 = +12dB 11111 = -34.5dB DACR DACL LINER LINEL PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC 0Ah:4-0 00000 = +12dB 11111 = -34.5dB 0Eh:4-0 00000 = +12dB 11111 = -34.5dB LINER AGNDAVDD CAP VREF VMICBIAS 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB Headphone Mixer L 0Ch:15 0Ah:15 08h:15 16h:15-12 10h:4-0 10h:4-0 14h:15-11 14h:15-11 1Ah:15-12 18h:15-12 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 0dB / 20dB 0dB / 20dB 0dB / 20dB 0dB / 20dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB MONO Mixer 0Ch:13 0Ch:13 0Ah:13 0Ah:13 16h7:4 10h:7+5 10h:6+5 14h:10-8 1Ah:7-4 14h:10-8 18h:7-4 Speaker Mixer 0Ah:14 0Ah14 0Ch:14 0Ch:14 08h:14 16h:11-8 1Ah:11-8 18h:11-8 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB DACR DACL LINER LINEL PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC ADC Right AC'97 Link 40h:7 (Loopback)
18 Bit DACR
40h:13 (3DE) 0Ch:4-0 00000 = +12dB 11111 = -34.5dB ADC Left AC'97 Link 40h:7 (Loopback)
18 Bit DACL
40h:13 (3DE) 0Ch:12-8 00000 = +12dB 11111 = -34.5dB LINER LINEL MICB MICA PCBEEP MONOIN LINER LINEL MICB MICA PCBEEP MONOIN LINER LINEL MICB MICA PCBEEP MONOIN LINER LINEL MICB MICA PCBEEP MONOIN MIC1 MIC2A MICCM MIC2B Vmid Vmid Vmid 22h:11-10 00 = +12dB 11 = +30dB 22h:9-8 00 = +12dB 11 = +30dB 22h: 13-12
16 Bit PCM
AC'97 Link PCM Link DACR DACL LINER LINEL PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC DACR DACL LINER LINEL PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC LINER LINEL MICB MICA PCBEEP MONOIN 1Eh:12-10 MONOMIX HPMIXL HPMIXR SPKMIX INV1 INV2 MONOMIX HPMIXL HPMIXR SPKMIX INV1 INV2 MONOMIX HPMIXL HPMIXR SPKMIX INV1 INV2 MONOMIX HPMIXL HPMIXR SPKMIX INV1 INV2 MONOMIX HPMIXL HPMIXR SPKMIX INV1 INV2 08h:4-0 00000 = 0dB 11111 = -46.5dB Zero-cross detect 08h:6 (ZC) 08h:7 (MUTE) MONO 1Ch:15-14 Vmid 02h:12-8 00000 = 0dB 11111 = -46.5dB Zero-cross detect 02h:14 (ZC) 02h:15 (MUTE) SPKL 1Ch:13-11 Vmid 04h:12-8 00000 = 0dB 11111 = -46.5dB Zero-cross detect 04h:14 (ZC) 04h:15 (MUTE) 1Ch:7-6 Vmid HPL 06h:4-0 00000 = 0dB 11111 = -46.5dB Zero-cross detect 06h:6 (ZC) 06h:7 (MUTE) OUT3 1Ch:3-2 Vmid 06h:12-8 00000 = 0dB 11111 = -46.5dB Zero-cross detect 06h:14 (ZC) 06h:15 (MUTE) OUT4 1Ch:1-0 Vmid 02h:4-0 00000 = 0dB 11111 = -46.5dB Zero-cross detect 02h:6 (ZC) 02h:7 (MUTE) SPKR 1Ch:10-8 Vmid 04h:4-0 00000 = 0dB 11111 = -46.5dB Zero-cross detect 04h:6 (ZC) 04h:7 (MUTE) HPR 1Ch:5-4 Vmid DACR DACL LINER LINEL PCBEEP MONOIN MIC2 MICA RECMUXR RECMUXL AUXDAC VXDAC DACL LINEL PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC DACL LINEL PCBEEP LINER MICB MICA RECMUXR RECMUXL AUXDAC VXDAC DACR DACR LINER PCBEEP MONOIN MICB MICA RECMUXR RECMUXL AUXDAC VXDAC LINER LINEL DACR DACL PCBEEP MONOIN AUXDAC VXDAC HPMIXL HPMIXL SPKMIX INV1 MONOMIX INV1 INV1 INV2 HPMIXR HPMIXR SPKMIX INV2
18 Bit ADC
5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h 14h:5-3 12h:14 (GRL=1) 12h:13-8 11111 = +30dB 00000 = -17.25dB 14h:6 0 = 0dB 1 = 20dB 12h:14 (GRL=0) 12h:11:8 0000 = 0db 1111 = +22.5dB PCM Link AC'97 Link Sent to Both 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h 14h:2-0 12h:6 (GRR=1) 12h:5-0 11111 = +30dB 00000 = -17.25dB 14h:6 0 = 0dB 1 = 20dB 12h:6 (GRR=0) 12h:3:0 0000 = 0db 1111 = +22.5dB PCM Link AC'97 Link Sent to Both 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB Headphone Mixer R 0Ch:15 0Ah:15 08h:15 16h:15-12 10h:4-0 10h:4-0 14h:15-11 14h:15-11 1Ah:15-12 18h:15-12 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 1Eh:15-13 PR0 - Audio ADCs & record mux PR1 - Stereo DAC PR2 - Input PGAs & mixers PR3 - Refs, input PGAs, mixers & output PGAs PR6 - Output PGAs PR Bit Code Note: PR bits are active low - i.e. 0 = "ON"; 1 = "OFF" => Enable when { (PR0 || PR2) && PR3 } are low Figure 9 Audio Paths Overview
20 Rev 4.0 CLOCK GENERATION WM9713L supports clocking from 2 separate sources, which can be selected via the AC’97 interface: External clock input MCLKA External clock input MCLKB The source clock is divided to appropriate frequencies in order to run the AC’97 interface, PCM interface, voice DAC and hi-fi DSP by means of a programmable divider block. Clock rates may be changed during operation via the AC’97 link in order to support alternative modes, for example low power mode when voice data is being transmitted only. A PLL is present to add flexibility in selection of input clock frequencies, typical choices being 2.048MHz, 4.096MHz or 13MHz. INITIALISING THE AC’97 LINK By default, the AC’97 link is disabled a nd therefore will not be running after power on or a COLD reset event. Before any register map configuration can begin, it is necessary to start the AC’97 link. This is achieved by sending a WARM reset to the CODEC as defined in Figure 6. Default mode on power -up also assumes a clock will be present on MCLKA with the PLL powered down. After a WARM reset the CODEC will start the AC’97 link using MCLKA as a reference. This enables data to be clocked via the AC’97 lin k to define the desired clock divider mode and whether PLL needs to be activated. Note: MCLKA can be any available frequency. When muxing between MCLKA and MCLKB both clocks must be active for at least two clock cycles after the switching event. CLOCK DIVISION MODES Figure 10 shows the clocking strategy for WM9713L. Clocking is contro lled by CLK_MUX, CLK_SRC and S[6:0]. CLKAX2, CLKBX2 – clock doublers on inputs MCLKA and MCLKB. CLK_MUX - selects between MCLKA and MCLKB. CLK_SRC – selects between external or PLL derived clock reference. S[3:0] – sets the voice DAC clock rate and PCM interface clock when in master mode (division ratio 1 to 16 available). S[6:4] - sets the hi-fi clocking rate (division ratio 1 to 8 available). The registers used to set these switches can be accessed from register address 44h (see Table 3). If a mode c hange requires switching from a n external clock to a PLL generated clock then it is recommended to set the cloc k division ratios required for the PLL clock scheme prior to switching between clocks. This option is accommodated by means of two sets of registers . SPLL[6:0] is used to set the divide ratio of the clock when in PLL mode and SEXT[6:0] is used to divide th e clock when it is derived from an external source . If the PLL is selected (CLK_SRC = 0) , S[6:0] = SPLL[6:0]. SPLL[6:0] is defined in register 46h (see Table 4) and is written to using the page address mode. More details o n page address mode for controlling the PLL are found on page 25. Register 46h also contains a number of separate control bits relating to the PLL’s function. I f an external clock is selected (CLK_SRC = 1) S[6:0] = SEXT[6:0]. SEXT[6:0] is defined in register address 44h. Writing to registers 44h and 46h enables pre-programming of the required clock mode before the PLL output is selected.
Rev 4.0 21 AC'97 MCLKA MCLKB CLKSRC 0 PCM PLL DIV 1-16 DIV 1-8 SEXT[3:0] / SPLL[3:0] / SEXT[6:4] / SPLL[6:4] / VOICE DAC HIFI DSP L/R ADCs L/R DACs AUX DAC WM9713L data bus clock VOICE DAC CLOCK AC97 CLK HIFI CLK CLK_MUX MUX 0 1 x2 x2 CLKBX2CLKAX2 SYSCLK DIV 2 BCLK DIV 1-16 AUX ADC PENDIV [2:0] PCMCLK AC-Link Figure 10 Clocking Architecture for WM9713L INTERNAL CLOCK FREQUENCIES The internal clock frequencies are defined as follows (refer to Figure 10): AC97 CLK – nominally 24.576MHz, used to generate AC97 BITCLK at 12.288MHz HIFI CLK – for hi-fi playback at 48ks/s HIFI C LK = 24.576MHz. See Table 2 for voice only playback. Voice DAC CLK – see Table 2 for sample rate vs clock frequency. SAMPLE RATE VOICE DAC CLK FREQUENCY HIFI CLK FREQUENCY 8ks/s voice and hi-fi 2.048MHz 24.576MHz 8ks/s voice only (power save) 2.048MHz 4.096MHz 16ks/s voice and hi-fi 4.096MHz 24.576MHz 16ks/s voice only (power save) 4.096MHz 8.192MHz 32ks/s voice and hi-fi 8.192MHz 24.576MHz 48ks/s voice and hi-fi 12.288MHz 24.576MHz Table 2 Clock Division Mode Table
22 Rev 4.0 AUXADC The clock for the AUXADC nominally runs at 768kHz and is derived from BITCLK. The divisor for the clock generator is set by PENDIV. This enables the AUXADC clock frequency to be set according to power consumption and conversion rate considerations. Clock mode and division ratios are controlled by register 44h as shown in Table 3. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 44h 14:12 SEXT[6:4] 000 (div 1) Hi-fi Block Clock Division Control 000 = f 001 = f/2 111 = f/8 11:8 SEXT[3:0] 0000 (div 1) Voice DAC Clock Division Control 0000 = f 0001 = f/2 1111 = f/16
7 CLKSRC 1 (ext clk) AC97 CLK Source Control
1 = External clock 0 = PLL clock 5:3 PENDIV 000 (div 16) AUXADC Clock Division Control 000 = f/16 001 = f/12 010 = f/8 011 = f/6 100 = f/4 101 = f/3 110 = f/2 111 = f
2 CLKBX2 0 (Off) MCLKB Multiplier Control
0 = Normal 1 = Multiply by 2
1 CLKAX2 0 (Off) MCLKA Multiplier Control
0 = Normal 1 = Multiply by 2
0 CLKMUX 0 (MCLKA) External Clock Source Control
0 = Use MCLKA 1 = Use MCLKB Note: On power-up clock must be present on MCLKA and must be active for 2 clock cycles after switching to MCLKB Table 3 Clock Muxing and Division Control PLL MODE The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation: Integer N Fractional N The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz – 19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1). Through use of a clock divider (div by 2 / 4) on the input to the PLL frequencies up to 78.6 MHz can be accommodated. The input clock divider is enabled by DIVSEL (0=Off) and the division ratio is set by DIVCTL (0=div2, 1=div4).
Rev 4.0 23 PLL DIV N DIV4/1 DIV 4/2/1MCLK SDM K[21:0] N[3:0] LF DIVSEL DIVCTL 98.304MHz WM9713 PLL CLK_OUTPLL_IN PLL_OUT DIV 4 SDM Figure 11 PLL Architecture REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 46h 15:12 N[3:0] 0000 PLL N Divide Control 0000 = Divide by 1 0001 = Divide by 1 0010 = Divide by 2 1111 = Divide by 15 Note: must be set between 05h and 0Ch for integer N mode
11 LF 0 = off PLL Low Frequency Input Control
1 = Low frequency mode (input clock < 8.192MHz) 0 = Normal mode 46h 10 SDM 0 = off PLL SDM Enable Control 1 = Enable SDM (required for fractional N mode) 0 = Disable SDM 46h 9 DIVSEL 0 = off PLL Input Clock Division Control 0 = Divide by 1 1 = Divide according to DIVCTL
8 DIVCTL 0 PLL Input Clock Division Value Control
0 = Divide by 2 1 = Divide by 4 46h 6:4 PGADDR 000 Pager Address Pager address bits to access programming of K[21:0] and SPLL[6:0] 46h 3:0 PGDATA 0000 Pager Data Pager data bits Table 4 PLL Clock Control
24 Rev 4.0 INTEGER N MODE The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz which is divided by 4 to achieve a nominal system clock of 24.576MHz. The integer division ratio (N) is determined by: FPLL_out / FPLL_IN , and is set by N[3:0] and must be in the range 5 to 12 for integer N operation (0101 = div by 5, 1100 = div by 12 ). No te that setting LF=1 enables a further division by 4 required for input frequencies in the range 2.048MHz – 4.096MHz. Integer N mode is selected by setting SDM=0. FRACTIONAL N MODE Fractional N mode provides a divide resolution of 1/2 22 and is set by K[21 :0] (register 46h, see section). The relationship between the required division X, the fractional division K[21:0] and the integer division N[3:0] is: NXK 222 where 0 < (X – N) < 1 and K is rounded to the nearest whole number. For example, if the PLL _IN clock is 13MHz and the desired PLL_OUT clock is 98.304MHz then the desired division, X, is 7.5618. So N[3:0] will be 7h and K[21:0] will be 23F488h to produce the desired 98.304MHz clock (see Table 5). INPUT CLOCK (PLL_IN) DESIRED PLL OUTPUT (PLL_OUT) DIVISION REQUIRED (X) FRACTIONAL DIVISION (K) INTEGER DIVISION (N) 2.048MHz 98.304MHz 48 0 12x4* 4.096MHz 98.304MHz 24 0 6x4* 12.288MHz 98.304MHz 8 0 8 13MHz 98.304MHz 7.5618 0.5618 7 27MHz (13.5MHz)** 98.304MHz 7.2818 0.2818 7 *Divide by 4 enabled in PLL feedback path for low frequency inputs. (LF = 1) **Divide by 2 enabled at PLL input for frequencies > 14.4MHz > 38MHz (DIVSEL = 1, DIVCTL = 0) Table 5 PLL Modes of Operation
Rev 4.0 25 PLL REGISTER PAGE ADDRESS MAPPING The clock division control bits S PLL[6:0] and the PLL fractional N division bits are accessed through register 46h using a sub -page address system. The 3-bit pager address allows 8 blocks of 4 -bit data words to be accessed whilst the register address is set to 46h. This means that when register address 46h is selected a further 7 cycles of programming are required to set all of the page data bits. Control bit allocation for these page addresses is described in Table 6. PAGE ADDRESS BIT LABEL DEFAULT DESCRIPTION 111 31:28 SPLL[6:4] 0h Clock division control bus SPLL[6:0]. Clock divider reads this control word if PLL is enabled. Bits [6:4] and [3:0] have the same functionality as 44h [14:12] and [11:8] respectively 110 27:24 SPLL[3:0] 0h 101 23:22 Reserved 0h Reserved bits 21:20 K[21:0] 0h Sigma Delta Modulator control word for fractional N division. Division resolution is 100 19:16 0h 011 15:12 0h 010 11:8 0h 001 7:4 0h 000 3:0 SPLL[3:0] 0h Table 6 Pager Control Bit Allocation Powerdown for the PLL and internal clocks is via registers 26h and 3Ch (see Table 7). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 26h 13 PR5 1 (Off) Internal Clock Disable Control 1 = Disabled 0 = Enabled 3Ch 9 PLL 1 (Off) PLL Disable Control 1 = Disabled 0 = Enabled N.B. both PR5 and PLL must be asserted low before PLL is enabled Table 7 PLL Powerdown Control DIGITAL INTERFACES The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface. The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and RESETB) and is the sole control interface with access to all data stre ams on the device except for the Voice DAC. The PCM interface is available through the GPIO pins (PCMCLK, PCMF S, PCMDAC and PCMADC) and provides access to the Voice DAC. It can also transmit the data from the Stereo ADC. This can be useful, for example, to allow both sides of a phone conversation to be recorded by mixing the transmit and receive paths on one of the ADC channels and transmitting it over the PCM interface.
26 Rev 4.0 AC97 INTERFACE INTERFACE PROTOCOL The WM9713L uses an AC’97 interface for both data transfer and control. The AC-Link has 5 wires: SDATAIN (pin 8) carries data from the WM9713L to the controller SDATAOUT (pin 5) carries data from the controller to the WM9713L BITCLK (pin 6) is a clock, derived from either MCLKA or MCLKB inputs and supplied to the controller. SYNC is a synchronization signal generated by the controller and passed to the WM9713L RESETB resets the WM9713L to its default state CONTROLLER e.g. CPU WM9713L RESETB SDATAIN SDATAOUT BITCLK SYNC AC-LINK ANALOGUE INPUTS / OUTPUTS Figure 12 AC-Link Interface (typical case with BITCLK generated by the AC97 CODEC) The SDATAIN and SDATAOUT signals each carry 13 time -division multiplexed data streams (slots 0 to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio, touchpanel, AUXDAC, control) at sample rates up to 48kHz. Detailed information can be found in the AC’97 (Revision 2.2) specification, which ca n be obtained at www.intel.com/design/chipsets/audio/ Note: SDATAOUT and SYNC must be held low when RESETB is applied. These signals must be held low for the entire duration of the RESETB puls e and especially during the low -to-high transition of RESETB. If SDATAOUT or SYNC is high during reset , the WM9713L may enter test modes. Information relating to this operation is available in the AC'97 specification and in Application Note WAN 0104. PCM INTERFACE OPERATION WM9713L can implement a PCM voice CODEC function using the dedicated VXDAC and either one or both of the existing hi -fi ADC’s. In PCM CODEC mode, VXDAC input and ADC output are interfaced via a PCM style port via GPIO pins. This interface can support one ADC channel, or stereo/dual ADC channels if required, (two channels of data are sent per PCM frame as back to back words). In voice-only mode, the AC link is used only for control information, not audio data. Therefore it will generally be shut down (PR4=1), except when control data must be sent. The PCM interface makes use of 4 of the GPIO interface pins, for clock, frame, and data in/out. If the PCM CODEC function is not enabled then the GPIO pins may be used for other functions.
Rev 4.0 27 INTERFACE PROTOCOL The WM9713L PCM audio interface is used for the input of data to the Voice DAC and the output of data from the Stereo ADC. When enabled, the PCM audio interface uses four GPIO pins: GPIO1/PCMCLK: Bit clock GPIO3/PCMFS: Frame Sync GPIO4/PCMDAC: Voice DAC data input GPIO5/PCMADC: Stereo ADC data output Depending on the mode of operation (see “PCM Interface Modes ”), at least one of these four pins must be set up as an output by writing to register 4Ch (see Table 62). When not enabled the GPIOs may be used for other functions on the WM9713L. PCM INTERFACE MODES The WM9713L PCM audio interface may be configured in one of four modes: Disabled Mode: The WM9713L disables and tri-states all PCM interface pins. Any clock input is ignored and ADC/DAC data is not transferred. Slave Mode: The WM9713L accepts PCMCLK and PCMFS as inputs from an external source. Master Mode: The WM9713L generates PCMCLK and PCMFS as outputs. Partial Master Mode: The WM9713L generates PCMCLK as an output, and accepts PCMFS as an external input. PCM AUDIO DATA FORMATS Four different audio data formats are supported: DSP mode Left justified Right justified I2S All four of these modes are MSB first. They are described below. R efer to “Signal Timing Requirements” for timing information. Note: PCMCLK and PCMFS must be synchronized with the BITCLK from the AC’97 interface. The PCM Interface may be configured for Mono mode, where only one channel of ADC data is output. In this mode the interface should be configured for DSP mode. A short or long frame sync is supported and the MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of VXCLK. Note that when operating in stere o mode the mono Voice DAC always uses the left channel data as its input.
28 Rev 4.0 PCMFS PCMCLK PCMADC/ PCMDAC n321 n-2 n-1 LSBMSB
1 PCMCLK
Input Word Length (WL) 1/fs Figure 13 PCM Interface Mono Mode (mode A, FSP=0) PCMFS PCMCLK PCMADC/ PCMDAC n321 n-2 n-1 LSBMSB Input Word Length (WL) 1/fs Figure 14 PCM Interface Mono Mode (mode B, FSP=1) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of PCMCLK (selectable by FSP) following a rising edge of PCMFS. Right channel data immediately follows left channel data. D epending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of the right channel data and the next sample. LEFT CHANNEL RIGHT CHANNEL PCMFS PCMCLK PCMADC/ PCMDAC n321 n-2 n-1 LSBMSB n321 n-2 n-1
1 BCLK / VXCLK
Input Word Length (WL) 1/fs Figure 7 DSP Mode Audio Interface (mode A, FSP=0)
Rev 4.0 29 LEFT CHANNEL RIGHT CHANNEL PCMFS PCMCLK PCMADC/ PCMDAC n321 n-2 n-1 LSBMSB n321 n-2 n-1 Input Word Length (WL) 1/fs Figure 15 DSP Mode Audio Interface (mode B, FSP=1) In Left Justified mode, the MSB is available on the first rising edge of PCMCLK following a PCMFS transition. The other bits up to the LSB are then transmitted in order . Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles before each PCMFS transition. LEFT CHANNEL RIGHT CHANNEL PCMFS PCMCLK PCMADC/ PCMDAC 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB Figure 16 Left Justified Audio Interface (assuming n-bit word length) In R ight Justified mode, the LSB is available on the last rising edge of PCMCLK before a PCMFS transition. All other bits are transmitted before (MSB first). Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles after each PCMFS transition. LEFT CHANNEL RIGHT CHANNEL PCMFS PCMCLK PCMADC / PCMDAC 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB Figure 17 Right Justified Audio Interface (assuming n-bit word length)
30 Rev 4.0 In I 2S mode, the MSB is available on the second rising edge of PCMCLK following a PCMFS transition. The othe r bits up to the LSB are then transmitted in order. Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of one sample and the MSB of the next. LEFT CHANNEL RIGHT CHANNEL PCMFS PCMCLK PCMADC/ PCMDAC 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB
1 BCLK1 BCLK
Figure 18 I2S Justified Audio Interface (assuming n-bit word length) CONTROL The register bits controlling PCM audio format, word length and operating modes are summarised below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE must be set to specify master/slave modes. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 36h PCM Control
15 CTRL 0 GPIO Pin Configuration Control
0 = GPIO pins as GPIOs 1 = GPIO pins configured as PCM interface and controlled by this register 14:13 MODE 10 PCM Interface Mode Control 00 = PCM interface disabled [PCMCLK tri- stated, PCMFS tri-stated] 01 = PCM interface in slave mode [PCMCLK as input, PCMFS as input] 10 = PCM interface in master mode [PCMCLK as output, PCMFS as output] 11 = PCM interface in partial master mode [PCMCLK as output, PCMFS as input] 11:9 DIV 010 PCMCLK Rate Control 000 = Voice DAC clock 001 = Voice DAC clock / 2 010 = Voice DAC clock / 4 011 = Voice DAC clock / 8 100 = Voice DAC clock / 16 All other values are reserved
8 VDACOSR 1 Voice DAC Oversampling Rate Control
0: 128 x fs 1: 64 x fs
7 CP 0 PCMCLK Polarity Control
0 = Normal 1 = Inverted
6 FSP 0 FMT = 00, 01 or 10 FMT = 11
0 = Normal 1 = Inverted DSP Mode Control 0 = DSP Mode A 1 = DSP Mode B
Rev 4.0 31 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5:4 SEL 10 PCM ADC Output Channel Control 00 = Normal stereo 01 = Reverse stereo 10 = Output left ADC data only 11 = Output right ADC data only 3:2 WL 00 PCM Data Word Length Control 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not supported when FMT=00) 1:0 FMT 11 PCM Data Format Control 00 = Right justified 01 = Left justified 10 = I2S 11 = DSP mode Table 8 PCM CODEC Control Note: Right justified does not support 32-bit data.
32 Rev 4.0 AUDIO ADCS STEREO ADC The WM9713L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high quality audio recording at low power consumption. The ADC sample rate can be controlled by writing to a control register (see “Variable Rate Audio / Sample Rate Conversion”). It is independent of the DAC sample rate. To save power, the left and right ADCs can be separately switched off using the Powerdown bits ADCL and ADCR (register 3Ch, bits 5:4) , whereas PR0 disables both ADCs (see “Power Management”). If only one ADC is running, the same ADC data appears on both the left and right AC - Link slots. The output from the ADC can be sent over either the AC link as usual, or output via the PCM interface which may be configured on the GPIO pins. HIGH PASS FILTER The WM9713L audio ADC incorporates a digital high pass filter that eliminates any DC bias from the ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by writing a ‘1’ to the HPF bit (register 5Ch, bit 3). This high pass filter corner frequency can be selected to have different values in WM9713L, to suit applications such as voice where a higher cutoff frequency is required. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5Ch 3 HPF 0 ADC HPF Disable Control 0 = HPF enabled (for audio) 1 = HPF disabled (for DC measurements) 5Ah 5:4 HPMODE 00 HPF Cut-Off Control 00 = 7Hz @ fs=48kHz 01 = 82Hz @ fs=16kHz 10 = 82Hz @ fs=8kHz 11 = 170Hz @ fs=8kHz Note: the filter corner frequency is proportional to the sample rate. Table 9 Controlling the ADC High-pass Filter ADC SLOT MAPPING By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the right ADC data appears on slot 4. Howe ver, the ADC output data can also be sent to other slots, by setting the ASS (ADC slot select) control bits as shown below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5Ch Additional Functions (2) 1:0 ASS 00 ADC Data Slot Mapping Control Left Data Right Data 00 = Slot 3 Slot 4 01 = Slot 7 Slot 8 10 = Slot 6 Slot 9 11 = Slot 10 Slot 11 Table 10 ADC Slot Mapping
Rev 4.0 33 RECORD SELECTOR The record selector determines which input signals are routed into the audio ADC. The left and right channels can be selected independently. This is useful for recording a phone call: one channel can be used for the RX signal and the other for the TX signal, so that both sides of the conversation are digitized. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 14h Record Routing / Mux Select
6 RECBST 0 ADC Record Boost Control
1 = +20dB 0 = 0dB Note: RECBST gain is in addition to the microphone pre-amps (MPABST and MPBBST bits) and record gain (GRL and GRR / GRL bits). 5:3 RECSL 000 Left Record Mux Source Control 000 = MICA (pre-PGA) 001 = MICB (pre-PGA) 010 = LINEL (pre-PGA) 011 = MONOIN (pre-PGA) 100 = HPMIXL 101 = SPKMIC 110 = MONOMIX 111 = Reserved 2:0 RECSR 000 Right Record Mux Source Control 000 = MICA (pre-PGA) 001 = MICB (pre-PGA) 010 = LINEL (pre-PGA) 011 = MONOIN (pre-PGA) 100 = HPMIXL 101 = SPKMIC 110 = MONOMIX 111 = Reserved Table 11 Audio Record Selector
34 Rev 4.0 RECORD GAIN The amplitude of the signal that enters the audio ADC is controlled by the Record PGA (Programmable Gain Amplifier). The PGA gain can be programmed either by writing to the Record Gain register, or by the Automatic Level Control (ALC) circuit (see page 35). If the ALC is enabled, any writes to the Record Gain register have no effect. Two different gain ranges can be implemented: the standard gain range defined in the AC’97 standard, or an extended gain range with smaller gain steps. The ALC circuit always uses the extended gain range, as this has been found to result in better sound quality. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 12h Record Gain
15 RMU 1 Audio ADC Input Mute Control
1 = Mute 0 = No mute Note: This control applies to both channels
14 GRL 0 Left ADC PGA Gain Range Control
1 = Extended 0 = Standard 13:8 RECVOLL 000000 Left ADC Recording Volume Control Standard (GRL=0) Extended (GRL=1) XX0000: 0dB XX0001: +1.5dB … (1.5dB steps) XX1111: +22.5dB 000000: -17.25dB 000001: -16.5dB … (0.75dB steps) 111111: +30dB
7 ZC 0 ADC PGA Zero Cross Control
1 = Zero cross enabled (volume changes when signal is zero or after time-out) 0 = Zero cross disabled (volume changes immediately)
6 GRR 0 Right ADC PGA Gain Range Control
1 = Extended 0 = Standard 5:0 RECVOLR 000000 Right ADC Recording Volume Control Standard (GRR=0) Extended (GRR=1) XX0000 = 0dB … (1.5dB steps) XX1111 = +22.5dB 000000 = -17.25dB … (0.75dB steps) XX1111 = +30dB Table 12 Record Gain Register The output of the Record PGA can also be mixed into the phone and/or headphone outputs (see “Audio Mixers”). This makes it possible to use the ALC function for the microphone signal in a smartphone application.
Rev 4.0 35 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 14h Record Routing 15:14 R2H 11 (mute) Record Mux to Headphone Mixer Path Control 00 = stereo 01 = left ADC only 10 = right ADC only 11=mute left and right 13:11 R2HVOL 010 (0dB) Record Mux to Headphone Mixer Path Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB 10:9 R2M 11 (mute) Record Mux to Mono Mixer Path Control 00 = stereo 01 = left record mux only 10 = right record mux only 11 = mute left and right
8 R2MBST 0 (OFF) Record Mux to Headphone Mixer Boost
1 = +20dB 0 = 0dB Table 13 Record PGA Routing Control AUTOMATIC LEVEL CONTROL The WM9713L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. hold time decay time attack time input signal signal after ALC PGA gain ALC target level Figure 19 ALC Operation The ALC function is enabled using the ALCSEL control bi ts. When enabled, the recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register bits. HLD, DCY and ATK control the hold, decay and attack times, respectively.
36 Rev 4.0 HOLD TIME Hold time i s the time delay bet ween the peak level detected being below target and the PGA gain applies to gain ramp -up, there is no delay before ramping the gain down when the signal level is above target. DECAY (GAIN RAMP-UP) TIME Decay time i s the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from –15B up to 27.75d B). The time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the decay time. The decay time can be program med in power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. ATTACK (GAIN RAMP-DOWN) TIME Attack time is the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from 27.75dB down to –15B gain). The time it takes for th e recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in power -of-two (2n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register. When one ADC channel is unused, the p eak detector disregards that channel. The ALC function can also operate when the two ADC outputs are mixed to mono in the digital domain, but not if they are mixed to mono in the analogue domain, before entering the ADCs.
Rev 4.0 37 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 62h ALC / Noise Gate Control 15:14 ALCSEL 00 (OFF) ALC Function Channel Control 00 = ALC disabled 01 = ALC on right channel only 10 = ALC or left channel only 11 = ALC on both left and right channels 13:11 MAXGAIN 111 (+30dB) ALC PGA Gain Limit Control 000 = -12dB … (6dB steps) 111 = +30dB 10:9 ZCTIMEOUT 11 ALC Zero Cross Timeout Delay Control 00 = 214 x tBITCLK (1.33ms) 01 = 215 x tBITCLK (2.67ms) 10 = 216 x tBITCLK (5.33ms) 11 = 217 x tBITCLK (10.67ms) Note: Timeout delay values shown when BITCLK=12.288MHz 60h ALC Control 15:12 ALCL 1011 (-12dB) ALC Target Level Control 0000 = -28.5dBFS … (1.5dB steps) 1111 = -6dBFS Note: This is the target signal level at the ADC input 11:8 HLD 0000 (0ms) ALC Hold Time Control 0000 = 0ms 0001 = 2.67ms … (time doubles with every step) 1111 = 43.691s 7:4 DCY 0011 (192ms) ALC Decay Time Control 0000 = 24ms … (time doubles with every step) 1010 to 1111 = 24.58s 3:0 ATK 0010 (24ms) ALC Attack Time Control 0000 = 6ms … (time doubles with every step) 1010 to 1111 = 6.14s Table 14 ALC Control MAXIMUM GAIN The MAXGAIN register sets the maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
38 Rev 4.0 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. (Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used). NOISE GATE When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM9713L has a noise gate function that prevents noise pumping by comparing the signal level at the input pins (i.e. before the record PGA) against a noise gate threshold, NGTH. Provided that the noise gate function is enabled ( NGAT = 1), the noise gate cuts in when: Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dB] < NGTH [dB] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). If the NGG bit is set, the ADC output is also muted when the noise gate cuts in. Table 15 summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set –up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 62h ALC / Noise Gate Control
7 NGAT 0 Noise Gate Enable Control
0 = Disabled 1 = Enabled
5 NGG 0 Noise Gate Function Control
0 = Hold PGA gain at last value 1 = Mute ADC output 4:0 NGTH(4:0) 00000 Noise Gate Threshold Control 00000 = -76.5dBFS … (1.5dB steps) 11111 = -30dBFS Table 15 Noise Gate Control
Rev 4.0 39 AUDIO DACS STEREO DAC The WM9713L has a stereo sigma -delta DAC that achieves high quality audio pla yback at low power consumption. Digital tone control, adaptive bass boost and 3-D enhancement functions operate on the digital audio data before it is passed to the stereo DAC. (Contrary to the AC’97 specification, they have no effect on analogue input sig nals or signals played through the auxiliary DAC. Nevertheless, the ID2 and ID5 bits in the reset register, 00h, are set to ‘1’ to indicate that the WM9713L supports tone control and bass boost.) The DAC output has a PGA for volume control. The DAC sample rate can be controlled by writing to a control register (see “Variable Rate Audio / Sample Rate Conversion”). It is independent of the ADC sample rate. When not in use the DACs can be separately powered down using the Powerdown register bits DACL and DACR (register 3Ch, bits [7:6]). STEREO DAC VOLUME The volume of the DAC output signal is controlled by a PGA (Programmable Gain Ampl ifier). Each DAC can be mixed into the headphone, speaker and mono mixer paths (see “Audio Mixers”) controlled by register 0Ch. Each DAC-to-mixer path has an independent mute bit. When all DAC -to-mixer paths are muted the DAC PGA is muted automatically. When not in use the DAC PGAs can be powered down using the Powerdown register bits DACL and DACR (register 3Ch, bits [7:6]). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0Ch DAC Volume
15 D2H 1 DAC to Headphone Mixer Mute Control
1 = Mute 0 = No mute
14 D2S 1 DAC to Speaker Mixer Mute Control
1 = Mute 0 = No mute
13 D2M 1 DAC to Mono Mixer Mute Control
1 = Mute 0 = No mute 12:8 DACL VOL 01000 (0dB) Left DAC to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 4:0 DACR VOL 01000 (0dB) Right DAC to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 5Ch Additional Functions (2)
15 AMUTE 0 DAC Automute Status (Read-Only)
0 = DAC not muted 1 = DAC auto-muted
7 AMEN 0 DAC Automute Control
0 = Disabled 1 = Enabled (DAC automatically muted when digital input is zero) Table 16 Stereo DAC Volume Control
40 Rev 4.0 TONE CONTROL / BASS BOOST The WM9713L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. Treble control applies a user programmable gain, without any adaptive boost function. Treble, linear bass and 3D enhancement can all produce signals that exceed full -scale. In order to avoid limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input signal by 6dB. The gain at the outputs should be increased by 6dB to compensate for the attenuation. Cut-only tone adjustment (i.e. bass and treble gains ≤ 0) and adaptive bass boost cannot produce signals above full-scale and therefore do not require the DAT bit to be set. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 20h DAC Tone Control
15 BB 0 Bass Mode Control
0 = Linear bass control 1 = Adaptive bass boost
12 BC 0 Bass Cut-off Frequency Control
0 = Low (130Hz at 48kHz sampling) 1 = High (200Hz at 48kHz sampling) 11:8 BASS 1111 (off) Bass Intensity Control BB=0 BB=1 0000 = +9dB 0001 = +9dB … (1.5dB steps) 0111 = 0dB … (1.5dB steps) 1011-1110 = -6dB 1111 = Bypass (off) 0000 = 15dB … (1dB steps) 1110 = 1dB 1111 = Bypass (off)
6 DAT 0 Pre-DAC Attenuation Control
0 = 0dB 1 = -6dB
4 TC 0 Treble Cut-off Frequency Control
0 = High (8kHz at 48kHz sampling) 1 = Low (4kHz at 48kHz sampling) 3:0 TRBL 1111 (Disabled) Treble Intensity Control 0000 = +9dB 0001 = +9dB … (1.5dB steps) 0111 = 0dB … (1.5dB steps) 1011-1110 = -6dB 1111 = Bypass (off) Table 17 DAC Tone Control Note: 1. All cut-off frequencies change proportionally with the DAC sample rate.
Rev 4.0 41 3D STEREO ENHANCEMENT The 3D stereo enh ancement function artificially increases the separation between the left and right channels by amplifying the (L -R) difference signal in the frequency range where the human ear is sensitive to directionality. The programmable 3D depth setting controls the degree of stereo expansion introduced by the function. Additionally, the upper and lower limits of the frequency range used for 3D enhancement can be selected using the 3DFILT control bits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 40h General Purpose 13 3DE 0 (disabled) 3D Enhancement Control 1 = Enabled 0 = Disabled 1Eh DAC 3D Control 5 3DLC 0 3D Lower Cut-off Frequency Control 1 = High (500Hz at 48kHz sampling) 0 = Low (200Hz at 48kHz sampling) 4 3DUC 0 3D Upper Cut-off Frequency Control 1 = Low (1.5kHz at 48kHz sampling) 0 = High (2.2kHz at 48kHz sampling) 3:0 3DDEPTH 0000 3D Depth Control 0000 = 0% … (6.67% steps) 1111 = 100% Table 18 Stereo Enhancement Control Note: 1. All cut-off frequencies change proportionally with the DAC sample rate. VOICE DAC VXDAC is a 16 -bit mono DAC intended for playback of Rx voice signals input via the PCM interface. Performance has been optimised for operating at 8ks/s or 16ks/s. The VXDAC will function at other sample rates up to 48ks/s, but this is not recommended. The analogue output of VXDAC is routed directly into the output mixers. The signal gain into each mixer can be adjusted at the mixer inputs using control register 18h. When not in use the VXDAC can be powered down using the Powerdown register bit VXDAC (register 3Ch, bit 12).
42 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3Ch Powerdown (1)
12 VXDAC 1 VXDAC Disable Control
1 = Disabled 0 = Enabled 18h VXDAC Output Control
15 V2H 1 VXDAC to Headphone Mixer Mute
1 = Mute 0 = No mute 14:12 V2HVOL 010 (0dB) VXDAC to Headphone Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
11 V2S 1 VXDAC to Speaker Mixer Mute
1 = Mute 0 = No mute 10:8 V2SVOL 010 (0dB) VXDAC to Speaker Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
7 V2M 1 VXDAC to Mono Mixer Mute Control
1 = Mute 0 = No mute 6:4 V2MVOL 010 (0dB) VXDAC to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Table 19 VXDAC Control Note: 1. In order to minimise power consumption, the following sequence should be executed before disabling the Voice DAC: R44h = 0280h Run Voice DAC at fs=48 kHz wait at least 3 AC link frames for mode to change R44h = 0F80h Run Voice DAC at fs=6 kHz R3Ch: bit 12 = 1 Disable Voice DAC. This write must occur immediately after the write to register R44h. AUXILIARY DAC AUXDAC is a simple 12 -bit mono DAC. It can be used to generate DC signals (with the numeric input written into a control register), or AC signals such as telephone-quality ring tones or system beeps (with the input signal supplied through an AC -Link slot). In AC mode (XSLE = 1), the input data is binary offset coded; in DC mode (XSLE = 0), there is no offset. The analogue output of AUXDAC is routed directl y into the output mixers. The signal gain into each mixer can be adjusted at the mixer inputs using control register 12h. In slot mode (XSLE = 1), the AUXDAC also supports variable sample rates (See “Variable Rate Audio / Sample Rate Conversion”). When not in use the auxiliary DAC can be powered down using the Powerdown register bit AUXDAC (register 3Ch, bit 11).
Rev 4.0 43 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3Ch Powerdown (1)
11 AUXDAC 0 AUXDAC Disable Control
1 = Disabled 0 = Enabled 64h AUXDAC Input Control
15 XSLE 0 AUXDAC Input Select Control
0 = From AUXDACVAL[11:0] (for DC signals) 1 = From AC-Link (for AC signals) 14:12 AUXDAC SLT
000 AUXDAC Input Control (XSLE=1)
000 = Slot 5, bits 8-19 001 = Slot 6, bits 8-19 010 = Slot 7, bits 8-19 011 = Slot 8, bits 8-19 100 = Slot 9, bits 8-19 101 = Slot 10, bits 8-19 110 = Slot 11, bits 8-19 111 = Reserved 11:0 AUXDAC VAL 000h AUXDAC Input Control (XSLE=0) 000h = Minimum FFFh = Full scale 1Ah AUXDAC Output Control
15 A2H 1 AUXDAC to Headphone Mixer Mute
1 = Mute 0 = No mute 14:12 A2HVOL 010 (0dB) AUXDAC to Headphone Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
11 A2S 1 AUXDAC to Speaker Mixer Mute
1 = Mute 0 = No mute 10:8 A2SVOL 010 (0dB) AUXDAC to Speaker Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
7 A2M 1 AUXDAC to Mono Mixer Mute
1 = Mute 0 = No mute 6:4 A2MVOL 010 (0dB) AUXDAC to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Table 20 AUXDAC Control
44 Rev 4.0 VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION By using an AC’97 Rev2.2 compliant audio interface, the WM9713L can record and playback at all commonly used audio sample rates, and offer full split -rate support (i.e. the DAC, ADC and AUXDAC sample rates are completely independent of each other – any combination is possible). The default sample rate is 48kHz. If the VRA bit in register 2Ah is set, then other sample rates can be selected by writing to registers 2Ch, 32h and 2Eh. The AC-Link continues to run at 48k frames per second irrespective of the sample rate selected. However, if the sample rate is less than 48kHz, then some frames do not carry an audio sample. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2Ah Extended Audio Stat/Ctrl
0 VRA 0 (OFF) Variable Rate Audio Control
1 = Enable VRA 0 = Disable VRA (ADC and DAC run at 48kHz) Note: When VRA=1, sample rates are controlled by 2Ch, 2Eh and 32h 2Ch Audio DAC Sample Rate 15:0 DACSR BB80h (48kHz) Stereo DAC Sample Rate Control 1F40h = 8kHz 2B11h = 11.025kHz 2EE0h = 12kHz 3E80h = 16kHz 5622h = 22.05kHz 5DC0h = 24kHz 7D00h = 32kHz AC44h = 44.1kHz BB80h = 48kHz Any other value defaults to the nearest supported sample rate 32h Audio ADC Sample Rate 15:0 ADCSR BB80h (48kHz) Stereo ADC Sample Rate Control Values as DACSR 2Eh AUXDAC Sample Rate 15:0 AUXDA CSR BB80h (48kHz) AUXDAC Sample Rate Control Values as DACSR Table 21 Audio Sample Rate Control Note: Changing the ADC and / or DAC sample rate will only be effective if the ADCs and DACs are enabled and powered up before the sample rate is changed. This is done by setting the relevant bits in registers 26h and 3Ch, as well as the VRA bit in register 2Ah. The process is as follows: 1. Enable and power up ADCs and or DACs in registers 26h and 3Ch. 2. Enable VRA bit in 2Ah, bit 0. 3. Change the sample rate in the respective register.
Rev 4.0 45 AUDIO INPUTS The following sections give an overview of the analogue audio input pins and their function. See Applications Information” for more information on recommended external components. LINE INPUT The LINEL and LINER inputs are designed to record line level signals, and/or to mix into one of the analogue outputs. Both pins are directly connected to the record selector. The record PGA adjusts the recording v olume, controlled by register 12h or by the ALC function. For analogue mixing, the line input signals pass through a separat e PGA, controlled by register 0A h. The signals can be mixed into the headphone, speaker and mono mixer paths (see “Audio Mixers”). Each LINE-to-mixer path has an independent mute bit . When all LINE -to-mixer paths are muted the line PGA is muted automatically . When the line inputs are not used, the line PGA can be switched off to save power (see “Power Management”). LINEL and LINER are biased internally to the reference voltage VREF. Whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special anti - thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0Ah 15 L2H 1 LINE to Headphone Mixer Mute Control 1 = Mute 0 = No mute
14 L2S 1 LINE to Speaker Mixer Mute Control
1 = Mute 0 = No mute
13 L2M 1 LINE to Mono Mixer Mute Control
1 = Mute 0 = No mute 12:8 LINEL VOL 01000 (0dB) LINEL to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 4:0 LINER VOL 01000 (0dB) LINER to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Table 22 Line Input Control Additionally, line inputs can be used as single -ended microphone inputs through the record mux to provide a click -less ALC function by bypassing offset intro duced through the microphone pre -amps. Note that the line inputs to the mixers should all be deselected if this is input configuration is used. MICROPHONE INPUT MICROPHONE PRE-AMPS There are two microphone pre-amplifiers, MPA and MPB, which can be configured in a variety of ways to accommodate up to 3 selectable differential microphone inputs or 2 differential microphone inputs operating simultaneously for stereo or noise cancellation. The microphone input circuit is shown in Figure 20.
46 Rev 4.0 MIC1 MIC2A MICCM MIC2B Vmid Vmid Vmid 22h:11-10 00 = +12dB 11 = +30dB 22h:9-8 00 = +12dB 11 = +30dB 22h: 13-12 MICA MICB Figure 20 Microphone Input Circuit The input pins used for the microphones are MIC1, MICCM, MIC2A and MIC2B. Note that input pins MIC2A and MIC2B are multi -function inputs and must be configured for use as microphone i nputs when required. This is a chieved using MICCMPSEL[1:0] in register 22h (see Table 23). The input to microphone pre-amp A can be selected from any of the three microphone inputs MIC1, MIC2A and MIC2B using MPASEL [1:0]. Each pre -amp has independent boost control from +12dB to +30dB in four steps. This is controlled by MPABST[1:0] and MPBBST[1:0]. When not in use each microphone pre -amp can be powered down using the Powerdown register bits MPA and MPB (register 3Eh, bits [1:0]). If disabled, the inputs are tied to Vmid (for MIC2A and MIC2B, this only applies if they are selected as microphone inputs – otherwise, they are left floating). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 22h 15:14 MICCMPSEL 00 MIC2A/MIC2B Pin Function Control 00 = MIC2A and MIC2B are mic inputs 01 = MIC2A mic input only 10 = MIC2B mic input only 11 = MIC2A and MIC2B are not mic inputs 13:12 MPASEL 00 MPA Pre-Amp Source Control 00 = MIC1 01 = MIC2A 10 = MIC2B 11 = Reserved 11:10 MPABST 00 MPA Pre-Amp Volume Control 00 = +12dB 01 = +18dB 10 = +24dB 11 = +30dB 9:8 MPBBST 00 MPB Pre-Amp Volume Control As MPABST Table 23 Microphone Pre-amp Control SINGLE MIC OPERATION Up to three microphones can be connected in a single-ended configuration. Any one of the three MICs can be selected as the input to MPA using MPASEL[1:0] ( Register 22h, bits 13 :12). Only the microphone on MIC2B can be selected to MPB. Note that MPABST always sets the gain for the selected MPA input microphone. If MIC2B is the selected input for MPA it is recommended that MPB is disabled.
Rev 4.0 47 DUAL MIC OPERATION Up to two microphones can be connected in a dual differential configuration. This is suitable for stereo microphone or noise cancellation applications. Mic1 is connected between the MIC2A and MICCM inputs and mic 2 is conn ected between the MIC2B and MICCM inputs as shown in Figure 21. Additionally, another microphone can be supported on MIC1 selected through the MPA input mux. Note that the microphones can be connected in a single-ended configuration. MICBIAS Vmid MICB MIC2B MPB MPBEN Vmid MICA MIC2A MPA MPAEN Vmid MICCM RR WM9713L R MIC1 MIC2 Figure 21 Dual Microphone Configuration MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference vo ltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to “Applications Information” for recommended external components. The MICBIAS volta ge can be altered via MBVOL in register 22h. When MBVOL=0, MICBIAS=0.9*AVDD and when MBVOL=1, MICBIAS=0.75*AVDD. The microphone bias is driven to a dedicated MICBIAS pin 28 and is enabled by MPOP1EN in register 22h. It can also be configured to drive out on GPIO8 pin 12 enabled by MPOP2E N in register 22h. When not in us e the microphone bias can be powered down using the Powerdown register bit MICBIAS (register 3Eh, bit 14).
48 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 22h 7 MBOP2EN 0 (Off) MICBIAS Output 2 Enable Control 1 = Enable MICBIAS output on GPIO8 (pin 12) 0 = Disable MICBIAS output on GPIO8 (pin 12)
6 MBOP1EN 1 (On) MICBIAS Output 1 Enable Control
1 = Enable MICBIAS output on MICBIAS (pin 28) 0 = Disable MICBIAS output on MICBIAS (pin 28)
5 MBVOL 0 MICBIAS Output Voltage Control
1 = 0.75 x AVDD 0 = 0.9 x AVDD Table 24 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 22. Note that the maximum source current capability for MICBIAS is 3mA. The ext ernal biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA. AGND MICBIAS = 1.8 x CAP2 = 0.9 X AVDD CAP2 WM9713L Figure 22 Microphone Bias Schematic MICBIAS CURRENT DETECT The WM9713L includes a microphone bias current detect circuit with programmable thresholds for the microphone bias current, above which an interrupt will be triggered. There are two separate interrupt bits, MICDET to e.g. distinguish between one or two microphones connected to the WM 9713L, and MICSHT to detect a shorted microphone (mic button press). The microphone current detect threshold is set by MCDTHR [2:0], for MICDET, and MCDSCTHR [1:0] for MICSHT. Thresholds for each code are shown in Table 25 When not in us e the microphone bias current detect circuit can be powered down using the Powerdown register bit MCD (register 3Eh, bit 15). See the GPIO and Interrupt Controller sections for details on the interrupt and status readback for these MICBIAS current detection features.
Rev 4.0 49 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 22h 4:2 MCDTHR 000 Mic Detect Threshold Control 000 = 100µA … (100µA steps) 111 = 800µA Note: These values are for 3.3V supply and scale with supply voltage (AVDD). 1:0 MCDSCTR 00 Mic Detect Short Circuit Threshold Control 00 = 600µA 01 = 1200uA 10 = 1800uA 11 = 2400µA Note: These values are for 3.3V supply and scale with supply voltage (AVDD). Table 25 Microphone Current Detect Control MICROPHONE PGAS The microphone pre-amps MPA and MPB drive into two microphone PGAs whose gain is controlled by register 0Eh. The PGA signals can be routed into the headphone mixers and the mono mixer, but not the speaker mixer (to prevent forming a feedback loop) controlled by register 10h. If the PGA signals are not selected as an input to any of the mixers , the outputs of the PGAs are muted automatically. When not in use the microphone PGAs can be powered down using the Powerdown register bits MA and MB (register 3Eh, bits [3:2]). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0Eh Mic PGA Volume 12:8 MICAVOL 01000 (0dB) MICA PGA Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 4:0 MICBVOL 01000 (0dB) MICB PGA Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Table 26 Microphone PGA Volume Control
50 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10h MIC Routing
7 MA2M 1 MICA to Mono Mixer Mute Control
1 = Mute 0 = No mute
6 MB2M 1 MICB to Mono Mixer Mute Control
1 = Mute 0 = No mute
5 MIC2MBST 0 MIC to Mono Mixer Boost Control
1 = +20dB 0 = 0dB 4:3 MIC2H 11 MIC to Headphone Mixer Path Control 00 = stereo 01 = MICA only 10 = MICB only 11 = mute MICA and MICB 2:0 MIC2HVOL 010 (0dB) MIC to Headphone Mixer Path Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Table 27 Microphone PGA Routing Control MONOIN INPUT Pin 20 (MONOIN) is a mono input designed to connect to the receive path of a telephony device. The pin connects directly to the record selector for phone call recording (Note: to record both sides of a phone call, one ADC channel should record the MONOIN signal while the other channel records the MIC signal). The record PGA adjusts the recording volume, and is controlled by register 12h or by the ALC function (see “Record Gain” and “Automatic Level Control”). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 14h Record Routing 15:14 R2H 11 (mute) Record Mux to Headphone Mixer Path Control 00 = stereo 01 = left record mux only 10 = right rec mux only 11=mute left and right 13:11 R2HVOL 010 (0dB) Record Mux to Headphone Mixer Path Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB 10:9 R2M 11 (mute) Record Mux to Mono Mixer Path Control 00 = stereo 01 = left record mux only 10 = right record mux only 11 = mute left and right
8 R2MBST 0 (0dB) Record Mux to Headphone Mixer Boost
1 = +20dB 0 = 0dB Table 28 Record PGA Routing Control
Rev 4.0 51 To listen to the MONOIN signal, the signal passes through a separat e PGA, controlled by register 08h. The signal can be routed into the headphone mixer (for normal phone call operation) and/or the speaker mixer (for speakerphone op eration), but not into the mono mixer (to prevent formin g a feedback loop). When the signal is not selected as an input to any of the mixers the output of the PGA is muted automatically. When not in use , the MONOIN PGA can be powered down using the Powerdown register bit MOIN (register 3Eh, bit 4). MONOIN is bi ased internally to the reference voltage VREF. Whenever the input is muted or the device placed into standby mode, the input remains biased to VREF using special anti -thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 08h MONOIN PGA Vol / Routing
15 M2H 1 MONOIN to Headphone Mixer Mute
1 = Mute 0 = No mute
14 M2S 1 MONOIN to Speaker Mixer Mute Control
1 = Mute 0 = No mute 12:8 MONOIN VOL 01000 (0dB) MONOIN to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Table 29 Mono PGA Control PCBEEP INPUT Pin 19 (PCBEEP) is a mono, line level input intended for externally generated signal or warning tones. It is routed directly to the record sel ector and all three output mixers, without an input amplifier. The signal gain into each mixer can be independently controlled, with a separate mute bit for each signal path. PCBEEP is biased internally to the reference voltage VREF. When the signal is not selected as an input to any of the mixers the input remains biased to VREF using special anti -thump circuitry to suppress any audible clicks when changing inputs.
52 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 16h PCBEEP input
15 B2H 1 PCBEEP to Headphone Mixer Mute
1 = Mute 0 = No mute 14:12 B2HVOL 010 (0dB) PCBEEP to Headphone Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
11 B2S 1 PCBEEP to Speaker Mixer Mute Control
1 = Mute 0 = No mute 10:8 B2SVOL 010 (0dB) PCBEEP to Speaker Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
7 B2M 1 PCBEEP to Mono Mixer Mute Control
1 = Mute 0 = No mute 6:4 B2MVOL 010 (0dB) PCBEEP to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Table 30 PCBEEP Control DIFFERENTIAL MONO INPUT PCBEEP and MONOIN inputs can be configured to provide a differential mono input. This is achieved by mixing the two inputs together using the headphone mixers or the speaker mixer. Note that the gain of the MON OIN PGA must match the gain of the PCBEEP mixer input to achieve a balanced differential mono input.
Rev 4.0 53 AUDIO MIXERS MIXER OVERVIEW The WM9713L has four separate low -power audio mixers to cover all audio functions required by smartphones, PDAs and handheld computers. These mixers are used to drive the audio outputs HPL, HPR, MONO, SPKL, SPKR, OUT3 and OUT4. There are also two inverters used to provide differential output signals (e.g. for driving BTL loads) HEADPHONE MIXERS There are two headphone mixers, he adphone mixer left and headphone mixer right (HPMIXL and HPMIXR). These mixers are the stereo output driver source. They are used to drive the stereo outputs HPL and HP R. They can also be used to drive SPKL and SPKR outputs and, when used in conjunction with OUT3 and OUT4, they can be configured to drive complementary signals through the two output inverters to support bridge -tied load (BTL) stereo loudspeaker outputs. The following signals can be mixed into the headphone path: MONOIN (controlled by register 08h, see “Audio Inputs”) LINEL/R (controlled by register 0Ah, see “Audio Inputs”) the output of the Record PGA (controlled by register 14h, see “Audio ADCs”, “Record Gain”) the stereo DAC signal (controlled by register 0Ch, see “Audio DACs”) the MIC signal (controlled by register 10h, see “Audio Inputs”) PC_BEEP (controlled by register 16h, see “Audio Inputs”) the VXDAC signal (controlled by register 18h, see “Audio DACs”) the AUXDAC signal (controlled by register 1Ah, see “Auxiliary DAC”) In a typical smartphone application, the headphone signal is a mix of MONOIN / VXDAC and sidetone (for phone calls) and the stereo DAC signal (for music playback). If not in use , the headphone mixers can be powered down using the Powerdown register bits HPLX and HPRX (register 3Ch, bits [3:2]). SPEAKER MIXER The speaker mixer (SPKMIX) is a mono source. It is typically used to drive a mono loudspeaker in BTL configuration. The following signals can be mixed into the speaker path: MONOIN (controlled by register 08h, see “Audio Inputs”) LINEL/R (controlled by register 0Ah, see “Audio Inputs”) the stereo DAC signal (controlled by register 0Ch, see “Audio DACs”) PC_BEEP (controlled by register 16h, see “Audio Inputs”) the VXDAC signal (controlled by register 18h, see “Audio DACs”) the AUXDAC signal (controlled by register 1Ah, see “Auxiliary DAC”) In a typical smartphone application, the speaker signal is a mix of AUXDAC (for system alerts or ring tone playback) , MONOIN / VXDAC (for speakerphone function), and PC_BEEP (for externally generated ring tones). Note that when selected the stereo input pairs LINEL/R and DACL/R are summed and attenuated by - 6dB so that 0dBFS signals on each channel sum to give a 0dBFS mono signal. If not in use , the speaker mixer can be powered down using the Powerdown register bit SPKX (register 3Ch, bit 1).
54 Rev 4.0 MONO MIXER The mono mixer drives the MONO pin. The following signals can be mixed into MONO: LINEL/R (controlled by register 0Ah, see “Audio Inputs”) the output of the Record PGA (controlled by register 14h, see “Audio ADCs”, “Record Gain”) the stereo DAC signal (controlled by register 0Ch, see “Audio DACs”) the MIC signal (controlled by register 10h, see “Audio Inputs”) PC_BEEP (controlled by register 16h, see “Audio Inputs”) the VXDAC signal (controlled by register 18h, see “Audio DACs”) the AUXDAC signal (controlled by register 12h, see “Auxiliary DAC”) In a typical smartphone appl ication, the MONO signal is a mix of the amplified microphone signal (possibly with Automatic Gain Control) and (if enabled) an audio playback signal from the stereo DAC or the auxiliary DAC. Note that when selected the stereo input pairs LINEL/R and DACL/R are summed and attenuated by - 6dB so that 0dBFS signals on each channel sum to give a 0dBFS mono signal. If not in use , the mono mixer can be powered down using the Powerdown register bit MX (register 3Ch, bit 0). MIXER OUTPUT INVERTERS There are two general purpose mixer output inv erters, INV1 and INV2. Each inverter can be selected to drive HPMIXL, HPMIXR, SPKMIX, MONOMIX or { ( HPMIXL + HPMIXR ) / 2 }. The outputs of the inverters can be used to generate complimentary signals (to drive BTL configured loads) and to provide greater flexibility in output driver configurations. INV1 can be selected as the source for SPKL, MONO and OUT3 and INV2 as the source for SPKR and OUT4. The input source for each inverter is selected using INV1[2:0] and INV2[2:0] in register 1Eh (see Table 31). If no input is selected, the inverter is powered down. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1Eh 15:13 INV1 000 (no input) INV1 Source Select 000 = No input (tri-stated) 001 = MONOMIX 010 = SPKMIX 011 = HPMIXL 100 = HPMIXR 101 = HPMIXMONO 110 = Reserved 111 = VMID 12:10 INV2 000 (no input) INV2 Source Select 000 = No input (tri-stated) 001 = MONOMIX 010 = SPKMIX 011 = HPMIXL 100 = HPMIXR 101 = HPMIXMONO 110 = Reserved 111 = VMID Table 31 Mixer Inverter Source Select
Rev 4.0 55 ANALOGUE AUDIO OUTPUTS The following sections give an overview of the analogue audio output pins. The WM9713L has three outputs capable of driving loads down to 16 (headphone / line drivers) – HPL, HPR and MONO - and four outputs capable of driving loads down to 8 (loudspeaker / line drivers) – SPKL, SPKR, OUT3 and OUT4. The combination of output drivers, mixers and mixer inverters means that many output configurations can be supported. For examples of typical output and mixer confi gurations, see “ Typical Output Configurations ”. For more information on recommended external components, see “Applications Information”. Each output is driven by a PGA with a gain range of 0dB to -46.5dB in -1.5dB steps. Each PGA has an input source mux , mute and zero -cross detect circuit (delaying gain changes until a zero -cross is detected, or after time-out). HEADPHONE OUTPUTS – HPL AND HPR The HPL and HP R outputs (pins 39 and 41) are designed to drive a 16 or 32 headphone load. They can also be used as line outputs . They can be used in and AC coupled or DC coupled (capless) configuration. The available input sources are HPMIXL/R and Vmid (see Table 32). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1Ch Output PGA Mux Select 7:6 HPL 00 (Vmid) HPL Source Control 00 = VMID 01 = No input (tri-stated if HPL is disabled in 3Eh) 10 = HPMIXL 11 = Reserved 5:4 HPR 00 (Vmid) HPR Source Control 00 = VMID 01 = No input (tri-stated if HPR is disabled in 3Eh) 10 = HPMIXR 11 = Reserved Table 32 HPL / HPR PGA Input Source The signal volume on HPL and HPR can be independently adjusted under software control by writing to register 04h. When not in us e HPL and HPR can be powered down using the Powerdown register bits HPL and HPR (register 3Eh, bits [10:9]). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. T his ensures the same DC level is maintained on the output pin throughout.
56 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 04h Headphone Volume
15 MUL 1 (Mute) HPL Mute Control
1 = Mute 0 = No mute
14 ZCL 0 HPL Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 13:8 HPLVOL 000000 (0dB) HPL Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB
7 MUR 1 (Mute) HPR Mute Control
1 = Mute 0 = No mute
6 ZCR 0 HPR Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 5:0 HPRVOL 000000 (0dB) HPR Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Table 33 HPL / HPR PGA Control MONO OUTPUT The MONO output (pin 31) is designed to drive a 16 headphone load and can also be used as a line output. The available input sources are MONOMIX, INV1 and Vmid (see Table 34) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1Ch Output PGA Mux Select 15:14 MONO 00 (Vmid) MONO Source Control 00 = VMID 01 = No input (tri-stated if MONO is disabled in 3Eh) 10 = MONOMIX 11 = INV1 Table 34 MONO PGA Input Source The signal volume on MONO can be independently adjusted under software control by writing to register 08h. When not in use MONO can be powered down using the Powerdown register bit MONO (register 3Eh, bit 13). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout.
Rev 4.0 57 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 08h MONO Vol
7 MU 1 (Mute) MONO Mute Control
1 = Mute 0 = No mute
6 ZC 0 MONO Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 5:0 MONOVOL 000000 (0dB) MONO Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Table 35 Mono PGA Control SPEAKER OUTPUTS – SPKL AND SPKR The SPKL and SPKR ( pins 35 and 36) are designed to drive a loudspeaker load down to 8 and can also be used as line outputs and headphone outputs. They are designed to drive an 8 load AC coupled or in a BTL (capless) configuration. The available input sources are HPMIXL/R, SPKMIXL/R, INV1/2 and Vmid (see Table 36). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1Ch Output PGA Mux Select 13:11 SPKL 000 (Vmid) SPKL Source Control 000 = VMID 001 = No input (tri-stated if SPKL is disabled in 3Eh) 010 = HPMIXL 011 = SPKMIX 100 = INV1 All other values are reserved 10:8 SPKR 000 (Vmid) SPKR Source Control 000 = VMID 001 = No input (tri-stated if SPKR is disabled in 3Eh) 010 = HPMIXR 011 = SPKMIX 100 = INV2 All other values are reserved Table 36 SPKL / SPKR PGA Input Source The signal volume on SPKL and SPKR can be independently adjusted under software c ontrol by writing to register 02h. When not in use SPKL and SPKR can be powered down using the Powerdown register bits SPKL and SPKR (register 3Eh, bits [8:7 ]). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout.
58 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 02h Speaker Volume
15 MUL 1 (Mute) SPKL Mute Control
1 = Mute 0 = No mute
14 ZCL 0 SPKL Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 13:8 SPKLVOL 000000 (0dB) SPKL Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB
7 MUR 1 (Mute) SPKR Mute Control
1 = Mute 0 = No mute
6 ZCR 0 SPKR Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 5:0 SPKRVOL 000000 (0dB) SPKR Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Table 37 SPKL / SPKR PGA Control Note: 1. For BTL speaker drive, it is recommended that both PGAs have the same gain setting. AUXILIARY OUTPUTS – OUT3 AND OUT4 The OUT3 and OUT4 outputs (pins 37 and 33) are designed to drive a louds peaker load down to 8 and can also be used as line outputs and headphone outputs. They are designed to drive an 8 load AC coupled or in a BTL (cap -less) configuration and can be used as a mid -rail buffer to drive the headphone outputs in a cap -less DC configuration. The available input sources are INV1/2 and Vmid (see Table 38). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1Ch Output PGA Mux Select 3:2 OUT3 00 (Vmid) OUT3 Source Control 00 = VMID 01 = No input (tri-stated if OUT3 is disabled in 3Eh) 10 = INV1 11 = Reserved 1:0 OUT4 00 (Vmid) OUT4 Source Control 00 = VMID 01 = No input (tri-stated if OUT4 is disabled in 3Eh) 10 = INV2 11 = Reserved Table 38 OUT3 / OUT4 PGA Input Source
Rev 4.0 59 The signal volume on OUT3 and OUT4 can be independently adjusted under software control by writing to register 06h. When not in use OUT3 and OUT4 can be powered down using the Powerdown register bits OUT3 and OUT4 (register 3Eh, bits [ 11:12]). To minimise pops and clicks when the PGA is powered down / up it is recommended that the Vmid input is selected during the power down / up cycle. This ensures the same DC level is maintained on the output pin throughout. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 06h Speaker Volume
15 MU4 1 (Mute) OUT4 Mute Control
1 = Mute 0 = No mute
14 ZC4 0 OUT4 Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 13:8 OUT4VOL 000000 (0dB) OUT4 Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB
7 MU3 1 (Mute) OUT3 Mute Control
1 = Mute 0 = No mute
6 ZC3 0 OUT3 Zero Cross Control
1 = Zero cross enabled (change volume only on zero crossings, or after time-out) 0 = Zero cross disabled (change volume immediately) 5:0 OUT3VOL 000000 (0dB) OUT3 Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Table 39 OUT3 / OUT4 PGA Control
60 Rev 4.0 THERMAL SENSOR The speaker and headphone outputs can drive very large currents. To protect the WM9713L from becoming too hot, a thermal sensor has been built in. If the chip temperature reaches approximately 150C, and the TSHUT bit is cleared, and the GP11 bit is set, the WM9713L de -asserts TI, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt Control”). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3Ch 13 TSHUT 1 (disabled) Thermal Sensor Disable Control 1 = Disabled 0 = Enabled 4Eh 11 GP11 1 Thermal Sensor Polarity Control 1 = Active Low 0 = Active High 54h 11 TI 0 Thermal Sensor Status Bit (Virtual GPIO) See also “GPIO and Interrupt Control” section. GP11 = 1 (default) GP11 = 0 1 = Temp < 150C 0 = Temp > 150C 1 = Temp > 150C 0 = Temp < 150C Table 40 Thermal Shutdown Control JACK INSERTION AND AUTO-SWITCHING In a phone application, a BTL ear speaker may be connected across MONO and HPL, a st ereo headphone on HPL and HPR and stereo speakers on SPKL, SPKR, OUT3 and OUT4 (see Figure 23). Typically, only one of these three output devices is used at any given time: when no headphone is plugged in, the BTL ear speaker or stereo speakers are active, otherwise the headphone is used. HEADPHONE MIXER SPEAKER MIXER PHONE MIXER HP 16/32R Ear Speaker 32R HPL HPR MONO Hands-free 32R Stereo Speaker (R) Stereo Speaker (L) OUT4 OUT3 SPKL SPKR Figure 23 Typical Output Configuration The presence of a headphone can be detected using one of GPIO1/6/7/8 (pins 44, 3, 11 & 12) and an external pull-up resistor (see Figure 43, page 127 for a circuit diagram). When the jack is inserted, the GPIO is pulled low by a switch on the socket. When the jack is removed the GPIO is pulled high by a resistor. If the JIEN bit is set, the WM9713L automatically switches between headphone and any other output configuration, typically ear speaker or stereo speaker that has been set up in the Powerdown and Output PGA Mux Select registers.
Rev 4.0 61 Note: Please refer to Application Note WAN 0182 for further information on jack detect configuration. In addition to the typical configuration explained above , the WM9713L can also support automatic switching between the following three configurations set as BTL ear speaker and headphone. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 24h Output Volume Mapping (Jack Insert) 1:0 EARSPKSEL 00 Ear Speaker Source Control 00 = Default, no ear speaker configuration selected. 01 = MONO and HPL driver selected as BTL ear speaker. 10 = OUT3 and HPL driver selected as BTL ear speaker. 11 = OUT4 and HPL driver selected as BTL ear speaker. Table 41 Ear Speaker Configuration For example , if OUT4 and HPL is selected as the BTL ear speaker, t he user should select EARSPKSEL = 3h, then OUT4 is tri -stated on jack insert to prevent sound across the ear speaker during headphone operation and HPL volume is set to OUT4 volume on jack out to ensure correct ear speaker operation. It should be noted tha t all other outputs except HPL, HPR and selected ear speaker driver are disabled and internally connected to VREF on jack insert. This maintains VREF at those outputs and helps prevent pops when the outputs are enabled. Finally if the user wishes to DC cou ple the headphone outputs the user needs to select between OUT3 and OUT4 as the mid -rail output buffer driver. The selected mid -rail output buffer is enabled on jack insert. On jack out it defaults to whatever configuration has been set up in the Powerdown and Output PGA Mux Select registers. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 24h Output Volume Mapping (Jack Insert) 3:2 DCDRVSEL 00 Jack Insert Headphone DC Reference Control 00 = AC coupled headphones, no DC source 01 = OUT3 is mid-rail output buffer 10 = Reserved 11 = OUT4 is mid-rail output buffer Table 42 DC Coupled Headphone Configuration In summary: JIEN not set: Outputs work as normal as selected in the Powerdown and Output PGA Mux Select registers. JIEN set: On jack insert ion, GPIO1/6/7/8 is pulled low, HPL and HPR are enabled, DCDRVSEL decides if the headphones are DC or AC coupled and configures OUT3 or OUT4 to suit, EARSPKSEL decides if MONO, OUT3 or OUT4 need to be tri-stated to ensure no sound out on the ear-speaker and finally all other outputs are disabled as explained above to prevent pops on re-enabling. On jack removal, GPIO1/6/7/8 is pulled high, the outputs work as normal as selected in the Powerdown and Output PGA Mux Select registers except that HPL Volume is controlled by EARSPKSEL to ensure correct ear speaker operation.
62 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 24h Output Volume Mapping (Jack Insert)
4 JIEN 0 (OFF) Jack Insert Control
0 = Disable jack insert circuitry 1 = Enable jack insert circuitry 5Ah Additional Functions (1) 7:6 JSEL 00 (GPIO1) Jack Detect Pin Input Control 00 = GPIO1 01 = GPIO6 10 = GPIO7 11 = GPIO8 Table 43 Jack Insertion / Auto-Switching (1)
Rev 4.0 63 JIEN EARSPKSEL DCDRVSEL GPIO1 MODE DESCRIPTION HPL STATE HPL VOLUME HPR STATE HPR VOLUME MONO STATE OUT3 STATE OUT4 STATE SPKL STATE SPKR STATE
0 XX XX X Jack Insert Detection
Disabled. User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled 1 00 00 0 Jack Insert Detection Enabled. Headphone plugged in. No Ear Speaker Selected. AC Coupled Headphone Selected. Enabled HPL Volume Enabled HPR Volume HZ HZ HZ HZ HZ 1 01 00 0 Jack Insert Detection Enabled. Headphone plugged in. MONO Ear Speaker Selected. AC Coupled Headphone Selected. Enabled HPL Volume Enabled HPR Volume Tri-Stated HZ HZ HZ HZ 1 10 00 0 Jack Insert Detection Enabled. Headphone plugged in. OUT3 Ear Speaker Selected. AC Coupled Headphone Selected. Enabled HPL Volume Enabled HPR Volume HZ Tri-Stated HZ HZ HZ 1 11 00 0 Jack Insert Detection Enabled. Headphone plugged in. OUT4 Ear Speaker Selected. AC Coupled Headphone Selected. Enabled HPL Volume Enabled HPR Volume HZ HZ Tri-Stated HZ HZ 1 11 01 0 Jack Insert Detection Enabled. Headphone plugged in. OUT4 Ear Speaker Selected. OUT3 DC Coupled Headphone Selected. Enabled HPL Volume Enabled HPR Volume HZ VMID Tri-Stated HZ HZ 1 00 XX 1 Jack Insert Detection Enabled. Headphone plugged out. No Ear Speaker Selected. User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled 1 11 XX 1 Jack Insert Detection Enabled. Headphone plugged out. OUT4 Ear Speaker Selected. User Controlled OUT4 Volume User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled User Controlled Table 44 Jack Insertion / Auto-Switching (2)
64 Rev 4.0 DIGITAL AUDIO (S/PDIF) OUTPUT The WM9713L supports the S/PDIF standard. Pins 48 & 12 can be used to output the S/PDIF data. Note that pins 48 & 12 can also be used as GPIO pins. The GE5 & GE8 bits (register 56h, bit 5 & bit 8) select between GPIO and S/PDIF functionality for pins 48 & 12 respectively (see “GPIO and Interrupt Control”). Register 3Ah is a read/write register that controls S/PDIF functionality and manages bit fields propagated as channel status (or sub -frame in the V case). With the exception of V, this register should only be written to when the S/PDIF transmitter is disabled ( S/PDIF bit in register 2Ah is ‘0’). Once the desired values have been written to this register, the contents should be read back to ensure that the sample rate in particular is supported, then S/PDIF validity bit SPCV in register 2Ah should be read to ensure the desired configuration is valid. Only then should the S/PDIF enable bit in register 2Ah be set. This ensures that control and status information start up correctly at the beginning of S/PDIF transmission. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2Ah Extended Audio
10 SPCV 0 S/PDIF Validity Bit (Read Only)
1 = Valid 0 = Not valid 5:4 SPSA 01 S/PDIF Slot Assignment Control 00 = Slots 3 and 4 01 = Slots 6 and 9 10 = Slots 7 and 8 11 = Slots 10 and 11 Note: This control is only valid when ADCO=0 in 5Ch
2 SEN 0 S/PDIF Output Enable Control
1 = Enabled 0 = Disabled 3Ah S/PDIF Control Register
15 V 0 S/PDIF Validity Bit
1 = Valid 0 = Not valid
14 DRS 0 Indicates that the WM9713L does not support
double rate S/PDIF output (read-only) 13:12 SPSR 10 Indicates that the WM9713L only supports 48kHz sampling on the S/PDIF output (read- only)
11 L 0 S/PDIF L-bit Control
Programmed as required by user 10:4 CC 0000000 S/PDIF Category Code Control Category code; programmed as required by user
3 PRE 0 S/PDIF Pre-emphasis Indication Control
0 = no pre-emphasis 1 = 50/15µs pre-emphasis
2 COPY 0 S/PDIF Copyright Indication Control
0 = Copyright not asserted 1 = Copyright asserted
1 AUDIB 0 S/PDIF Non-audio Indication Control
0 = PCM data 1 = Non-PCM data (e.g. DD or DTS)
0 PRO 0 S/PDIF Professional Indication Control
0 = Consumer mode 1 = Professional mode
Rev 4.0 65 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5Ch Additional Function Control
4 ADCO 0 S/PDIF Data Source Control
0 = From SDATAOUT (pin 5) 1 = Output from audio ADC Note: Slot selected by SPSA in 2Ah Table 45 S/PDIF Output Control TOUCHPANEL INTERFACE The WM9713L includes a touchpanel driver and digitiser circuit for use with 4 -wire or 5-wire resistive touchpanels. The following functions are implemented: X co-ordinate measurement Y co-ordinate measurement Pen down detection, with programmable sensitivity Touch pressure measurement (4-wire touchpanel only) Auxiliary measurement from COMP1/AUX1 (pin 29), COMP2/AUX2 (pin 30), or WIPER/AUX4 (pin 12) The touchpanel digitiser uses a very low power, 12-bit successive approximation type ADC. The same ADC can also be used for battery and auxiliary measurements (see “Battery Alarm and Analogue Comparators” and “Auxiliary ADC Inputs”). An on-chip switch matrix connects each touchpanel terminal to the supply voltage TPVDD, to ground (TPGND), or to the ADC input, as required. AUX ADC X+/BR (14) X-/TL (16) TPGND Y+/TR (15) Y-/BL (17) WIPER/AUX4 (12) zero power comparator IP TPVDD RPU PEN DOWN AUX2 (30) AUX1 (29) 20K 10K SPKVDD AUX3 Figure 24 Touchpanel Switch Matrix
Rev 4.0 69 WM9713L WIPER (12) TR (15) TPGND TPGND TPGND TPGND BR (14) BL (17) TL (16) zero power comparator AVDD RPU PEN DOWN Figure 31 Pen Down Detection on 5-wire Touchpanel Pen down detection works in a similar fashion for both 4 -wire and 5-wire touchpanels (see “Principle of Operation – Four-wire Touchpanel”). On a 5 -wire touchpanel, all four contacts of the bottom plate are grounded, and the top plate cont act is connected to the internal programmable pull -up resistor, RPU. CONTROLLING THE TOUCHPANEL DIGITISER All touchpanel functions are accessed and controlled through the AC-Link interface. PHYSICAL CHARACTERISTICS The physical characteristics of the tou chpanel interface are controlled through register 78 h, as shown in Table 46. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 78h 12 45W 0 (4-wire) Touchpanel Type Control 0 = 4-wire 1 = 5-wire
8 PIL 0 (200A) Pressure Measurement Current Control
0 = IP = 200A 1 = IP = 400A 0:5 RPU 000001 (64k) Internal Pull-up Resistor Control 000000 = Reserved 000001 = 64kΩ/1 (most sensitive) 000010 = 64kΩ/2 000011 = 64kΩ/3 … (64kΩ/binary value of RPU) 111111 = 64kΩ/63 (least sensitive) Note: used to adjust sensitivity of Pen Down detection Table 46 Touchpanel Digitiser Control (Physical Characteristics)
70 Rev 4.0 POWER MANAGEMENT To save power, the touchpanel digitiser and the pen -down detector can be independently disable d when they are not used. The power consumption of the pen -down detector is normally negligible, except when the pen is down. The pen ADC is powered-down using PADCPD, register 3Ch bit 15. The state of the digitiser and pen-down detector is controlled by using the bits described in Table 47. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3Ch 15 PADCPD 1 = off Touchpanel / AUXADC Disable Control 1 = Disabled 0 = Enabled 78h 15:14 PRP 00 Touchpanel Digitiser Power State Control 00 = Pen digitiser off, pen detect off, no wake-up on pen down (default) 01 = Pen digitiser powered off, pen detect enabled, touchpanel digitiser wakes up (changes to state 11) on pen-down 10 = Pen digitiser off, pen detect enabled, no wake-up on pen down 11 = Pen digitiser and pen detect enabled
13 RPR 0 Pen Detect Wake-up Mode Control
0 = Wake-up the AC-Link only (hold SDATAIN high until controller sends warm reset or cold reset) 1 = Wake-up the WM9713L without waiting for a reset signal from the controller Table 47 Touchpanel Digitiser Control (Power Management) INITIATION OF MEASUREMENTS The WM9713L touchpanel interface supports both polling routines and DMA (direct memory access) to control the flow of data from the touchpanel ADC to the host CPU. In a polling routine, the CPU starts each measurement individually by writing to the POLL bit (regis ter 74h, bit 9). This bit automatically resets itself when the measurement is completed. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 74h 9 POLL 0 Poll Measurement Control Writing “1” initiates a measurement (when CTC=0)
8 CTC 0 AUXADC Measurement Mode
0 = Polling mode 1 = Continuous mode (for DMA)
Rev 4.0 71 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 76h 9:8 CR 00 Continuous Mode Conversion Rate Continuous mode rate (DEL ≠ 1111) 00: 93.75 Hz (every 512 AC-Link frames) 01: 120 Hz (every 400 AC-Link frames) 10: 153.75 Hz (every 312 AC-Link frames) 11: 187.5Hz (every 256 AC-Link frames) Continuous mode “fast rate” (DEL = 1111) 00: 8 kHz (every six AC-Link frames) 01: 12 kHz (every four AC-Link frames) 10: 24 kHz (every other AC-Link frame) 11: 48 kHz (every AC-Link frame) Note: PENDIV bits in 44h [5:3] should be set to 111 in 48kHz mode to ensure that samples occur synchronously on the AC97 data channel 78h 11 PDEN 0 Touchpanel Measurement Pen Status Control 0 = Measure regardless of pen status 1 = Measure only when pen is down (when CTC=0 and POLL=1, measurement is delayed until pen-down; when CTC=1, measurements are stopped on pen-up)
10 PDPOL 0 PENDOWN Polarity Control
0 = Normal 1 = Inverted Table 48 Touchpanel Digitiser Control (Initiation of Measurements) In continuous mode (CTC = 1), the WM9713L autonomously initiates measurements (or sets of measurements) at the rate set by CR, and supplies the measured data to the CPU on one of the unused AC’97 time slots. DMA -enabled CPUs can write the data directly into a FIFO without any intervention by the CPU core. This reduces CPU loading and speeds up the execution of user programs in handheld systems. Note that the measurement frequency in continuous mode is also affected by the DEL bits (see “Touchpanel Settling Time ”). The faster rates achieved when DEL = 1111 may be useful when the ADC is used for auxiliary measurements.
72 Rev 4.0 MEASUREMENT TYPES The ADCSEL control bits determine which type of measurement is performed (seeTable 49). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 74h 7 ADCSEL_AUX4 0 AUX4 Measurement Enable Control 0 = Disable AUX4 measurement (pin 12) 1 = Enable AUX4 measurement (pin 12)
6 ADCSEL_AUX3 0 AUX3 Measurement Enable Control
0 = Disable AUX3 measurement (SPKVDD/3) 1 = Enable AUX3 measurement (SPKVDD/3)
5 ADCSEL_AUX2 0 AUX2 Measurement Enable Control
0 = Disable AUX2 measurement (pin 30) 1 = Enable AUX2 measurement (pin 30)
4 ADCSEL_AUX1 0 AUX1 Measurement Enable Control
0 = Disable AUX1 measurement (pin 29) 1 = Enable AUX1 measurement (pin 29)
3 ADCSEL_PRESSURE 0 Pressure Measurement Enable Control
0 = Disable pressure measurement 1 = Enable pressure measurement
2 ADCSEL_Y 0 Y Co-ordinate Measurement Enable
0 = Disable Y co-ordinate measurement 1 = Enable Y co-ordinate measurement
1 ADCSEL_X 0 X Co-ordinate Measurement Enable
0 = Disable X co-ordinate measurement 1 = Enable X co-ordinate measurement
0 COO 0 Co-ordinate Mode Control
0 = Single measurement 1 = Co-ordinate measurement Table 49 Touchpanel Digitiser Control (Measurement Types) When COO is ‘0’, the WM9713L perfo rms a single measurement – either in polling mode or continuously, as indicated by the CTC bit. The type of measurement is specified by the ADCSEL[7:1] bits. If CTC=0 (polling mode) then only one of the ADCSEL[7:1] bits should be set. If operating in con tinuous mode (CTC=1), then more than one ADCSEL[7:1] bit may be set and selected conversions will be performed cyclically in the following order: X, Y, PRESSURE, AUX1, AUX2, AUX3, AUX4 The co-ordinate mode (COO = ‘1’) makes it easier to obtain co -ordinate pairs rather than single co - ordinates. In polling -coordinate mode (CTC = ‘0’, COO = ‘1’), the WM9713L performs an X co - ordinate, then a Y co -ordinate, followed by a single additional measurement determined by ADCSEL[7:1], then stops. In continuous -coordinate mode (CTC = ‘1’, COO = ‘1’), the WM9713L continuously repeats a sequence consisting of an X -co-ordinate,Y co -ordinate, then an additional measurement determined by ADCSEL[7:1] . At least one of the ADCSEL bits must be set in continuous coordinate mode when CTC = COO = 1 ). Should more than one of the ADCSEL[7:1] bits be set during continuous co -ordinate mode then the additional measurement alternates for every set of three measurements. For example , if ADCSEL_AUX1 and ADCSEL_AUX3 were both selected whilst CTC = ‘1’, COO = ‘1’ then the following sequence of conversions would be performed: X, Y, AUX1, X, Y, AUX3, X, Y, AUX1, X, Y, AUX3
Rev 4.0 73 CONVERSION RATE As stated previously, the conversion rate is specified by the CR bits (reg 76h). CR may be set to 93. 75Hz (every 512 AC -Link Frames), 120Hz (every 400 AC -Link Frames), 153.75Hz (every 312 AC-Link frames) or 187.5Hz (every 256 AC-Link frames). If only one ADRSEL[7:1] bit is set, each individual conversion occurs at the rate specified by CR. If multiple ADR SEL[7:1] bits are set , the complete set of conversions requested is complet ed at the rate specified by CR. DATA READBACK This data is stored in register 7Ah, and can be retrieved by reading the register in the usual manner (see “AC97 Interface”). Additionally, the data can also be passed to the controller on one of the AC - Link time slots not used for audio functions. The output data word of the touchpanel interface consists of three parts: Pen Status (1 bit) – this is also passed to the GPIO logic block, which can be programmed to generate an interrupt and/or wake up the WM9713L on pen down (see GPIO and Interrupt Control). Output data from the touchpanel ADC (12 bits) ADCSRC: 3 additional bits that indicate the source of the ADC data. In co-ordinate mode (COO = ‘1’), the WM9713L schedules different types of measurements autonomously and so these register bits may be required. If the data is being read back using the polling method, there are several ways to determine when a measurement has finished: Reading back the POLL bit. If it has been reset to ‘0’, then the measurement has finished. Monitoring the ADA signal (see “GPIO and Interrupt Control ”). ADA goes high after every single conversion. If operati ng in co -ordinate mode (COO=1) then ADA goes high after every group of 3 conversions. Reading back 7Ah until the new data appears REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7Ah or AC-Link slot selected by SLT
15 PNDN 0 Pen Status (Read-only)
0 = Pen up 1 = Pen down 14:12 ADCSRC 000 Touchpanel ADC Source 000 = No measurement 001 = X co-ordinate measurement 010 = Y co-ordinate measurement 011 = Pressure measurement (4-wire only) 100 = COMP1/AUX1 measurement (pin 29) 101 = COMP2/AUX2 measurement (pin 30) 110 = AUX3 measurements (SPKVDD/3) 111 = WIPER/AUX4 measurement (pin 12) 11:0 ADCD 000h Touchpanel ADC Data (Read-only) Bit 0 = LSB Bit 11 = MSB 78h 9 WAIT 0 Touchpanel ADC Data Control 0 = Overwrite existing data in 7Ah with new data 1 = Retain existing data in 7Ah until it is read Table 50 Touchpanel Digitiser Data
74 Rev 4.0 When operating in co -ordinate mode (COO=1) there will be 3 results to read back from each set of measurements – X, Y, and the third additional measurement. Aft er the co -ordinate set has finished the X result will be present in register 7Ah. Once this has been read back by the user the Y result will overwrite register 7Ah, as indicated by ADCSRC. Finally, after the Y result has been read back, the result of the third, additional, measurement will become present in 7Ah, again indicated by ADCSRC. To avoid losing data that has not yet been read, the WM9713L can delay overwriting register 7Ah with new conversions until the old data has been read. This function is e nabled using the WAIT bit, and applies to both single and co-ordinate conversion mode. The flow diagram in Figure 32 shows the timing of touchpanel conversions, and data readback from register 7Ah - dependent on the individual settings of the COO, POLL, ADCSEL and CTC bits. Poll (74h) Reset Poll (74h) Set X Measurement(1) Y Measurement(2) Read Data This occurs when user sets POLL - or automatically when CTC=1 COO=1COO=0 Measurement(3) as described by ADCSEL (74h) ADCSELL!=000_0000 ADCSELL=000_0000 ADA goes high ADA remains high until data has been read from a register or sent out on an AC-LINK slot (dependent on value of SLEN) User reads back single conversion (CO=0) OR 1,2,3 in sequential order (CO=1) from register 7Ah POLL (74h) Starts a single measurement CTC (74h) Starts a co-ordinate measurement at specified conversion rate COO (74h) Enables Co-ordinate mode ADCSEL (74H) Specifies the type of measurement to be made Figure 32 Touchpanel Conversion Flow Diagram
Rev 4.0 75 If the SLEN bit is set to ‘1’, then the touchpanel data appears on the AC -Link slot selected by the SLT control bits, as shown below. The Slot 0 ‘tag’ bit c orresponding to the selected time slot is asserted whenever there is new data on that slot. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 76h 3 SLEN 0 Slot Readback Enable Control 0 = Disabled (readback through register map only) 1 = Enabled (readback slot selected by SLT) 2:0 SLT 110 AC’97 Slot for Touchpanel Data Control 000 = Slot 5 001 = Slot 6 010 = Slot 7 011 = Slot 8 100 = Slot 9 101 = Slot 10 110 = Slot 11 111 = Reserved Table 51 Returning Touchpanel Data Through an AC-Link Time Slot TOUCHPANEL SETTLING TIME For accurate touchpanel measurements, some settling time may be required between the switch matrix applying a voltage across the touchpanel plate and the ADC sampling the signal. This time delay function is built into the WM9713L and can be programmed as shown below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 76h 7:4 DEL 0000 (1 frame) Touchpanel Settling Time Control See Table 53 for details Table 52 Touchpanel Settling Time Control (1) DEL DELAY (AC-LINK FRAMES) DELAY (TIME) 0000 1 20.8s 0001 2 41.7s 0010 4 83.3s 0011 8 167s 0100 16 333s 0101 32 667s 0110 48 1ms 0111 64 1.33ms 1000 96 2ms 1001 128 2.67ms 1010 160 3.33ms 1011 192 4ms 1100 224 4.67ms 1101 256 5.33ms 1110 288 6ms
1111 No delay, switch matrix always on
Table 53 Touchpanel Settling Time Control (2)
76 Rev 4.0 The total time for co -ordinate or auxiliary measurements to complete is the delay time DEL, plus one AC-Link frame (20.8s). For a pressure measurement, the time taken is DEL plus two AC -Link frames (41.6s). Although the DELAY is variable the maximum value that may be programmed depends on the number of ADCSEL[7:1] bits set, as shown in the following tab le. Setting multiple ADCSEL[7:1] bits leaves less spare AC_Link frames for the DELAY. NUMBERS OF ADCSEL[1:7] BITS SET CR SETTING MAX DELAY SETTING 1 00 (93.75Hz) 288 1 01 (120Hz) 288 1 10 (153.75Hz) 288 1 11 (187.5Hz) 256 2 00 (93.75Hz) 256 2 01 (120Hz) 192 2 10 (153.75Hz) 128 2 11 (187.5Hz) 128 3, 4 00 (93.75Hz) 96 3, 4 01 (120Hz) 96 3, 4 10 (153.75Hz) 64 3, 4 11 (187.5Hz) 48 5,6,7 00 (93.75Hz) 48 5,6,7 01 (120Hz) 48 5,6,7 10 (153.75Hz) 32 5,6,7 11 (187.5Hz) 16 1 (if COO=1) 00 (93.75Hz) 224 1 (if COO=1) 01 (120Hz) 192 1 (if COO=1) 10 (153.75Hz) 128 1 (if COO=1) 11 (187.5Hz) 96 2,3,4,5,6,7 (if COO=1) 00 (93.75Hz) 160 2,3,4,5,6,7 (if COO=1) 01 (120Hz) 128 2,3,4,5,6,7,8 (if COO=1) 10 (153.75Hz) 96 2,3,4,5,6,7,8 (if COO=1) 11 (187.5Hz) 64 Table 54 Maximum Delay Values Setting DEL to ‘1111’ reduces the settling time to zero, i.e. measurements begin immediately. This mode is intended for fast sampling on AUX inputs. It is NOT intended for touchpanel digitis ation. There are several side-effects when DEL is set to ‘1111’: Co-ordinate mode does not work, i.e. the WM9713L behaves as if COO = 0, even if COO = 1 (see “Measurement Types”) If X / Y co-ordinate or touch pressure measurements are selected (ADCSEL = 001, 010 or 011), then the switch matrix is constantly on, and current constantly flows in the touchpanel. This increases power consumption in the system, and is therefore not recommended for battery powered systems In continuous mode (CTC = 1), setting DEL = 1111 increases the sampling rate of the touchpanel ADC (see “Initiation of Measurements”)
Rev 4.0 77 MASK INPUT CONTROL Sources of glitch noise, such as the signals driving an LCD display, may feed through to the touchpanel plates and affect measurement accuracy. In order to minimise this effect, a signal may be applied to MASK (pin 47 / pin 3 ) to delay or synchronise the sampling of any input to the ADC. The effect of the MASK signal depends on the MSK bits of register 78h, as described in Table 55. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 78h 7:6 MSK 00 Mask Input Control see Table 56 for details Table 55 MASK Input Control MSK[1-0] EFFECT OF SIGNAL ON MASK PIN
00 Mask has no effect on conversions GPIO input disabled (default)
01 Static; ‘hi’ on MASK pin stops conversions, ‘lo’ has no effect.
10 Edge triggered; rising or falling edge on MASK pin delays conversions
by an amount set in the DEL[3-0] register. Conversions are asynchronous to the MASK signal.
11 Synchronous mode; conversions wait until rising or falling edge on MASK initiates
cycle; screen starts to be driven when the edge arrives, the conversion sample being taken a period set by DEL[3-0] after the edge. Table 56 Controlling the MASK Feature Note that pin 47 / pin 3 can also be used as a GPIO (see “GPIO and Interrupt Control ”), or to output the ADA signal (see below). ADA (ADC DATA AVAILABLE) SIGNAL Whenever data becomes available from the touchpanel ADC, the internal ADA (ADC Data Available) signal goes high and remains high until the data has been read from register 7Ah (if SLEN = 0) or until it has been sent out on an AC-Link slot (if SLEN = 1). ADA goes high either- After every touchpanel ADC conversion (in normal mode, COO=0) After every set of 3 conversions (co-ordinate mode, COO=1) ADA can be used to generate an interrupt, if the AW bit (register 52h, bit 1 2) is set (see “GPIO and Interrupt Control”). It is also possible to output the ADA signal on pin 47 / pin 3 , if this pin is not used as a GPIO. The GE4/6 bit must be set to ‘0’ to achieve this (see “GPIO and Interrupt Control”). Alternatively, ADA can be read from bit 12 in register 54h.
78 Rev 4.0 ADDITIONAL FEATURES AUXILIARY ADC INPUTS The ADC used for touchpanel digitisation can also be used for the sole purpose of auxiliary measurements, provided that it is en abled (register 78h, PRP = 11). The WM9713L has three pins that can be used as auxiliary ADC inputs: MIC2A / COMP1 / AUX1 (pin 29) MIC2B / COMP2 / AUX2 (pin 30) WIPER / AUX4 (pin 12) Additionally, the speaker supply (SPKVDD) can be used as an auxiliary ADC input through an on-chip potential divider giving an input to the auxiliary ADC of SPKVDD/3. This input i s referred to as the AUX3 input (see Figure 24). Note that pin 12 connects to the wiper of a 5 -wire touchpanel wiper function. A uxiliary measurements taken on pin 12 are only meaningful when it is not connected to a touchpanel (i.e. a 4-wire touchpanel, or no touchpanel at all, is used). Pins 29 and 30 are also used as comparator inputs (see “Battery Alarm and Analogue Comparators ”), but auxiliary measurements can still be taken on these pins at any time. The ADCSEL control bits select between different ADC inputs, as shown in Table 57. The ADCSEL control bits determine which type o f measurement is performed (see Table 57). When performing auxiliary conversions the co-ordinate mode bit, COO, should be off (0). If CTC=0 then only one of the ADCSEL[7:1] bits should be set. If operating in continuous mode (CTC=1), then more than one ADCSEL[7:1] bit may be set, and conversions will be performed cyclically in the following order: AUX1, AUX2, AUX3, AUX4 (dependent on which bits are set). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 74h 7 ADCSEL_ AUX4
0 AUX4 Measurement Enable Control
0 = Disable AUX4 measurement (pin 12) 1 = Enable AUX4 measurement (pin 12)
6 ADCSEL_
0 AUX3 Measurement Enable Control
0 = Disable AUX3 measurement (SPKVDD/3) 1 = Enable AUX3 measurement (SPKVDD/3)
5 ADCSEL_
0 AUX2 Measurement Enable Control
0 = Disable AUX2 measurement (pin 30) 1 = Enable AUX2 measurement (pin 30)
4 ADCSEL_
0 AUX1 Measurement Enable Control
0 = Disable AUX1 measurement (pin 29) 1 = Enable AUX1 measurement (pin 29) 0 = Single measurement 1 = Co-ordinate measurement Note: When not measuring a touchpanel, set COO=0 Table 57 Auxiliary ADC Measurements Auxiliary ADC measurements are initiated in the same way as touchpanel measurements, and the data is returned in the same manner – see “Controlling the Touchpanel Digitiser”.
Rev 4.0 79 BATTERY ALARM AND ANALOGUE COMPARATORS The battery alarm function differs from battery measurement in that it does not actually measure the battery voltage. Battery alarm only indicates “OK”, “Low” or “Dead”. The advantage of the battery alarm function is that it does not require a clock and can therefore be used in low -power sleep or standby modes. AUX1/ COMP1 AUX2/ COMP2 VREF GPIO2/ IRQ GPIO PINS DEAD BAT LOW BAT GPIO / INTERRUPT LOGIC C VBATT WM9713L IALARM VOLTAGE REGULATOR AVDD, DCVDD, ... Figure 33 Battery Alarm Example Schematic The typical schematic for a dual threshold battery alarm is shown above. This alarm has two thresholds, “dead battery” (COMP1) and “low battery” (COMP2). R1, R2 and R3 set the threshold voltages. Their values c an be up to about 1M in order to keep the battery current [I ALARM = VBATT / (R1+R2+R3)] to a minimum (higher resistor values may affect the accuracy of the system as leakage currents into the input pins become significant). Dead battery alarm: COMP1 triggers when VBATT < VREF (R1+R2+R3) / (R2+R3) A dead battery alarm is the highest priority of interrupt in the system. It should immediately save all unsaved data and shut down the system. The GP15, GS15 and GW15 bits must be set to generate this interrupt. Low battery alarm: COMP2 triggers when VBATT < VREF (R1+R2+R3) / R3 A low battery alarm has a lower priority than a dead battery alarm. Since the threshold voltage is higher than for a dead battery alarm, there is enough power left in the battery to g ive the user a warning and/or shut down “gracefully”. When V BATT gets close to the low battery threshold, spurious alarms are filtered out by the COMP2 delay function. The purpose of the capacitor C is to remove from the comparator inputs any high frequen cy noise or glitches that may be present on the battery (for example, noise generated by a charge pump). It forms a low pass filter with R1, R2 and R3. Low pass cutoff fc [Hz] = 1/ (2 C (R1 || (R2+R3))) Provided that the cutoff frequency is several orde rs of magnitude lower than the noise frequency f n, this simple circuit can achieve excellent noise rejection. Noise rejection [dB] = 20 log (fn / fc) The circuit shown above also allows for measuring the battery voltage V BATT. This is achieved simply by setting the touchpanel ADC input to be either COMP1 (ADCSEL = 100) or COMP2 (ADCSEL = 101) (see also Auxiliary ADC Inputs).
80 Rev 4.0 The WM9713L has two on -chip comparators that can be used to implement a battery alarm function, or other functions such as a window c omparator. Each comparator has one of its inputs tied to COMP1 (pin 29) or COMP2 (pin 30), and the other tied to a voltage reference. The voltage reference can be either internally generated (VREF = AVDD/2) or externally connected on AUX4 (pin 12). The comparator output signals are passed to the GPIO logic block (see “ GPIO and Interrupt Control ” section), where they can be used to send an interrupt to the CPU via the AC -Link or via the IRQ pin, and / or to wake up the WM9713L from sleep mode. COMP1/AUX1 (pin 29) corresponds to GPIO bit 15 and COMP2/AUX2 (pin30) to bit 14. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4Eh 15 CP1 1 COMP1 Polarity Control 0: Alarm when COMP1 voltage is below VREF 1: Alarm when COMP1 voltage is above VREF Note: see also “GPIO and Interrupt Control”
14 CP2 1 COMP2 Polarity Control
0: Alarm when COMP2 voltage is below VREF 1: Alarm when COMP2 voltage is above VREF Note: see also “GPIO and Interrupt Control” 5Ah 15:13 COMP2 DEL
000 Low Battery Alarm Delay Control
000 = No delay 001 = 213 AC-link frames (0.17s) 010 = 214 AC-link frames (0.34s) 011 = 215 AC-link frames (0.68s) 100 = 216 AC-link frames (1.4s) 101 = 217 AC-link frames (2.7s) 110 = 218 AC-link frames (5.5s) 111 = 219 AC-link frames (10.9s) Table 58 Comparator Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5Ch Additional Analogue Functions
14 C2REF 0 Comparator 2 Reference Voltage Select
0 = AVDD/2 1 = WIPER/AUX4 (pin 12) 13:12 C2SRC 00 Comparator 2 Signal Source 00 = AVDD/2 when C2REF=1, else COMP1 powered down 01 = COMP1/AUX1 (pin 29) 10 = COMP2/AUX2 (pin 30) 11 = Reserved
11 C1REF 0 Comparator 1 Reference Voltage Select
0 = AVDD/2 1 = WIPER/AUX4 (pin 12) 10:9 C1SRC 00 Comparator 1 Signal Source 00 = AVDD/2 when C1REF=1, else COMP2 powered down 01 = COMP1/AUX1 (pin 29) 10 = COMP2/AUX2 (pin 30) 11 = Reserved Table 59 Comparator Reference and Source Control
Rev 4.0 81 COMP2 DELAY FUNCTION COMP2 has an optional delay function for use whe n the input signal is noisy. When COMP2 triggers and the delay is enabled (i.e. COMP2DEL is non -zero), then GPIO bit 14 does not change state immediately, and no interrupt is generated. Instead, the WM9713L starts a delay timer and checks COMP2 again after the delay time has passed. If COMP2 is still active, then the GPIO bit is set and an interrupt may be generated (depending on the state of the GW14 bit). If COMP2 is no longer active, the GPIO bit is not set, i.e. all register bits are as if COMP2 had never triggered. COMP2 TRIGGERS START TIMER COMP2? WAIT time=COMP2DEL SHUT DOWN TIMER Inactive Active SET GI14 END END [FALSE ALARM] COMP2 DEL? non-zero C2W? 0 END 000 Figure 34 COMP2 Delay Flow Chart
82 Rev 4.0 GPIO AND INTERRUPT CONTROL The WM9713L has eight GPIO pins that operate as defined in the AC’97 Revision 2.2 specification. Each GPIO pin can be set up as an input or as an output, and has corresponding bits in register 54h and in slot 12. The state of a GPIO output is determined by sending data through slot 12 of outgoing frames (SDATAOUT). Data can be returned from a GPIO input by reading the register bit, or examining slot 12 of incoming frames (SDATAIN). GPIO inputs can be made sticky, and c an be programmed to generate an interrupt, transmitted either through the AC -Link or through a dedicated, level-mode interrupt pin (GPIO2/IRQ, pin 45). In addition, the GPIO pins 1, 3, 4 and 5 can be used for the PCM interface by setting bit 15 of register 36h (see “PCM Audio Data Formats” section). Setting this bit disables any GPIO functions selected on these pins. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 36h PCM CODEC Control 0 = GPIO pins used as GPIOs 1 = GPIO pins used as PCM interface Note: For PCM interface, one or more of these pins (depending on master/slave/partial master mode) must be set up as an output by writing to register 4Ch (see Table 62) 56h GPIO Pin Sharing 8:2 GEn 1 (GPIO) Toggle GPIO pin function 0: secondary function enabled 1: GPIO enabled Table 60 GPIO Additional Function Control GPIO pins 2 to 8 are multi-purpose pins that can also be used for other (non -GPIO / -PCM) purposes, e.g. as a S/PDIF output or to signal pendown. This is controlled by register 56h (see Table 63). Note that GPIO6/7/8 each have an additional fun ction independent of the GPIO / auxiliary functions discussed above. If these pins are to be used as GPIO then the independent function needs to be disabled using its own control registers, e.g. to use pin 11 as a GPIO then the RESETB function needs to be disabled (RSTDIS, register 5Ah, bit 8). Independently of the GPIO pins, the WM9713L also has seven virtual GPIOs. These are signals from inside the WM9713L, which are treated as if they were GPIO input signals. From a software perspective, virtual GPIOs are the same as GPIO pins, but they cannot be set up as outputs, and are not tied to an actual pin. This allows for simple, uniform processing of different types of signals that may generate interrupts (e.g. pen down, battery warnings, jack insertion, high -temperature warning, or GPIO signals).
Rev 4.0 83 8 circuits like this (one for each GPIO pin) XNOR WRITE '0' TO 54h.n STATUS (SLOT12.n) GPIO PIN POLARITY (4Eh.n) AND CONFIGURATION (4Ch.n) STICKY (50h.n) WAKE-UP (52h.n) RSFF R S Q MUX MUX STATUS READBACK 54h.n / SLOT12.n STICKY (50h.n) CONFIGURATION (4Ch.n) IRQ PIN 45 XOR GE2=0: CLOSED GE2=1: OPEN AND WAKEEN 5Ah, bit 1 IRQINV 5Ah, bit 0 IF WM9713L SLEEPING: WAKE UP AC-LINK IF WM9713L AWAKE: SET GPIO_INT (SLOT12, BIT0) OTHER FUNCTION 56h.n OR OTHER GPIOs STATUS 54h.n / SLOT12.n XNOR WRITE '0' TO 54h.n WM9713L internal signal POLARITY (4Eh.n) STICKY (50h.n) WAKE-UP (52h.n) RSFF R S Q MUX STICKY (50h.n) AND STATUS READBACK 54h.n / SLOT12.n 7 circuits like this (one for each virtual GPIO) CLEAR STICKY 0=NOT STICKY 1=STICKY 0=O/P 1=I/P 58h.n 58h.n FUNCTION SELECT Figure 35 GPIO Logic GPIO BIT SLOT
12 BIT
TYPE PIN NO. 2 6 GPIO Pin 45 GPIO2 / IRQ enabled only when pin not used as IRQ 3 7 GPIO Pin 46 GPIO3 / PENDOWN enabled only when pin not used as PENDOWN 4 8 GPIO Pin 47 GPIO4 / ADA / MASK enabled only when pin not used as ADA 5 9 GPIO Pin 48 GPIO5 / S/PDIF_OUT enabled only when pin not used as S/PDIF_OUT 6 10 GPIO Pin 3 GPIO6 / ADA / MASK Enabled only when pin not used as ADA 7 11 GPIO Pin 11 GPIO7 / PENDOWN enabled only when pin not used as PENDOWN 8 12 GPIO Pin 12 GPIO8 / S/PDIF_OUT enabled only when pin not used as S/PDIF_OUT 9 13 Virtual GPIO - [MICDET] Internal microphone bias current detect, generates an interrupt above a threshold (see MICBIAS Current Detect) 10 14 Virtual GPIO - [MICSHT] Internal shorted microphone detect, generates an interrupt above a threshold (see MICBIAS Current Detect) 11 15 Virtual GPIO - [Thermal Cutout] Internal thermal cutout signal, indicates when internal temperature reaches approximately 150C (see “Thermal Sensor”) 12 16 Virtual GPIO - [ADA] Internal ADA (ADC Data Available) Signal enabled only when touchpanel ADC is active 13 17 Virtual GPIO - [PEN DOWN] Internal PENDOWN Signal enabled only when pen-down detection is active 14 18 Virtual GPIO - [COMP2] Internal COMP2 output (Low Battery Alarm) enabled only when COMP2 is on 15 19 Virtual GPIO - [COMP1] Internal COMP1 output (Dead Battery Alarm) enabled only when COMP1 is on Table 61 GPIO Bits and Pins
84 Rev 4.0 Note: GPIO7 (Pin 11) has an independent RESETB function. This must be disabled using RSTDIS (Register 5Ah, bit 8) before using Pin 11 as a GPIO / PENDOWN. The properties of the GPIOs are controlled through registers 4Ch to 52h, as shown below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4Ch n GCn 1 GPIO Pin Configuration Control 0 = Output 1 = Input (GC9-15 are always inputs) 4Eh n GPn 1 GPIO Pin Polarity / Type (Note 1) Input (GCn = 1) Output (GCn = 0) 0 = Active low 1 = Active high 0 = CMOS output 1 = Open drain 50h n GSn 0 GPIO Pin Sticky Control 0 = Not sticky 1 = Sticky 52h n GWn 0 GPIO Pin Wake-up Control 0 = No wake-up (no interrupts generated by GPIO) 1 = Wake-up (generate interrupts from GPIO) 54h n GIn N/A GPIO Pin Status Read = Returns status of GPIO Write = Writing 0 clears sticky bits Table 62 GPIO Control Note 1: Excludes GP11. For Thermal Sensor Polarity Control (GP11) see Table 40 on page 60. The following procedure is recommended for handling interrupts: When the controller receives an interrupt, check register 54h. For e ach GPIO bit in descending order of priority, check if the bit is ‘1’. If yes, execute corresponding interrupt routine, then write ‘0’ to corresponding bit in 54h. If no, continue to next lower priority GPIO. After all GPIOs have been checked, check if int errupt still present or no. If yes, repeat procedure. If no, then jump back to process that ran before the interrupt. If the system CPU cannot execute such an interrupt routine, it may be preferable to switch internal signals (such as PENDOWN) directly ont o the GPIO pins. However, in this case the interrupt signals cannot be made sticky, and more GPIO pins are tied up both on the WM9713L and on the CPU.
Rev 4.0 85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 56h GPIO pins function select
2 GE2 1 GPIO2 (Pin 45) Function Control
0 = Pin 45 is not controlled by GPIO logic 1 = Pin 45 is controlled by GPIO logic Note: When GE2=0, set GC2=0 in 4Ch to output IRQ
3 GE3 1 GPIO3 (Pin 46) Function Control
0 = Pin 46 is not controlled by GPIO logic 1 = Pin 46 is controlled by GPIO logic Note: When GE3=0, set GC3=0 in 4Ch to output PENDOWN
4 GE4 1 GPIO4 (Pin 47) Function Control
0 = Pin 47 is not controlled by GPIO logic 1 = Pin 47 is controlled by GPIO logic Note: When GE4=0, set GC4=0 in 4Ch to output ADA set GC4=1 in 4Ch to input MASK
5 GE5 1 GPIO5 (Pin 48) Function Control
0 = Pin 48 is not controlled by GPIO logic 1 = Pin 48 is controlled by GPIO logic Note: When GE5=0, set GC5=0 in 4Ch to output S/PDIF
6 GE6 1 GPIO6 (Pin 3) Function Control
0 = Pin 3 is not controlled by GPIO logic 1 = Pin 3 is controlled by GPIO logic Note: When GE6=0, set GC6=0 in 4Ch to output ADA signal set GC6=1 in 4Ch to input MASK signal
7 GE7 1 GPIO7 (Pin 11) Function Control
0 = Pin 11 is not controlled by GPIO logic 1 = Pin 11 is controlled by GPIO logic Note: When GE7=0, set GC7=0 in 4Ch to output PENDOWN
8 GE8 1 GPIO8 (Pin 12) Function Control
0 = Pin 12 is not controlled by GPIO logic 1 = Pin 12 is controlled by GPIO logic Note: When GE8=0, set GC8=0 in 4Ch to output S/PDIF Table 63 Using GPIO Pins for Non-GPIO Functions
86 Rev 4.0 POWER MANAGEMENT INTRODUCTION The WM9713L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks o f the device through register Powerdown registers 3Ch and 3E h. Each particular circuit block is active when both the relevant bit in r egister 26h AND the relevant bit in the Powerdown registers 3Ch and 3Eh are set to ‘0’. Note that the default power-up condition is all OFF. AC97 CONTROL REGISTER REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 26h Powerdown/ Status register
14 PR6 1
(disabled) Output PGAs Disable Control 1 = Disabled 0 = Enabled
13 PR5 1
(disabled) Internal Clock Disable Control 1 = Disabled 0 = Enabled
12 PR4 1
(disabled) AC-Link Disable Control 1 = Disabled 0 = Enabled
11 PR3 1
(disabled) Analogue Disable Control 1 = Disabled 0 = Enabled Note: This control disables VREF, input PGAs, DACs, ADCs, mixers and outputs
10 PR2 1
(disabled) Input PGAs and Mixers Disable Control 1 = Disabled 0 = Enabled
9 PR1 1
(disabled) Stereo DAC Disable Control 1 = Disabled 0 = Enabled
8 PR0 1
(disabled) Stereo ADC and Record Mux Disable Control 1 = Disabled 0 = Enabled
3 REF 0 VREF Ready (Read Only)
1 = VREF ready 0 = VREF not ready
2 ANL 0 Analogue Mixers Ready (Read Only)
1 = Analogue mixers ready 0 = Analogue mixers not ready
1 DAC 0 Stereo DAC Ready (Read Only)
1 = DAC ready 0 = DAC not ready
0 ADC 0 Stereo ADC Ready (Read Only)
1 = ADC ready 0 = ADC not ready Table 64 Powerdown and Status Register (Conforms to AC’97 Rev 2.2)
Rev 4.0 87 EXTENDED POWERDOWN REGISTERS REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3Ch Powerdown (1)
15 PADCPD 1
(disabled) Touchpanel / AUXADC Disable Control 1 = Disabled 0 = Enabled
14 VMID1M 1
(disabled) 1Meg VMID String Disable Control 1 = Disabled 0 = Enabled
13 TSHUT 1
(disabled) Thermal Shutdown Disable Control 1 = Disabled 0 = Enabled
12 VXDAC 1
(disabled) Voice DAC Disable Control 1 = Disabled 0 = Enabled
11 AUXDAC 1
(disabled) AUXDAC Disable Control 1 = Disabled 0 = Enabled
10 VREF 1
(disabled) VREF Disable Control 1 = Disabled 0 = Enabled
9 PLL 1
(disabled) PLL Disable Control 1 = Disabled 0 = Enabled
7 DACL 1
(disabled) Left DAC Disable Control (see Note 1) 1 = Disabled 0 = Enabled
6 DACR 1
(disabled) Right DAC Disable Control (see Note 1) 1 = Disabled 0 = Enabled
5 ADCL 1
(disabled) Left ADC Disable Control 1 = Disabled 0 = Enabled
4 ADCR 1
(disabled) Right ADC Disable Control 1 = Disabled 0 = Enabled
3 HPLX 1
(disabled) Left Headphone Mixer Disable Control 1 = Disabled 0 = Enabled
2 HPRX 1
(disabled) Right Headphone Mixer Disable Control 1 = Disabled 0 = Enabled
1 SPKX 1
(disabled) Speaker Mixer Disable Control 1 = Disabled 0 = Enabled
0 MX 1
(disabled) Mono Mixer Disable Control 1 = Disabled 0 = Enabled Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. Table 65 Extended Power Down Register (1) (Additional to AC’97 Rev 2.2) Note: When disabling a PGA, always ensure that it is muted first.
88 Rev 4.0 Table 66 Extended Power Down Register (2) (Additional to AC’97 Rev 2.2) Note: When disabling a PGA, always ensure that it is muted first. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3Eh Powerdown (2)
15 MCD 1
(disabled) Microphone Current Detect Disable Control 1 = Disabled 0 = Enabled
14 MICBIA
S (disabled) Microphone Bias Disable Control (see Note 1) 1 = Disabled 0 = Enabled
13 MONO 1
(disabled) MONO PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
12 OUT4 1
(disabled) OUT4 PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
11 OUT3 1
(disabled) OUT3 PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
10 HPL 1
(disabled) HPL PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
9 HPR 1
(disabled) HPR PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
8 SPKL 1
(disabled) SPKL PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
7 SPKR 1
(disabled) SPKR PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
6 LL 1
(disabled) LINEL PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
5 LR 1
(disabled LINER PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
4 MOIN 1
(disabled) MONOIN PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
3 MA 1
(disabled) MICA PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
2 MB 1
(disabled) MICB PGA Disable Control (see Note 1) 1 = Disabled 0 = Enabled
1 MPA 1
(disabled) Mic Pre-amp MPA Disable Control 1 = Disabled 0 = Enabled
0 MPB 1
(disabled) Mic Pre-amp MPB Disable Control 1 = Disabled 0 = Enabled Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled.
Rev 4.0 89 ADDITIONAL POWER MANAGEMENT Mixer output inverters: see “Mixer Output Inverters” section. Inverters are disabled by default. Touchpanel Interface: see “Controlling the Touchpanel Digitiser”. The touchpanel digitiser is OFF by default. SLEEP MODE Whenever the PR4 bit (reg. 26h) is set, the AC -Link interface is disabled, and the WM9713L is in sleep mode. There is in fact a very large number of different sleep modes, depending on the other control bits. For example, the low -power standby mode described below is a sleep mode. It is desirable to use sleep modes whenever possible, as this will save power. The following functions do not require a clock and can therefore operate in sleep mode: Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode Pen-down detection GPIO and interrupts Battery alarm / analogue comparators The WM9713L can awake from sleep mode as a result of A warm reset on the AC-Link (according to the AC’97 specification) A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see “GPIO and Interrupt Control” section) A virtual GPIO event such as pen-down, battery alarm, etc. (see “GPIO and Interrupt Control” section) LOW-POWER STANDBY MODE If all the bits in registers 26h, 3C h and 3Eh are set except VMID1M (register 3Ch, bit 14) , then the WM9713L is in low -power standby mode and consumes very little current. A 1M resistor string remains connected across AVDD to generate V REF. This is necessary if the on -chip analogue comparators are used (see “ Battery Alarm and Analogue Comparators ” section), and helps shorten the delay between wake -up and playback readiness. If VREF is not required, the 1M resistor string can be disabled by setting the VMID1M bit, reducing current consumption further. SAVING POWER AT LOW SUPPLY VOLTAGES The analogue supplies to the WM9713L can run from 1.8V to 3.6V. By default, all analogue circuitry on the IC is optimized to r un at 3.3V. This set -up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5Ch 6:5 VBIAS 00 Analogue Bias Optimization Control 0X = Default bias current, optimized for 3.3V 10 = Low bias current, optimized for 2.5V 11 = Lowest bias current, optimized for 1.8V Table 67 Analogue Bias Selection
90 Rev 4.0 POWER-ON RESET (POR) The WM9713L has an internal power on reset (PORB) which ensures that a reset is applied to all registers until a supply threshold has been exceeded. The POR circuitry monitors the voltage for both AVDD and DCV DD and will release the internal reset signal on ce these supplies are both nominally greater than 1.36V. The internal reset signal is an AND of the PORB and RESETB input signal. It is recommended that for operation of the WM9713L, all device power rails sh ould be stable before configuring the device for operation.
Rev 4.0 91 REGISTER MAP R e g N a m e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D e f a u lt Reset 0 SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 61 74h Speaker Volume M UL ZCL M UR ZCR 8080h Headphone Volume M UL ZCL M UR ZCR 8080h OUT3/4 Volume M U4 ZC4 M U3 ZC3 8080h M ONO Vol & M ONOIN PGA Vol / Routing M 2H M 2S 0 MU ZC C880h LINEIN PGA Volume / Routing L2H L2S L2M 0 0 0 E808h DAC PGA Volume / Routing D2H D2S D2M 0 0 0 E808h M IC PGA Volume 0 0 0 0 0 0 0808h M IC Routing 0 0 0 0 0 0 0 0 M A2M M B2M M IC2M BST 00DAh Record PGA Volume RM U GRL ZC GRR 8000h Record Routing / M ux Select R2M BST
0 REC
PCBEEP Volume / Routing B2H B2S B2M 0 0 0 0 AAA0h VxDAC Volume / Routing V2H V2S V2M 0 0 0 0 AAA0h AUXDAC Volume / Routing A2H A2S A2M 0 0 0 0 AAA0h Output PGA M ux Select 0000h DAC 3D Control & INV M ux Select 0 0 0 0 3DLC 3DUC 0000h DAC Tone Control BB 0 0 BC 0 DAT 0 TC 0F0Fh M IC Input Select & Bias / Detect Ctrl M BOP 2EN M BOP1 EN M BVO L 0040h Output Volume M apping (Jack Insert) 0 0 0 0 0 0 0 0 0 0 0 JIEN 0000h Powerdown Ctrl/Stat 0 PR6 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC 7F00h Extended Audio ID ID1 ID0 0 0 REV1 REV0 AM AP LDAC SDAC CDAC 0 0 VRM SPDIF DRA VRA 0405h Ext'd Audio Stat/Ctrl 0 0 0 0 0 SPCV 0 0 0 0 0 SEN 0 VRA 041 0h Audio DACs Sample Rate BB80h AUXDAC Sample Rate BB80h Audio ADCs Sample Rate BB80h PCM codec control CTRL 0 VDAC OSR CP FSP 4523h SPDIF control V DRS L PRE COPY AUD IB PRO 2000h Powerdown (1 ) PADCP D VM ID TSHUT VXDA C AUXD AC VREF PLL 1 DACL DACR ADCL ADCR HPLX HPRX SPKX MX FDFFh Powerdown (2) M CD M IC BIAS M ONO OUT4 OUT3 HPL HPR SPKL SPKR LL LR M OIN MA MB M PA M PB FFFFh General Purpose 0 0 3DE 0 0 0 0 0 LB 0 0 0 0 0 0 0 0000h Fast Power-Up Control 0 0 0 0 0 0 0 0 0 M ONO SPKL SPKR HPL HPR OUT3 OUT4 0000h M CLK / PLL Control 0 CLKSR C
0 CLKBX
X 0080h M CLK / PLL Control LF SDM DIVSEL DIVCTL 0 0000h GPIO Pin Configuration 1 1 1 1 1 1 1 GC8 GC7 GC6 GC5 GC4 GC3 GC2 GC1 0 FFFEh GPIO Pin Polarity / Type C1 P C2P PP AP TP SP MP GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 1 FFFFh GPIO Pin Sticky C1 S C2S PS AS TS SS MS GS8 GS7 GS6 GS5 GS4 GS3 GS2 GS1 0 0000h GPIO Pin Wake-Up C1 W C2W PW AW TW SW MW GW8 GW7 GW6 GW5 GW4 GW3 GW2 GW1 0 0000h GPIO Pin Status C1 I C2I PI AI TI SI MI GI8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 0 GPIO pins GPIO Pin Sharing 1 1 1 1 1 1 1 GE8 GE7 GE6 GE5 GE4 GE3 GE2 1 0 FFFEh GPIO Pull UP/DOWN Ctrl PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 4000h Additional Functions (1 ) 0 0 0 0 RSTDIS WAKEE N IRQ INV 0000h Additional Functions (2) AMUTE C2 REF C1 REF 0 AM EN ADCO HPF 0 0000h ALC Control B032h ALC / Noise Gate Control 0 NGAT 0 NGG 3E00h AUXDAC input control XSLE 0000h Digitiser Reg 1 0 0 0 0 0 0 POLL CTC COO 0000h Digitiser Reg 2 0 0 0 0 0 0 SLEN 0006h Digitiser Reg 3 RPR 45W PDEN PDPOL WAIT PIL 0001 h Digitiser Read Back PNDN 0000h Vendor ID1 574Dh Vendor ID2 4C1 3h 00h 02h SPKLVOL SPKRVOL 04h HPLVOL HPRVOL 06h OUT4VOL OUT3VOL 08h M ONOINVOL M ONOVOL 0Ah LINELVOL LINERVOL 0Ch DACLVOL DACRVOL 0Eh M ICAVOL M ICBVOL 1 0h M IC2H M IC2HVOL 1 2h (Extended) RECVOLL (Extended) RECVOLR RECSL RECSR 1 6h B2HVOL B2SVOL B2M VOL 1 4h R2H R2HVOL R2M 1 8h V2HVOL V2SVOL V2M VOL
1 Ah A2HVOL A2SVOL A2M VOL
1 Ch M ONO SPKL SPKR HPL HPR OUT3 OUT4
1 Eh INVA INVB 3DDEPTH
22h M ICCM PSEL M PASEL M PABST M PBBST M CDTHR M CDSCTHR 24h 26h DCY (decay time) ATK (attack time) N[3:0] PGADDR PGDATA SEXT[6:4] SEXT[3:0] 28h 2Ah SPSA 2Ch DACSR (Audio DACs Sample Rate) 2Eh AUXDACSR (Auxiliary DAC Sample Rate) 32h ADCSR (Audio ADCs Sample Rate) 3Ch 3Eh 36h 3Ah 40h 42h 44h 46h 4Ch 4Eh Die RevisionHPM ODEJSEL 50h 52h 54h 56h VBIAS 58h 5Ah COM P2DEL ALCL (target level) HLD (hold time) 5Ch C2SRC C1 SRC 64h ASS 60h 62h ALCSEL M AXGAIN ZCTIM EOUT NGTH (threshold) 74h 76h CR 78h PRP M SK RPU ASCII character “ W” ASCII character “ M ” DEL SLT 7Eh ASCII character “ L” Device Identifier AUXDACSLT AUXDAC VAL ADCSEL 7Ah ADCSRC ADCD (TOUCHPANEL ADC Y DATA) 7Ch PENDIV DCDRVSEL EARSPKSEL M ODE DIV SEL WL FM T SPSR CC (Category Code) Table 68 WM9713L Register Map Note: Register 46h provides access to a sub-page address system to set the SPLL[6:0] and K[21:0] register bits (see Table 6).
92 Rev 4.0 REGISTER BITS BY ADDRESS REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 00h read-only 14:10 SE [4:0] 11000 Indicates a CODEC from Cirrus Logic Intel’s AC’97 Component Specification, Revision 2.2, page 50 9:6 ID9:6 0101 Indicates 18 bits resolution for ADCs and DACs
5 ID5 1 Indicates that the WM9713L supports bass boost
4 ID4 1 Indicates that the WM9713L has a headphone
3 ID3 0 Indicates that the WM9713L does not support
2 ID2 1 Indicates that the WM9713L supports bass and
1 ID1 0 Indicates that the WM9713L does not support
0 ID0 0 Indicates that the WM9713L does not have a
Register 00h is a read-only register. Writing any value to this register resets all registers to their default, but does not change the contents of reg. 00h. Reading the register reveals information about the codec to the driver, as required by the AC’97 Specification, Revision 2.2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 02h 15 MUL 1 (mute) SPKL Mute Control 1 = Mute 0 = No mute Analogue Audio Outputs
14 ZCL 0 (disabled) SPKL Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 13:8 SPKLVOL 000000 (0dB) SPKL Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB 1 = Mute 0 = No mute
6 ZCR 0 (disabled) SPKR Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 5:0 SPKRVOL 000000 (0dB) SPKR Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Register 02h controls the output pins SPKL and SPKR.
Rev 4.0 93 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 04h 15 MUL 1 (mute) HPL Mute Control 1 = Mute 0 = No mute Analogue Audio Outputs
14 ZCL 0 (disabled) HPL Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 13:8 HPL VOL 000000 (0dB) HPL Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB 1 = Mute 0 = No mute
6 ZCR 0 (disabled) HPR Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 5:0 HPR VOL 000000 (0dB) HPR Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Register 04h controls the headphone output pins, HPL and HPR. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 06h 15 MU4 1 (mute) OUT4 Mute Control 1 = Mute 0 = No mute Analogue Audio Outputs
14 ZC4 0 (disabled) OUT4 Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 13:8 OUT4VOL 000000 (0dB) OUT4 Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB 1 = Mute 0 = No mute
6 ZC3 0 (disabled) OUT3 Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 5:0 OUT3VOL 000000 (0dB) OUT3 Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Register 06h controls the analogue output pins OUT3 and OUT4.
94 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 08h 15 M2H 1 (mute) MONOIN to Headphone Mixer Mute Control 1 = Mute 0 = No mute Analogue Inputs; Analogue Audio Outputs
14 M2S 1 (mute) MONOIN to Speaker Mixer Mute Control
1 = Mute 0 = No mute 12:8 MONOINVO L 01000 (0dB) MONOIN to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 1 = Mute 0 = No mute
6 ZC 0 (disabled) MONO Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled 5:0 MONOVOL 000000 (0dB) MONO Volume Control 000000 = 0dB (maximum) … (1.5dB steps) 011111 = -46.5dB 1xxxxx = -46.5dB Register 08h controls the analogue output pin MONO and the analogue input pin MONOIN. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0Ah 15 L2H 1 (mute) LINE to Headphone Mixer Mute Control 1 = Mute 0 = No mute Analogue Inputs, Line Input
14 L2S 1 (mute) LINE to Speaker Mixer Mute Control
1 = Mute 0 = No mute
13 L2M 1 (mute) LINE to Mono Mixer Mute Control
1 = Mute 0 = No mute 12:8 LINELVOL 01000 (0dB) LINEL to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 4:0 LINERVOL 01000 (0dB) LINER to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Register 0Ah controls the analogue input pins LINEL and LINER.
Rev 4.0 95 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0Ch 15 D2H 1 (mute) DAC to Headphone Mixer Mute Control 1 = Mute 0 = No mute Audio DACs
14 D2S 1 (mute) DAC to Speaker Mixer Mute Control
1 = Mute 0 = No mute
13 D2M 1 (mute) DAC to Mono Mixer Mute Control
1 = Mute 0 = No mute 12:8 DACLVOL 01000 (0dB) Left DAC to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 4:0 DACRVOL 01000 (0dB) Right DAC to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Register 0Ch controls the audio DACs (but not AUXDAC). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0Eh 12:8 MICAVOL 01000 (0dB) MICA PGA Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Analogue Inputs, Microphone Input 4:0 MICBVOL 01000 (0dB) MICB PGA Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB Register 0Eh controls the microphone PGA volume (MICA and MICB). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 10h 7 MA2M 1 (mute) MICA to Mono Mixer Mute Control 1 = Mute 0 = No mute Analogue Inputs, Microphone Input
6 MB2M 1 (mute) MICB to Mono Mixer Mute Control
1 = Mute 0 = No mute
5 MIC2MBST 0 (0dB) MIC to Mono Mixer Boost Control
1 = +20dB 0 = 0dB 4:3 MIC2H 11 (mute) MIC to Headphone Mixer Path Control 00 = stereo 01 = MICA only 10 = MICB only 11 = mute MICA and MICB 2:0 MIC2HVOL 010 (0dB) MIC to Headphone Mixer Path Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Register 10h controls the microphone routing (MICA and MICB).
96 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 12h 15 RMU 1 (mute) Audio ADC Input Mute Control 1 = Mute 0 = No mute Audio ADC, Record Gain
14 GRL 0 (standard) Left ADC PGA Gain Range Control
1 = Extended 0 = Standard 13:8 RECVOLL 000000 (0dB) Left ADC Recording Volume Control Standard (GRL=0) Extended (GRL=1) XX0000 = 0dB … (1.5dB steps) XX1111 = +22.5dB 000000 = -17.25dB … (0.75dB steps) XX1111 = +30dB
7 ZC 0 (disabled) ADC PGA Zero Cross Control
1 = Zero cross enabled 0 = Zero cross disabled
6 GRR 0 (standard) Right ADC PGA Gain Range Control
1 = Extended 0 = Standard 5:0 RECVOLR 000000 (0dB) Right ADC Recording Volume Control Standard (GRR=0) Extended (GRR=1) XX0000 = 0dB … (1.5dB steps) XX1111 = +22.5dB 000000 = -17.25dB … (0.75dB steps) XX1111 = +30dB Register 12h controls the record volume.
Rev 4.0 97 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 14h 15:14 R2H 11 (mute) Record Mux to Headphone Mixer Path Control 00 = stereo 01 = left record mux only 10 = right rec mux only 11=mute left and right Audio ADC, Record Selector 13:11 R2HVOL 010 (0dB) Record Mux to Headphone Mixer Path Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB 10:9 R2M 11 (mute) Record Mux to Mono Mixer Path Control 00 = stereo 01 = left record mux only 10 = right record mux only 11 = mute left and right
8 R2MBST 0 (0dB) Record Mux to Headphone Mixer Boost Control
1 = +20dB 0 = 0dB
6 RECBST 0 (0dB) ADC Record Boost Control
1 = +20dB 0 = 0dB 5:3 RECSL 000 (mic) Left Record Mux Source Control 000 = MICA (pre-PGA) 001 = MICB (pre-PGA) 010 = LINEL (pre-PGA) 011 = MONOIN (pre-PGA) 100 = HPMIXL 101 = SPKMIC 110 = MONOMIX 111 = Reserved 2:0 RECSR 000 (mic) Right Record Mux Source Control 000 = MICA (pre-PGA) 001 = MICB (pre-PGA) 010 = LINEL (pre-PGA) 011 = MONOIN (pre-PGA) 100 = HPMIXL 101 = SPKMIC 110 = MONOMIX 111 = Reserved Register 14h controls the record selector and the ADC to mono mixer path.
98 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 16h 15 B2H 1 (mute) PCBEEP to Headphone Mixer Mute Control 1 = Mute 0 = No mute Analogue Inputs, PCBEEP Input 14:12 B2HVOL 010 (0dB) PCBEEP to Headphone Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
11 B2S 1 (mute) PCBEEP to Speaker Mixer Mute Control
1 = Mute 0 = No mute 10:8 B2SVOL 010 (0dB) PCBEEP to Speaker Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
7 B2M 1 (mute) PCBEEP to Mono Mixer Mute Control
1 = Mute 0 = No mute 6:4 B2MVOL 010 (0dB) PCBEEP to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Register 16h controls the analogue input pin PCBEEP. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 18h 15 V2H 1 (mute) VXDAC to Headphone Mixer Mute Control 1 = Mute 0 = No mute Audio Mixers, Side Tone Control 14:12 V2HVOL 010 (0dB) VXDAC to Headphone Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
11 V2S 1 (mute) VXDAC to Speaker Mixer Mute Control
1 = Mute 0 = No mute 10:8 V2SVOL 010 (0dB) VXDAC to Speaker Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
7 V2M 1 (mute) VXDAC to Mono Mixer Mute Control
1 = Mute 0 = No mute 6:4 V2MVOL 010 (0dB) VXDAC to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Register 18h controls the output signal of the Voice DAC.
Rev 4.0 99 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 1Ah 15 A2H 1 (mute) AUXDAC to Headphone Mixer Mute Control 1 = Mute 0 = No mute Auxiliary DAC 14:12 A2HVOL 010 (0dB) AUXDAC to Headphone Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
11 A2S 1 (mute) AUXDAC to Speaker Mixer Mute Control
1 = Mute 0 = No mute 10:8 A2SVOL 010 (0dB) AUXDAC to Speaker Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB
7 A2M 1 (mute) AUXDAC to Mono Mixer Mute Control
1 = Mute 0 = No mute 6:4 A2MVOL 010 (0dB) AUXDAC to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB Register 1Ah controls the output signal of the auxiliary DAC.
100 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 1Ch 15:14 MONO 00 (VMID) MONO Source Control 00 = VMID 01 = No input (tri-stated if MONO is disabled) 10 = MONOMIX 11 = INV1 Analogue Audio Outputs 13:11 SPKL 000 (VMID) SPKL Source Control 000 = VMID 001 = No input (tri-stated if SPKL is disabled) 010 = HPMIXL 011 = SPKMIX 100 = INV1 All other values are reserved 10:8 SPKR 000 (VMID) SPKR Source Control 000 = VMID 001 = No input (tri-stated if SPKR is disabled) 010 = HPMIXR 011 = SPKMIX 100 = INV2 All other values are reserved 7:6 HPL 00 (VMID) HPL Source Control 00 = VMID 01 = No input (tri-stated if HPL is disabled) 10 = HPMIXL 11 = Reserved 5:4 HPR 00 (VMID) HPR Source Control 00 = VMID 01 = No input (tri-stated if HPR is disabled) 10 = HPMIXR 11 = Reserved 3:2 OUT3 00 (VMID) OUT3 Source Control 00 = VMID 01 = No input (tri-stated if OUT3 is disabled) 10 = INV1 11 = Reserved 1:0 OUT4 00 (VMID) OUT4 Source Control 00 = VMID 01 = No input (tri-stated if OUT4 is disabled) 10 = INV2 11 = Reserved Register 1Ch controls the inputs to the output PGAs.
Rev 4.0 101 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 1Eh 15:13 INV1 000 (no input) INV1 Source Select 000 = No input (tri-stated) 001 = MONOMIX 010 = SPKMIX 011 = HPMIXL 100 = HPMIXR 101 = HPMIXMONO 110 = Reserved 111 = VMID Audio Mixers, Mixer Output Inverters 12:10 INV2 000 (no input) INV2 Source Select 000 = No input (tri-stated) 001 = MONOMIX 010 = SPKMIX 011 = HPMIXL 100 = HPMIXR 101 = HPMIXMONO 110 = Reserved 111 = VMID 5 3DLC 0 (low) 3D Lower Cut-off Frequency Control 1 = High (500Hz at 48kHz sampling) 0 = Low (200Hz at 48kHz sampling) Audio DAC, Stereo DAC, 3D Stereo Enhancement 4 3DUC 0 (high) 3D Upper Cut-off Frequency Control 1 = Low (1.5kHz at 48kHz sampling) 0 = High (2.2kHz at 48kHz sampling) 3:0 3DDEPTH 0000 (0%) 3D Depth Control 0000 = 0% … (6.67% steps) 1111 = 100% Register 1Eh controls 3D stereo enhancement for the audio DACs and input muxes to the output inverters INV1 and INV2.
102 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 20h 15 BB 0 (linear) Bass Mode Control 0 = Linear bass control 1 = Adaptive bass boost Audio DACs, Tone Control / Bass Boost
12 BC 0 (low) Bass Cut-off Frequency Control
0 = Low (130Hz at 48kHz sampling) 1 = High (200Hz at 48kHz sampling) 11:8 BASS 1111 (off) Bass Intensity Control BB=0 BB=1 0000 = +9dB 0001 = +9dB … (1.5dB steps) 0111 = 0dB … (1.5dB steps) 1011-1110 = -6dB 1111 = Bypass (off) 0000 = 15dB … (1dB steps) 1110 = 1dB 1111 = Bypass (off)
6 DAT 0 (0dB) Pre-DAC Attenuation Control
0 = 0dB 1 = -6dB
4 TC 0 (high) Treble Cut-off Frequency Control
0 = High (8kHz at 48kHz sampling) 1 = Low (4kHz at 48kHz sampling) 3:0 TRBL 1111 (off) Treble Intensity Control 0000 = +9dB 0001 = +9dB … (1.5dB steps) 0111 = 0dB … (1.5dB steps) 1011-1110 = -6dB 1111 = Bypass (off) Register 20h controls the bass and treble response of the left and right audio DAC (but not AUXDAC).
Rev 4.0 103 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 22h 15:14 MICCMP SEL 00 (mics) MIC2A/MIC2B Pin Function Control 00 = MIC2A and MIC2B are microphone inputs 01 = MIC2A microphone input only 10 = MIC2B microphone input only 11 = MIC2A and MIC2B are not microphone inputs Analogue Inputs, Microphone Input 13:12 MPASEL 00 (MIC1) MPA Pre-Amp Source Control 00 = MIC1 01 = MIC2A 10 = MIC2B 11 = Reserved 11:10 MPABST 00 (+12dB) MPA Pre-Amp Volume Control 00 = +12dB 01 = +18dB 10 = +24dB 11 = +30dB 9:8 MPBBST 00 (+12dB) MPB Pre-Amp Volume Control 00 = +12dB 01 = +18dB 10 = +24dB 11 = +30dB
7 MBOP2EN 0 (disabled) MICBIAS Output 2 Enable Control
1 = Enable MICBIAS output on GPIO8 (pin 12) 0 = Disable MICBIAS output on GPIO8 (pin 12)
6 MBOP1EN 1 (enabled) MICBIAS Output 1 Enable Control
1 = Enable MICBIAS output on MICBIAS (pin 28) 0 = Disable MICBIAS output on MICBIAS (pin 28) 5 MBVOL 0 (0.9xAVDD) MICBIAS Output Voltage Control 1 = 0.75 x AVDD 0 = 0.9 x AVDD 4:2 MCDTHR 000 (100uA) Mic Detect Threshold Control 000 = 100µA … (100µA steps) 111 = 800µA 1:0 MCDSCTHR 00 (600uA) Mic Detect Short Circuit Threshold Control 00 = 600µA 01 = 1200uA 10 = 1800uA 11 = 2400µA Register 22h controls the microphone input configuration and microphone bias and detect configuration.
104 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 24h 4 JIEN 0 (disabled) Jack Insert Control 0 = Disable jack insert circuitry 1 = Enable jack insert circuitry Jack Insertion and Auto- Switching 3:2 DCDRVSEL 00 (AC) Jack Insert Headphone DC Reference Control 00 = AC coupled headphones, no DC source 01 = OUT3 is mid-rail output buffer 10 = Reserved 11 = OUT4 is mid-rail output buffer 1:0 EARSPK SEL 00 (none) Ear Speaker Source Control 00 = No ear speaker 01 = MONO and HPL 10 = OUT3 and HPL 11 = OUT4 and HPL Register 24h controls the output volume mapping on headphone jack insertion. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 26h 14 PR6 1 (disabled) Output PGAs Disable Control 1 = Disabled 0 = Enabled Power Management
13 PR5 1 (disabled) Internal Clock Disable Control
1 = Disabled 0 = Enabled
12 PR4 1 (disabled) AC-Link Disable Control
1 = Disabled 0 = Enabled
11 PR3 1 (disabled) Analogue Disable Control
1 = Disabled 0 = Enabled
10 PR2 1 (disabled) Input PGAs and Mixers Disable Control
1 = Disabled 0 = Enabled
9 PR1 1 (disabled) Stereo DAC Disable Control
1 = Disabled 0 = Enabled
8 PR0 1 (disabled) Stereo ADC and Record Mux Disable Control
1 = Disabled 0 = Enabled
3 REF 0 (not ready) VREF Ready (Read Only)
1 = VREF ready 0 = VREF not ready
2 ANL 0 (not ready) Analogue Mixers Ready (Read Only)
1 = Analogue mixers ready 0 = Analogue mixers not ready
1 DAC 0 (not ready) Stereo DAC Ready (Read Only)
1 = DAC ready 0 = DAC not ready
0 ADC 0 (not ready) Stereo ADC Ready (Read Only)
1 = ADC ready 0 = ADC not ready Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit blocks depends on both register 26h AND registers 3Ch and 3Eh.
Rev 4.0 105 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 28h read-only 15:14 ID 00 Indicates that the WM9713L is configured as the primary CODEC in the system. Intel’s AC’97 Component Specification, Revision 2.2, page 59 11:10 REV 01 Indicates that the WM9713L conforms to AC’97 Rev2.2
9 AMAP 0 Indicates that the WM9713L does not support slot
8 LDAC 0 Indicates that the WM9713L does not have an LFE
7 SDAC 0 Indicates that the WM9713L does not have
6 CDAC 0 Indicates that the WM9713L does not have a
3 VRM 0 Indicates that the WM9713L does not have a
dedicated, variable rate microphone ADC
2 SPDIF 1 Indicates that the WM9713L supports S/PDIF
1 DRA 0 Indicates that the WM9713L does not support
0 VRA 1 Indicates that the WM9713L supports variable rate
Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9713L supports. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 2Ah 10 SPCV 0 S/PDIF Validity Bit (Read Only) 1 = Valid 0 = Not valid Digital Audio (S/PDIF) Output 5:4 SPSA 01 (slots 6, 9) S/PDIF Slot Assignment Control 00 = Slots 3 and 4 01 = Slots 6 and 9 10 = Slots 7 and 8 11 = Slots 10 and 11
2 SEN 0 (disabled) S/PDIF Output Enable Control
1 = Enabled 0 = Disabled 1 = Enable VRA 0 = Disable VRA (ADC and DAC run at 48kHz) Register 2Ah controls the S/PDIF output and variable rate audio.
106 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 2Ch all DACSR BB80h (48kHz) Stereo DAC Sample Rate Control 1F40h = 8kHz 2B11h = 11.025kHz 2EE0h = 12kHz 3E80h = 16kHz 5622h = 22.05kHz 5DC0h = 24kHz 7D00h = 32kHz AC44h = 44.1kHz BB80h = 48kHz Any other value defaults to the nearest supported sample rate Variable Rate Audio / Sample Rate Conversion 2Eh all AUXDACSR BB80h (48kHz) AUXDAC Sample Rate Control 1F40h = 8kHz 2B11h = 11.025kHz 2EE0h = 12kHz 3E80h = 16kHz 5622h = 22.05kHz 5DC0h = 24kHz 7D00h = 32kHz AC44h = 44.1kHz BB80h = 48kHz Any other value defaults to the nearest supported sample rate 32h all ADCSR BB80h (48kHz) Stereo ADC Sample Rate Control 1F40h = 8kHz 2B11h = 11.025kHz 2EE0h = 12kHz 3E80h = 16kHz 5622h = 22.05kHz 5DC0h = 24kHz 7D00h = 32kHz AC44h = 44.1kHz BB80h = 48kHz Any other value defaults to the nearest supported sample rate Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively.
Rev 4.0 107 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 36h 15 CTRL 0 (GPIO reg) GPIO Pin Configuration Control 0 = GPIO pins used as GPIOs 1 = GPIO pins used as PCM interface PCM CODEC 14:13 MODE 10 (master mode) PCM Interface Mode Control 00 = PCM interface disabled 01 = Slave mode 10 = Master mode 11 = Partial master mode 11:9 DIV 010 (1/4) PCMCLK Rate Control 000 = Voice DAC clock 001 = Voice DAC clock / 2 010 = Voice DAC clock / 4 011 = Voice DAC clock / 8 100 = Voice DAC clock / 16 All other values are reserved
8 VDACOSR 0 (64x) Voice DAC Oversampling Rate Control
0 = 64 x fs 1 = 128 x fs
7 CP 0 (normal) PCMCLK Polarity Control
0 = Normal 1 = Inverted
6 FSP 0 (normal) FMT = 00, 01 or 10 FMT = 11
0 = Normal 1 = Inverted DSP Mode Control 0 = DSP Mode A 1 = DSP Mode B 5:4 SEL 00 (normal) PCM ADC Output Channel Control 00 = Normal stereo 01 = Reverse stereo 10 = Output left ADC data only 11 = Output right ADC data only 3:2 WL 10 (24 bits) PCM Data Word Length Control 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not supported when FMT=00) 1:0 FMT 10 (I2S) PCM Data Format Control 00 = Right justified 01 = Left justified 10 = I2S 11 = DSP mode Register 36h controls the PCM CODEC.
108 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3Ah 15 V 0 S/PDIF Validity Bit 1 = Valid 0 = Not valid Digital Audio (S/PDIF) Output double rate S/PDIF output (read-only) 13:12 SPSR 10 Indicates that the WM9713L only supports 48kHz sampling on the S/PDIF output (read-only) Programmed as required by user 10:4 CC 0000000 S/PDIF Category Code Control Category code; programmed as required by user 0 = no pre-emphasis 1 = 50/15µs pre-emphasis 0 = Copyright not asserted 1 = Copyright asserted 0 = PCM data 1 = Non-PCM data 0 = Consumer mode 1 = Professional mode Register 3Ah Read/Write. Controls the S/PDIF output.
Rev 4.0 109 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3Ch 15 PADCPD 1 (disabled) Touchpanel / AUXADC Disable Control 1 = Disabled 0 = Enabled Power Management
14 VMID1M 1 (disabled) 1Meg VMID String Disable Control
1 = Disabled 0 = Enabled
13 TSHUT 1 (disabled) Thermal Shutdown Disable Control
1 = Disabled 0 = Enabled
12 VXDAC 1 (disabled) Voice DAC Disable Control
1 = Disabled 0 = Enabled
11 AUXDAC 1 (disabled) AUXDAC Disable Control
1 = Disabled 0 = Enabled
10 VREF 1 (disabled) VREF Disable Control
1 = Disabled 0 = Enabled
9 PLL 1 (disabled) PLL Disable Control
1 = Disabled 0 = Enabled
7 DACL 1 (disabled) Left DAC Disable Control
1 = Disabled 0 = Enabled
6 DACR 1 (disabled) Right DAC Disable Control
1 = Disabled 0 = Enabled
5 ADCL 1 (disabled) Left ADC Disable Control
1 = Disabled 0 = Enabled
4 ADCR 1 (disabled) Right ADC Disable Control
1 = Disabled 0 = Enabled
3 HPLX 1 (disabled) Left Headphone Mixer Disable Control
1 = Disabled 0 = Enabled
2 HPRX 1 (disabled) Right Headphone Mixer Disable Control
1 = Disabled 0 = Enabled
1 SPKX 1 (disabled) Speaker Mixer Disable Control
1 = Disabled 0 = Enabled
0 MX 1 (disabled) Mono Mixer Disable Control
1 = Disabled 0 = Enabled * “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0. Register 3Ch is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 3Ch AND register 26h.
110 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3Eh 15 MCD 1 (disabled) Microphone Current Detect Disable Control 1 = Disabled 0 = Enabled Power Management
14 MICBIAS 1 (disabled) Microphone Bias Disable Control
1 = Disabled 0 = Enabled
13 MONO 1 (disabled) MONO PGA Disable Control
1 = Disabled 0 = Enabled
12 OUT4 1 (disabled) OUT4 PGA Disable Control
1 = Disabled 0 = Enabled
11 OUT3 1 (disabled) OUT3 PGA Disable Control
1 = Disabled 0 = Enabled
10 HPL 1 (disabled) HPL PGA Disable Control
1 = Disabled 0 = Enabled
9 HPR 1 (disabled) HPR PGA Disable Control
1 = Disabled 0 = Enabled
8 SPKL 1 (disabled) SPKL PGA Disable Control
1 = Disabled 0 = Enabled
7 SPKR 1 (disabled) SPKR PGA Disable Control
1 = Disabled 0 = Enabled
6 LL 1 (disabled) LINEL PGA Disable Control
1 = Disabled 0 = Enabled
5 LR 1 (disabled) LINER PGA Disable Control
1 = Disabled 0 = Enabled
4 MOIN 1 (disabled) MONOIN PGA Disable Control
1 = Disabled 0 = Enabled
3 MA 1 (disabled) MICA PGA Disable Control
1 = Disabled 0 = Enabled
2 MB 1 (disabled) MICB PGA Disable Control
1 = Disabled 0 = Enabled
1 MPA 1 (disabled) Mic Pre-amp MPA Disable Control
1 = Disabled 0 = Enabled
0 MPB 1 (disabled) Mic Pre-amp MPB Disable Control
1 = Disabled 0 = Enabled * “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0. Register 3Eh is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 3Eh AND register 26h.
Rev 4.0 111 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 40h 13 3DE 0 (disabled) 3D Enhancement Control 1 = Enabled 0 = Disabled Audio DACs, 3D Stereo Enhancement
7 LB 0 (disabled) Digital Loopback Control
1 = Enabled 0 = Disabled Intel’s AC’97 Component Specification, Revision 2.2, page 55 Register 40h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the WM9713L. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 42h 6 MONO 0 (normal) MONO Fast Power Up Control 1 = Fast power up 0 = Normal power up Analogue Audio Outputs, Power-Up
5 SPKL 0 (normal) SPKL Fast Power Up Control
1 = Fast power up 0 = Normal power up
4 SPKR 0 (normal) SPKR Fast Power Up Control
1 = Fast power up 0 = Normal power up
3 HPL 0 (normal) HPL Fast Power Up Control
1 = Fast power up 0 = Normal power up
2 HPR 0 (normal) HPR Fast Power Up Control
1 = Fast power up 0 = Normal power up
1 OUT3 0 (normal) OUT3 Fast Power Up Control
1 = Fast power up 0 = Normal power up
0 OUT4 0 (normal) OUT4 Fast Power Up Control
1 = Fast power up 0 = Normal power up Register 42h controls power-up conditions for output PGAs.
112 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 44h 14:12 SEXT[6:4] 000 (div 1) Hi-Fi Block Clock Division Control 000 = f 001 = f/2 111 = f/8 Clock Generation 11:8 SEXT[3:0] 0000 (div 1) Voice DAC Clock Division Control 0000 = f 0001 = f/2 1111 = f/16
7 CLKSRC 1 (external) AC97 CLK Source Control
1 = External clock 0 = PLL clock 5:3 PENDIV 000 (f/16) AUXADC Clock Division Control 000 = f/16 001 = f/12 010 = f/8 011 = f/6 100 = f/4 101 = f/3 110 = f/2 111 = f
2 CLKBX2 0 (normal) MCLKB Multiplier Control
0 = Normal 1 = Multiply by 2 0 = Normal 1 = Multiply by 2 0 = Use MCLKA 1 = Use MCLKB Register 44h controls clock division and muxing.
Rev 4.0 113 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 46h 15:12 N[3:0] 0000 (div by 1) PLL N Divide Control 0000 = Divide by 1 0001 = Divide by 1 0010 = Divide by 2 1111 = Divide by 15 PLL Mode
11 LF 0 (normal) PLL Low Frequency Input Control
1 = Low frequency mode (input clock < 8.192MHz) 0 = Normal mode
10 SDM 0 (disabled) PLL SDM Enable Control
1 = Enable SDM (required for fractional N mode) 0 = Disable SDM
9 DIVSEL 0 (div by 1) PLL Input Clock Division Control
0 = Divide by 1 1 = Divide according to DIVCTL 0 = Divide by 2 1 = Divide by 4 6:4 PGADDR 000 Pager Address Pager address bits to access programming of K[21:0] and SPLL[6:0] 3:0 PGDATA 0000 Pager Data Pager data bits Register 46h controls PLL clock generation.
114 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 4Ch n GCn 1 (input) GPIO Pin Configuration Control 0 = Output 1 = Input (GC9-15 are always inputs) GPIO and Interrupt Control 4Eh n GPn 1 (active high) GPIO Pin Polarity / Type Input (GCn = 1) Output (GCn = 0) 0 = Active low 1 = Active high 0 = CMOS output 1 = Open drain 50h n GSn 0 (not sticky) GPIO Pin Sticky Control 0 = Not sticky 1 = Sticky 52h n GWn 0 (no wake- up) GPIO Pin Wake-up Control 0 = No wake-up (no interrupts generated by GPIO) 1 = Wake-up (generate interrupts from GPIO) 54h n GIn N/A GPIO Pin Status Read = Returns status of GPIO Write = Writing 0 clears sticky bits Bit definitions for registers 4Ch to 54h Controls Comparator 1 signal (virtual GPIO)
14 Controls Comparator 2 signal (virtual GPIO)
13 Controls Pen-Down Detector signal (virtual GPIO)
12 Controls ADA signal (virtual GPIO)
11 Controls Thermal sensor signal (virtual GPIO)
10 Controls Microphone short detect (virtual GPIO)
9 Controls Microphone insert detect (virtual GPIO)
8 Controls GPIO8 (pin 12)
7 Controls GPIO7 (pin 11)
6 Controls GPIO6 (pin 3)
5 Controls GPIO5 (pin 48)
4 Controls GPIO4 (pin 47)
3 Controls GPIO3 (pin 46)
2 Controls GPIO2 (pin 45)
1 Controls GPIO1 (pin 44)
Register 4Ch to 54h control the GPIO pins and virtual GPIO signals.
Rev 4.0 115 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 56h 8 GE8 1 (GPIO) GPIO8 (Pin 12) Function Control 0 = Pin 12 is not controlled by GPIO logic 1 = Pin 12 is controlled by GPIO logic GPIO and Interrupt Control
7 GE7 1 (GPIO) GPIO7 (Pin 11) Function Control
0 = Pin 11 is not controlled by GPIO logic 1 = Pin 11 is controlled by GPIO logic
6 GE6 1 (GPIO) GPIO6 (Pin 3) Function Control
0 = Pin 3 is not controlled by GPIO logic 1 = Pin 3 is controlled by GPIO logic
5 GE5 1 (GPIO) GPIO5 (Pin 48) Function Control
0 = Pin 48 is not controlled by GPIO logic 1 = Pin 48 is controlled by GPIO logic
4 GE4 1 (GPIO) GPIO4 (Pin 47) Function Control
0 = Pin 47 is not controlled by GPIO logic 1 = Pin 47 is controlled by GPIO logic
3 GE3 1 (GPIO) GPIO3 (Pin 46) Function Control
0 = Pin 46 is not controlled by GPIO logic 1 = Pin 46 is controlled by GPIO logic
2 GE2 1 (GPIO) GPIO2 (Pin 45) Function Control
0 = Pin 45 is not controlled by GPIO logic 1 = Pin 45 is controlled by GPIO logic Register 56h controls the use of GPIO pins for non-GPIO functions. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 58h 15:8 PU 01000000 GPIO Pin Pull-Up Control 1 = Enables weak pull-up on GPIO pins 0 = No pull-up on GPIO pins GPIO and Interrupt Control 7:0 PD 00000000 GPIO Pin Pull-Down Control 1 = Enables weak pull-down on GPIO pins 0 = No pull-down on GPIO pins Register 58h controls GPIO pull-up/down.
116 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 5Ah 15:13 COMP2DEL 000 (no delay) Low Battery Alarm Delay Control 000 = No delay 001 = 213 AC-link frames 010 = 214 AC-link frames 011 = 215 AC-link frames 100 = 216 AC-link frames 101 = 217 AC-link frames 110 = 218 AC-link frames 111 = 219 AC-link frames Battery Alarm
8 RSTDIS 0 (RESETB
enabled) RESETB Pin Disable Control 0 = Pin 11 is RESETB 1 = Pin 11 is GPIO (RESETB function disabled) GPIO Interrupt and Control 7:6 JSEL 00 (GPIO1) Jack Detect Pin Input Control 00 = GPIO1 01 = GPIO6 10 = GPIO7 11 = GPIO8 Jack Insertion & Auto- Switching 5:4 HPMODE 00 (7Hz) HPF Cut-Off Control 00 = 7Hz @ fs=48kHz 01 = 82Hz @ fs=16kHz 10 = 82Hz @ fs=8kHz 11 = 170Hz @ fs=8kHz Audio ADCs 3:2 DIE REV N/A Device Revision (Read-Only) 00 = Rev.A 01 = Rev.B 10 = Rev.C N/A
1 WAKEEN 0 (disabled) GPIO Wake Up Control
0 = Disable wake-up 1 = Enable wake up GPIO and Interrupt Control
0 IRQ INV 0 (normal) IRQ Polarity Control
0 = Normal 1 = Inverted Register 5Ah controls several additional functions.
Rev 4.0 117 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 5Ch 15 AMUTE 0 DAC Automute Status (Read-Only) 0 = DAC not muted 1 = DAC auto-muted Audio DACs, Stereo DACs
14 C2REF 0 (AVDD/2) Comparator 2 Reference Voltage Select
0 = AVDD/2 1 = WIPER/AUX4 (pin 12) Battery Alarm 13:12 C2SRC 00 (power down) Comparator 2 Signal Source 00 = AVDD/2 when C2REF=1, else powered down 01 = COMP1/AUX1 (pin 29) 10 = COMP2/AUX2 (pin 30) 11 = Reserved
11 C1REF 0 (AVDD/2) Comparator 1 Reference Voltage Select
0 = AVDD/2 1 = WIPER/AUX4 (pin 12) 10:9 C1SRC 00 (OFF) Comparator 1 Signal Source 00 = AVDD/2 when C1REF=1, else powered down 01 = COMP1/AUX1 (pin 29) 10 = COMP2/AUX2 (pin 30) 11 = Reserved
7 AMEN 0 (OFF) DAC Automute Control
0 = Disabled 1 = Enabled Stereo DAC 6:5 VBIAS 00 (3.3V) Analogue Bias Optimization Control 0X = Optimized for 3.3V 10 = Optimized for 2.5V 11 = Optimized for 1.8V Power Management
4 ADCO 0
(SDATAOUT) S/PDIF Data Source Control 0 = From SDATAOUT 1 = Output from audio ADC Digital Audio (S/PDIF) Output
3 HPF 0 (enabled) ADC HPF Disable Control
0 = HPF enabled 1 = HPF disabled Audio ADC 1:0 ASS 00 (slots 3, 4) ADC Data Slot Mapping Control Audio ADC, ADC Slot Mapping Left Data Right Data 00 = Slot 3 Slot 4 01 = Slot 7 Slot 8 10 = Slot 6 Slot 9 11 = Slot 10 Slot 11 Register 5Ch controls several additional functions.
118 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 60h 15:12 ALCL 1011 (-12dB) ALC Target Level Control 0000 = -28.5dBFS … (1.5dB steps) 1111 = -6dBFS Audio ADC, Automatic Level Control 11:8 HLD 0000 (0ms) ALC Hold Time Control 0000 = 0ms 0001 = 2.67ms … (time doubles with every step) 1111 = 43.691s 7:4 DCY 0011 (192ms) ALC Decay Time Control 0000 = 24ms … (time doubles with every step) 1010 to 1111 = 24.58s 3:0 ATK 0010 (24ms) ALC Attack Time Control 0000 = 6ms … (time doubles with every step) 1010 to 1111 = 6.14s 62h 15:14 ALCSEL 00 (disabled) ALC Function Channel Control 00 = ALC disabled 01 = ALC on right channel only 10 = ALC or left channel only 11 = ALC on both left and right channels 13:11 MAXGAIN 111 (+30dB) ALC PGA Gain Limit Control 000 = -12dB … (6dB steps) 111 = +30dB 10:9 ZC TIMEOUT 11 (slowest) ALC Zero Cross Timeout Delay Control 00 = 214 x tBITCLK (1.33ms) 01 = 215 x tBITCLK (2.67ms) 10 = 216 x tBITCLK (5.33ms) 11 = 217 x tBITCLK (10.67ms)
7 NGAT 0 (disabled) Noise Gate Enable Control
0 = Disabled 1 = Enabled
5 NGG 0 (hold gain) Noise Gate Function Control
0 = Hold PGA gain at last value 1 = Mute ADC output 4:0 NGTH 00000 (- 76.5dB) Noise Gate Threshold Control 00000 = -76.5dBFS … (1.5dB steps) 11111 = -30dBFS Registers 60h and 62h control the ALC and Noise Gate functions.
Rev 4.0 119 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 64h 15 XSLE 0 (DC) AUXDAC Input Select Control 0 = From AUXDACVAL[11:0] (for DC signals) 1 = From AC-Link (for AC signals) Auxiliary DAC 14:12 AUXDAC SLT 000 (Slot 5) AUXDAC Input Control (XSLE=1) 000 = Slot 5, bits 8-19 001 = Slot 6, bits 8-19 010 = Slot 7, bits 8-19 011 = Slot 8, bits 8-19 100 = Slot 9, bits 8-19 101 = Slot 10, bits 8-19 110 = Slot 11, bits 8-19 111 = Reserved 11:0 AUXDAC VAL 000h (min) AUXDAC Input Control (XSLE=0) 000h = Minimum FFFh = Full scale Register 64h controls the input signal of the auxiliary DAC. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 74h 9 POLL 0 Poll Measurement Control Writing “1” initiates a measurement (when CTC is not set) Touchpanel Interface
8 CTC 0 (Polling) AUXADC Measurement Mode
0 = Polling mode 1 = Continuous mode (for DMA)
7 ADCSEL_
0 (disabled) AUX4 Measurement Enable Control 0 = Disable AUX4 measurement (pin 12) 1 = Enable AUX4 measurement (pin 12) 0 (disabled) AUX3 Measurement Enable Control 0 = Disable AUX3 measurement (SPKVDD/3) 1 = Enable AUX3 measurement (SPKVDD/3) 0 (disabled) AUX2 Measurement Enable Control 0 = Disable AUX2 measurement (pin 30) 1 = Enable AUX2 measurement (pin 30) 0 (disabled) AUX1 Measurement Enable Control 0 = Disable AUX1 measurement (pin 29) 1 = Enable AUX1 measurement (pin 29)
3 ADCSEL_
0 (disabled) Pressure Measurement Enable Control 0 = Disable pressure measurement 1 = Enable pressure measurement
2 ADCSEL_Y 0 (disabled) Y Co-ordinate Measurement Enable Control
0 = Disable Y co-ordinate measurement 1 = Enable Y co-ordinate measurement
1 ADCSEL_X 0 (disabled) X Co-ordinate Measurement Enable Control
0 = Disable X co-ordinate measurement 1 = Enable X co-ordinate measurement
0 COO 0 (single) Co-ordinate Mode Control
0 = Single measurement 1 = Co-ordinate measurement Register 74h controls the measurements for the touchpanel interface.
120 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 76h 9:8 CR 00 (93.75Hz) Continuous Mode Conversion Rate Touchpanel Interface DEL < 1111 DEL = 1111 00 = 93.75Hz 00 = 8kHz 01 = 120Hz 01 = 12kHz 10 = 153.75kHz 10 = 24kHz 11 = 187.5Hz 11 = 48kHz 7:4 DEL 0000 (20.8s) Touchpanel Settling Time Control 0000 = 1 AC-link frame (20.8µs) 0001 = 2 AC-link frames (41.7µs) 0010 = 4 AC-link frames (83.3µs) 0011 = 8 AC-link frames (167µs) 0100 = 16 AC-link frames (333µs) 0101 = 32 AC-link frames (667µs) 0110 = 48 AC-link frames (1ms) 0111 = 64 AC-link frames (1.33ms) 1000 = 96 AC-link frame (2ms) 1001 = 128 AC-link frames (2.67ms) 1010 = 160 AC-link frames (3.33ms) 1011 = 192 AC-link frames (4ms) 1100 = 224 AC-link frames (4.67ms) 1101 = 256 AC-link frames (5.33ms) 1110 = 288 AC-link frames (6ms) 1111 = No delay, switch matrix always on
3 SLEN 1 (enabled) Slot Readback Enable Control
0 = Disabled (readback through register map only) 1 = Enabled (readback slot selected by SLT) 2:0 SLT 110 (slot 11) AC’97 Slot for Touchpanel Data Control 000 = Slot 5 001 = Slot 6 010 = Slot 7 011 = Slot 8 100 = Slot 9 101 = Slot 10 110 = Slot 11 111 = Reserved Register 76h controls the touchpanel interface measurement timing.
Rev 4.0 121 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 78h 15:14 PRP 00 (disabled) Touchpanel Digitiser Power State Control 00 = Disabled 01 = Enable pen detect, wake-up on pen down 10 = Enable pen detect, no wake-up on pen down 11 = Pen detect and pen digitizer enabled Touchpanel Interface
13 RPR 0 (AC-link) Pen Detect Wake-up Mode Control
0 = Wake AC-link only 1 = Wake-up AC-link and WM9713 12 45W 0 (4-wire) Touchpanel Type Control 0 = 4-wire 1 = 5-wire
11 PDEN 0 (always) Touchpanel Measurement Pen Status Control
0 = Measure regardless of pen status 1 = Measure only when pen is down
10 PDPOL 0 (normal) PENDOWN Polarity Control
0 = Normal 1 = Inverted
9 WAIT 0 (overwrite) Touchpanel ADC Data Control
0 = Overwrite existing data in 7Ah with new data 1 = Retain existing data in 7Ah until it is read 0 = 200µA 1 = 400µA 7:6 MSK 00 (disabled) Mask Input Control 00 = Disabled 01 = Static 10 = Edge-triggered 11 = Synchronous 5:0 RPU 000001 (64k) Internal Pull-up Resistor Control 000000 = Reserved 000001 = 64kΩ/1 (most sensitive) 000010 = 64kΩ/2 000011 = 64kΩ/3 … (64kΩ/binary value of RPU) 111111 = 64kΩ/63 (least sensitive) Register 78h controls the physical properties of the touchpanel interface.
122 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 7Ah read only
15 PNDN 0 (pen up) Pen Status (Read-only)
0 = Pen up 1 = Pen down Touchpanel Interface 14:12 ADCSRC 000 (none) Touchpanel ADC Source 000 = No measurement 001 = X co-ordinate measurement 010 = Y co-ordinate measurement 011 = Pressure measurement (4-wire only) 100 = COMP1/AUX1 measurement (pin 29) 101 = COMP2/AUX2 measurement (pin 30) 110 = AUX3 measurements (SPKVDD/3) 111 = WIPER/AUX4 measurement (pin 12) 11:0 ADCD 000h Touchpanel ADC Data (Read-only) Bit 0 = LSB Bit 11 = MSB Registers 7Ah is a read-only register which reports the touchpanel interface status and measurement results. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 7Ch read-only 15:8 F7:0 57h ASCII character “W” for Wolfson Intel’s AC’97 Component Specification , Revision 2.2, page 50 7:0 S7:0 4Dh ASCII character “M” 7Eh read-only 15:8 T7:0 4Ch ASCII character “L” 7:0 REV7:0 13h Device identifier Register 7Ch and 7Eh are read-only registers that indicate to the driver that the CODEC is a WM9713L.
Rev 4.0 123 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 36 Recommended External Component Diagram
124 Rev 4.0 LINE OUTPUT The headphone o utputs, HPL and HPR, can be used as stereo line outputs. The speaker outputs, SPKL and SPKR, can also be used as line outputs. Recommended external components are shown below. HPGND/SPKGND HPGND/SPKGND LINE-OUT SOCKET (LEFT) 1uF
100 Ohm
(RIGHT)C2 1uF Figure 37 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1, C2 = 10F: Increasing the capacitance low ers fc, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly. AC-COUPLED HEADPHONE OUTPUT The circuit diagram below shows how to connect a stereo headphone to the WM9713L. C2 220uF HPL HPR HPGND = 0V C1 220uF WM9713L Figure 38 Simple Headphone Output Circuit Diagram The DC blocking capacitors C1 and C2 together with the load resistance determine the lower cut -off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. For example, with a 16 load and C1 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz
Rev 4.0 131 PACKAGE DIMENSIONS e DM103.AFL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH INDEX AREA (D/2 X E/2) TOP VIEW Caaa2 X SEE DETAIL 2 E2/2 b L D2/2 Caaa2 X 37 48 D E e Datum SEE DETAIL 1 C0.08 Cccc A A1C (A3) SEATING PLANE DETAIL 3 DETAIL 3 DETAIL 2 Terminal Tip e/2 DETAIL 1 (A3) G T H W b Exposed lead Half etch tie bar Symbols Dimensions (mm) MIN NOM MAX NOTE A b D E e L 0.80 0.90 1.00 0.300.250.18
7.00 BSC
5.755.655.55
0.5 BSC
5.65 5.755.55 0.30 0.4 0.50 0 0.02 0.05
0.20 REF
G H 0.20 0.10 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. JEDEC, MO-220, VARIATION VKKD-4 Tolerances of Form and Position T W aaa bbb ccc 0.103 0.15 0.15 0.10 0.10 REF EXPOSED GROUND PADDLE EXPOSED GROUND PADDLE BOTTOM VIEW SIDE VIEW 0.30mm 45°
132 Rev 4.0 IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. For the purposes of our terms and conditions of sale, "Preliminary" or "Advanced" datasheets are non-final datasheets that include but are not limited to datasheets marked as “Target”, “Advance”, “Product Preview”, “Preliminary Technical Data” and/or “Pre- production.” Products provided with any such datasheet are therefore subject to relevant terms and conditions associated with "Preliminary" or "Advanced" designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners. Copyright © 2008–2016 Cirrus Logic, Inc. All rights reserved.
Rev 4.0 133
REVISION HISTORY
DATE REV ORIGINATOR CHANGES PAGE 13/10/08 3.3 BK Corrected pin numbers for GPIO6 and GPIO8 114
3.3 BK Added note with power-down sequence for VXDAC (see CE000296) 42
24/12/09 3.3 BK Added AUXDAC THD/SNR min/typ specs 03/08/10 3.3 SS Made changes to ‘Thermal Sensor’ section and Table 40 to correct and clarify. 60 30/08/10 3.3 SS Added note in Table 62 ‘GPIO Control’ to exclude Thermal Sensor from polarity description and refer to Table 40 ‘Thermal Shutdown Control’. 13/10/11 3.3 JMacD Order codes updated from WM9713LGEFL/RV and WM9713LGEFL/RV to WM9713CLGEFL/RV and WM9713CLGEFL/RV to reflect change to copper wire bonding 13/10/11 3.3 JMacD Package Diagram changed to DM103.A 136 19/12/16 4.0 PH Updated to Cirrus Logic template