CS5126-KL

CS5126 CIRRUS | Alldatasheet

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Technical content

Features

lMonolithic CMOS A/D Converter - Inherent Sampling Architecture - Stereo or Monaural Capability - Serial Output lMonaural Sampling Rates up to 100 kHz - 50 kHz/Channel Stereo Sampling lSignal-to-(Noise+Distortion): 92 dB lDynamic Range: 92 dB - 95 dB in 2X Oversampling Schemes lInterchannel Isolation: 90 dB l2's Complement or Binary Coding lLow Power Dissipation: 260 mW - Power Down Mode for Portable Applications lEvaluation Board Available

Description

The CS5126 CMOS analog-to-digital converter is an ide- al front-end for stereo or monaural digital audio systems. The CS5126 can be configured to handle two channels at up to 50 kHz sampling per channel, or it can be con- figured to sample one channel at rates up to 100 kHz. The CS5126 executes a successive approximation algo- rithm using a charge redistribution architecture. On-chip self-calibration circuitry has 18-bit resolution thus avoid- ing any degradation in performance with low-level signals. The charge redistribution technique also pro- vides an inherent sampling function which avoids the need for external sample/hold amplifiers. Signal-to-(noise+distortion) in stereo operation is 92 dB, and is dominated by internal broadband noise (1/2 LSB rms). When the CS5126 is configured for 2X oversam- pling, digital post-filtering bandlimits this white noise to 20 kHz, increasing dynamic range to 95 dB.

ORDERING INFORMATION

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ANALOG CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V; VA-, VD- = -5V; Full-Scale Input Sinewave, 1kHz; fclk = 24.576MHz; VREF = 4.5V; Analog Source Impedance = 200Ω ; Stereo operation, L/R toggling at 48 kHz unless otherwise specified.) Parameter* Symbol Min Typ Max Units Resolution - - 16 Bits Dynamic Performance Signal-to-(Noise plus Distortion) VIN = ±FS (10 Hz to 20 kHz) VIN = -20dB (f = 20 kHz) S/(N+D) dB dB Total Harmonic Distortion THD - 0.001 - % Dynamic Range Stereo Mode Monaural (20 kHz BW) DR 90 dB dB Idle Channel Noise V n(ic) -1 / 2- L S B rms Interchannel Isolation (Note 1) I ic 88 90 - dB Interchannel Mismatch M ic -0 . 0 1- d B dc Accuracy Full-Scale Error FSE - ±4 -L S B Bipolar Offset Error BPO - ±4 -L S B Analog Input Aperture Time t apt -3 0- n s Aperture Jitter t ajt - 100 - ps Input Capacitance (Note 2) C in - 200 - pF Power Supplies Power Supply Current Positive Analog (Note 3) Negative Analog (SLEEP High) Positive Digital Negative Digital IA+ IA- ID+ ID- -18 -23 -12 mA mA mA mA Power Dissipation (SLEEP High) (Notes 3, 4) (SLEEP Low) P do Pds 260 350 mW mW Power Supply Rejection Positive Supplies (Note 5) Negative Supplies PSR - dB dB Notes: 1. One input grounded; dc to 20kHz, Full Scale input on the other channel. Guaranteed by characterization. 2. Applies only in the track mode. When converting or calibrating, input capacitance will typically be 10 pF. 3. All outputs unloaded. All inputs CMOS levels. 4. Power dissipation in sleep mode applies with no master clock applied (CLKIN high or low). 5. With 300mV p-p, 1kHz ripple applied to each supply separately. A plot of typical power supply rejection appears in the Analog Circuit Connections section. * Refer to Parameter Definitions at the end of this data sheet. Specifications are subject to change without notice. CS5126

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DIGITAL CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V±10%; VA-,VD- = -5V±10%) Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V High-Level Output Voltage (Note 6) V OH (VD+)-1.0V - - V Low-Level Output Voltage Iout = 1.6 mA V OL -- 0 . 4 V Input Leakage Current I in -- 1 0 µA Notes: 6. IOUT = -100 µA. This specification guarantees that each digital output will drive one TTL load (VOH = 2.4V @ IOUT = -40 µA). RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see note 7.) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 V V V V Analog Reference Voltage VREF 2.5 4.5 (VA+)-0.5 V Analog Input Voltage (Note 8) V AIN -VREF - VREF V Notes: 7. All voltages with respect to ground. 8. The CS5126 can accept input voltages up to the analog supplies (VA+, VA-). It will produce an output of all 1’s for inputs above VREF and all 0’s for inputs below -VREF. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.) Parameter Symbol Min Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 0.3 -0.3 0.3 (VA+)+0.3 -6.0 6.0 -6.0 V V V V Input Current, Any Pin Except Supplies (Note 9) I in - ±10 mA Analog Input Voltage (AIN and VREF pins) V INA (VA-)-0.3 (VA+)+0.3 V Digital Input Voltage V IND -0.3 (VD+)+0.3 V Ambient Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Notes: 9. Transient currents of up to 100 mA will not cause SCR latch-up. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. CS5126 DS32F1 3

SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units Master Clock Period t clk 40 - - ns HOLD to SSH2 Falling (Note 10) t dfsh2 -8 0- n s HOLD to TRKL, TRKR SSH1 Falling t dfsh1 198tclk - 214t clk+50 ns HOLD to TRKL, TRKR SSH1, SSH2 Rising t drsh -8 0- n s RST Pulse Width t rst 150 - - ns RST to STBY Falling t drrs - 100 - ns RST Rising to STBY Rising t cal - 34,584,480 - t clk HOLD Pulse Width t hold 2tclk+50 - 192t clk ns HOLD to L/R Edge (Note 10) t dhlri -30 - 192t clk ns SCLK period t sclk 200 - - ns SCLK Pulse Width Low t sclkl 50 - - ns SCLK Pulse Width High t sclkh 50 - - ns SCLK Falling to SDATA Valid t dss - 100 140 ns HOLD Falling to SDATA Valid t dhs - 140 200 ns Notes: 10. SSH2 only works correctly if HOLD falling edge is within ±30ns of L/R edge OR if HOLD falling edge occurs between 30ns before HOLD rises to 192 tclk after HOLD falls. TRKR (o) TRKL (o) HOLD (i) SSH2 (o) dfsh2t drsht dfsh1t Control Output Timing rstt calt drrst RST STBY Reset and Calibration Timing dhlrit holdt L/R HOLD Channel Selection Timing sclklt sclkht dsst SDATA SCLK sclkt Serial Data Timing SCLK MSB dhst HOLD SDATA Data Transmit Start Timing CS5126

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The CS5126 is a 2-channel, 100kHz A/D con- verter designed specifically for stereo digital audio. The device includes an inherent sam- ple/hold and an on-chip analog switch for stereo operation. Both left and right channels can thus be sampled and converted at rates up to 50kHz per channel. Alternatively, the CS5126 can be implemented in 2X oversampling schemes for improved dynamic range and distortion. Output data is available in serial form with either binary or 2’s complement coding. Control outputs are also supplied for use with an external sample/hold amplifier to implement simultane- ous sampling. THEORY OF OPERATION The CS5126 implements a standard successive approximation algorithm using a charge-redistri- bution architecture. Instead of the traditional re- sistor network, the DAC is an array of binary- weighted capacitors. When not converting, the CS5126 tracks the analog input signal. The input voltage is applied across each leg of the DAC capacitor array, thus performing a voltage-to- charge conversion. When the conversion command is issued, the charge is trapped on the capacitor array and the analog input is thereafter ignored. In effect, the entire DAC capacitor array serves as analog memory during conversion much like a hold ca- pacitor in a sample/hold amplifier. The conversion consists of manipulating the bi- nary-weighted legs of the capacitor array to the voltage reference and analog ground. All legs share one common node at the input to the con- verter’s comparator. This forms a binary- weighted capacitive divider. Since the charge at the comparator’s input remains fixed, the voltage at that point depends on the proportion of ca- pacitance tied to VREF versus AGND. The suc- cessive-approximation algorithm is used to find the proportion of capacitance which will drive the voltage to the comparator’s trip point. That binary fraction of capacitance represents the con- verter’s digital output. Calibration The ability of the CS5126 to convert accurately clearly depends on the accuracy of its DAC. The CS5126 uses an on-chip self-calibration scheme to insure low distortion and excellent dynamic range independent of input signal conditions. Each binary-weighted bit capacitor actually con- sists of several capacitors which can be manipu- lated to adjust the overall bit weight. During calibration, an on-chip microcontroller manipu- lates the sub-arrays to precisely ratio the bits. Each bit is adjusted to just balance the sum of all less significant bits plus one dummy LSB (for example, 16C = 8C + 4C + 2C + C + C). The result is typical differential nonlinearity of ±1/4 LSB. That is, codes typically range from 3/4 to 5/4 LSB’s wide. The CS5126 should be reset upon power-up, thus initiating a calibration cycle which takes 1.4 seconds to complete. The CS5126 then stores its calibration coefficients in on-chip SRAM, and can be recalibrated at any later time. SYSTEM DESIGN WITH THE CS5126 All timing and control inputs to the CS5126 can be easily generated from a master system clock. The CS5126 outputs serial data and a variety of digital outputs which can be used to control an external sample/hold amplifier for simultaneous sampling. The actual circuit connections depend on the system architecture (stereo or monaural 2X oversampling), and on the sampling charac- teristics (simultaneous or sequential sampling between channels). CS5126 DS32F1 5

RST rises to guarantee an accurate calibration. conversion or midcalibration. fully powered up and stable by the end of reset. 96kHz monaural oversampling.

24.576 MHz master clock is required for a sam-

pling rate of 48kHz per channel. the hold mode and initiates a conversion cycle. one master clock cycle plus 50ns. Figure 1. Power-On Reset Circuit

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independent of signal level. trous to sound quality with low-level signals. tional hybrid ADC capable of only 14-bit DNL. drastic effect on a converter’s ac performance. Figure 4. FFT Plot of CS5126 in Stereo Mode Figure 5. FFT Plots of CS5126 in Stereo Mode

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quality independent of signal level. nonideal sampling of the analog input voltage. conversion process proceeds flawlessly. distortion at low input frequencies (Figure 4). overall S/(N+D) performance. the time the entire conversion cycle finishes. Figure 6. THD vs Input Frequency

cycles (7.8µs for 48kHz stereo sampling). Figure 8. Simultaneous Sampling Connections Figure 7. External Sampling Control Output Timing

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(7.8µs for 48kHz stereo sampling). ple and perfectly linear phase. Figure 9. Monaural 2X Oversampling Connections

perior system-level distortion. the CS5126 and remove sampling distortion. sion immediately after SLEEP is brought high. Figure 11. High-Slew Monaural Connections Figure 12. FFT Plot of CS5126 in Monaural 2X Over- Figure 10. Example Oversampling System Diagram

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ease the demands placed on external circuitry. ramic capacitor is recommended. Figure 13. Suggested Voltage Reference Circuits

The CS5126 can operate with a wide range of reference voltages, but signal-to-noise perform- ance is maximized by using as wide a signal range as possible. The recommended reference voltage is 4.5 volts. The CS5126 can actually accept reference voltages up to the positive ana- log supply. However, as the reference voltage approaches VA+ the external drive requirements may increase at VREF. An internal reference buffer is used to protect the external reference from current transients during conversion. This internal buffer enlists the aid of an external 0.1µF ceramic capacitor which must be tied between its output, REFBUF, and the negative analog supply, VA-. Analog Input Connection Each time the CS5126 finishes a conversion cy- cle it switches the internal capacitor array to the appropriate analog input pin, AINL or AINR. This creates a minor dynamic load at the sam- pling frequency. All throughput specifications apply for maximum analog source impedances of 200Ω at AINL and AINR. In addition, the comparator requires source impedances of less than 400Ω around 2MHz for stability, which is met by practically all bipolar op amps. For more information, see our Application Note: "Input Buffers for the CS501X/CSZ511X Series of A/D Converters" Analog Input Range/Coding Format The CS5126 features a bipolar input range with the reference voltage applied to VREF defining both positive and negative full-scale. The coding format is set by the state of the CODE input. If high, coding is 2’s complement; if low, the CS5126’s output is in offset-binary format. Grounding and Power Supply Decoupling The CS5126 uses the analog ground connection, AGND, only as a reference voltage. No dc power or signal currents flow through the AGND connection, thus minimizing the potential for interchannel crosstalk. Also, AGND is com- pletely independent of DGND. However, any noise riding on the AGND input relative to the system’s analog ground will induce conversion errors. Therefore, both analog inputs and the ref- erence voltage should be referred to the AGND pin, which should be used as the entire system’s analog ground. The digital and analog supplies are isolated within the CS5126 and are pinned out separately to minimize coupling between the analog and digital sections of the chip. All four supplies should be decoupled to their respective grounds using 0.1 µF ceramic capacitors. If sig- nificant low frequency noise is present on the supplies, 1 µF tantalum capacitors are recom- mended in parallel with the 0.1 µF capacitors. The positive digital power supply of the CS5126 must never exceed the positive analog supply by more than a diode drop or the CS5126 could experience permanent damage. If the two sup- plies are derived from separate sources, care must be taken that the analog supply comes up first at power-up. The system connection dia- grams in figures 2 and 9 show a decoupling scheme which allows the CS5126 to be powered from a single set of ± 5V rails. The positive digital supply is derived from the analog supply through a 10Ω resistor to avoid the analog sup- ply dropping below the digital supply. If this scheme is utilized, care must be taken to insure that any digital load currents (which flow through the 10 Ω resistors) do not cause the magnitude of digital supplies to drop below the analog supplies by more than 0.5 volts. Digital CS5126

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NEGATIVE DIGITAL POWER VD- SLEEP SLEEP (LOW POWER) MODE RESET & INITIATE CALIBRATION RST TST4 TEST MASTER CLOCK INPUT CLKIN TST3 TEST NO CONNECTION NC VA+ POSITIVE ANALOG POWER STANDBY (CALIBRATING) STBY AINR RIGHT CHANNEL ANALOG INPUT DIGITAL GROUND DGND VA- NEGATIVE ANALOG POWER POSITIVE DIGITAL POWER VD+ AGND ANALOG GROUND TRACKING LEFT CHANNEL TRKL REFBUF REFERENCE BUFFER TRACKING RIGHT CHANNEL TRKR VREF VOLTAGE REFERENCE SIMULTANEOUS SAMPLE/HOLD 1 SSH1 AINL LEFT CHANNEL ANALOG INPUT SIMULTANEOUS SAMPLE/HOLD 2 SSH2 TST2 TEST HOLD & CONVERT HOLD TST1 TEST LEFT/RIGHT CHANNEL SELECT L/RC O D E BINARY/2’s COMPLEMENT SELECT SERIAL DATA CLOCK SCLK SDATA SERIAL DATA OUTPUT NEGATIVE DIGITAL POWER VD- RESET & INITIATE CALIBRATION RST SLEEP SLEEP (LOW POWER) MODE MASTER CLOCK INPUT CLKIN TST4 TEST NO CONNECTION NC TST3 TEST STANDBY (CALIBRATING) STBY VA+ POSITIVE ANALOG POWER DIGITAL GROUND DGND AINR RIGHT CHANNEL ANALOG INPUT POSITIVE DIGITAL POWER VD+ VA- NEGATIVE ANALOG POWER TRACKING LEFT CHANNEL TRKL AGND ANALOG GROUND TRACKING RIGHT CHANNEL TRKR REFBUF REFERENCE BUFFER SIMULTANEOUS SAMPLE/HOLD 1 SSH1 VREF VOLTAGE REFERENCE SIMULTANEOUS SAMPLE/HOLD 2 SSH2 AINL LEFT CHANNEL ANALOG INPUT HOLD & CONVERT HOLD TST2 TEST LEFT/RIGHT CHANNEL SELECT L/R TST1 TEST SERIAL DATA CLOCK SCLK CODE BINARY/2’s COMPLEMENT SELECT SDATA SERIAL DATA OUTPUT top view 22 2532 7242 6 281 12 14 16 1813 15 17 CS5126

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VD+ - Positive Digital Power, PIN 7. Positive digital power supply. Nominally +5 volts. VD- - Negative Digital Power, PIN 1. Negative digital power supply. Nominally -5 volts. DGND - Digital Ground, PIN 6. Digital ground reference. VA+ - Positive Analog Power, PIN 25. Positive analog power supply. Nominally +5 volts. VA- - Negative Analog Power, PIN 23. Negative analog power supply. Nominally -5 volts. AGND - Analog Ground, PIN 22. Analog ground reference. Oscillator CLKIN - Clock Input, PIN 3. All conversions and calibrations are timed from a master clock which must be externally supplied. Digital Inputs HOLD - Hold, PIN 12. A falling transition on this pin sets the CS5126 to the hold state and initiates a conversion. This input must remain low at least one master clock cycle plus 50ns. L/R - Left/Right Input Channel Select, PIN 13. Status at the end of a conversion cycle determines which analog input channel will be acquired for the next conversion cycle. SLEEP - Sleep, PIN 28. When brought low causes the CS5126 to enter a low-power quiescent state. All calibration coefficients are retained in memory, so no recalibration is needed after returning to the normal operating mode. CODE - 2’s Complement/Binary Coding Select, PIN 16. Determines whether data appears in 2’s complement or offset-binary format. If high, 2’s complement; if low, offset-binary. SCLK - Serial Clock, PIN 14. Serial data changes status on a falling edge of this input, and is valid on a rising edge. CS5126 DS32F1 17

RST - Reset, PIN 32. When taken low, all internal digital logic is reset. Upon returning high, a full calibration sequence is initiated which takes 34,584,480 master clock cycles to complete. Analog Inputs AINL, AINR - Left and Right Channel Analog Inputs, PINS 19 and 24. Analog input connections for the left and right input channels. VREF - Voltage Reference, PIN 20. The analog reference voltage which sets the analog input range. Its magnitude sets both positive and negative full-scale. Digital Outputs STBY - Standby (Calibrating), PIN 5. Indicates calibration status after reset. Remains low throughout the calibration sequence and returns high upon completion. SDATA - Serial Output, PIN 15. Presents each output data bit on a falling edge of the SCLK input. Data is valid to be latched on the rising edge of SCLK. SSH1, SSH2 - Simultaneous Sample/Hold 1 and 2, PINS 10 and 11. Used to control external sample/hold amplifier(s) to achieve simultaneous stereo sampling. TRKL, TRKR - Tracking Left, Tracking Right, PINS 8 and 9. Indicate the end of a conversion cycle. Either TRKL or TRKR falls at the end of a conversion cycle depending on the status of L/R and which channel is to be tracked. Analog Outputs REFBUF - Reference Buffer Output, PIN 21. Reference buffer output. A 0.1µF ceramic capacitor must be tied between this pin and VA-. Miscellaneous NC - No Connection, PIN 4. Must be left floating for proper operation. TST1, TST2, TST3, TST4 - Test, PINS 17, 18, 26, 27. Allow access to the CS5126’s test functions which are reserved for factory use. Must be tied to VD+. CS5126

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Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value of the signal. Units in percent. Signal-to-Noise plus Distortion Ratio - The ratio of the rms value of the signal to the rms sum of all other spectral components below the Nyquist rate (excepting dc), including distortion components. Ex- pressed in decibels. Dynamic Range - Full-scale Signal-to-Noise plus Distortion with the input signal 60dB below full- scale. Units in decibels. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test grounded and a full-scale signal ap- plied to the other channel. Units in decibels. Full Scale Error - The deviation of the last code transition from the ideal (VREF-3/2 LSB’s) after all offsets have been externally compensated. Units in decibels relative to full scale. (1/2 LSB below AGND). Units in microvolts. Interchannel Mismatch - The difference in output codes between the left and right channels with the same analog input applied. Units expressed in decibels relative to full scale. Tested at full scale input. Aperture Time - The time required after the hold command for the sampling switch to open fully. Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in nanosec- onds. Aperture Jitter - The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. CS5126 DS32F1 19

• Notes •

Copyright  Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB5126 Evaluation Board for CS5126 /c108 Serial to Parallel Conversion /c108 All Timing Signals Provided /c108 Adjustable Voltage Reference /c108 ±5 V Regulators /c108 Digital and Analog Patch Areas The CDB5126 Evaluation Board allows fast evaluation of the CS5126 2-Channel, 16-bit Analog-to-Digital Converter. Analog inputs are via BNC connectors. Digital outputs are available both directly from the ADC in serial form, and in 16 bit parallel form. An adjustable monolithic voltage reference is included. I -15V +15V VA+ VA- VD+VD- VREF REFBUF AINL AINR BP/UP SLEEP TEST TEST CODE Clock Generator Sampling Timing Control Serial to Parallel Conversion Serial Clock Switching CLKIN HOLD L/R SDATA SCLK TRKR TRKL SSH2 Digital Patch Area TP TP TP TP Header HOLD EXT CLKIN Mode Select Switches VA- Analog Patch Area AINL AINR +5V Regulators AGND VL+ +5V0V DGND CS5126 SSH1 Voltage Reference MAR ‘95 DS32DB5

Figure 1 shows the power supply arrangements. ing the part before it is powered. polar mode or 0 V to +Vref in the unipolar mode. outside the power supplies of the ADC (± 5 V). rectly, solder in J2 and cut the VREF trace. evaluated by adding it to the analog patch area. Figure 1. Power Supplies

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with the regulator (U4 and U5) common leads. nating resistor for the external clock BNC. Figure 4. ADC Connections

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Figure 6. Serial to Parallel Converter

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∗ 1 - Select on-board clock generated by U6. P2 ∗ 0 - Select on-board generated HOLD. 1 - Select external HOLD via BNC connector. P3 ∗ Connect SCLK to on-board shift registers. P4 ∗ 0 − Pull L/R select pin high, selecting the left channel only. 1 - Drive L/R select at 48 kHz from the on-board timing generator. 2 - Pull L/R select pin low, selecting the right channel only. P6 ∗ Connect the OE pins of the shift registers to ground. Permanently enables the 3-state output buffers. P7 ∗ 0 - Connects the on-board Data Ready signal to the shift registers. 1 - Connects the NAND gate outputs (U11, pin 11) to the shift registers. P8 ∗ 1 - Connects the un-latched on-board Data Ready signal to P5. P9 ∗ Connects the on-board generated SCLK to the rest of the on-board circuitry. P10 ∗ 0 - Causes the on-board Data Ready generating circuit to flag data ready every conversion. be in position 1 for this to work. be in position 1 for this to work. P11 0 - Connects TRKL & TRKR to U10B, the handshake flip-flop. ∗ 1 - Connects the on-board data ready signal to U10B. P12 ∗ 0 - Allows selection of the DRDY signals for alternate channels. 1 - Connects the TRKL & TRKR to U11, pin 13. Table 1. Solder Link Options Table 2. Shorting Plug Selectable Options J1 - Joins analog ground to digital ground on the board. allows evaluation of different reference configurations. J4 - Connects an external clock to CLKIN on the ADC.

Figure 7. DIP switch configuration

1 Normal mode

Table 3. DIP Switch Selection Options Table 4. CDB5126 Test Points

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Figure 9. CDB5126 Component Layout

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• Notes • CDB5126 DS32DB5 31