CS5532-ASZ

CS5531_08 CIRRUS | Alldatasheet

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Technical content

Features

‰Chopper-stabilized PGIA (Programmable Gain Instrumentation Amplifier, 1x to 64x) – 12 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x – 1200 pA Input Current with Gains >1 ‰Delta-sigma Analog-to-digital Converter – Linearity Error: 0.0007% FS – Noise Free Resolution: Up to 23 bits ‰Two- or Four-channel Differential MUX ‰Scalable Input Span via Calibration – ±5 mV to differential ±2.5V ‰Scalable VREF Input: Up to Analog Supply ‰Simple Three-wire Serial Interface – SPI™ and Microwire™ Compatible – Schmitt Trigger on Serial Clock (SCLK) ‰R/W Calibration Registers Per Channel ‰Selectable Word Rates: 6.25 to 3,840 Sps ‰Selectable 50 or 60 Hz Rejection ‰Power Supply Configurations – VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V – VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V – VA+ = +3 V; VA- = -3 V; VD+ = +3 V General Description The CS5531/32/33/34 are highly integrated ∆Σ Analog- to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. To accommodate these applications, the ADCs come as either two-channel (CS5531/32) or four-channel (CS5533/34) devices and include a very low noise chop- per-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×. These ADCs also include a fourth order ∆Σ modu- lator followed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240 , 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz). To ease communication between the ADCs and a micro- controller, the converters include a simple three-wire se- rial interface which is SPI and Microwire compatible with a Schmitt-trigger input on the serial clock (SCLK). High dynamic range, programmable output rates, and flexible power supply options makes these ADCs ideal solutions for weigh scale and process control applications.

ORDERING INFORMATION

4TH ORDER ∆Σ MODULATOR PGIA 1,2,4,8,16 PROGRAMMABLE SINC FIR FILTER MUX (CS5533/34 SHOWN) AIN1+ AIN1- AIN2+ AIN2- AIN3+ AIN3- AIN4+ AIN4- SERIAL INTERFACE LATCH CLOCK GENERATOR CALIBRATION SRAM/CONTROL LOGIC DGND CS SDI SDO SCLK OSC2OSC1A1A0/GUARDVA- 32,64 OCT ‘08 DS289F5

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1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32) (See Notes 1 and 2.) Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C. 2. Specifications guaranteed by design, characterization , and/or test. LSB is 16 bits for the CS5531/33 and LSB is 24 bits for the CS5532/34. 3. This specification applies to the device only a nd does not include any effects by external parasitic thermocouples. 4. Drift over specified temperature range after calibration at power-up at 25 °C. Parameter CS5531/CS5533 UnitMin Typ Max Accuracy Linearity Error - ±0.0015 ±0.003 %FS No Missing Codes 16 - - Bits Bipolar Offset - ±1± 2 L S B Unipolar Offset - ±2 ±4L S B 16 Offset Drift (Notes 3 and 4) - 10 - nV/°C Bipolar Full-scale Error - ±8 ±31 ppm Unipolar Full-scale Error - ±16 ±62 ppm Full-scale Drift (Note 4) - 2 - ppm/°C Parameter CS5532/CS5534 UnitMin Typ Max Accuracy Linearity Error - ±0.0015 ±0.003 %FS No Missing Codes 24 - - Bits Bipolar Offset - ±16 ±32 LSB Unipolar Offset - ±32 ±64 LSB 24 Offset Drift (Notes 3 and 4) - 10 - nV/°C Bipolar Full-scale Error - ±8 ±31 ppm Unipolar Full-scale Error - ±16 ±62 ppm Full-scale Drift (Note 4) - 2 - ppm/°C

ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) Notes: 5. The voltage on the analog inputs is amplified by the PGIA, and becomes V CM ± Gain*(AIN+ - AIN-)/2 at the differential outputs of the amplifier. In addition to the input common mode + signal requirements for the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and (VA+ - 0.1 V) to avoid saturation of the output stage. 6. See the section of the data sheet which discusses input models. 7. Input current on AIN+ or AIN- (with Gain = 1), or VREF+ or VREF- may increase to 250 nA if operated within 50 mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions. Parameter Min Typ Max Unit Analog Input Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode Gain = 1 Gain = 2, 4, 8, 16, 32, 64 (Note 5) VA- VA- + 0.7 VA+ VA+ - 1.7 V V CVF Current on AIN+ or AIN- Gain = 1 (Note 6, 7) Gain = 2, 4, 8, 16, 32, 64 1200 nA pA Input Current Noise Gain = 1 Gain = 2, 4, 8, 16, 32, 64 200 pA/√Hz pA/√Hz Input Leakage for Mux when Off (at 25 °C) - 10 - pA Off-channel Mux Isolation - 120 - dB Open Circuit Detect Current 100 300 - nA Common Mode Rejection dc, Gain = 1 dc, Gain = 64 50, 60 Hz 130 120 dB dB dB Input Capacitance - 60 - pF Guard Drive Output - 20 - µA Voltage Reference Input Range (VREF+) - (VREF-) 1 2.5 (VA+)-(VA-) V CVF Current (Note 6, 7) - 50 - nA Common Mode Rejection dc 50, 60 Hz 120 120 dB dB Input Capacitance 11 - 22 pF System Calibration Specifications Full-scale Calibration Range Bi polar/Unipolar Mode 3 - 110 %FS Offset Calibration Range Bipolar Mode -100 - 100 %FS Offset Calibration Range Unipolar Mode -90 - 90 %FS

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ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) 8. All outputs unloaded. All input CMOS levels. 9. Power is specified when the instrumentation amplifier (Gain ≥ 2) is on. Analog supply current is reduced by approximately 1/2 when the instrumentation amplifier is off (Gain = 1). 10. Tested with 100 mV change on VA+ or VA-. Parameter Min Typ Max Unit Power Supplies DC Power Supply Currents (Normal Mode) I A+, IA- ID+ 0.6 mA mA Power Consumption Normal Mode (Notes 8 and 9) Standby Sleep 500 mW mW µW Power Supply Rejection (Note 10) dc Positive Supplies dc Negative Supply 115 115 dB dB

TYPICAL RMS NOISE (nV), CS5531/32/33/34 (See notes 11, 12 and 13) Notes: 11. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C. 12. For peak-to-peak noise multiply by 6.6 for all ranges and output rates. 13. Word rates and -3dB points with FRS = 0. When FR S = 1, word rates and -3dB points scale by 5/6. TYPICAL NOISE-FREE RESOLUTION(BITS), CS5532/34 (See Notes 14 and 15) 14. Noise-free resolution listed is for bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. For unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The noise-free resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the noise-free resolution accordingly. 15. “Noise-free resolution” is not the same as “effective resolution”. Effective resolution is based on the RMS noise value, while noise-free resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2). Specifications are subject to change without notice. Output Word Rate (Sps) -3 dB Filter Frequency (Hz) Instrumentation Amplifier Gain x64 x32 x16 x8 x4 x2 x1 7 . 5 1 . 9 4 1 71 71 92 64 27 9 1 5 5 15 3.88 24 25 27 36 59 111 218 30 7.75 34 35 39 51 84 157 308 60 15.5 48 49 54 72 118 222 436 120 31 68 70 77 102 167 314 616 240 62 115 160 276 527 1040 2070 4150 480 122 163 230 392 748 1480 2950 5890 960 230 229 321 554 1060 2090 4170 8340 1,920 390 344 523 946 1840 3650 7290 14600 3,840 780 1390 2710 5390 10800 21500 43000 86100 Output Word Rate (Sps) -3 dB Filter Frequency (Hz) Instrumentation Amplifier Gain x64 x32 x16 x8 x4 x2 x1 7 . 5 1 . 9 4 1 92 02 12 22 22 22 2 15 3.88 19 20 21 21 21 22 22 30 7.75 18 19 20 21 21 21 21 60 15.5 18 19 20 20 20 21 21 1 2 0 3 1 1 71 81 92 02 02 02 0 2 4 0 6 2 1 61 71 71 71 71 71 7 480 122 16 17 17 17 17 17 17 960 230 15 16 16 16 16 16 16 1 , 9 2 0 3 9 0 1 51 51 51 51 51 51 5 3 , 8 4 0 7 8 0 1 31 31 31 31 31 31 3

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5 V DIGITAL CHARACTERISTICS

(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 16.)

3 V DIGITAL CHARACTERISTICS

(TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 16.) 16. All measurements performed under static conditions. Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLK SCLK VIH 0.6 VD+ (VD+) - 0.45 VD+ VD+ V Low-level Input Voltage All Pins Except SCLK SCLK VIL 0.0 0.0 -0 . 8 0.6 V High-level Output Voltage A0 and A1, I out = -1.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 1.0 (VD+) - 1.0 --V Low-level Output Voltage A0 and A1, I out = 1.0 mA SDO, Iout = 5.0 mA VOL - - (VA-) + 0.4 0.4 V Input Leakage Current I in -± 1 ± 1 0 µ A SDO Tri-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9-p F Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLK SCLK VIH 0.6 VD+ (VD+) - 0.45 -V D + VD+ V Low-level Input Voltage All Pins Except SCLK SCLK VIL 0.0 0.0 -0 . 8 0.6 V High-level Output Voltage A0 and A1, I out = -1.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 1.0 (VD+) - 1.0 -- V Low-level Output Voltage A0 and A1, I out = 1.0 mA SDO, Iout = 5.0 mA VOL - - (VA-) + 0.4 0.4 V Input Leakage Current I in -± 1 ± 1 0 µ A SDO Tri-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9-p F

1. The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 filter followed by a Sinc3 filter for the other OWRs. OWRsinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc5 filter. 18. The single conversion mode only outputs fully se ttled conversions. See Table 1 for more details about single conversion mode timing. OWRSC is used here to designate the different conversion time associated with single conversions. 19. The continuous conversion mode ou tputs every conversion. This means that the filter’s settling time with a full-scale step input in the continuous conversion mode is dictated by the OWR. ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 20.) Notes: 20. All voltages with respect to ground. 21. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V. 22. VD+ and VA- must sati sfy {(VD+) - (VA-)} ≤ +7.5 V. 23. Applies to all pins including continuous overvo ltage conditions at the analog input (AIN) pins. 24. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 25. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Ratio Unit Modulator Sampling Rate f s MCLK/16 Sps Filter Settling Time to 1/2 LSB (Full-scale Step Input) Single Conversion mode (Notes 17, 18, and 19) Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Sps t s ts ts 1/OWRSC 5/OWRsinc5 + 3/OWR 5/OWR s s s Parameter Symbol Min Typ Max Unit DC Power Supplies (Notes 21 and 22) Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 +0.3 +6.0 +6.0 -3.75 V V V Input Current, Any Pin Except Supplies (Notes 23 and 24) I IN -- ± 1 0 m A Output Current I OUT -- ± 2 5 m A Power Dissipation (Note 25) PDN - - 500 mW Analog Input Voltage VREF pins AIN Pins VINR VINA (VA-) -0.3 (VA-) -0.3 (VA+) + 0.3 (VA+) + 0.3 V V Digital Input Voltage V IND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature T A -40 - 85 °C Storage Temperature T stg -65 - 150 °C

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(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF; See Figures 1 and 2.) Notes: 26. Device parameters are specified with a 4.9152 MHz clock. 27. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 28. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Master Clock Frequency (Note 26) External Clock or Crystal Oscillator MCLK 1 4.9152 5 MHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 27) Any Digital Input Except SCLK SCLK Any Digital Output t rise 1.0 100 µs µs ns Fall Times (Note 27) Any Digital Input Except SCLK SCLK Any Digital Output t fall 1.0 100 µs µs ns Start-up Oscillator Start-up Time XTAL = 4.9152 MHz (Note 28) t ost -2 0- m s Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz Serial Clock Pulse Width High Pulse Width Low 250 250 ns ns SDI Write Timing CS Enable to Valid Latch Clock t 3 50 - - ns Data Set-up Time prior to SCLK rising t 4 50 - - ns Data Hold Time After SCLK Rising t 5 100 - - ns SCLK Falling Prior to CS Disable t 6 100 - - ns SDO Read Timing CS to Data Valid t 7 -- 1 5 0 n s SCLK Falling to New Data Bit t 8 -- 1 5 0 n s CS Rising to SDO Hi-Z t 9 -- 1 5 0 n s

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control, scientific, and medical applications. per second (MCLK = 4.9152 MHz). (MCLK = 4.9152 MHz, see Figure 4).

4 Order

3 Serial

Figure 3. Multiplexer Configuration

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function of a DAC if desired. Figure 6. CS5531/32/33/34 Register Diagram

instruct the converter to perform single or multiple conversions or calibrations with the converter in the mode defined by one of these Setups. Using the single conversi on mode, an 8-bit com- mand word can be written into the serial port. The command includes po inter bits which ‘point’ to a 16-bit command in one of the Channel Setup Reg- isters which is to be executed. The 16-bit Setups can be programmed to perform a conversion on any of the input channels of the converter. More than one of the 16-bit Setups can be used for the same analog input channel. This allows the user to con- vert on the same signal with either a different con- version speed, a different gain range, or any of the other options available in the channel setup regis- ters. Alternately, the user can set up the registers to perform different conversion conditions on each of the input channels. The ADCs also include continuous conversion ca- pability. The ADCs can be instructed to continu- ously convert, referenc ing one 16-bit command Setup. In the continuous conversions mode, the conversion data words are loaded into a shift regis- ter. The converter issues a flag on the SDO pin when a conversion cycle is completed so the user can read the register, if need be. See the section on Performing Conversions for more details. The following pages document how to initialize the converter, perform offset and gain calibrations, and how to configure the converter for the various con- version modes. Each of the bits of the configuration register and of the Channe l Setup Registers is de- scribed. A list of examples follows the description section. Also the Command Register Quick Refer- ence can be used to decode all valid commands (the first 8-bits into the serial port). 2.2.1. System Initialization The CS5531/32/33/34 provide no power-on-reset function. To initialize the ADCs, the user must per- form a software reset by resetting the ADC’s serial port with the Serial Port Initialization sequence. This sequence resets the serial port to the command mode and is accomplished by transmitting at least

15 SYNC1 command bytes (0xFF hexadecimal),

followed by one SYNC0 command (0xFE hexa- decimal). Note that this sequence can be initiated at anytime to reinitialize the serial port. To complete the system initialization sequence, the user must also perform a system re set sequence which is as follows: Write a logic 1 into the RS bit of the con- figuration register. This will reset the calibration registers and other logic (but not the serial port). A valid reset will set the RV bit in the configuration register to a logic 1. Afte r writing the RS bit to a logic 1, wait 20 microseconds, then write the RS bit back to logic 0. While this involves writing an en- tire word into the configuration register, the RV bit is a read only bit, theref ore a write to the configu- ration register will not overwrite the RV bit. After clearing the RS bit back to logic 0, read the config- uration register to check the state of the RV bit as this indicates that a valid reset occurred. Reading the configuration register clears the RV bit back to logic 0. Completing the reset cycle initializes the on-chip registers to the following states: Note: Previous datasheets stated that the RS bit would clear itself back to logic 0 and therefore the user was not required to write the RS bit back to logic 0. The current data sheet instruction that requires the user to write into the configuration register to clear the RS bit has been added to insure that the RS bit is cleared. Characterization across multiple lots of silicon has indicated some chips do not automatically reset the RS bit to logic 0 in the configuration register, although the reset function is completed. This occurs only on small number of chips when the VA- supply is negative with respect to DGND. This has not Configuration Register: 00000000(H) Offset Registers: 00000000(H) Gain Registers: 01000000(H) Channel Setup Registers: 00000000(H)

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caused an operational issue for customers because their start-up sequence includes writing a word (with RS=0) into the configuration register after performing a reset. The change in the reset sequence to include writing the RS bit back to 0 insures the clearing of the RS bit in the event that a user does not write into the configuration register after the RS bit has been set. The RV bit in the Configuration Register is set to indicate a valid reset ha s occurred. The RS bit should be written back to logic “0” to complete the reset cycle. After a system initialization or reset, the on-chip controller is initialized into command mode where it waits for a valid command (the first 8-bits written into the serial port are shifted into the command register). Once a valid command is re- ceived and decoded, the byte instructs the converter to either acquire data from or transfer data to an in- ternal register(s), or perform a conversion or a cal- ibration. The Command Register Descriptions section can be used to decode all valid commands.

2.2.2. Command Register Quick Reference D7(MSB) D6 D5 D4 D3 D2 D1 D0

0 ARA CS1 CS0 R/W RSB2 RSB1 RSB0

D7 Command Bit, C 0 Must be logic 0 for these commands. These commands are invalid if this bit is logic 1. D6 Access Registers as Arrays, ARA Ignore this function. Access the respective registers, offset, gain, or channel-setup, as an array of regis- ters. The particular registers accessed are determined by the RS bits. The registers are accessed MSB first with physical channel 0 accessed first followed by physical channel 1 next and so forth. D5-D4 Channel Select Bits, CS1-CS0 CS1-CS0 provide the address of one of the two (four for CS5533/34) physical input channels. These bits are also used to access the calibration registers associated with the respective physical input channel. Note that these bits are ignored when reading data register. D3 Read/Write , R/W 0 Write to selected register. Read from selected register. D2-D0 Register Select Bit, RSB3-RSB0 000 001 010 011 101 110 111 Reserved Offset Register Gain Register Configuration Register Channel-Setup Registers Reserved Reserved D7(MSB) D6 D5 D4 D3 D2 D1 D0

1 MC CSRP2 CSRP1 CSRP0 CC2 CC1 CC0

D7 Command Bit, C 0 These commands are invalid if this bit is logic 0. Must be logic 1 for these commands. D6 Multiple Conver- sions, MC Perform fully settled single conversions. Perform conversions continuously. D5-D3 Channel-Setup Reg- ister Pointer Bits, CSRP 000 ... 111 These bits are used as pointers to the Channel-Setup registers. Either a single con- version or continuous conversions are performed on the channel setup register pointed to by these bits. D2-D0 Conversion/Calibra- tion Bits, CC2-CC0 000 001 010 011 100 101 110 111 Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved

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2.2.3. Command Register Descriptions READ/WRITE ALL OFFSET CALIBRATION REGISTERS Function: These commands are used to ac cess the offset registers as arrays. R/W (Read/Write) 0 Write to selected registers. 1 Read from selected registers. READ/WRITE ALL GAIN CALIBRATION REGISTERS Function: These commands are used to access the gain registers as arrays. R/W (Read/Write) 0 Write to selected registers. 1 Read from selected registers. READ/WRITE ALL CHANNEL-SETUP REGISTERS Function: These commands are used to acce ss the channel-setup registers as arrays. R/W (Read/Write) 0 Write to selected registers. 1 Read from selected registers. READ/WRITE INDIVIDUAL OFFSET REGISTER Function: These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[1:0] (Channel Select Bits)

00 Offset Register 1 (All devices)

01 Offset Register 2 (All devices)

10 Offset Register 3 (CS5533/34 only)

11 Offset Register 4 (CS5533/34 only)

D7(MSB) D6 D5 D4 D3 D2 D1 D0

0100 R / W 001

D7(MSB) D6 D5 D4 D3 D2 D1 D0

0100 R / W 010

D7(MSB) D6 D5 D4 D3 D2 D1 D0

0100 R / W 101

D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 0 CS1 CS0 R/W 001

READ/WRITE INDIVIDUAL GAIN REGISTER Function: These commands are used to access each gain register separately. CS1 - CS0 decode the reg- isters accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[1:0] (Channel Select Bits)

00 Gain Register 1 (All devices)

01 Gain Register 2 (All devices)

10 Gain Register 3 (CS5533/34 only)

11 Gain Register 4 (CS5533/34 only)

READ/WRITE INDIVIDUAL CHANNEL-SETUP REGISTER Function: These commands are used to access each channel-setup register separately. CS1 - CS0 de- code the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[1:0] (Channel Select Bits)

00 Channel-Setup Register 1 (All devices)

01 Channel-Setup Register 2 (All devices)

10 Channel-Setup Register 3 (All devices)

11 Channel-Setup Register 4 (All devices)

READ/WRITE CONFIGURATION REGISTER Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 0 CS1 CS0 R/W 010 D7(MSB) D6 D5 D4 D3 D2 D1 D0 0 0 CS1 CS0 R/W 101 D7(MSB) D6 D5 D4 D3 D2 D1 D0

0000 R / W 011

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Function: These commands instruct the ADC to perform either a single, fully-settled conversion or con- tinuous conversions on the physical input channel pointed to by the pointer bits (CSRP2 - CRSP0) in the channel-setup register. MC (Multiple Conversions) 0 Perform a single conversion. 1 Perform continuous conversions. CSRP [2:0] (Channel Setup Register Pointer Bits)

000 Setup 1 (All devices)

001 Setup 2 (All devices)

010 Setup 3 (All devices)

011 Setup 4 (All devices)

100 Setup 5 (All devices)

101 Setup 6 (All devices)

110 Setup 7 (All devices)

111 Setup 8 (All devices)

D7(MSB) D6 D5 D4 D3 D2 D1 D0

1 MC CSRP2 CSRP1 CSRP0 0 0 0

Function: These commands instruct t he ADC to perform a calibration on the physical input channel se- lected by the setup register which is chosen by the command byte pointer bits (CSRP2 - CSRP0). CSRP [2:0] (Channel Setup Register Pointer Bits) CC [2:0] (Calibration Control Bits)

000 Reserved

001 Self-Offset Calibration

010 Self-Gain Calibration

011 Reserved

100 Reserved

101 System-Offset Calibration

110 System-Gain Calibration

111 Reserved

Function: Part of the serial port re-initialization sequence. SYNC0 Function: End of the serial port re-initialization sequence. NULL Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. D7(MSB) D6 D5 D4 D3 D2 D1 D0 1 0 CSRP2 CSRP1 CSRP0 CC2 CC1 CC0 D7(MSB) D6 D5 D4 D3 D2 D1 D0 11111111 D7(MSB) D6 D5 D4 D3 D2 D1 D0 11111110 D7(MSB) D6 D5 D4 D3 D2 D1 D0 00000000

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details the command and data word timing. the port can function as a three-wire interface.

8 SCLKs Clear SDO FlagSDO

details about conversion timing. Figure 7. Command and Data Word Timing

2.2.5. Reading/Writing On-Chip Registers The CS5531/32/33/34’s offset, gain, configuration, and channel-setup register s are readable and writ- able while the conversion data register is read only. As shown in Figure 7, to write to a particular regis- ter the user must transmit the appropriate write command and then follow that command by 32 bits of data. For example, to write 0x80000000 (hexa- decimal) to physical channel one’s gain register, the user would first tr ansmit the command byte 0x02 (hexadecimal) followed by the data 0x80000000 (hexadecimal). Similarly, to read a particular register the user must transmit the appro- priate read command and then acquire the 32 bits of data. Once a register is written to or read from, the serial port returns to the command mode. In addition to accessing the internal registers one at a time, the gain and offset registers as well as the channel setup registers can be accessed as arrays (i.e. the entire register set can be accessed with one command). In the CS5531/ 32, there are two gain and offset registers, and in the CS5533/34, there are four gain and offset registers. There are four chan- nel setup registers in all parts. As an example, to write 0x80000000 (hexadecimal ) to all four gain registers in the CS5533, the user would transmit the command 0x42 (hexadecimal) followed by four it- erations of 0x80000000 (hexadecimal), (i.e. 0x42 followed by 0x80000000, 0x80000000, 0x80000000, 0x80000000). The registers are writ- ten to or read from in sequential order (i.e, 1, fol- lowed by 2, 3, and 4). Once the registers are written to or read from, the serial port returns to the com- mand mode. 2.3. Configuration Register To ease the architectural design and simplify the serial interface, the conf iguration register is 32 long, however, only eleven of the 32 bits are used. The following sections detail the bits in the config- uration register. 2.3.1. Power Consumption The CS5531/32/33/34 acco mmodate three power consumption modes: norma l, standby, and sleep. The default mode, “normal mode”, is entered after power is applied. In this mode, the CS5531/32/33/34 devices typically consume 35 mW. The other two modes are referred to as the power-save modes. They power down most of the analog portion of the chip and stop filter convolu- tions. The power-save modes are entered whenever the power-down (P DW) bit of the configuration register is set to logic 1. The particular power-save mode entered depends on state of the PSS (Power Save Select) bit. If PSS is logic 0, the converter en- ters the standby mode reducing the power con- sumption to 4 mW. The standby mode leaves the oscillator and the on-chip bias generator for the an- alog portion of the chip active. This allows the con- verter to quickly return to the normal mode once PDW is set back to a logic 1. If PSS and PDW are both set to logic 1, the sleep mode is entered reduc- ing the consumed power to around 500 µW. Since this sleep mode disables the oscillator, approxi- mately a 20 ms oscillator start-up delay period is required before returning to the normal mode. If an external clock is used, there will be no delay. Fur- ther note that when the chips are used in the Gain = 1 mode, the PGIA is powered down. With the PGIA powered down, the power consumed in the normal power mode is reduced by approximate- ly 1/2. Power consumption in the sleep and standby modes is not affected by the amplifier setting. 2.3.2. System Reset Sequence The reset system (RS) bit permits the user to per- form a system reset. A system reset can be initiated at any time by writing a logic 1 to the RS bit in the configuration register. Af ter the RS bit has been set, the internal logic of the chip will be initialized to a reset state. The reset valid (RV) bit is set indi- cating that the internal logic was properly reset. The RV bit is cleared after the configuration regis-

24 DS289F5

after the RS bit has been cleared). nection diagram for the guard signal. VA+ and the VREF- pin can not go below VA-. established before the reference voltage. the output latch select (OLS) bit is logic 0 (default). latch bit settings in th e configuration register. Figure 8. Guard Signal Shielding Scheme

when performing conversions and calibrations.

60 Hz rejection when operating from a

1920, or 3840 Sps when using a 4.9152 MHz clock. scale linearly with the clock frequency that is used. Figure 9. Input Reference Model when VRS = 1 Figure 10. Input Reference Model when VRS = 0

26 DS289F5

2.3.9. Configuration Register Descriptions PSS (Power Save Select)[31] 0 Standby Mode (Oscillator active, allows quick power-up). 1 Sleep Mode (Oscillator inactive). PDW (Power Down Mode)[30]

0 Normal Mode

1 Activate the power save select mode. RS (Reset System)[29] 0 Normal Operation. 1 Activate a Reset cycle. See System Re set Sequence in the datasheet text. RV (Reset Valid)[28]

0 Normal Operation

1 System was reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read. IS (Input Short)[27]

0 Normal Input

1 All signal input pairs for each channel are disco nnected from the pins and shorted internally. GB (Guard Signal Bit)[26] 0 Normal Operation of A0 as an output latch. 1 A0’s output is modified to output the common mode output voltage of the instrumentation amplifier (typically 2.5 V). The output latch select bit is ignored when the guard buffer is activated. VRS (Voltage Reference Select)[25] 0 2.5 V < V REF ≤ [(VA+) - (VA-)] 11 V ≤ VREF ≤ 2.5V A1-A0 (Output Latch bits)[24:23] The latch bits (A0 and A1) will be set to the logic state of these bits upon command word execution if the output latch select bit (OLS) is set. Note that these logic outputs are powered from VA+ and VA-.

00 A0 = 0, A1 = 0

01 A0 = 0, A1 = 1

10 A0 = 1, A1 = 0

11 A0 = 1, A1 = 1

Output Latch Select, OLS[22] 0 When low, uses the Channel-Setup Regi ster as the source of A1 and A0. 1 When set, uses the Configuration Regi ster as the source of A1 and A0. NU (Not Used)[21] 0 Must always be logic 0. Reserved for future upgrades. Offset and Gain Select OGS[20] 0 Calibration registers used are based on th e CS1-CS0 bits of the referenced Setup. 1 Calibration registers used are based on th e OG1-OG0 bits of the referenced Setup. D31(MSB) D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 PSS PDW RS RV IS GB VRS A1 A0 OLS NU OGS FRS NU NU NU D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9 D 8D 7D 6D 5D 4D 3D 2D 1D 0 NU NU NU NU NU NU NU NU NU NU NU NU NU NU NU NU

Filter Rate Select, FRS[19] 0 Use the default output word rates. 1 Scale all output word rates and their correspondi ng filter characteristics by a factor of 5/6. NU (Not Used)[18:0] 0 Must always be logic 0. Reserved for future upgrades. 2.4. Setting up the CSRs for a Measurement The CS5531/32/33/34 have four channel-setup reg- isters (CSRs). Each CSR contains two 16-bit Setups which are programmed by the user to contain data conversion information such as: 1) which physical channel will be converted, 2) at what gain will the channel be converted, 3) at what word rate will the channel be converted, 4) will the output conversion be unipolar or bipolar, 5) what will be the state of the output latch during the conversion, 6) will the con- verter delay the start of a conversion to allow time for the output latch to settle before the conversion is begun, and 7) will the open circuit detect current source be activated for that Setup. In addition, when the OGS bit in the Configuration Register is set, the Setup selects which set of offset and gain registers to use when performing conve rsions or calibrations. Note that a particular physical input channel can be represented in more than one Setup with different output rates, gain ranges, etc. (i.e. each Setup is in- dependently defined). Refer to section 2.4.1 for more details about the Channel Setup Registers. Each 32-bit CSR is individually accessible and contains two 16-bit Setups. As an example, to con- figure Setup 1 in the CS5531/32/33/34 with the write individual channel- setup register command (0x05 hexadecimal), bits 31 to 16 of CSR 1 con- tains the information for Setup 1 and bits 15 to 0 contain the information for Setup 2. Note that while reading/writing CSRs, tw o Setups are accessed in pairs as a single 32-bit CSR register. Even if one of the Setups isn’t used, it must be written to or read. Examples detailing the power of the CSRs are pro- vided in section 2.6.3.

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2.4.1. Channel-Setup Register Descriptions CS1-CS0 (Channel Select Bits) [31:30] [15:14]

00 Select physical channel 1 (All devices)

01 Select physical channel 2 (All devices)

10 Select physical channel 3 (CS5533/34 only)

11 Select physical channel 4 (CS5533/34 only)

G2-G0 (Gain Bits) [29:27] [13:11] For VRS = 0, A = 2; For VRS = 1, A = 1; Bipolar input span is twice the unipolar input span. 000 Gain = 1, (Input Span = [(VR EF+)-(VREF-)]/1*A for unipolar). 001 Gain = 2, (Input Span = [(VR EF+)-(VREF-)]/2*A for unipolar). 010 Gain = 4, (Input Span = [(VR EF+)-(VREF-)]/4*A for unipolar). 011 Gain = 8, (Input Span = [(VR EF+)-(VREF-)]/8*A for unipolar). 100 Gain = 16, (Input Span = [(VREF+)-(VREF-)]/16*A for unipolar). 101 Gain = 32, (Input Span = [(VREF+)-(VREF-)]/32*A for unipolar). 110 Gain = 64, (Input Span = [(VREF+)-(VREF-)]/64*A for unipolar). WR3-WR0 (Word Rate) [26:23] [10:7] The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will scale linearly with the clock frequency used. The very first conversion using continuous conversion mode will last longer, as will conversions done with the single conversion mode. See the section on Performing Conversions and Tables 1 and 2 for more details. Bit WR (FRS = 0) WR (FRS = 1) 0000 120 Sps 100 Sps 0001 60 Sps 50 Sps 0010 30 Sps 25 Sps 0011 15 Sps 12.5 Sps 0100 7.5 Sps 6.25 Sps 1000 3840 Sps 3200 Sps 1001 1920 Sps 1600 Sps 1010 960 Sps 800 Sps 1011 480 Sps 400 Sps 1100 240 Sps 200 Sps All other combinations are not used. D31(MSB) D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 CS1 CS0 G2 G1 G0 WR3 WR2 WR1 WR0 U/B OL1 OL0 DT OCD OG1 OG0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CS1 CS0 G2 G1 G0 WR3 WR2 WR1 WR0 U/B OL1 OL0 DT OCD OG1 OG0 CSR #1 Setup 1 Bits <127:112> Setup 2 Bits <111:96> #4 Setup 7 Bits <31:16> Setup 8 Bits <15:0>

U/B (Unipolar / Bipolar) [22] [6] 0 Select Bipolar mode. 1 Select Unipolar mode. OL1-OL0 (Output Latch Bits) [21:20] [5:4] The latch bits will be set to the logic state of these bits upon command word execution when the output latch select bit (OLS) in the configuration register is logic 0. Note that the logic outputs on the chip are powered from VA+ and VA-. DT (Delay Time Bit) [19] [3] When set, the converter will wait for a delay time before starting a conversion. This allows settling time for A0 and A1 outputs before a conversion begins. The delay time will be 1280 MCLK cycles when FRS = 0, and 1536 MCLK cycles when FRS = 1. 0 Begin Conversions Immediately. 1 Wait 1280 MCLK cycles (FRS = 0) or 1536 MC LK cycles (FRS = 1) before starting conversion. OCD (Open Circuit Detect Bit) [18] [2] When set, this bit activates a 300 nA current source on the input channel (AIN+) selected by the channel select bits. Note that the 300nA current source is rated at 25°C. At -55°C, the current source doubles to approximately 600 nA. This feature is particularly useful in thermocouple applications when the user wants to drive a suspected open thermocouple lead to a supply rail. 0 Normal mode. 1 Activate current source. OG1-OG0 (Offset / Gain Register Pointer Bits) [17:16] [1:0] These bits are only used when OGS in the Configuration Register is set to ‘1’. They allow the user to select the offset and gain register to use while performing a conversion or calibration. When the OGS bit in the Configuration Register is set to ‘0’, the offset and gain register for the referenced physical channel (CS1- CS0 bits of the Setup) will be used.

00 Use offset and gain register from physical channel 1

01 Use offset and gain register from physical channel 2

10 Use offset and gain register from physical channel 3

11 Use offset and gain register from physical channel 4

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2.5. Calibration Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5531/32/33/34 offer both self-calibration and system calibration. Note: After the ADCs are re set, they are functional and can perform measurements without being calibrated (remember that the VRS bit in the configuration register must be properly configured). In this case, the converter will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words. Any initial offset and gain errors in the internal circuitry of the chip will remain. 2.5.1. Calibration Registers The CS5531/32/33/34 converters have an individu- al offset and gain regist er for each channel input. The gain and offset registers, which are used during both self and system calibration, are used to set the zero and gain slope of the converter’s transfer func- tion. As shown in Offset Register section, one LSB in the offset register is 1.835007966 x 2-24 propor- tion of the input span (bi polar span is 2 times the The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 pos- itive, 1 negative). Note that the magnitude of the offset that is trimmed from the input is mapped through the gain register. The converter can typi- cally trim ±100% of the input span. As shown in the Gain Register section, the gain register spans from 0 to (64 - 2 -24). The decimal equivalent meaning of the gain register is where the binary numbers have a value of either zero or one (b D29 is the binary value of bit D29). While gain register se ttings of up to 64 - 2 -24 are available, the gain regist er should never be set to values above 40. 2.5.2. Gain Register The gain register span is from 0 to (64-2-24). After Reset D24 is 1, all other bits are ‘0’. 2.5.3. Offset Register One LSB represents 1.835007966 X 2-24 proportion of the input span (bipolar span is 2 times unipolar span). Offset and data word bits align by MSB. After reset, all bits are ‘0’. The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0. Db D2925 bD2824 bD2723 … bD02 24– )+++ + bDi 2 24– i+() i 0= ∑== MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 NU NU 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 0000000100000000 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 222 2-23 2-24 0000000000000000 MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Sign 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 0000000000000000 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 NU NU NU NU NU NU NU NU 0000000000000000

2.5.4. Performing Calibrations To perform a calibration, the user must send a com- mand byte with its MSB = 1, its pointer bits (CSRP2-CSRP0) set to address the desired Setup to calibrate, and the appropriate calibration bits (CC2- CC0) set to choose the type of calibration to be per- formed. Note that calib ration assumes that the CSRs have been previously initialized because the information concerning th e physical channel, its filter rate, gain range, and polarity, comes from the channel-setup register addressed by the pointer bits in the command byte. Once the CSRs are initial- ized, a calibration can be performed with one com- mand byte. The length of time it takes to do a calibration is slightly less than the amount of time it takes to do a single conversion (see Table 1 for single conver- sion timing). Offset calibration takes 608 clock cy- cles less than a single conversion when FRS = 0, and 729 clock cycles less when FRS = 1. Gain cal- ibration takes 128 clock cy cles less than a single conversion when FRS = 0, and 153 clock cycles less when FRS = 1. Once a calibration cycle is complete, SDO falls and the results are automatically stored in either the gain or offset register for the physical channel be- ing calibrated when the OGS bit in the Configura- tion Register is set to ‘0’. If the OGS bit is set to ‘1’, the results will be stored in the register specified by the OG1-OG0 bits of the selected Setup. See the OGS bit description for more details (Section 2.3.7). SDO will remain low until the next com- mand word is begun. If additional calibrations are performed while referencing the same calibration registers, the last calibration results will replace the effects from the previous calibration as only one offset and gain register is available per physical channel. Only one calib ration is performed with each command byte. To calibrate all the channels, additional calibration commands are necessary. 2.5.5. Self-calibration The CS5531/32/33/34 offer both self-offset and self-gain calibrations. For the self-calibration of offset, the converters internally tie the inputs of the 1x amplifier together and routes them to the AIN- pin as shown in Figure 11. For accurate self calibra- tion of offset to occur, the AIN pins must be at the proper common-mode voltage as specified in the Analog Characteristics section. Self-offset calibra- tion uses the 1x gain amplifier, and is therefore not valid in the 2x-64x gain ranges. A self-offset calibra- tion of these gain ranges can be performed by setting the IS bit in the configuration register to a ‘1’, and performing a system offset calibration. The IS bit must be returned to ‘0’ afterwards for normal opera- tion of the device. For self calibration of ga in, the differential inputs of the modulator are c onnected to VREF+ and VREF- as shown in Figure 12. Self calibration of gain will not work with (VREF+ - VREF-) > 2.5V. Self calibration of gain is performed in the GAIN = 1x mode without regard to the setup regis- ter’s gain setting. Gain errors in the PGIA gain steps 2x to 64x are not calibrated as this would re- quire an accurate low-voltage source other than the reference voltage. A syst em calibration of gain should be performed if accurate gains are to be achieved on the ranges other than 1x, or when (VREF+ – VREF-) > 2.5V.

32 DS289F5

trates system offset calibration. to the System Calibration Specifications). should be calibrated at one of these lower rates. Figure 11. Self-calibration of Offset Figure 12. Self-calibration of Gain Figure 13. System Calibration of Offset Figure 14. System Calibration of Gain

crocontroller and the ADC, and may prematurely halt the calibration cycle. For maximum accuracy, calibrations should be per- formed for both offset and gain (selected by chang- ing the G2-G0 bits of the channel-setup registers). Note that only one gain range can be calibrated per physical channel when the OGS bit in the Configu- ration Register is set to ‘0’. Multiple gain ranges can be calibrated for a single channel by manipulat- ing the OGS bit and the OG 1-OG0 bits of the se- lected Setup (see Section 2.3.7 for more details). If factory calibration of the user’s system is per- formed using the system calibration capabilities of the CS5531/32/33/34, the offset and gain register contents can be read by the system microcontroller and recorded in non-volatile memory. These same calibration words can then be uploaded into the off- set and gain registers of the converter when power is first applied to the system, or when the gain range is changed. When the device is used without calibration, the uncalibrated gain accuracy is about ±1% and the gain tracking from range to range (2x to 64x) is ap- proximately ±0.3 percent. Note that the gain from the offset register to the output is 1.83007966 decimal, not 1. If a user wants to adjust the calibration coefficients externally, they will need to divide the information to be writ- ten to the offset regist er by the scale factor of 1.83007966. (This discussion assumes that the gain is also multiplied by the gain register before being applied to the output conversion words). 2.5.8. Limitations in Calibration Range System calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. For gain calibration, the full-scale input signal can be reduced to 3% of the nominal full- scale value. At this point, the gain register is ap- proximately equal to 33.33 (decimal). While the gain register can hold num bers all the way up to 64 – 2 -24, gain register settings above a decimal value of 40 should not be used. With the convert- er’s intrinsic gain error, this minimum full-scale in- put signal may be higher or lower. In defining the minimum Full Scale Calibration Range (FSCR) under Analog Characteristics, margin is retained to accommodate the intrinsic gain error. Inversely, the input full-scale signal can be increased to a point in which the modulator reaches its 1’s density limit of 86 percent, which under nominal conditions occurs when the full-scale input signal is 1.1 times the nominal full-scale value. With the chip’s intrinsic gain error, this maximum full-scale input signal maybe higher or lower. In defining the maximum FSCR, margin is again incorporated to accommo- date the intrinsic gain error. 2.6. Performing Conversions The CS5531/32/33/34 offers tw o distinctly differ- ent conversion modes. The three sections that fol- low detail the difference s and provide examples illustrating how to use the conversion modes with the channel-setup registers. 2.6.1. Single Conversion Mode Based on the information provided in the channel- setup registers (CSRs), after the user transmits the conversion command, a singl e, fully settled con- version is performed. The command byte includes a pointer address to the Se tup register to be used during the conversion. Once transmitted, the serial port enters data mode where it waits until the con- version is complete. When the conversion data is available, SDO falls to logic 0. Forty SCLKs are then needed to read the conversion data word. The first 8 SCLKs are used to clear the SDO flag. Dur- ing the first 8 SCLKs, SDI must be logic 0. The last 32 SCLKs are needed to read the conversion result. Note that the user is forc ed to read the conversion in single conversion mode as SDO will remain low (i.e. the serial port is in data mode) until SCLK transitions 40 times. After reading the data, the se-

34 DS289F5

between the SCLK input and the oscillator. Table 1. Conversion Timing – Single Mode

the address decoding of the pointer the bits. lowing physical channel order: 4, 1, 1, 2, 4, 3, 4, 4. the serial port returns to the command mode. Example 2: Continuous conversions using Setup 3. this example, Setup 3 points to physical channel 1. continuous conversion section. Table 2. Conversion Timing – Continuous Mode Table 3. Command Byte Pointer

000 CSR #1 1

001 CSR #1 2

010 CSR #2 3

011 CSR #2 4

100 CSR #3 5

101 CSR #3 6

110 CSR#4 7

111 CSR #4 8

36 DS289F5

settle full-scale step inputs. from the same oscillator source. CS5532 parts is shown in Figure 15. sion data register contai ns data monitoring flags. Output Descriptions section for more details. lar mode, and from -VFS to VFS in bipolar mode. Figure 15. Synchronizing Multiple ADCs

These bits depict the latest output conversion. These bits are masked logic zero. 0 Bit is clear when over-range condition has not occurred. mode) or when the input is more negative than the negative full scale (bipolar mode). These bits indicate which physical input channel was converted.

00 Physical Channel 1

01 Physical Channel 2

10 Physical Channel 3

11 Physical Channel 4

Table 4. Output Coding for 16-bit CS5531 and CS5533 Table 5. Output Coding for 24-bit CS5532 and CS5534

38 DS289F5

The converter’s digital fi lters scale with MCLK. Figure 16. Digital Filter Response (WR = 60 Sps) Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz Figure 18. 120 Sps Filter Phase Plot to 120 Hz Figure 19. Z-Transforms of Digital Filters

40 DS289F5

2 AIN1-

4.9152 MHz

20 AIN2+

19 AIN2-7 A08 A1

Figure 21. CS5532 Configured with a Single +5 V Supply

Figure 22. CS5532 Configured with ±2.5 V Analog Supplies Figure 23. CS5532 Configured with ±3 V Analog Supplies

42 DS289F5

Figure 24. CS5532 Configured for Thermocouple Measurement Figure 25. Bridge with Series Resistors

2.12. Getting Started This A/D converter has se veral features. From a software programmer’s prospective, what should be done first? To begin, a 4.9152 MHz or

4.096 MHz crystal takes a pproximately 20 ms to

start. To accommodate for this, it is recommended that a software delay of approximately 20 ms start the processor’s ADC init ialization code. Next, since the CS5531/32/33/34 do not provide a power- on-reset function, the user mu st first initialize the ADC to a known state. This is accomplished by re- setting the ADC’s serial po rt with the Serial Port Initialization sequence. This sequence resets the se- rial port to the command mode and is accomplished by transmitting 15 SYNC1 command bytes (0xFF hexadecimal), followed by one SYNC0 command (0xFE hexadecimal). Once the serial port of the ADC is in the command mode, the user must reset all the internal logic by performing a system reset sequence (see 2.3.2 System Reset Sequence). The next action is to initiali ze the voltage reference mode. The voltage reference select (VRS) bit in the configuration register mu st be set based upon the magnitude of the refere nce voltage between the VREF+ and the VREF- pins. After this, the channel-setup registers (CSRs) should be initialized, as these registers determine how cali- brations and conversions will be performed. Once the CSRs are initialized, the user has three options in calibrating the ADC: 1) don’t calibrate and use the default settings; 2) perform self or system calibra- tions; or 3) upload previously saved calibration re- sults to the offset and gain registers. At this point, the ADC is ready to perform conversions. 2.13. PCB Layout For optimal performance, the CS5531/32/33/34 should be placed entirely over an analog ground plane. All grounded pins on the ADC, including the DGND pin, should be connected to the analog ground plane that runs beneath the chip. In a split- plane system, place the analog-digital plane split immediately adjacent to the digital portion of the chip.

44 DS289F5

1. PIN DESCRIPTIONS Clock Generator OSC1; OSC2 - Master Clock. An inverting amplifier inside the chip is connected between these pins and can be used with a crystal to provide the master clock for the devic e. Alternatively, an external (CMOS compatible) clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock for the device. Control Pins and Serial Data I/O CS - Chip Select. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. 81 7 12 13 CS5533/4 VREF+ VREF- CS DGND SDO SERIAL DATA INPUT POSITIVE ANALOG POWER AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT DIFFERENTIAL ANALOG INPUT CHIP SELECT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA OUTMASTER CLOCK DIFFERENTIAL ANALOG INPUT AIN3+ AIN3- SDI VD+NEGATIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUTAIN2- AIN2+ VA- VA+ AIN4- AIN4+ OSC1 OSC2 AIN1- AIN1+ SCLK SERIAL CLOCK INPUT LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK 81 3 VREF+ VREF- SCLK CS DGND VA- VA+ AIN1- AIN1+ 10 11

12 SDO

LOGIC OUTPUT (ANALOG)/GUARD POSITIVE ANALOG POWER AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT DIFFERENTIAL ANALOG INPUT CHIP SELECT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA OUTMASTER CLOCK CS5531/2 DIFFERENTIAL ANALOG INPUT AIN2+ AIN2- SDI VD+NEGATIVE ANALOG POWER MASTER CLOCK LOGIC OUTPUT (ANALOG)

SDI - Serial Data Input. SDI is the input pin of the serial input port. Da ta will be input at a rate determined by SCLK. SDO - Serial Data Output. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input. A clock signal on this pin determines the input/ output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0 - Logic Output (Analog)/Guard , A1 - Logic Output (Analog). The logic states of A1-A0 mimic the OL1-OL0 bits in the selected Setup, or the A1-A0 bits in the Configuration Register, depending on the state of the OLS bit in the Configuration Register. Logic Output 0 = VA-, and Logic Output 1 = VA+. Alternately, A0 can be used as a guard drive for the instrumentation amplifier with proper setting of the GB bit in the Configuration Register. Measurement and Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input. Differential input pins into the device. VREF+, VREF- - Voltage Reference Input. Fully differential inputs which establish the voltage reference for the on-chip modulator. C1, C2 - Amplifie r Capacitor Inputs. Connections for the instrumentation amplifier’s capacitor. Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. VD+ - Positive Digital Power. Positive digital supply voltage (nominally +3.0 V or +5 V). VA- - Negative Analog Power. Negative analog supply voltage. DGND - Digital Ground. Digital Ground.

46 DS289F5

1. SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the ADC transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full-scale Error The deviation of the last code transition from the ideal {[(VREF+) - (VREF-)] - 3/2 LSB}. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs.

1. ORDERING INFORMATION 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Number Bits Channels Linearity Error (Max) Temperature Range Package CS5531-AS 16 2 ±0.003% -40 °C to +85°C 20-pin 0.2" Plastic SSOP CS5531-ASZ 16 2 ±0.003% -40 °C to +85°C 20-pin 0.2" Plastic SSOP , Lead Free CS5533-AS 16 4 ±0.003% -40 °C to +85°C 24-pin 0.2" Plastic SSOP CS5533-ASZ 16 4 ±0.003% -40 °C to +85°C 24-pin 0.2" Plastic SSOP , Lead Free CS5532-AS 24 2 ±0.003% -40 °C to +85°C 20-pin 0.2" Plastic SSOP CS5532-ASZ 24 2 ±0.003% -40 °C to +85°C 20-pin 0.2" Plastic SSOP , Lead Free CS5534-AS 24 4 ±0.003% -40 °C to +85°C 24-pin 0.2" Plastic SSOP CS5534-ASZ 24 4 ±0.003% -40 °C to +85°C 24-pin 0.2" Plastic SSOP , Lead Free Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5531-AS 240 °C 2 365 Days CS5531-ASZ 260 °C 3 7 Days CS5533-AS 240 °C 2 365 Days CS5533-ASZ 260 °C 3 7 Days CS5532-AS 240 °C 2 365 Days CS5532-ASZ 260 °C 3 7 Days CS5534-AS 240 °C 2 365 Days CS5534-ASZ 260 °C 3 7 Days

48 DS289F5

1. PACKAGE DRAWINGS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A -- 0.084 -- 2.13 A1 0.002 0.010 0.05 0.25 A2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.272 0.295 6.90 7.50 1 E 0.291 0.323 7.40 8.20 E1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 L 0.025 0.040 0.63 1.03 ∝ 0° 8° 0° 8°

20 PIN SSOP PACKAGE DRAWING

E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A -- 0.084 -- 2.13 A1 0.002 0.010 0.05 0.25 A2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.311 0.335 7.90 8.50 1 E 0.291 0.323 7.40 8.20 E1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 L 0.025 0.040 0.63 1.03 ∝ 0° 8° 0° 8°

24 PIN SSOP PACKAGE DRAWING

E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

50 DS289F5

PP1 Jan 1999 Initial release PP6 Sep 2004 Added lead-free devices F1 Jul 2005 Updated with most-current characterization data. F2 Oct 2005 Updated Input Noise Current spec ., Normal Mode Current spec., & note 9. F3 Nov 2006 Removed -BS devices from the data sheet. Added MSL data. F4 Apr 2007 Corrected noise spec. on p1 (12 nV/sqrtHz vs 6 nV/sqrtHz). F5 Oct 2008 Changed Input Current spec to 1200 pA. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.