WM8711BL

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Ultra-Small Audio DAC with Headphone Amplifier WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, December 2011, Rev 4.2 Copyright 2011 Wolfson Microelectronics plc

DESCRIPTION

The WM8711BL is an ultra-small, low power stereo DAC with an integrated headphone driver. It is designed specifically for portable audio systems requiring hi-fi stereo playback through headphones. Stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. Stereo audio outputs are buffered for driving headphones from a programmable volume control, line level outputs are also provided along with anti-thump mute and power up/down circuitry. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. The device is available in an ultra- small 24-lead QFN (4x4x0.9 mm Body) package. A USB clocking mode is provided where all audio rates can be derived from a single 12MHz or 24MHz MCLK, saving on the need for a PLL or multiple crystals.

FEATURES

 Audio Performance - DAC SNR 97dB (‘A’ weighted) at AVDD = 3.3V - DAC SNR 90dB (‘A’ weighted) at AVDD = 1.8V  Low Power Headphone Playback - Down to 6mW at 1.8V - 1.42 – 3.6V Digital Supply Operation - 1.8 – 3.6 V Analogue Supply Operation  DAC Sampling Frequency: 8kHz – 96kHz  2 or 3-Wire MPU Serial Control Interface  Programmable Audio Data Interface Modes - I S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths - Master or Slave Clocking Mode  Stereo Audio Outputs  Output Volume and Mute Controls  Highly Efficient Headphone Driver  24-lead QFN (4x4x0.9 mm) package

APPLICATIONS

 Multimedia Mobile Phones  Portable MP3 / CD Players BLOCK DIAGRAM XTI/MCLK XTO CLKOUT DIGITAL FILTERS CONTROL INTERFACE VOL/ MUTE VOL/ MUTE H/P DRIVER H/P DRIVER CSB RHPOUT LHPOUT ROUT LOUT DBVDD (3.3V) DGND +6 to -73dB 1 dB Steps HPVDD HPGND +6 to -73dB 1 dB Steps DCVDD (1.5V) DIGTAL AUDIO INTERFACE DACLRC BCLK DACDAT AVDD AGND VMID MUTE MUTE DAC DAC LLINEIN RLINEIN OSC CLKIN DIVIDER (Div x1, x2) CLKIN DIVIDER (Div x1, x2) WM8711B SDIN SCLK MODE

w PD, Rev 4.2, December 2011 244 TABLE OF CONTENTS

w PD, Rev 4.2, December 2011 343 PIN CONFIGURATION

ORDERING INFORMATION

RANGE AVDD RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8711CBLGEFL/V -25 to 85 o C 1.8 to 3.6V 24-lead QFN (Pb-free) MSL3 260 o C WM8711CBLGEFL/RV -25 to 85 o C 1.8 to 3.6V 24-lead QFN (Pb-free, tape and reel) MSL3 260 o C Note: Reel quantity = 3500

w PD, Rev 4.2, December 2011 444 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION

1 XTI/MCLK Digital Input Crystal Input or Master Clock Input (MCLK)

2 XTO Digital Output Crystal Output

3 DCVDD Supply Digital Core VDD

4 DGND Ground Digital GND

5 DBVDD Supply Digital Buffers VDD

6 CLKOUT Digital Output Buffered Clock Output

7 BCLK Digital Input/Output Digital Audio Bit Clock, Pull Down (see Note 1)

8 DACDAT Digital Input DAC Digital Audio Data Input

9 DACLRC Digital Input/Output DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)

10 HPVDD Supply Headphone VDD

11 LHPOUT Analogue Output Left Channel Headphone Output

12 RHPOUT Analogue Output Right Channel Headphone Output

13 HPGND Ground Headphone GND

14 LOUT Analogue Output Left Channel Line Output

15 ROUT Analogue Output Right Channel Line Output

16 AVDD Supply Analogue VDD

17 AGND Ground Analogue GND

18 VMID Analogue Output Mid-rail reference decoupling point

19 RLINEIN Analogue Input Right Channel Line Input (AC coupled)

20 LLINEIN Analogue Input Left Channel Line Input (AC coupled)

21 MODE Digital Input Control Interface Selection, Pull up (see Note 1)

22 CSB Digital Input 3-Wire MPU Chip Select/ 2-Wire MPU interface address

selection, active low, Pull up (see Note 1)

23 SDIN Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input

24 SCLK Digital Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input

Note: 1. Pull Up/Down only present when Control Regi ster Interface ACTIVE=0 to conserve power. 2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.

w PD, Rev 4.2, December 2011 543 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION MIN MAX Digital supply voltage -0.3V +3.63V Analogue supply voltage -0.3V +3.63V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -25C +85 C Storage temperature after soldering -65C +150 C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. 2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) 3. DCVDD must always be less than or equal to DBVDD RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.42 3.6 V Digital supply range (Buffer) DBVDD 1.8 3.6 V Analogue supply range AVDD, HPVDD 1.8 3.6 V Ground DGND,AGND,HPGND 0 V

w PD, Rev 4.2, December 2011 644

ELECTRICAL CHARACTERISTICS

AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 o C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels) Input LOW level VIL 0.3 x DBVDD V Input HIGH level VIH 0.7 x DBVDD V Output LOW VOL I OL = 1mA 0.1 x DBVDD V Output HIGH VOH I OH = -1mA 0.9 x DBVDD V Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off 0.9 V Hysteresis 0.3 V DCVDD Threshold Off -> On 0.6 V Analogue Reference Levels Reference voltage (VMID) VVMID AVDD/2 V Potential divider resistance RVMID 50k  Line Output for DAC Playback Only (Load = 10K. 50pF) 0dBFs Full scale output voltage At LINE outputs AVDD/3.3 Vrms Signal to Noise Ratio A-weighted (Note 1,2) SNR AVDD=HPVDD=3.3V 97 dB AVDD=HPVDD=1.8V 85 90 AVDD=HPVDD=1.8V, fs = 96kHz Dynamic Range (Note 2) DR A-weighted, -60dB full scale input 85 90 dB Total Harmonic Distortion THD AVDD=HPVDD=3.3V, 1kHz, 0dBFS -84 dB AVDD=HPVDD=1.8V, 1kHz, 0dBFs -81 -75 AVDD=HPVDD=1.8V 1kHz, -3dBFs -88 Power Supply Rejection Ratio PSRR 1kHz 100mVpp 50 dB 20Hz to 20kHz 100mVpp DAC channel separation 1kHz, 0dB signal 100 dB Analogue Line Input to Line Output (Load = 10k. 50pF, No Gain on Input ) Bypass Mode 0dB Full scale output voltage AVDD/3.3 Vrms Signal to Noise Ratio A-weighted (Note 1,2) SNR AVDD=HPVDD=3.3V 99 dB AVDD=HPVDD=1.8V 90 101 Total Harmonic Distortion THD AVDD=HPVDD=3.3V, 1kHz, 0dBFS -90 dB AVDD=HPVDD=1.8V , 1kHz, 0dB -93 -85

w PD, Rev 4.2, December 2011 743 Test Conditions AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 o C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Stereo Headphone Output 0dB Full scale output voltage AVDD/3.3 Vrms Max Output Power PO AVDD=HPVDD=3.3V, RL = 32 20 mW AVDD=HPVDD=1.8V, RL = 32 AVDD=HPVDD=1.8V, RL = 16 Signal to Noise Ratio A-weighted (Note 1,2) SNR AVDD=HPVDD=3.3V 96 dB AVDD=HPVDD=1.8V 80 86 Total Harmonic Distortion THD AVDD=HPVDD=3.3V, 1kHz, RL = 32 @ PO = 14mW rms 0.07 -63 dB AVDD=HPVDD=1.8V, 1kHz, RL = 32 @ PO = 4.5mW rms 0.05 -66 0.18 -55 Power Supply Rejection Ratio PSRR 1kHz 100mVpp 50 dB 20Hz to 20kHz 100mVpp Programmable Gain 1kHz -73 6 6 dB Programmable Gain Step Size 1kHz 1 dB Mute attenuation 1kHz, 0dB 80 dB TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rm s values, of (Noise + Distortion)/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.

w PD, Rev 4.2, December 2011 844 POWER CONSUMPTION MODE DESCRIPTION POWEROFF CLKOUTPD OSCPD OUTPD DACPD CURRENT CONSUMPTION TYPICAL AVDD HPVDD DCVDD DBVDD UNITS V I (mA) V I (mA) V I (mA) V I (mA) DAC Playback (USB master mode), oscillator and CLKOUT enabled, MCLK=12MHz, fs=48kHz 0 0 0 0 0 DAC Playback (slave mode using external

12.288 MCLK),

fs=48kHz 0 1 1 0 0 Standby No clocks Power Down No clocks Table 1 Current Consumption Examples Notes: 1. T A = +25 o C, fs = 48kHz. 2. All figures are quiescent, with no signal. 3. The power dissipation in the headphone itself not included in the above table.

w PD, Rev 4.2, December 2011 943 HEADPHONE SNR VS AVDD 24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=32Ohm; fs=44.1kHz; Output=-5dBFS (sine) SNR vs AVDD (DAC Playback to Headphone) 1.5 2 2.5 3 3.5 4 AVDD = HPVDD (V) SNR (dB) ANALOGUE SUPPLY CURRENT VS AVDD 24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=16Ohm; fs=44.1kHz; Output=quiescent Supply Current vs AVDD (DAC Playback to Headphone) 1.5 2.5 3.5 11 . 522 . 533 . 54 A VDD = HPVDD (V) IAVDD (mA)

w PD, Rev 4.2, December 2011 1244 Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 o C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 20 ns SCLK pulse width high tSCH 20 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns CSB pulse width low tCSL 20 ns CSB pulse width high tCSH 20 ns CSB rising to SCLK rising tCSS 20 ns SDIN SCLK t6 t2 t10 Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 o C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 0 526 kHz SCLK Low Pulsewidth t1 1.3 us SCLK High Pulsewidth t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 ns SDIN, SCLK Rise Time t6 300 ns SDIN, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t10 900 ns

w PD, Rev 4.2, December 2011 1343 DEVICE DESCRIPTION INTRODUCTION The WM8711BL is a low power audio DAC designed specifically for portable audio products. Its features, performance and low power consumption make it ideal for portable MP3, CD and mini-disc players. The WM8711BL includes line and headphone outputs from the on-board DAC, configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1 kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. The DAC outputs and Line Inputs (BYPASS) are available both at line level and through a headphone amplifier capable of efficiently driving low impedance headphones. The headphone output volume is adjustable in the analogue domain over a range of +6dB to –73dB and can be muted. The design of the WM8711BL minimises power consumption without compromising performance. It includes the ability to power off selective parts of the circuitry under software control, thus conserving power. Separate power save modes can be configured under software control including a standby and power off mode. Special techniques allow the audio to be muted and the dev ice safely placed into standby, sections of the device powered off, volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes may be used dynamically under software control, whenever playback is not required. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. The WM8711BL has two schemes to support the programmable sample rates: Normal industry standard 256/384fs sampling mode may be used. A special USB mode is included, where all audio sampling rates can be generated from a 12.00MHz USB clock. The digital filters used for playback are optimised for each sampling rate used. The digital audio interface can support a range of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The software control uses either a 2 or 3-wire MPU interface.

w PD, Rev 4.2, December 2011 1444 AUDIO SIGNAL PATH DAC FILTERS The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 6 illustrates the DAC digital filter path. FROM DIGITAL AUDIO INTERFACE MUTE DIGITAL INTERPOLATION FILTER TO LINE OUTPUTS DIGITAL DE_EMPHASIS DEEMP DACMU Figure 6 DAC Filter Schematic The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 2. The DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000101 Digital Audio Path Control 2:1 DEEMP[1:0] 00 De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable

3 DACMU 1 DAC Soft Mute Control

(Digital) 1 = Enable soft mute 0 = Disable soft mute Note 1 Table 2 DAC Software ControlNote 1 Not valid when SR[3:0] = 1111 or 0111. To ensure correct DACMU operation at fs = 88.2kHz, set SR[3:0] = 1000. To ensure correct DACMU operation at fs = 96kHz, set SR[3:0] = 0000.

w PD, Rev 4.2, December 2011 1644 The software control for the line outputs is shown in Table 3. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000100 Analogue Audio Path Control

3 BYPASS 1 Bypass Switch

1 = Enable Bypass 0 = Disable Bypass

4 DACSEL 0 DAC Select

1 = Select DAC 0 = Don’t select DAC Table 3 Output Software Control The recommended external components are shown in Figure 9. AGND AGND LINEOUT Figure 9 Line Outputs Application Drawing Recommended values are C1 = 10F, R1 = 47k, R2 = 100 C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output. HEADPHONE AMPLIFIER The WM8711BL has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed specifically for driving 16 or 32 ohm headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function.

w PD, Rev 4.2, December 2011 1743 The scheme of the circuit is shown in Figure 10. VMID HPOUT FROM DAC VIA LINEOUT Figure 10 Headphone Amplifier Schematic LHPOUT and RHPOUT volumes can be independently adjusted under software control using the LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB. The headphone outputs can be separately muted by writing codes less than 0110000 to LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN and RZCEN bits of the headphone output control register. Using these controls the volume control values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises any audible clicks and zipper noise as the gain values are changed or the device muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage input of more than approximately 20mV, then the gain will not be updated. This zero cross function is enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low will force a volume update, regardless of the DC level. LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively, the user can lock the two channels together, allowing both to be updated simultaneously, halving the number of serial writes required, provided that the same gain is needed for both channels. This is achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The corresponding effect on updating RLHPBOTH is also achieved.

w PD, Rev 4.2, December 2011 1844 The software control is given in Table 4. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000010 Left Headphone Out 6:0 LHPVOL[6:0] 1111001 ( 0dB ) Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE

7 LZCEN 0 Left Channel Zero Cross detect

1 = Enable 0 = Disable

8 LRHPBOTH 0 Left to Right Channel Headphone

Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load 0000011 Right Headphone Out 6:0 RHPVOL[7:0] 1111001 ( 0dB ) Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE

7 RZCEN 0 Right Channel Zero Cross Detect

1 = Enable 0 = Disable

8 RLHPBOTH 0 Right to Left Channel Headphone

Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[6:0] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load Table 4 Headphone Output Software Control

w PD, Rev 4.2, December 2011 1943 The recommended external components required to complete the application are shown in Figure 11. AGND AGND HPOUT Figure 11 Headphone Output Application Drawing Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from rising to a level that may damage the headphones. DEVICE OPERATION DEVICE RESETTING The WM8711BL contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001111 Reset Register 8:0 RESET not reset Reset Register Writing 00000000 to register resets device Table 5 Software Control of Reset When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 21).

w PD, Rev 4.2, December 2011 2044 CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. To allow WM8711BL to be used in a centrally clocked system, the WM8711BL is capable of either generating this system clock itself or receiving it from an external source as will be discussed. For applications where it is desirable that the WM8711BL is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input and XTO output pins (see CRYSTAL OSCILLATOR section). For applications where a component other than the WM8711BL will generate the reference clock, the external system Master Clock can be applied directly through the XTI/MCLK input pin with no software configuration necessary. Note that in this situation, the oscillator circuit of the WM8711BL can be safely powered down to conserve power (see POWER DOWN section) CORE CLOCK The WM8711BL DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 6 below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001000 Sampling Control

6 CLKIDIV2 0 Core Clock divider select

1 = Core Clock is MCLK divides by 2 0 = Core Clock is MCLK Table 6 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode. CRYSTAL OSCILLATOR The WM8711BL includes a crystal oscillator circuit that allows the audio system’s reference clock to be generated on the device. This is available to the rest of the audio system in buffered form on CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application circuit is shown Figure 12. XTI/MCLK XTO DGND DGND Cp Cp Figure 12 Crystal Oscillator Application Circuit The WM8711BL crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for high quality audio DACs, regardless of the converter architecture. The WM8711BL architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. In applications where there is more than one source for the master clock, it is recommended that the clock is generated by the WM8711BL to minimise such problems.

w PD, Rev 4.2, December 2011 2143 CLOCKOUT The Core Clock is internally buffered and made available externally to the audio system on the CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for driving external loads. There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to Electrical Characteristics. CLKOUT can also be divided by 2 under software control, refer to Table 7. Note that if CLKOUT is not required then the CLKOUT buffer on the WM8711BL can be safely powered down to conserve power (see POWER DOWN section). If the system architect has the choice between using F CLKOUT = F MCLK or FCLKOUT = F MCLK/2 in the interface, the latter is recommended to conserve power. When the divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical Characteristics for timing information. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001000 Sampling Control

7 CLKODIV2 0 CLKOUT divider select

1 = CLOCKOUT is Core Clock divided by 2 0 = CLOCKOUT is Core Clock Table 7 Programming CLKOUT CLKOUT is disabled and set low whenever the device is in reset. DIGITAL AUDIO INTERFACES WM8711BL may be operated in either one of the 4 offered audio interface modes. These are:  Right justified  Left justified  I S  DSP mode All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified mode where 32 bit data is not supported. The digital audio interface receives the digital audi o data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section

w PD, Rev 4.2, December 2011 2244 There are four digital audio interface formats accommodated by the WM8711BL. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a DACLRC transition. LEFT CHANNEL RIGHT CHANNEL DACLRC BCLK DACDAT 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB Figure 13 Left Justified Mode I S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC transition. LEFT CHANNEL RIGHT CHANNEL DACLRC BCLK DACDAT 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB

1 BCLK1 BCLK

correct number of BCLK cycles to suit the chosen word length. LRC. In these situations DACLRC can be made non 50:50. clocks per LRC period. Therefore the DACLRC output will have a mark space ratio of 187:188. zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs. Table 8. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the MSB relative to the rising edge of DACLRC.

w PD, Rev 4.2, December 2011 2543 To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is controlled via the software shown in Table 8. This is especially appropriate for DSP mode. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000111 Digital Audio Interface Format 1:0 FORMAT[1:0] 10 Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits

4 LRP 0 DACLRC phase control (in left, right

S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I S mode) or DSP mode A/B select ( in DSP mode only) 1 = MSB is available on 2 nd BCLK rising edge after DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge

5 LRSWAP 0 DAC Left Right Clock Swap

1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right

6 MS 0 Master Slave Mode Control

1 = Enable Master Mode 0 = Enable Slave Mode

7 BCLKINV 0 Bit Clock Invert

1 = Invert BCLK 0 = Don’t invert BCLK Table 8 Digital Audio Interface Control Note: If right justified 32 bit mode is selected then the WM8711BL defaults to 24 bits.

w PD, Rev 4.2, December 2011 2644 MASTER AND SLAVE MODE OPERATION The WM8711BL can be configured as either a master or slave mode device. As a master mode device the WM8711BL controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8711BL responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 9. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000111 Digital Audio Interface Format 1 = Enable Master Mode 0 = Enable Slave Mode Table 9 Programming Master/Slave Modes As a master mode device the WM8711BL controls the sequencing of data transfer (DACDAT) and output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 18. DACDAT is always an input to the WM8711BL independent of master or slave mode. BCLK DACDAT DACLRCWM8711 DAC DSP DECODER Figure 18 Master Mode As a slave device the WM8711BL sequences the data transfer (DACDAT) over the digital audio interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 19. BCLK DACDAT DACLRCWM8711 DAC DSP DECODER Figure 19 Slave Mode Note that the WM8711BL relies on controlled phase relationships between audio interface BCLK, DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section for detailed information.

w PD, Rev 4.2, December 2011 2743 AUDIO DATA SAMPLING RATES The WM8711BL provides for two modes of operation (normal and USB) to generate the required DAC sampling rates. Normal and USB modes are programmed under software control according to the table below. In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the sample rate control register setting. The WM8711BL can support sample rates from 8ks/s up to 96ks/s. In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8711BL can be directly used within such systems. WM8711BL can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001000 Sampling Control

0 USB/

0 Mode Select

1 = USB mode (250/272fs) 0 = Normal mode (256/384fs)

1 BOSR 0 Base Over-Sampling Rate

0 = 250fs 1 = 272fs Normal Mode 96/88.2 kHz 0 = 256fs 0 = 128fs 1 = 384fs 1 = 192fs 5:2 SR[3:0] 0000 DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Table 10 Sample Rate Control NORMAL MODE SAMPLE RATES In normal mode MCLK is set up according to the desired sample rates of the DAC. For DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.

w PD, Rev 4.2, December 2011 2844 The table below should be used to set up the device to work with the various sample rate combinations. Refer to Digital Filter Characteris tics section for an explanation of the different filter types. SAMPLING RATE MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE DAC kHz MHz BOSR SR3 SR2 SR1 SR0 48 12.288 0 (256fs) 0 0 0 0 1 18.432 1 (384fs) 0 0 0 0 8 12.288 0 (256fs) 0 0 0 1 1 18.432 1 (384fs) 0 0 0 1 32 12.288 0 (256fs) 0 1 1 0 1 18.432 1 (384fs) 0 1 1 0 96 12.288 0 (128fs) 0 1 1 1 2 18.432 1 (192fs) 0 1 1 1 44.1 11.2896 0 (256fs) 1 0 0 0 1 16.9344 1 (384fs) 1 0 0 0 (Note 1) 11.2896 0 (256fs) 1 0 0 1 1 16.9344 1 (384fs) 1 0 0 1 88.2 11.2896 0 (128fs) 1 1 1 1 2 16.9344 1 (192fs) 1 1 1 1 Table 11 Normal Mode Sample Rate Look-up Table Notes: 1. 8k not exact, actual = 8.018kHz 2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711BL digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate required by the DAC. The exact sample rates achieved are defined by the relationships in Table 12 below. TARGET SAMPLING RATE ACTUAL SAMPLING RATE BOSR=0 BOSR=1 MCLK=12.288 MCLK=11.2896 MCLK=18.432 MCLK=16.9344 kHz kHz kHz kHz kHz 8 8 8.018 8 8.018 (12.288MHz/256) x 1/6 (11.2896MHz/256) x 2/11 (18.432MHz/384) x 1/6 (16.9344MHz/384) x 2/11 32 32 not available 32 not available (12.288MHz/256) x 2/3 (18.432MHz/384) x 2/3 44.1 not available 44.1 not available 44.1 11.2896MHz/256 16.9344MHz /384 48 48 not available 48 not available 12.288MHz/256 18.432MHz/384 88.2 not available 88.2 not available 88.2 (11.2896MHz/256) x 2 (16.9344MHz /384) x 2 96 96 not available 96 not available (12.288MHz/256) x 2 (18.432MHz/384) x 2 Table 12 Normal Mode Actual Sample Rates

w PD, Rev 4.2, December 2011 2943 128/192FS NORMAL MODE The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8711BL is also capable of being clocked from a 128/192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE DAC kHz MHz BOSR SR3 SR2 SR1 SR0 48 6.144 0 0 1 1 1 2 9.216 1 0 1 1 1 44.1 5.6448 0 1 1 1 1 2 8.4672 1 1 1 1 1 Table 13 128/192fs Normal Mode Sample Rate Look-up Table 512/768FS NORMAL MODE 512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the device otherwise operates as in Table 9 but with MCLK at twice the specified rate. USB MODE SAMPLE RATES In USB mode the MCLK input is 12MHz only. SAMPLING RATE MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE DAC kHz MHz BOSR SR3 SR2 SR1 SR0 48 12.000 0 0 0 0 0 0 44.1 (Note 2) 12.000 1 1 0 0 0 1 8 12.000 0 0 0 0 1 0 (Note 1) 12.000 1 1 0 0 1 1 32 12.000 0 0 1 1 0 0 96 12.000 0 0 1 1 1 3 88.2 (Note 3) 12.000 1 1 1 1 1 2 Table 14 USB Mode Sample Rate Look-Up Table Notes: 1. 8k not exact, actual = 8.021kHz 2. 44.1k not exact, actual = 44.118kHz 3. 88.1k not exact, actual = 88.235kHz 4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711BL digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250Fs, with BOSR = 1, the base over-sampling rate is defined at 272Fs. This can be used to determine the actual audio sampling rate required by the DAC.

w PD, Rev 4.2, December 2011 3044 The exact sample rates supported for all combinations are defined by the relationships in Table 15 below. TARGET SAMPLING RATE ACTUAL SAMPLING RATE BOSR=0 ( 250FS) BOSR=1 (272FS) kHz kHz kHz 8 8 8.021 12MHz/(250 x 48/8) 12MHz/(272 x 11/2) 32 32 not available 12MHz/(250 x 48/32) 44.1 not available 44.117 12MHz/272 48 48 not available 12MHz/250 88.2 not available 88.235 12MHz/136 96 96 not available 12MHz/125 Table 15 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO INTERFACE To prevent any communication problems from arising across the Digital Audio Interface is disabled (tristate with weak 100k pulldown) at power on. Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001001 Active Control

0 ACTIVE 0 Activate Interface

1 = Active 0 = Inactive Table 16 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set. SOFTWARE CONTROL INTERFACE The software control interface may be operated using either a 3-wire or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses. SELECTION OF SERIAL CONTROL MODE The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin. MODE INTERFACE FORMAT 0 2 wire 1 3 wire Table 17 Control Interface Mode Selection

w PD, Rev 4.2, December 2011 3244 Once the WM8711BL has acknowledged a correct address, the controller will send eight data bits (bits B[15]-B[8]). WM8711BL will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711BL will then acknowledge again by pulling SDIN low. A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. After receiving a complete address and data sequence the WM8711BL returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits. POWER DOWN MODES The WM8711BL contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000110 Power Down Control

3 DACPD 1 DAC Power Down

1 = Enable Power Down 0 = Disable Power Down

4 OUTPD 1 Line Output Power Down

1 = Enable Power Down 0 = Disable Power Down

5 OSCPD 0 Oscillator Power Down

1 = Enable Power Down 0 = Disable Power Down

6 CLKOUTPD 0 CLKOUT Power Down

1 = Enable Power Down 0 = Disable Power Down

7 POWEROFF 1 Power Off Device

1 = Device Power Off 0 = Device Power On Table 19 Power Conservation Modes Software Control The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used.

w PD, Rev 4.2, December 2011 3343 DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops will result unless the following guidelines are followed. In order to prevent pops, the DAC should first be soft-muted (DACMU), the output should then be de-selected from the line and headphone output (DACSEL), then the DAC powered down (DACPD). Th is is of use when the device enters Pause or Stop modes. During DACPD the digital audio interface is remains active. OUTPD: Powers down the Line and Headphone Outputs. If this is done dynamically then audible pops may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters Record, Pause or Stop modes. The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 20. POWER OFF CLKOUTPD OSCPD OUTPD DACPD 0 0 0 1 1 STANDBY, but with Crystal Oscillator OS and CLKOUT available 0 1 0 1 1 STANDBY, but with Crystal Oscillator OS available, CLKOUT not-available 0 1 1 1 1 STANDBY, Crystal oscillator and CLKOUT not-available. Table 20 Standby Mode In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode. The device can be powered off by writing to the POWEROFF bit of the Power Down register. In POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. Refer to Table 21. POWER OFF CLKOUTPD OSCPD OUTPD DACPD 1 0 0 X 1 POWEROFF, but with Crystal Oscillator OS and CLKOUT available 1 1 0 X 1 POWEROFF, but with Crystal Oscillator OS available, CLKOUT not-available 1 1 1 X 1 POWEROFF, Crystal oscillator and CLKOUT not-available. Table 21 Poweroff Mode

w PD, Rev 4.2, December 2011 3444 REGISTER MAP The complete register map is shown in Table 23. The detailed description can be found in the relevant text of the device description. There are 8 r egisters with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER B B B B B B B B8 B7 B6 B5 B4 B3 B2 B1 B0 R2 (04h) 0 0 0 0 0 1 0 LRHP BOTH LZCEN LHPVOL R3 (06h) 0 0 0 0 0 1 1 RLHP BOTH RZCEN RHPVOL R4 (08h) 0 0 0 0 1 0 0 0 0 0 0 DAC SEL BYPASS 0 0 0 R5 (0Ah) 0 0 0 0 1 0 1 0 0 0 0 0 DAC MU DEEMPH 0 R6 (0Ch) 0 0 0 0 1 1 0 0 POWER OFF CLK OUTPD OSCPD OUTPD DACPD 1 1 1 R7 (0Eh) 0 0 0 0 1 1 1 0 BCLK INV MS LR SWAP LRP IWL FORMAT R8 (10h) 0 0 0 1 0 0 0 0 CLK0 DIV2 CLKI DIV2 SR BOSR USB/ NORM R9 (12h) 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 ACTIVE R15(1Eh) 0 0 0 1 1 1 1 RESET ADDRESS DATA Table 22 Mapping of Program Registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000010 Left Headphone Out 6:0 LHPVOL [6:0] 1111001 ( 0dB ) Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE

7 LZCEN 0 Left Channel Zero Cross detect Enable

1 = Enable 0 = Disable Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load

w PD, Rev 4.2, December 2011 3543 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000011 Right Headphone Out 6:0 RHPVOL [6:0] 1111001 ( 0dB ) Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE 1 = Enable 0 = Disable Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[60] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load 0000100 Audio Path Control 1 = Enable Bypass 0 = Disable Bypass

4 DACSEL 0 DAC Select (Analogue)

1 =Select DAC 0 = Don’t select DAC 0000101 Digital Audio Path Control 2:1 DEEMP[1:0] 00 De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable

3 DACMU 1 DAC Soft Mute Control (Digital)

1 = Enable soft mute 0 = Disable soft mute See note 1, page 14 0000110 Power Down Control 1 = Enable Power Down 0 = Disable Power Down

4 OUTPD 1 Outputs Power Down

1 = Enable Power Down 0 = Disable Power Down 1 = Enable Power Down 0 = Disable Power Down 1 = Enable Power Down 0 = Disable Power Down

7 POWEROFF 1 POWEROFF mode

1 = Enable POWEROFF 0 = Disable POWEROFF

w PD, Rev 4.2, December 2011 3644 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000111 Digital Audio Interface Format 1:0 FORMAT[1:0] 10 Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits

4 LRP 0 DACLRC phase control (in left, right or

I S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I S mode) or DSP mode A/B select ( in DSP mode only) 1 = Mode A (MSB is available on 2 nd BCLK rising edge after DACLRC rising edge) 0 = Mode B (MSB is available on 1st BCLK rising edge after DACLRC rising edge) 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right 1 = Enable Master Mode 0 = Enable Slave Mode 1 = Invert BCLK 0 = Don’t invert BCLK

w PD, Rev 4.2, December 2011 3743 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001000 Sampling Control 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) 0 = 250fs 1 = 272fs 5:2 SR[3:0] 0000 DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Normal Mode 0 = 256fs 1 = 384fs 1 = Core Clock is MCLK divide by 2 0 = Core Clock is MCLK 1 = CLOCKOUT is MCLK divide by 2 0 = CLOCKOUT is MCLK 0001001 Active Control 1 = Active 0 = Inactive 0001111 Reset Register 8:0 RESET not reset Reset Register Writing 00000000 to register resets device Table 23 Register Map Description Note: All other bits not explicitly defined in the register table should be set to zero unless specified otherwise. DIGITAL FILTER CHARACTERISTICS The DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter Type 0 (USB mode, 250fs operation) Passband +/- 0.03dB 0 0.416fs -6dB 0.5fs Passband Ripple +/-0.03 dB Stopband 0.584fs Stopband Attenuation f > 0.584fs -50 dB DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) Passband +/- 0.03dB 0 0.4535fs -6dB 0.5fs Passband Ripple +/- 0.03 dB Stopband 0.5465fs Stopband Attenuation f > 0.5465fs -50 dB Table 24 Digital Filter Characteristics

w PD, Rev 4.2, December 2011 4143 RECOMMENDED EXTERNAL COMPONENTS Figure 36 External Components Diagram WM8711BL DAC RHPOUT VMID LOUT 47k 100 LHPOUT 47k220F AVDD AGND 3.3V HPVDD HPGND 3.3V ROUT 47k 100 47k220F 0.1F 10F DACLRC DACDAT DBVDD DCVDD 3.3V DGND 1.5V - 3.3V BCLK Audio Serial Data I/F 3-wire or 2-wire MPU Interface 3-wire Interface 2-wire Interface SDIN CSB SCLK MODE 10F0 . 1 F 10k 3.3V DGND 10F 10F CLKOUT 100 CpCp XTI/MCLK XTO LLINEIN RLINEIN 0.1F 1F 1F Note 1. Where possible, it is recommended that NPO or COG type capacitors should be used for best performance. 2. *Ground Paddle in centre of QFN package back side. 3. X1 should have a CL of around 12pF and Cp should be around 15pF. 5.6k 220pF 5.6k 1M  VREF 5.6k 220pF 5.6k 1M  VREF 1F 1F *GND_PADDLE

w PD, Rev 4.2, December 2011 4244 PACKAGE DIMENSIONS DM102.CFL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH INDEX AREA (D/2 X E/2) TOP VIEW D E NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-8. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. G T H W b Exposed lead Half etch tie bar Dimensions (mm)Symbols MIN NOM MAX NOTE A 0.80 0.85 0.90 0.050.0350

0.203 REF

b D E e L 0.300.20

4.00 BSC

2.602.502.40

0.50 BSC

0.35 0.40 0.45 2.602.502.40 0.10 aaa bbb ccc REF: 0.10 0.10 JEDEC, MO-220, VARIATION VGGD-8. Tolerances of Form and Position 0.25 H 0.10 0.20G T 0.103 W 0.15 DETAIL 1 DETAIL 3 2419 e b7 1 BCbbb M A BOTTOM VIEW Caaa2 X Caaa2 X C SEATING PLANE C0.08 Cccc A SIDE VIEW EXPOSED GROUND PADDLE DETAIL 1 0.30mm 45° EXPOSED GROUND PADDLE SEE DETAIL 2 L e Datum DETAIL 2 Terminal Tip e/2 1 M M DETAIL 3

w PD, Rev 4.2, December 2011 4343 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House

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w PD, Rev 4.2, December 2011 4444

REVISION HISTORY

DATE REV ORIGINATOR CHANGES 20/10/11 4.2 JMacD Order codes changed from WM8711BLGEFL/V and WM8711BLGEFL/RV to WM8711CBLGEFL/V and WM8711CBLGEFL/RV to reflect change to copper wire bonding. 20/10/11 4.2 JMacD Package Diagram changed to DM102.C.