WM8281

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Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation http://www.cirrus.com Copyright  Cirrus Logic, Inc., 2014–2016 (All Rights Reserved) Rev 4.0 MAR ‘16 WM8281

DESCRIPTION

The WM8281 is a highly-integrated low-power audio system for smartphones, tablets and other portable audio devices. It combines a n advanced DSP feature set with a flexible, high- performance audio hub CODEC. The WM8281 digital core combines a quad -core, 600MMAC DSP system with a variety of power -efficient fixed -function audio processing blocks. The programmable DSP cores support advanced audio features, including multi-mic wideband noise reduction, high -performance acoustic echo cancellation (AEC), stereo ambient noise cancellation (ANC), speech enhancement, advanced media enhancement, and many more. The DSP cores are supported by a fully -flexible, all -digital mixing and routing engine with sample rate converters, for wide use-case flexibility. A SLIMbus ® interface supports multi -channel audio paths and host control register access. Multiple sample rates are supported concurrently via the SLIMbus interface. Three further digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial interface formats. Automatic sample rate detection enables seamless wideband/narrowband voice call handover. Three stereo headphone drivers each provide stereo ground - referenced or mono BTL outputs. 110dB SNR, and noise levels as low as 0.8μVRMS, offer hi-fi quality line or headphone output. The WM8281 also features a stereo pair of 2W Class-D outputs and four channels of stereo PDM output. A signal gener ator for controlling haptics devices is included; vibe actuators can connect directly to the Class -D speaker output, or via an external driver on the PDM output interface. All inputs, outputs and system interfaces can function concurrently. The WM8281 supports up to eight microphone inputs, (up to six analogue, or up to eight PDM digital, or combinations of each). Microphone activity detection with interrupt is available. A smart accessory interface supports most standard 3.5mm accessories. Impedance sensing and measurement is provided for external accessory and push-button detection. The WM8281 power, clocking and output driver architectures are all designed to maximise battery life in voice, music and standby modes. Low-power ‘Sleep’ is supported, with configurable wake-up events. The WM8281 is powered from a 1.8V external supply. A separate supply is required for the Class D speaker drivers (typically direct connection to 4.2V battery). Two integrated FLLs provide support for a wide range of system clock frequencies. The WM8281 is configured using the I2C, SPI™ or SLIMbus interfaces. The fully -differential internal analogue architecture, minimal analogue signal paths and on - chip RF noise fil ters ensure a very high degree of noise immunity.

FEATURES

 600 MIPS, 600MMAC multi-core audio-signal processor  Programmable wideband, multi-mic audio processing - Cirrus Logic® stereo adaptive ambient noise cancellation - Transmit-path noise reduction and echo cancellation - Wind noise, sidetone and other programmable filters - Dynamic Range Control, Fully parametric EQs - Multiband Compression, Virtual Surround Sound  Multi-channel asynchronous sample rate conversion  Integrated 6/8 channel 24-bit hi-fi audio hub CODEC - 6 ADCs, 100dB SNR microphone input (48kHz) - 8 DACs, 121dB SNR headphone playback (48kHz), (48kHz, eDRE software enabled)  Audio inputs - Up to 6 analogue or 8 digital microphone inputs - Single-ended or differential mic/line inputs  Multi-purpose headphone / earpiece / line output drivers - 3 stereo output paths - 33mW into 32Ω load at 1% THD+N - 100mW into 16Ω BTL load at 5% THD+N - 4mW typical headphone playback power consumption - Pop suppression functions - 0.8µVRMS noise floor (A-weighted)  Stereo (2 x 2W) Class D speaker output drivers - Direct drive of external haptics vibe actuators  Four-channel digital speaker (PDM) interface  SLIMbus audio and control interface  3 full digital audio interfaces - Standard sample rates from 4kHz up to 192kHz - Ultrasonic accessory function support - TDM support on all AIFs - Multi-channel input/output on AIF1 and AIF2 - Stereo input/output on AIF3  Flexible clocking, derived from MCLKn, BCLKn , LRCLKn or SLIMbus  2 low-power FLLs support reference clocks down to 32kHz  Advanced accessory detection functions - Low-power standby mode and configurable wake-up  Configurable functions on 5 GPIO pins  Integrated LDO regulators and charge pumps  Small W-CSP package, 0.4mm pitch

APPLICATIONS

 Smartphones, tablets, and multimedia handsets

2 Rev 4.0 BLOCK DIAGRAM Digital Core Stereo Adaptive RX ANC RX Speech Clarity Advanced Multi-Mic TX Noise Reduction Advanced Multi-Mic Acoustic Echo Cancellation Wind Noise Detection Multi-band Compression Virtual Surround Sound (VSS) 5-Band Equaliser (EQ) Dynamic Range Control (DRC) Low Pass / High Pass Filter (LHPF) Asynchronous Sample Rate Conversion Automatic Sample Rate Detection Advanced Programmable Multi-Core DSP Tone Generator Noise Generator PWM Signal Generator Haptic Control Signal Generator Digital Audio Interface AIF1 AIF1TXDAT AIF1RXDAT AIF1BCLK AIF1LRCLK Digital Audio Interface AIF2 AIF2TXDAT AIF2RXDAT AIF2BCLK AIF2LRCLK Digital Audio Interface AIF3 AIF3TXDAT AIF3RXDAT AIF3BCLK AIF3LRCLK Ambient Noise Cancellation (ANC) Stereo Anti-Noise outputs ADC ADC Digital Mic Interface ADC ADC Digital Mic Interface ADC ADC Digital Mic Interface IN1LN/DMICCLK1 IN1LP IN1RN/DMICDAT1 IN1RP IN2LN/DMICCLK IN2LP IN2RN/DMICDAT2 IN2RP IN3LN/DMICCLK3 IN3LP IN3RN/DMICDAT3 IN3RP SPKOUTLP SPKOUTLN SPKOUTRP SPKOUTRN DAC DAC SPKCLK2 SPKDAT2 SPKCLK1 SPKDAT1 HPOUT3L HPOUT3R DAC DAC HPOUT2L HPOUT2R DAC DAC HPOUT1L HPOUT1R DAC DAC HPOUT1FB1/MICDET2 HPOUT2FB HPOUT3FB SPKGNDRN SPKGNDRP SPKVDDR SPKGNDLN MICBIAS Generators Charge Pump 2 Charge Pump 1LDO 2 MICBIAS1 MICBIAS2 CP2CA CP2CB CP1C1A CP1C1B CP1VOUT1P CP1VOUT1N MICBIAS3 CPVDD CPGND CP2VOUT MICVDD LDO 1 LDOENA LDOVDD LDOVOUT DBVDD1 DGND RESET JTAG Test Access TDO TDI TCK TMS DBVDD2 DBVDD3 DCVDD Reference Generator AVDD AGND VREFC SLIM Bus Interface SLIMCLK SLIMDAT MICDET1/HPOUT1FB2 HPDETL HPDETR External Accessory Detect JACKDET IRQ CIF1SDA/CIF1MOSI CIF1SCLK CIF1ADDR/CIF1SS CIF1MODE CIF2SCLK CIF2SDA Control Interface DMICCLK4 DMICDAT4 Digital Mic Interface PDM Driver PDM Driver GPIO1 GPIO2 GPIO3 CIF1MISO/GPIO4 GPIO5 GPIO CP1C2A CP1C2B CP1VOUT2P CP1VOUT2N TRST SPKTST1 SPKTST2 SUBGND Stereo ANC inputs AIFnBCLK AIFnLRCLK SLIMCLK MCLK2 MCLK1 SYSCLK Clocking Control 2 x FLL ASYNCCLK AEC (Echo Cancellation) Loopback GPSWA GPSWB SPKGNDLP SPKVDDL

Rev 4.0 3 TABLE OF CONTENTS

4 Rev 4.0

Rev 4.0 5

6 Rev 4.0

Rev 4.0 7 PIN CONFIGURATION A F E D C B 65432 987 G H TOP VIEW – WM8281 J K L 121110 13 14 MICBIAS2 MICVDD MICBIAS3 MICBIAS1 NC CP1C1B CP1C2A CP1C1AIN1RP IN1LN/ DMICCLK1 IN3LN/ DMICCLK3 CP1C2BCPVDD IN2LP IN2LN/ DMICCLK2 IN3LP CPGNDIN1LP IN2RPIN3RP NCNC HPOUT3R HPOUT3L CP1VOUT2P CP1VOUT2N HPOUT3FBCP1VOUT1P CP1VOUT1N NC HPOUT2L HPOUT1RHPOUT2R HPOUT2FBNC HPDETR NC GPSWA HPOUT1L HPDETL JACKDET VREFC AVDD1 TRST IN3RN/ DMICDAT3 DMICDAT4 IN2RN/ DMICDAT2 AGND1 SUBGND TCKTDITMS CIF1MODE NC GPSWB IRQ RESET CIF1ADDR/ CIF1SS AGND2 LDOENA GPIO5 NC SPKTST1 SPKVDDR GPIO3 NC NC NC SPKTST2 AIF3TXDAT NCNC AIF2RXDAT SPKDAT2 SPKCLK1SPKCLK2 AIF1TXDAT CIF1SDA/ CIF1MOSI GPIO1 AIF1LRCLK CIF1MISO/ GPIO4 CIF1SCLK AIF1RXDAT AIF1BCLK SPKVDDR SPKVDDL SPKGNDLPSPKOUTRP SPKVDDLSPKOUTLP SPKGNDRN SPKGNDRP SPKOUTRN SPKOUTLNSPKGNDLN AIF2TXDAT AIF2BCLK DBVDD3 AIF3BCLK DGNDDCVDD TDO SLIMDATCIF2SDA DBVDD2DGND CIF2SCLK MCLK1 SLIMCLK MICDET1/ HPOUT1FB2 HPOUT1FB1/ MICDET2 AVDD2 SUBGND LDOVOUT LDOVDD MCLK2 DGND DCVDD DBVDD1 DGND NC IN1RN/ DMICDAT1 CP2CBCP2VOUT NC NCCP2CA NC DMICCLK4 NC NC AIF3RXDAT NCNC AIF3LRCLK AIF2LRCLK SPKDAT1 GPIO2

8 Rev 4.0

ORDERING INFORMATION

WM8281ECS/R -40C to +85C W-CSP (Pb-free, Tape and reel) MSL1 260C Note: Reel quantity = 7000 PIN DESCRIPTION A description of each pin on the WM8281 is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated. PIN NO NAME TYPE DESCRIPTION E2 AGND1 Supply Analogue ground (Return path for AVDD1) D13 AGND2 Supply Analogue ground (Return path for AVDD2) J13 AIF1BCLK Digital Input / Output Audio interface 1 bit clock H13 AIF1RXDAT Digital Input Audio interface 1 RX digital audio data H12 AIF1LRCLK Digital Input / Output Audio interface 1 left / right clock J11 AIF1TXDAT Digital Output Audio interface 1 TX digital audio data K9 AIF2BCLK Digital Input / Output Audio interface 2 bit clock J8 AIF2RXDAT Digital Input Audio interface 2 RX digital audio data J9 AIF2LRCLK Digital Input / Output Audio interface 2 left / right clock K8 AIF2TXDAT Digital Output Audio interface 2 TX digital audio data K7 AIF3BCLK Digital Input / Output Audio interface 3 bit clock H4 AIF3RXDAT Digital Input Audio interface 3 RXdigital audio data J7 AIF3LRCLK Digital Input / Output Audio interface 3 left / right clock H5 AIF3TXDAT Digital Output Audio interface 3 TX digital audio data E1 AVDD1 Supply Analogue supply C14 AVDD2 Supply Analogue supply F12 CIF1ADDR/ Digital Input Control interface 1 (I2C) address select / Control interface 1 (SPI) Slave Select (SS) J12 CIF1MISO/ GPIO4 Digital Input / Output Control interface 1 Master In Slave Out data / General Purpose pin GPIO4. The CIFMISO configuration is selectable CMOS or ‘Wired OR’. The GPIO4 output is selectable CMOS or Open Drain. F11 CIF1MODE Digital Input Control interface 1 mode select input G13 CIF1SCLK Digital Input Control interface 1 clock input G12 CIF1SDA/ CIF1MOSI Digital Input / Output Control interface 1 (I2C) data input and output / Control interface 1 (SPI) Master Out Slave In data. The output functions are implemented as an Open Drain circuit. L12 CIF2SCLK Digital Input Control interface 2 clock input K10 CIF2SDA Digital Input / Output Control interface 2 data input and output / acknowledge output. The output function is implemented as an Open Drain circuit. C5 CP1C1A Analogue Output Charge pump 1 fly-back capacitor 1 pin C6 CP1C1B Analogue Output Charge pump 1 fly-back capacitor 1 pin B6 CP1C2A Analogue Output Charge pump 1 fly-back capacitor 2 pin A6 CP1C2B Analogue Output Charge pump 1 fly-back capacitor 2 pin C7 CP1VOUT1N Analogue Output Charge pump 1 negative output 1 decoupling pin B8 CP1VOUT1P Analogue Output Charge pump 1 positive output 1 decoupling pin A7 CP1VOUT2N Analogue Output Charge pump 1 negative output 2 decoupling pin

Rev 4.0 9 PIN NO NAME TYPE DESCRIPTION B7 CP1VOUT2P Analogue Output Charge pump 1 positive output 2 decoupling pin D7 CP2CA Analogue Output Charge pump 2 fly-back capacitor pin D6 CP2CB Analogue Output Charge pump 2 fly-back capacitor pin D5 CP2VOUT Analogue Output Charge pump 2 output decoupling pin / Supply for LDO2 B5 CPGND Supply Charge pump 1 & 2 ground (Return path for CPVDD) A5 CPVDD Supply Supply for Charge Pump 1 & 2 K14 DBVDD1 Supply Digital buffer (I/O) supply (core functions and Audio Interface 1) L11 DBVDD2 Supply Digital buffer (I/O) supply (for Audio Interface 2) L7 DBVDD3 Supply Digital buffer (I/O) supply (for Audio Interface 3) J14, L8 DCVDD Supply Digital core supply H14, L9, L10, L14 DGND Supply Digital ground (Return path for DCVDD, DBVDD1, DBVDD2 and DBVDD3) F3 DMICCLK4 Digital Output Digital MIC clock output 4 E3 DMICDAT4 Digital Input Digital MIC data input 4 H11 GPIO1 Digital Input / Output General Purpose pin GPIO1. The output configuration is selectable CMOS or Open Drain. J10 GPIO2 Digital Input / Output General Purpose pin GPIO2. The output configuration is selectable CMOS or Open Drain. H6 GPIO3 Digital Input / Output General Purpose pin GPIO3. The output configuration is selectable CMOS or Open Drain. F13 GPIO5 Digital Input / Output General Purpose pin GPIO5. The output configuration is selectable CMOS or Open Drain. C12 GPSWA Analogue Input / Output General Purpose bi-directional switch contact D12 GPSWB Analogue Input / Output General Purpose bi-directional switch contact B13 HPDETL Analogue Input Headphone left (HPOUT1L) sense input B12 HPDETR Analogue Input Headphone right (HPOUT1R) sense input B14 HPOUT1FB1/ MICDET2 Analogue Input HPOUT1L and HPOUT1R ground feedback pin 1/ Microphone & accessory sense input 2 A13 HPOUT1L Analogue Output Left headphone 1 output A12 HPOUT1R Analogue Output Right headphone 1 output B11 HPOUT2FB Analogue Input HPOUT2L and HPOUT2R ground loop noise rejection feedback A11 HPOUT2L Analogue Output Left headphone 2 output A10 HPOUT2R Analogue Output Right headphone 2 output B9 HPOUT3FB Analogue Input HPOUT3L and HPOUT3R ground loop noise rejection feedback A9 HPOUT3L Analogue Output Left headphone 3 output A8 HPOUT3R Analogue Output Right headphone 3 output A4 IN1LN/ DMICCLK1 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 1 B4 IN1LP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input D4 IN1RN/ DMICDAT1 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 1 C4 IN1RP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input A3 IN2LN/ DMICCLK2 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 2 B3 IN2LP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input D3 IN2RN/ DMICDAT2 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 2 C3 IN2RP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input

10 Rev 4.0 PIN NO NAME TYPE DESCRIPTION A2 IN3LN/ DMICCLK3 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 3 B2 IN3LP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input D2 IN3RN/ DMICDAT3 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 3 C2 IN3RP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input E11 IRQ¯¯¯ Digital Output Interrupt Request (IRQ) output (default is active low). The pin configuration is selectable CMOS or Open Drain. C13 JACKDET Analogue Input Jack detect input E13 LDOENA Digital Input Enable pin for LDO1 (generates DCVDD supply). Logic 1 input enables LDO1. If using external DCVDD supply, then LDO1 is not used, and LDOENA must be held at logic 0. F14 LDOVDD Supply Supply for LDO1 E14 LDOVOUT Analogue Output LDO1 output. If using external DCVDD, then LDOVOUT must be left floating. K13 MCLK1 Digital Input Master clock 1 G14 MCLK2 Digital Input Master clock 2 D1 MICBIAS1 Analogue Output Microphone bias 1 C1 MICBIAS2 Analogue Output Microphone bias 2 B1 MICBIAS3 Analogue Output Microphone bias 3 A14 MICDET1/ HPOUT1FB2 Analogue Input Microphone & accessory sense input 1/ HPOUT1L and HPOUT1R ground feedback pin 2 A1 MICVDD Analogue Output LDO2 output decoupling pin (generated internally by WM8281). (Can also be used as reference/supply for external microphones.) E12 RESET¯¯¯¯¯¯ Digital Input Digital Reset input (active low) L13 SLIMCLK Digital Input / Output SLIM Bus Clock input / output K12 SLIMDAT Digital Input / Output SLIM Bus Data input / output H9 SPKCLK1 Digital Output Digital speaker (PDM) 1 clock output H8 SPKCLK2 Digital Output Digital speaker (PDM) 2 clock output H10 SPKDAT1 Digital Output Digital speaker (PDM) 1 data output H7 SPKDAT2 Digital Output Digital speaker (PDM) 2 data output L4 SPKGNDLN Supply Left speaker driver ground (Return path for SPKVDDL). See note. K4 SPKGNDLP Supply Left speaker driver ground (Return path for SPKVDDL). See note. L3 SPKGNDRN Supply Right speaker driver ground (Return path for SPKVDDR). See note. K3 SPKGNDRP Supply Right speaker driver ground (Return path for SPKVDDR). See note. L5 SPKOUTLN Analogue Output Left speaker negative output K5 SPKOUTLP Analogue Output Left speaker positive output L2 SPKOUTRN Analogue Output Right speaker negative output K2 SPKOUTRP Analogue Output Right speaker positive output H1 SPKTST1 Analogue Output Test function (recommend no external connection) H2 SPKTST2 Analogue Output Test function (recommend no external connection) K6, L6 SPKVDDL Supply Left speaker driver supply K1, L1 SPKVDDR Supply Right speaker driver supply D14, F2 SUBGND Supply Substrate ground F9 TCK Digital Input JTAG clock input. Internal pull-down holds this pin at logic 0 for normal operation.

Rev 4.0 11 PIN NO NAME TYPE DESCRIPTION F8 TDI Digital Input JTAG data input. Internal pull-down holds this pin at logic 0 for normal operation. K11 TDO Digital Output JTAG data output F7 TMS Digital Input JTAG mode select input. Internal pull-down holds this pin at logic 0 for normal operation. F6 TRST Digital Input JTAG Test Access Port reset (active low). Internal pull-down holds this pin at logic 0 for normal operation. F1 VREFC Analogue Output Bandgap reference external components connection B10, C8, C9, C10, C11, D8, D9, D10, D11, F4, G1, G2, G3, G4, H3, J1, J2, J3, J4, J5, J6 NC n/a No Connection Note: Separate P/N ground connections are provided for each speaker driver channel; this provides flexible support for current monitoring and output protection circuits. If this option is not used, then the respective ground connections should be tied together on the PCB.

12 Rev 4.0 The following table identifies the power domain and ground reference associated with each of the input / output pins. PIN NO NAME POWER DOMAIN GROUND DOMAIN J13 AIF1BCLK DBVDD1 DGND H13 AIF1RXDAT DBVDD1 DGND H12 AIF1LRCLK DBVDD1 DGND J11 AIF1TXDAT DBVDD1 DGND K9 AIF2BCLK DBVDD2 DGND J8 AIF2RXDAT DBVDD2 DGND J9 AIF2LRCLK DBVDD2 DGND K8 AIF2TXDAT DBVDD2 DGND K7 AIF3BCLK DBVDD3 DGND H4 AIF3RXDAT DBVDD3 DGND J7 AIF3LRCLK DBVDD3 DGND H5 AIF3TXDAT DBVDD3 DGND F12 CIF1ADDR/ DBVDD1 DGND J12 CIF1MISO/ GPIO4 DBVDD1 DGND F11 CIF1MODE DBVDD1 DGND G13 CIF1SCLK DBVDD1 DGND G12 CIF1SDA/ CIF1MOSI DBVDD1 DGND L12 CIF2SCLK DBVDD2 DGND K10 CIF2SDA DBVDD2 DGND F3 DMICCLK4 MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 The DMICCLK4 power domain is selectable using IN4_DMIC_SUP AGND E3 DMICDAT4 MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 The DMICDAT4 power domain is selectable using IN4_DMIC_SUP AGND H11 GPIO1 DBVDD1 DGND J10 GPIO2 DBVDD2 DGND H6 GPIO3 DBVDD3 DGND F13 GPIO5 DBVDD1 DGND C12 GPSWA D12 GPSWB B13 HPDETL AVDD AGND B12 HPDETR AVDD AGND B14 HPOUT1FB1/ MICDET2 CPVDD (Ground noise rejection) / MICVDD (Microphone / Accessory detection) CPGND A13 HPOUT1L CPVDD CPGND A12 HPOUT1R CPVDD CPGND B11 HPOUT2FB CPVDD CPGND A11 HPOUT2L CPVDD CPGND A10 HPOUT2R CPVDD CPGND B9 HPOUT3FB CPVDD CPGND A9 HPOUT3L CPVDD CPGND A8 HPOUT3R CPVDD CPGND A4 IN1LN DMICCLK1 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICCLK1 power domain is selectable using IN1_DMIC_SUP AGND B4 IN1LP MICVDD AGND D4 IN1RN/ DMICDAT1 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICDAT1 power domain is selectable using IN1_DMIC_SUP AGND

Rev 4.0 13 PIN NO NAME POWER DOMAIN GROUND DOMAIN C4 IN1RP MICVDD AGND A3 IN2LN/ DMICCLK2 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICCLK2 power domain is selectable using IN2_DMIC_SUP AGND B3 IN2LP MICVDD AGND D3 IN2RN/ DMICDAT2 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICDAT2 power domain is selectable using IN2_DMIC_SUP AGND C3 IN2RP MICVDD AGND A2 IN3LN/ DMICCLK3 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICCLK3 power domain is selectable using IN3_DMIC_SUP AGND B2 IN3LP MICVDD AGND D2 IN3RN/ DMICDAT3 MICVDD (analogue) / MICVDD, MICBIAS1, MICBIAS2, MICBIAS3 (digital) The DMICDAT3 power domain is selectable using IN3_DMIC_SUP AGND C2 IN3RP MICVDD AGND E11 IRQ¯¯¯ DBVDD1 DGND C13 JACKDET AVDD AGND E13 LDOENA DBVDD1 DGND K13 MCLK1 DBVDD1 DGND G14 MCLK2 DBVDD1 DGND D1 MICBIAS1 MICVDD AGND C1 MICBIAS2 MICVDD AGND B1 MICBIAS3 MICVDD AGND A14 MICDET1/ HPOUT1FB2 MICVDD (Microphone / Accessory detection) / CPVDD (Ground noise rejection) AGND L13 SLIMCLK DBVDD1 DGND K12 SLIMDAT DBVDD1 DGND H9 SPKCLK1 DBVDD2 DGND H8 SPKCLK2 DBVDD2 DGND H10 SPKDAT1 DBVDD2 DGND H7 SPKDAT2 DBVDD2 DGND L5 SPKOUTLN SPKVDDL SPKGNDL K5 SPKOUTLP SPKVDDL SPKGNDL L2 SPKOUTRN SPKVDDR SPKGNDR K2 SPKOUTRP SPKVDDR SPKGNDR F9 TCK DBVDD2 DGND F8 TDI DBVDD2 DGND K11 TDO DBVDD2 DGND F7 TMS DBVDD2 DGND F6 TRST DBVDD2 DGND F1 VREFC AVDD AGND

14 Rev 4.0 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Supply voltages (DCVDD) -0.3V 1.6V Supply voltages (CPVDD) -0.3V 2.5V Supply voltages (DBVDD1, DBVDD2, DBVDD3, LDOVDD, AVDD, MICVDD) -0.3V 5.0V Supply voltages (SPKVDDL, SPKVDDR) -0.3V 6.0V Voltage range digital inputs (DBVDD1 domain) SUBGND - 0.3V DBVDD1 + 0.3V Voltage range digital inputs (DBVDD2 domain) SUBGND - 0.3V DBVDD2 + 0.3V Voltage range digital inputs (DBVDD3 domain) SUBGND - 0.3V DBVDD3 + 0.3V Voltage range digital inputs (DMICDATn) SUBGND - 0.3V MICVDD + 0.3V Voltage range analogue inputs (INnLP, INnLN) SUBGND - 0.3V MICVDD + 0.3V Voltage range analogue inputs (INnRP, INnRN) SUBGND - 0.9V MICVDD + 0.3V Voltage range analogue inputs (HPOUT1FB1, HPOUT1FB2, HPOUTnFB) SUBGND - 0.3V SUBGND + 0.3V Voltage range analogue inputs (MICDETn, GPSWA, GPSWB) SUBGND - 0.3V MICVDD + 0.3V Voltage range analogue inputs (JACKDET, HPDETL, HPDETR) CP1VOUT2N - 0.3V AVDD + 0.3V Ground (AGND, DGND, CPGND, SPKGNDL, SPKGNDR) SUBGND - 0.3V SUBGND + 0.3V Operating temperature range, TA -40ºC +85ºC Operating junction temperature, TJ -40ºC +125ºC Storage temperature after soldering -65ºC +150ºC Notes: 1. DCVDD must not be powered if AVDD is not present. 2. The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD. 3. The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND. 4. The HPOUT1FBn and MICDETn functions share common pins. The Absolute Maximum Rating varies according to the applicable function of each pin. 5. CP1VOUT2N is an internal supply, generated by the WM8281 Charge Pump (CP1). The CP1VOUT2N voltage may vary between AGND and -CPVDD.

Rev 4.0 15 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN TYP MAX UNIT Digital supply range (Core) See notes 2, 3, 4 DCVDD 1.14 1.2 1.26 V Digital supply range (I/O) See note 5 DBVDD1, DBVDD2, DBVDD3 1.62 3.6 V LDO supply range See note 13 LDOVDD 1.71 1.8 1.89 V Charge Pump supply range CPVDD 1.71 1.8 1.89 V Speaker supply range SPKVDDL, SPKVDDR 2.4 5.5 V Analogue supply range See notes 2, 6, 7 AVDD 1.71 1.8 1.89 V Microphone Bias supply See note 8 MICVDD 0.9 2.5 3.78 V Ground See note 1 DGND, AGND, CPGND, SPKGNDL, SPKGNDR, SUBGND 0 V Power supply rise time See notes 9, 10, 11, 12 DCVDD 10 2000 µs All other supplies 10 Operating temperature range TA -40 85 °C Notes: 1. The impedance between DGND, AGND, CPGND and SUBGND should be less than 0.1 Ω.The impedance between SPKGNDL, SPKGNDR and SUBGND should be less than 0.2Ω. 2. AVDD must be supplied before or simultaneously to DCVDD. DCVDD must not be powered if AVDD is not present. There are no other power sequencing requirements. 3. An internal LDO (powered by LDOVDD) can be used to provide the DCVDD supply. 4. ‘Sleep’ mode is supported when DCVDD is below the limits noted, provided AVDD and DBVDD1 are present. 5. If the SLIMbus interface is enabled, then the maximum DBVDD1 voltage is 1.98V. 6. The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD. 7. The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND. 8. An internal Charge Pump and LDO (powered by CPVDD) provide the Microphone Bias supply; the MICVDD pin should not be connected to an external supply. 9. DCVDD and MICVDD minimum rise times do not apply when these domains are powered using the internal LDOs. 10. If DCVDD is supplied externally, and the rise time exceeds 2ms, then RESET¯¯¯¯¯¯ must be asserted (low) during the rise, and held asserted until after DCVDD is within the recommended operating limits. 11. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Cirrus Logic strongly advises that the recommended decoupling capacitors are present on the PCB and that appro priate layout guidelines are observed. 12. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. 13. When the internal LDO is used to provide the DCVDD supply, then the LDOVDD supply must b e suitably rated for the inrush current at start -up and wake -up. In the typical configuration, using the internal LDO, and with the LDOVDD / CPVDD / AVDD domains connected to a single supply, a peak current capability of 500mA is required on this supply.

16 Rev 4.0

ELECTRICAL CHARACTERISTICS

AVDD = 1.8V, With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Signal Level (IN1L, IN1R, IN2L, IN2R, IN3L, IN3R) Full-scale input signal level (0dBFS output) VINFS Single-ended PGA input, 0dB PGA gain 0.5 VRMS dBV Differential PGA input, 0dB PGA gain VRMS dBV Notes: 1. The full-scale input signal level is also the maximum analogue input level, before clipping occurs. 2. The full-scale input signal level changes in proportion with AVDD. For differential input, it is calculated as AVDD / 1.8. 3. A 1.0VRMS differential signal equates to 0.5VRMS/-6dBV per input. 4. A sinusoidal input signal is assumed. Test Conditions TA = +25ºC With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Pin Characteristics (IN1L, IN1R, IN2L, IN2R, IN3L, IN3R) Input resistance RIN Single-ended PGA input, All PGA gain settings 9 12 k Differential PGA input, All PGA gain settings 18 24 Input capacitance CIN 5 pF Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Input Programmable Gain Amplifiers (PGAs) Minimum programmable gain 0 dB Maximum programmable gain 31 dB Programmable gain step size Guaranteed monotonic 1 dB Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Microphone Input Signal Level (DMICDAT1, DMICDAT2, DMICDAT3, DMICDAT4) Full-scale input signal level (0dBFS output) 0dB gain -6 dBFS Notes: 5. The digital microphone input signal level is measured in dBFS, where 0dBFS is a signal level equal to the full-scale range (FSR) of the PDM input. The FSR is defined as the amplitude of a 1kHz sine wave whose positive and negative peaks are represented by the maximum and minimum digital codes respectively - this is the largest 1kHz sine wave that will fit in the digital output range without clipping. Note that, because the definition of FSR is based on a sine wave, the PDM data format can support signals larger than 0dBFS.

Rev 4.0 17 Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Line / Headphone / Earpiece Output Driver (HPOUTnL, HPOUTnR) Load resistance Normal operation, Single-ended mode 6 Ω Normal operation, Differential (BTL) mode Device survival with load applied indefinitely Load capacitance Direct connection, Single-ended mode 500 pF Direct connection, Differential (BTL) mode 200 Connection via 16Ω series resistor 2 nF Speaker Output Driver (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN) Load resistance Normal operation 4 Ω Device survival with load applied indefinitely Load capacitance 200 pF Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Line / Headphone / Earpiece Output Driver (HPOUTnL, HPOUTnR) DC offset at Load Single-ended mode 0.1 mV Differential (BTL) mode 0.2 Speaker Output Driver (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN) DC offset at Load 10 mV SPKVDD leakage current 1 µA

18 Rev 4.0 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Paths (INnL, INnR) to ADC (Differential Input Mode, INn_MODE = 00) Signal to Noise Ratio (A-weighted) SNR 48kHz sample rate 93 100 dB 16kHz sample rate, (wideband voice) 100 106 Total Harmonic Distortion THD -1dBV input -89 -81 dB Total Harmonic Distortion + Noise THD+N -1dBV input -88 dB Channel separation (Left/Right) 100 dB Input-referred noise floor A-weighted, PGA gain = +20dB 3.2 µVRMS Common mode rejection ratio CMRR PGA gain = +30dB 54 60 dB PGA gain = 0dB 60 70 PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 85 dB 100mV (peak-peak) 10kHz 82 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz >120 dB 100mV (peak-peak) 10kHz 70 Analogue Input Paths (INnLP, INnRP) to ADC (Single-Ended Input Mode, INn_MODE = 01) Signal to Noise Ratio (A-weighted) SNR 48kHz sample rate 91 96 dB 16kHz sample rate, (wideband voice) 102 Total Harmonic Distortion THD -7dBV input -85 -78 dB Total Harmonic Distortion + Noise THD+N -7dBV input -84 dB Channel separation (Left/Right) 100 dB Input-referred noise floor A-weighted, PGA gain = +20dB 3.2 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 77 dB 100mV (peak-peak) 10kHz 50 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz 90 dB 100mV (peak-peak) 10kHz 50

Rev 4.0 19 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Line Output (HPOUTnL, HPOUTnR; Load = 10k, 50pF) Full-scale output signal level VOUT 0dBFS input 1 Vrms dBV Signal to Noise Ratio (A-weighted) SNR Output signal = 1Vrms 107 115 dB Output signal = 1Vrms, eDRE software enabled 120 Total Harmonic Distortion THD 0dBFS input -92 -84 dB Total Harmonic Distortion + Noise THD+N 0dBFS input -90 dB Channel separation (Left/Right) 110 dB Output noise floor A-weighted, eDRE software enabled 0.8 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 80 dB 100mV (peak-peak) 10kHz 72 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz >120 dB 100mV (peak-peak) 10kHz >120 DAC to Headphone Output (HPOUTnL, HPOUTnR, RL = 32, Short Circuit Protection disabled) Maximum output power PO 0.1% THD+N 32 mW Signal to Noise Ratio (A-weighted) SNR Output signal = 1Vrms 107 115 dB Output signal = 1Vrms, eDRE software enabled 121 Total Harmonic Distortion THD PO = 20mW -89 dB Total Harmonic Distortion + Noise THD+N PO = 20mW -88 dB Total Harmonic Distortion THD PO = 5mW -91 -84 dB Total Harmonic Distortion Plus Noise THD+N PO = 5mW -88 dB Channel separation (Left/Right) 94 dB Output noise floor A-weighted, eDRE software enabled 0.8 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 89 dB 100mV (peak-peak) 10kHz 72 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz >120 dB 100mV (peak-peak) 10kHz >120 DAC to Headphone Output (HPOUTnL, HPOUTnR, RL = 16, Short Circuit Protection disabled) Maximum output power PO 0.1% THD+N 42 mW Signal to Noise Ratio (A-weighted) SNR Output signal = 1Vrms 107 115 dB Output signal = 1Vrms, eDRE software enabled 121 Total Harmonic Distortion THD PO = 20mW -88 dB Total Harmonic Distortion + Noise THD+N PO = 20mW -87 dB Total Harmonic Distortion THD PO = 5mW -88 -84 dB Total Harmonic Distortion + Noise THD+N PO = 5mW -87 dB Channel separation (Left/Right) 92 dB Output noise floor A-weighted, eDRE software enabled 0.8 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 89 dB 100mV (peak-peak) 10kHz 72 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz >120 dB 100mV (peak-peak) 10kHz >120

20 Rev 4.0 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Earpiece Output (HPOUTnL, HPOUTnR, Mono Mode, RL = 32 BTL, Short Circuit Protection disabled) Maximum output power PO 0.1% THD+N 106 mW Signal to Noise Ratio (A-weighted) SNR Output signal = 1.41Vrms 117 dB Output signal = 1.41Vrms, eDRE software enabled 126 Total Harmonic Distortion THD PO = 75mW -88 dB Total Harmonic Distortion + Noise THD+N PO = 75mW -86 dB Total Harmonic Distortion THD PO = 5mW -89 dB Total Harmonic Distortion + Noise THD+N PO = 5mW -88 dB Output noise floor A-weighted 2.25 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 105 dB 100mV (peak-peak) 10kHz 107 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz >120 dB 100mV (peak-peak) 10kHz >120 DAC to Earpiece Output (HPOUTnL, HPOUTnR, Mono Mode, RL = 16 BTL, Short Circuit Protection disabled) Maximum output power PO 0.1% THD+N 105 mW Signal to Noise Ratio (A-weighted) SNR Output signal = 1.41Vrms 117 dB Output signal = 1.41Vrms, eDRE software enabled 126 Total Harmonic Distortion THD PO = 75mW -86 dB Total Harmonic Distortion + Noise THD+N PO = 75mW -85 dB Total Harmonic Distortion THD PO = 5mW -86 dB Total Harmonic Distortion + Noise THD+N PO = 5mW -85 dB Output noise floor A-weighted 2.25 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 105 dB 100mV (peak-peak) 10kHz 112 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz >120 dB 100mV (peak-peak) 10kHz >120

Rev 4.0 21 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Speaker Output (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN; Load = 8, 22µH, BTL) Maximum output power PO SPKVDD = 5.0V, 1% THD+N 1.4 W SPKVDD = 4.2V, 1% THD+N 1.0 SPKVDD = 3.6V, 1% THD+N 0.7 Signal to Noise Ratio SNR A-weighted, Output signal = 2.83Vrms 85 95 dB Total Harmonic Distortion THD PO = 1.0W -40 dB Total Harmonic Distortion + Noise THD+N PO = 1.0W -40 dB Total Harmonic Distortion THD PO = 0.5W -70 -59 dB Total Harmonic Distortion + Noise THD+N PO = 0.5W -69 dB Channel separation (Left/Right) 80 dB Output noise floor A-weighted 51.2 177 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 76 dB 100mV (peak-peak) 10kHz 68 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz 72 dB 100mV (peak-peak) 10kHz 55 DAC to Speaker Output (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN; Load = 4, 15µH, BTL) Maximum output power PO SPKVDD = 5.0V, 1% THD+N 2.5 W SPKVDD = 4.2V, 1% THD+N 1.8 SPKVDD = 3.6V, 1% THD+N 1.3 Signal to Noise Ratio SNR A-weighted, Output signal = 2.83Vrms 95 dB Total Harmonic Distortion THD PO = 1.0W -70 dB Total Harmonic Distortion + Noise THD+N PO = 1.0W -69 dB Total Harmonic Distortion THD PO = 0.5W -69 dB Total Harmonic Distortion + Noise THD+N PO = 0.5W -68 dB Channel separation (Left/Right) 80 dB Output noise floor A-weighted 51.2 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 76 dB 100mV (peak-peak) 10kHz 68 PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz 72 dB 100mV (peak-peak) 10kHz 55

22 Rev 4.0 Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Input / Output (except DMICDATn and DMICCLKn) Digital I/O is referenced to DBVDD1, DBVDD2 or DBVDD3. See “Pin Description” for the domain applicable to each pin. Input HIGH Level VIH VDBVDDn = 1.8V ±10% 0.75  VDBVDDn V VDBVDDn = 2.5V ±10% 0.8  VDBVDDn VDBVDDn = 3.3V ±10% 0.7  VDBVDDn Input LOW Level VIL VDBVDDn = 1.8V ±10% 0.3  VDBVDDn V VDBVDDn = 2.5V ±10% 0.25  VDBVDDn VDBVDDn = 3.3V ±10% 0.2  VDBVDDn Note that digital input pins should not be left unconnected or floating. Output HIGH Level (IOH = 1mA) VOH VDBVDDn = 1.8V ±10% 0.75  VDBVDDn V VDBVDDn = 2.5V ±10% 0.65  VDBVDDn VDBVDDn = 3.3V ±10% 0.7  VDBVDDn Output LOW Level (IOL = 1mA) VOL VDBVDDn = 1.8V ±10% 0.25  VDBVDDn V VDBVDDn = 2.5V ±10% 0.3  VDBVDDn VDBVDDn = 3.3V ±10% 0.15  VDBVDDn Input capacitance 5 pF Input leakage -10 10 µA Pull-up / pull-down resistance (where applicable) 36 50 kΩ Digital Microphone Input / Output (DMICDATn and DMICCLKn) DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP, according to the INn_DMIC_SUP registers DMICDATn input HIGH Level VIH 0.65  VSUP V DMICDATn input LOW Level VIL 0.35  VSUP V DMICCLKn output HIGH Level VOH IOH = 1mA 0.8  VSUP V DMICCLKn output LOW Level VOL IOL = -1mA 0.2  VSUP V Input capacitance 25 pF Input leakage -1 1 µA General Purpose Input / Output (GPIOn) Clock output frequency GPIO pin configured as OPCLK or FLL output

50 MHz

The GPSWA pin should be positive-biased with respect to GPSWB. The GPSWB pin voltage must not exceed GPSWA + 0.3V. Switch resistance RDS(ON) Switch closed, I=1mA 40 Ω Switch resistance RDS(OFF) Switch open 100 MΩ

Rev 4.0 23 Test Conditions fs ≤ 48kHz With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ADC Decimation Filters Passband +/- 0.05dB 0 0.454 fs -6dB 0.5 fs Passband ripple +/- 0.05 dB Stopband 0.546 fs Stopband attenuation f > 0.546 fs 85 dB Group delay 2 ms DAC Interpolation Filters Passband +/- 0.05dB 0 0.454 fs -6dB 0.5 fs Passband ripple +/- 0.05 dB Stopband 0.546 fs Stopband attenuation f > 0.546 fs 85 dB Group delay 1.5 ms

24 Rev 4.0 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Bias (MICBIAS1, MICBIAS2, MICBIAS3) Note - No capacitor on MICBIASn Note - In regulator mode, it is required that VMICVDD - VMICBIAS > 200mV Minimum Bias Voltage VMICBIAS Regulator mode (MICBn_BYPASS=0) Load current ≤ 1.0mA 1.5 V Maximum Bias Voltage 2.8 V Bias Voltage output step size 0.1 V Bias Voltage accuracy -5% +5% V Bias Current Regulator mode (MICBn_BYPASS=0), VMICVDD - VMICBIAS >200mV 2.4 mA Bypass mode (MICBn_BYPASS=1) 5.0 Output Noise Density Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, Measured at 1kHz 100 nV/Hz Integrated noise voltage Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, 100Hz to 7kHz, A-weighted 5 µVrms Power Supply Rejection Ratio (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 100 dB 100mV (peak-peak) 10kHz 80 Load capacitance Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=0 50 pF Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=1 1.8 4.7 µF Output discharge resistance MICBn_ENA=0, MICBn_DISCH=1 2 kΩ

Rev 4.0 25 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT External Accessory Detect Load impedance detection range Detection via HPDETL pin (ACCDET_MODE=001) or HPDETR pin (ACCDET_MODE=010) HP_IMPEDANCE_ RANGE=00 4 30 Ω HP_IMPEDANCE_ RANGE=01 8 100 HP_IMPEDANCE_ RANGE=10 100 1000 HP_IMPEDANCE_ RANGE=11 1000 10000 Load impedance detection range Detection via MICDET1 or MICDET2 pin (ACCDET_MODE=100) 400 6000 Ω Load impedance detection accuracy (result derived from HP_DACVAL, ACCDET_MODE=001 or 010) HP_IMPEDANCE_ RANGE=01 or 10 -5 +5 % HP_IMPEDANCE_ RANGE=00 or 11 -10 +10 Load impedance detection accuracy (result derived from HP_LVL, ACCDET_MODE= 001, 010 or 100) -20 +20 % Load impedance detection range Detection via MICDET1 or MICDET2 pin (ACCDET_MODE=000). 2.2kΩ (2%) MICBIAS resistor. Note these characteristics assume no other component is connected to MICDETn. See “Applications Information” for recommended external components when a typical microphone is present. for MICD_LVL[0] = 1 0 3 Ω for MICD_LVL[1] = 1 17 21 for MICD_LVL[2] = 1 36 44 for MICD_LVL[3] = 1 62 88 for MICD_LVL[4] = 1 115 160 for MICD_LVL[5] = 1 207 381 for MICD_LVL[8] = 1 475 30000 Jack Detection input threshold voltage (JACKDET) VJACKDET Jack insertion 0.5 x AVDD V Jack removal 0.85 x AVDD

26 Rev 4.0 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT MICVDD Charge Pump and Regulator (CP2 and LDO2) Output voltage VMICVDD 0.9 2.7 3.3 V Programmable output voltage step size LDO2_VSEL=00h to 14h (0.9V to 1.4V) 25 mV LDO2_VSEL=14h to 27h (1.4V to 3.3V) 100 Maximum output current 8 mA Start-up time 4.7µF on MICVDD 1.5 2.5 ms Frequency Locked Loop (FLL1, FLL2) Output frequency 39 156 MHz Lock Time FREF = 32kHz, FOUT = 147.456MHz 10 ms FREF = 12MHz, FOUT = 147.456MHz RESET pin Input RESET input pulse width (To trigger a Hardware Reset, the RESET input must be asserted for longer than this duration) 1 µs Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. Device Reset Thresholds AVDD Reset Threshold VAVDD VAVDD rising 1.56 V VAVDD falling 0.92 1.55 DCVDD Reset Threshold VDCVDD VDCVDD rising 1.04 V VDCVDD falling 0.49 0.64 DBVDD1 Reset Threshold VDBVDD1 VDBVDD1 rising 1.54 V VDBVDD1 falling 0.58 1.52 Note that the reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to this section for the WM8281 power-up sequencing requirements.

Rev 4.0 27 TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal and the output with no input signal applied. (Note that this is measured without any mute function enabled.) 2. Total Harmonic Distortion (dB ) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. 3. Total Harmonic Distortion plus Noise (dB) – THD+N is the ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. 4. Power Supply Rejection Ratio (dB) - PSRR is the ratio of a specified po wer supply variation relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions. 5. Common Mode Rejection Ratio (dB) – CMRR is the ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it. 6. Channel Separation (L/R) (dB) – left-to-right and right -to-left channel separation is the difference in level between the active channel (driven to maximum full scale output) and the measured signal l evel in the idle channel at the test signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal meas ured at the output of the associated idle channel. 7. Multi-Path Crosstalk (dB) – is the difference in level between the output of the active path and the measured signal level in the idle path at the test signal frequency. The active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. 8. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. 9. All performance measurements are specified with a 20kHz low pass ‘brick -wall’ filter and, where noted, an A -weighted filter. Failure to use these filters will result in higher THD and lower SNR readings than are found in the Electrical Characteristic s. The low pass filter removes out-of-band noise.

28 Rev 4.0 THERMAL CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNIT Junction-to-ambient thermal resistance ΘJA 34.1 °C/W Junction-to-board thermal resistance ΘJB 9.8 °C/W Junction-to-case thermal resistance ΘJC 0.6 °C/W Junction-to-board thermal characterisation parameter ΨJB 8.8 °C/W Junction-to-top thermal characterisation parameter ΨJT 0.03 °C/W Notes: 1. The Thermal Characteristics data is based on simulated test results, with reference to JEDEC JESD51 standards. 2. The thermal resistance (Θ) parameters describe the thermal behaviour in a standardised measurement environment. 3. The thermal characterisation (Ψ) parameters describe the thermal behaviour in the environment of a typical application.

Rev 4.0 29 TYPICAL PERFORMANCE TYPICAL POWER CONSUMPTION Typical power consumption data is provided below for a number of different operating conditions. Test Conditions: DCVDD = 1.2V, DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, SPKVDDL = SPKVDDR = 4.2V, MICVDD = 3.0V (powered from LDO2), TA = +25ºC. OPERATING MODE TEST CONDITIONS SUPPLY CURRENT (1.2V) SUPPLY CURRENT (1.8V) SUPPLY CURRENT (4.2V) TOTAL POWER Music Playback to Headphone AIF1 to DAC to HPOUT1 (stereo) fs=48kHz, 24-bit I2S, Slave mode Load = 32, eDRE software enabled. Quiescent 2.3mA 1.1mA 0.0mA 4.7mW 1kHz sine wave, PO=10mW 2.4mA 35.6mA 0.0mA 66.9mW Music Playback to Line Output AIF1 to DAC to HPOUT2 (stereo) fs=48kHz, 24-bit I2S, Slave mode Load = 10k, 50pF, eDRE software enabled. Quiescent 2.3mA 1mA 0.0mA 4.6mW Music Playback to Earpiece AIF1 to DAC to HPOUT3 (mono) fs=48kHz, 24-bit I2S, Slave mode Load = 32, BTL, eDRE software enabled. Quiescent 1.53mA 1.2mA 0.0mA 4.0mW 1kHz sine wave, PO=30mW 1.3mA 60.6mA 0.0mA 110.6mW Music Playback to Speaker AIF1 to DAC to SPKOUT (stereo) fs=48kHz, 24-bit I2S, Slave mode Load = 8, 22µH, BTL. Quiescent 1.54mA 2.12mA 3.76mA 21.5mW 1kHz sine wave, PO=700mW 1.62mA 2.15mA 372mA 1568mW Full Duplex Voice Call Analogue Mic to ADC to AIF1 (out) AIF (in) to DAC to HPOUT3 (mono) fs=8kHz, 16-bit I2S, Slave mode. MEMS microphone powered from regulated MICBIAS (2.2V) output. Earpiece load = 32, BTL. Quiescent 2.6mA 4.2mA 0.0mA 10.7mW Stereo Line Record Analogue Line to ADC to AIF1 fs=48kHz, 24-bit I2S, Slave mode 1kHz sine wave, -1dBFS out 1.2mA 1.5mA 0.0mA 4.1mW Sleep Mode Accessory detect enabled (JD1_ENA=1) 0mA 0.022mA 0.0mA 0.039mW

30 Rev 4.0 TYPICAL SIGNAL LATENCY OPERATING MODE TEST CONDITIONS LATENCY INPUT OUTPUT DIGITAL CORE AIF to DAC Stereo Path Digital input (AIFn) to analogue output (HPOUT). Signal is routed via the digital core ASRC function in the asynchronous test cases only. fs = 48kHz fs = 48kHz Synchronous 358µs fs = 44.1kHz fs = 44.1kHz Synchronous 391µs fs = 16kHz fs = 16kHz Synchronous 720µs fs = 8kHz fs = 8kHz Synchronous 1428µs fs = 8kHz fs = 44.1kHz Asynchronous 1940µs fs = 16kHz fs = 44.1kHz Asynchronous 1240µs ADC to AIF Stereo Path Analogue input (INn) to digital output (AIFn). Digital core High Pass filter included in signal path. Signal is routed via the digital core ASRC function in the asynchronous test cases only. fs = 48kHz fs = 48kHz Synchronous 244µs fs = 44.1kHz fs = 44.1kHz Synchronous 260µs fs = 16kHz fs = 16kHz Synchronous 890µs fs = 8kHz fs = 8kHz Synchronous 1856µs fs = 44.1kHz fs = 8kHz Asynchronous 1320µs fs = 44.1kHz fs = 16kHz Asynchronous 820µs

Rev 4.0 31 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK & FREQUENCY LOCKED LOOP (FLL) MCLK tMCLKL tMCLKH tMCLKY VIH VIL Figure 1 Master Clock Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Master Clock Timing (MCLK1, MCLK2) MCLK cycle time MCLK as input to FLL, FLLn_REFCLK_DIV=00 74 ns MCLK as input to FLL, FLLn_REFCLK_DIV=01 MCLK as input to FLL, FLLn_REFCLK_DIV=10 MCLK as input to FLL, FLLn_REFCLK_DIV=11 12.5 MCLK as direct SYSCLK or ASYNCCLK source MCLK duty cycle MCLK as input to FLL 80:20 20:80 % MCLK as direct SYSCLK or ASYNCCLK source 60:40 40:60 MCLK2 frequency Sleep Mode 32.768 kHz Frequency Locked Loops (FLL1, FLL2) FLL input frequency FLLn_REFCLK_DIV=00 0.032 13.5 MHz FLLn_REFCLK_DIV=01 0.064 27 FLLn_REFCLK_DIV=10 0.128 54 FLLn_REFCLK_DIV=11 0.256 80 FLL synchroniser input frequency FLLn_SYNCCLK_DIV=00 0.032 13.5 MHz FLLn_SYNCCLK_DIV=01 0.064 27 FLLn_SYNCCLK_DIV=10 0.128 54 FLLn_SYNCCLK_DIV=11 0.256 80

32 Rev 4.0 Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal Clocking SYSCLK frequency SYSCLK_FREQ=000, SYSCLK_FRAC=0 -1% 6.144 +1% MHz SYSCLK_FREQ=000, SYSCLK_FRAC=1 -1% 5.6448 +1% SYSCLK_FREQ=001, SYSCLK_FRAC=0 -1% 12.288 +1% SYSCLK_FREQ=001, SYSCLK_FRAC=1 -1% 11.2896 +1% SYSCLK_FREQ=010, SYSCLK_FRAC=0 -1% 24.576 +1% SYSCLK_FREQ=010, SYSCLK_FRAC=1 -1% 22.5792 +1% SYSCLK_FREQ=011, SYSCLK_FRAC=0 -1% 49.152 +1% SYSCLK_FREQ=011, SYSCLK_FRAC=1 -1% 45.1584 +1% SYSCLK_FREQ=100, SYSCLK_FRAC=0 -1% 73.728 +1% SYSCLK_FREQ=100, SYSCLK_FRAC=1 -1% 67.7376 +1% SYSCLK_FREQ=101, SYSCLK_FRAC=0 -1% 98.304 +1% SYSCLK_FREQ=101, SYSCLK_FRAC=1 -1% 90.3168 +1% SYSCLK_FREQ=110, SYSCLK_FRAC=0 -1% 147.456 +1% SYSCLK_FREQ=110, SYSCLK_FRAC=1 -1% 135.4752 +1% ASYNCCLK frequency ASYNC_CLK_FREQ=000 -1% 6.144 +1% MHz -1% 5.6448 +1% ASYNC_CLK_FREQ=001 -1% 12.288 +1% -1% 11.2896 +1% ASYNC_CLK_FREQ=010 -1% 24.576 +1% -1% 22.5792 +1% ASYNC_CLK_FREQ=011 -1% 49.152 +1% -1% 45.1584 +1% Note: When MCLK1 or MCLK2 is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

Rev 4.0 33 AUDIO INTERFACE TIMING DIGITAL MICROPHONE (DMIC) INTERFACE TIMING (left data)(right data)DMICDAT (input) VIL VIH tRHtRSU tLHtLSU VOL DMICCLK (output) tCY VOH tr tf Figure 2 Digital Microphone Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Digital Microphone Interface Timing DMICCLKn cycle time tCY 160 163 1432 ns DMICCLKn duty cycle 45 55 % DMICCLKn rise/fall time (25pF load, 1.8V supply - see note) tr, tf 5 30 ns DMICDATn (Left) setup time to falling DMICCLK edge tLSU 15 ns DMICDATn (Left) hold time from falling DMICCLK edge tLH 0 ns DMICDATn (Right) setup time to rising DMICCLK edge tRSU 15 ns DMICDATn (Right) hold time from rising DMICCLK edge tRH 0 ns Notes: DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP. The applicable supply is selected using the INn_DMIC_SUP registers.

Rev 4.0 35 DIGITAL AUDIO INTERFACE - MASTER MODE BCLK (output) LRCLK (output) TXDAT (output) RXDAT (input) tDD tDHtDSU tLRD tBCH tBCL tBCY Figure 5 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 5 shows the default, non - inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. CLOAD = 15pF to 25pF (output pins). BCLK slew (10% to 90%) = 3.7ns to 5.6ns. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode AIFnBCLK cycle time tBCY 40 ns AIFnBCLK pulse width high tBCH 18 ns AIFnBCLK pulse width low tBCL 18 ns AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge tLRD 0 8.3 ns AIFnTXDAT propagation delay from BCLK falling edge tDD 0 5 ns AIFnRXDAT setup time to BCLK rising edge tDSU 9.2 ns AIFnRXDAT hold time from BCLK rising edge tDH 0 ns Audio Interface Timing - Master Mode, Slave LRCLK AIFnLRCLK setup time to BCLK rising edge tLRSU 14 ns AIFnLRCLK hold time from BCLK rising edge tLRH 0 ns Note: The descriptions above assume non-inverted polarity of AIFnBCLK.

36 Rev 4.0 DIGITAL AUDIO INTERFACE - SLAVE MODE BCLK (input) LRCLK (input) TXDAT (output) RXDAT (input) tDSU tDD tDH tLRH tLRSU tBCH tBCL tBCY Figure 6 Audio Interface Timing - Slave Mode Note that BCLK and LRCLK inputs can be inverted if required; Figure 6 shows the default, non - inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Slave Mode AIFnBCLK cycle time tBCY 40 ns AIFnBCLK pulse width high BCLK as direct SYSCLK or ASYNCCLK source tBCH 16 ns All other conditions 14 AIFnBCLK pulse width low BCLK as direct SYSCLK or ASYNCCLK source tBCL 16 ns All other conditions 14 Audio Interface Timing - Slave Mode CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns. AIFn[TX/RX]LRCLK set-up time to BCLK rising edge tLRSU 7 ns AIFn[TX/RX]LRCLK hold time from BCLK rising edge tLRH 0 ns AIFnTXDAT propagation delay from BCLK falling edge tDD 0 10.7 ns AIFnRXDAT set-up time to BCLK rising edge tDSU 2 ns AIFnRXDAT hold time from BCLK rising edge tDH 0 ns Audio Interface Timing - Slave Mode CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns. AIFn[TX/RX]LRCLK set-up time to BCLK rising edge tLRSU 7 ns AIFn[TX/RX]LRCLK hold time from BCLK rising edge tLRH 0 ns AIFnTXDAT propagation delay from BCLK falling edge tDD 0 12.7 ns AIFnRXDAT set-up time to BCLK rising edge tDSU 2 ns AIFnRXDAT hold time from BCLK rising edge tDH 0 ns Audio Interface Timing - Slave Mode, Master LRCLK AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns. tLRD 14.8 ns AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns. 15.9 Notes: The descriptions above assume non-inverted polarity of AIFnBCLK. When AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

38 Rev 4.0 CONTROL INTERFACE TIMING 2-WIRE (I2C) CONTROL MODE SCLK (input) SDA t4 t3 START STOPt2t1 t5 t9 t10 Figure 8 Control Interface Timing - 2-wire (I2C) Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SCLK Frequency 3400 kHz SCLK Low Pulse-Width t1 160 ns SCLK High Pulse-Width t2 100 ns Hold Time (Start Condition) t3 160 ns Setup Time (Start Condition) t4 160 ns SDA, SCLK Rise Time (10% to 90%) SCLK frequency > 1.7MHz t6 80 ns SCLK frequency > 1MHz 160 SCLK frequency ≤ 1MHz 2000 SDA, SCLK Fall Time (90% to 10%) SCLK frequency > 1.7MHz t7 60 ns SCLK frequency > 1MHz 160 SCLK frequency ≤ 1MHz 200 Setup Time (Stop Condition) t8 160 ns SDA Setup Time (data input) t5 40 ns SDA Hold Time (data input) t9 0 ns SDA Valid Time (data/ACK output) SCLK slew (90% to 10%) = 20ns, CLOAD (SDA) = 15pF t10 40 ns SCLK slew (90% to 10%) = 60ns, CLOAD (SDA) = 100pF 130 SCLK slew (90% to 10%) = 160ns, CLOAD (SDA) = 400pF 190 SCLK slew (90% to 10%) = 200ns, CLOAD (SDA) = 550pF 220 Pulse width of spikes that will be suppressed tps 0 25 ns

40 Rev 4.0 SLIMBUS INTERFACE TIMING SLIMDAT TDV TCLKL TCLKH VIH VIL TSETUP TH VIH, VOH VIL, VOL SLIMCLK VIL, VIH are the 35%/65% levels of the respective inputs. VOL, VOH are the 20%/80% levels of the respective outputs. The SLIMDAT output delay (TDV) is with respect to the input pads of all receiving devices. Figure 11 SLIMbus Interface Timing The signal timing information shown in Figure 11 describe the timing requirements of the SLIMbus interface as a whole, not just the WM8281 device. Accordingly, the following should be noted:  TDV is the propagation delay from the rising SL IMCLK edge (at WM8281 input) to the SLIMDAT output being achieved at the input to all devices across the bus.  TSETUP is the set -up time for SLIMDAT input (at WM8281), relative to the falling SL IMCLK edge (at WM8281).  TH is the hold time for SLIMDAT input (at WM8281) relative to the falling SLIMCLK edge (at WM8281). For more details of the interface timing, refer to the MIPI Alliance Specification for Serial Low -power Inter-chip Media Bus (SLIMbus). Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SLIMCLK Input SLIMCLK cycle time 35 ns SLIMCLK pulse width high TCLKH 12 ns SLIMCLK pulse width low TCLKL 12 ns SLIMCLK Output SLIMCLK cycle time 40 ns SLIMCLK pulse width high TCLKH 12 ns SLIMCLK pulse width low TCLKL 12 ns SLIMCLK slew rate (20% to 80%) CLOAD = 15pF, SLIMCLK_DRV_STR=0 SRCLK 0.09 x VDBVDD1 0.22 x VDBVDD1 V/ns CLOAD = 70pF, SLIMCLK_DRV_STR=0 0.02 x VDBVDD1 0.05 x VDBVDD1 CLOAD = 70pF, SLIMCLK_DRV_STR=1 0.04 x VDBVDD1 0.11 x VDBVDD1 SLIMDAT Input SLIMDAT setup time to SLIMCLK falling edge TSETUP 3.5 ns SLIMDAT hold time from SLIMCLK falling edge TH 2 ns

Rev 4.0 41 Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SLIMDAT Output SLIMDAT time for data output valid (wrt SLIMCLK rising edge) CLOAD = 15pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V TDV 4.7 8.1 ns CLOAD = 15pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 4.3 7.3 CLOAD = 30pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V 6.8 11.8 CLOAD = 30pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 5.8 10.0 CLOAD = 50pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V 9.6 16.6 CLOAD = 50pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 7.9 13.7 CLOAD = 70pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V 12.4 21.5 CLOAD = 70pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 10.0 17.4 SLIMDAT slew rate (20% to 80%) CLOAD = 15pF, SLIMDAT_DRV_STR=0 SRDATA 0.64 x VDBVDD1 V/ns CLOAD = 30pF, SLIMDAT_DRV_STR=0 0.35 x VDBVDD1 CLOAD = 30pF, SLIMDAT_DRV_STR=1 0.46 x VDBVDD1 CLOAD = 70pF, SLIMDAT_DRV_STR=0 0.16 x VDBVDD1 CLOAD = 70pF, SLIMCLK_DRV_STR=1 0.21 x VDBVDD1 Other Parameters Driver disable time TDD 6 ns Bus holder output impedance 0.1 x VDBVDD1 < V < 0.9 x VDBVDD1 RDATAS 18 50 kΩ

42 Rev 4.0 JTAG INTERFACE TIMING TCK (input) tCCH tCCL tCCY TDI (input) tDSU tDH TMS (input) tMSU tMH TDO (output) tDD TRST (input) tRSU tRH Figure 12 JTAG Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. CLOAD = 25pF (output pins). TCK slew (20% to 80%) = 5ns. PARAMETER SYMBOL MIN TYP MAX UNIT JTAG Interface Timing TCK cycle time TCCY 50 ns TCK pulse width high TCCH 20 ns TCK pulse width low TCCL 20 ns TMS setup time to TCK rising edge TMSU 1 ns TMS hold time from TCK rising edge TMH 2 ns TDI setup time to TCK rising edge TDSU 1 ns TDI hold time from TCK rising edge TDH 2 ns TDO propagation delay from TCK falling edge TDD 0 17 ns TRST setup time to TCK rising edge TRSU 3 ns TRST hold time from TCK rising edge TRH 3 ns TRST pulse width low 20 ns

Rev 4.0 43 DEVICE DESCRIPTION INTRODUCTION The WM8281 is a highly integrated low-power audio hub CODEC for mobile telephony and portable devices. It provides flexible, high -performance audio interfacing for handheld devices in a small and cost-effective package. It provides exceptional levels of performance and signal processing ca pability, suitable for a wide variety of mobile and handheld devices. The WM8281 digital core incorporates the Cirrus Logic Ambient Noise Cancellation (ANC) , and provides an extensive capability for programmable signal processing algorithms, including receive (RX) path noise cancellation , t ransmit (TX) path noise reduction, and Acoustic Echo Cancellation (AEC) algorithms. The WM8281 digital core supports audio enhancements such as Dynamic Range Control (DRC), Multi-band Compression (MBC), and Virtual Surrou nd Sound (VSS). Highly flexible digital mixing , including stereo full-duplex asynchronous sample rate conversion, provides use -case flexibility across a broad range of system architectures. A signal generator for controlling haptics vibe actuators is included. The WM8281 provides multiple digital audio interfaces , including SLIMbus, in order to provide independent and fully asynchronous connections to different processors (eg. application processor, baseband processor and wireless transceiver). A flexible clocking arrangement supports a wide variety of external clock references, including clocking derived from the digital audio interface. Two integrated Frequency Locked Loop (FLL) circuits provide additional flexibility. Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery -powered applications. Configurable ‘Wake -Up’ actions can be associated with the low-power standby (Sleep) mode. Versatile GPIO functionality is provided, and support for external accessory / push -button detection inputs. Comprehensive Interrupt (IRQ) logic and status readback are also provided. HI-FI AUDIO CODEC The WM8281 is a high -performance low -power audio CODEC whi ch uses a simple analogue architecture. 6 ADCs and 8 DACs are incorporated, providing a dedicated ADC for each analogue input and a dedicated DAC for each output channel. The analogue outputs comprise three 30mW ( 114dB SNR) stereo headphone amplifiers with ground- referenced output, and a Class D stereo speaker driver capable of delivering 2W per channel into a 4Ω load. Six analogue inputs are provided, each supporting single -ended or differential input modes. In differential mode, the input path SNR is 106d B (16kHz sample rate, ie. wideband voice mode). The ADC input paths can be bypassed, supporting up to 8 channels of digital microphone input. The audio CODEC is controlled direc tly via register access . The simple analogue architect ure, combined with the in tegrated tone generator, enables simple device configuration and testing, minimising debug time and reducing software effort. The WM8281 output drivers are designed to support as many different system architectures as possible. Each output has a dedicated DAC which allows mixing, equalisation, filtering, gain and other audio processing to be configured independently for each channel. This allows each signal path to be individually tailored for the load characteristics. All outputs have integrated pop and cl ick suppression features. The headphone output drivers are ground -referenced, powered from an integrated charge pump , enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. Ground loop feedback is incorporated, providing rejection of n oise on the ground connections. A mono mode is available on the headphone outputs; this configures the drivers as differential (BTL) outputs, suitable for an earpiece or hearing aid coil. The Class D speaker drivers deliver excellent power efficiency. High PSRR, low leakage and optimised supply voltage ranges enable powering from switching regulators or directly from the battery. Battery current consumption is minimised across a wide variet y of voice communication and multimedia playback use cases.

44 Rev 4.0 The WM8281 is cost -optimised for a wide range of mobile phone applications, and features two channels of Class D power amplification. For applications requiring more than two channels of power amplification, the PDM output channels can be used to drive up to four external PDM -input speaker drivers. In applications where stereo loudspeakers are physically widely separated, the PDM outputs can ease layout and EMC by avoiding the need to run the Class -D speaker outputs over long distances and interconnects. DIGITAL AUDIO CORE The WM8281 uses a core architecture based on all -digital signal routing, making digital audio effects available on all signal paths, regardless of whether the source data input i s analogue or digital. The digital mixing desk allows different audio effects to be applied simultaneously on many independent paths, whilst also supporting a variety of sample rates concurrently. This helps support many new audio use-cases. Soft mute and un-mute control allows smooth transitions between use-cases without interrupting existing audio streams elsewhere. The Cirrus Logic Ambient Noise Cancellation (ANC) processor within the WM8281 provides the capability to improve the intelligibility of a voi ce call by using destructive interference to reduce the acoustic energy of the ambient sound. The stereo ANC capability supports a wide variety of headset/handset applications. The Cirrus Logic ANC technology supports receive (RX) path noise cancellation. Transmit (TX) path noise reduction, and multi-mic Acoustic Echo Cancellation ( AEC) algorithms are also supported . The WM8281 is ideal for mobile telephony, providing enhanced voice communication quality for near -end and far-end handset users. The WM8281 digital core provides an extensive capability for programmable signal processing algorithms. The DSP can support functions such as wind noise, side -tone and other programmable filters. A wide range of application-specific filters and audio enhancements can also be implemented, including Dynamic Range Control (DRC), Multi -band Compression (MBC), and Virtual Surround Sound (VSS) . These digital effects can be used to improve audibility and stereo imaging while minimising supply current. Highly flexible digita l mixing, including mixing between audio interfaces , is possible . The WM8281 performs multi-channel full-duplex asynchronous sample rate conversion, providing use-case flexibility across a broad range of system architectures. Automatic sample rate detectio n is provided, enabling seamless wideband/narrowband voice call handover. Dynamic Range Controller (DRC) functions are available for optimising audio signal levels. In playback modes, the DRC can be used to maximise loudness, while limiting the signal leve l to avoid distortion, clipping or batter y droop, in particular for high -power output drivers such as speaker amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable. The 5 -band parametric equaliser ( EQ) functio ns can be used to compensate for the frequency characteristics of the output transducers. EQ functions can be cascaded to provide additional frequency control. Programmable high-pass and low-pass filters are also available for general filtering applications such as removal of wind and other low-frequency noise. DIGITAL INTERFACES Three serial digital audio interface s (AIFs) each support PCM, TDM and I2S data formats for compatibility with most industry -standard chipsets . AIF1 supports eight input/output channels; AIF2 supports six input/output channels; AIF3 supports two input/output channels. Bidirectional operation at sample rates up to 192kHz is supported. Eight digital PDM input channels are available (four stereo in terfaces); these are typically used for digital microphones, powered from the integrated MICBIAS power supply regulators. Four PDM output channels are also available (two stereo interfaces); these are typically used for external p ower amplifiers. Embedded mute codes provide a control mechanism for external PDM-input devices. The WM8281 features a MIPI -compliant SLIMbus interface, providing eight channels of audio input/output. Mixed audio sample rates are supported on the SLIMbus interface. The SLIMbus interface also supports read/write access to the WM8281 control registers. The WM8281 is equipped with an I2C/SPI control interface and an I2C-only control interface. The I2C slave port operates up to 3.4MHz; the SPI ports operate up to 26MHz. Full access to t he register map is also provided via the SLIMbus port.

Rev 4.0 45 OTHER FEATURES The WM8281 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. The phase relationship between the two generators is confi gurable, providing flexibility in creating differential signals, or for test scenarios. A white noise generator is provided, which can be routed within the digital core. The noise generator can provide ‘comfort noise’ in cases where silence (digital mute) is not desirable. Two Pulse Width Modulation (PWM) signal generators are incorporated. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. The PWM signal generators can be output directly on a GPIO pin. The WM8281 provides 5 GPIO pins, supporting selectable input/out put functions for interfacing, detection of external hardware, and to provide logic outputs to other devices. Comprehensive Interrupt (IRQ) functionality is also provided for monitoring internal and external event conditions. A signal generator for control ling haptics devices is included, compatible with both Eccentric Rotating Mass (ERM) and Linear Resonant Actuator (LRA) haptic devices. The haptics signal generator is highly configurable, and can execute programmable drive event profiles, including revers e drive control. An external vibe actuator can be driven directly by the Class D speaker output. The WM8281 can be powered from a 1.8V external supply. A separate supply (4.2V) is typically required for the Class D sp eaker driver. Integrated Charge Pump and LDO Regulators circuits are used to generate supply rails for internal functions and to support powering or biasing of external microphones. A smart accessory interface is included, supporting most standard 3.5mm accessories. Jack detection, accessory sensing and impedance measurement is provided , for external accessory and push-button detection . Accessory detection can be used as a ‘Wake -Up’ trigger from low -power standby. Microphone activity detection with interrupt is also available. System clocking can be derived from the MCLK1 or MCLK2 input pins. Alternatively, the SLIMbus interface, or the audio interfaces (configured in Slave mode), can be used to provide a clock reference. Two integrated Frequency Locked Loop ( FLL) circuits provide support for a wide range of clocking configurations, including the use of a 32kHz input clock reference.

46 Rev 4.0 INPUT SIGNAL PATH The WM8281 has eight highly flexible input channels . Selectable combinations of up to six analogue (mic or line) or eight digital input configurations are supported. The analogue input paths support single -ended and differential modes, programmable gain control and are digitised using a high performance 24-bit sigma-delta ADC. The digital input paths interface directly with external digital microph ones; a separate microphone interface clock is provided for 4 separate stereo pairs of digital microphones. Digital delay can be applied to any of the digital input paths; this can be used for phase adjustment of any digital input, including directional control of multiple microphones. Three microphone bias (MICBIAS) generators are available, which provide a low noise referen ce for biasing electret condense r microphones (ECMs) or for use as a low noise supply for MEMS microphones and digital microphones. Digital volume control is available on all inputs (analogue and digital), with programmable ramp control for smooth, glitch -free operation. Any pair of analogue or digital inputs may be selected as input to the Ambient Noise Cancellation (ANC) processing function. The IN1L and IN1R input signal paths and control registers are illustrated in Figure 13. The IN2 and IN3 signal paths are equivalent to the IN1 signal path. The IN4 signal path supports digital microphone input only. IN1L_PGA_VOL [6:0] ADC IN1_MODE [1:0] 00 = Differential IN1xP – IN1xN 01 = Single-ended IN1xP (non-inverting) 10 = Digital Microphone 11 = Reserved IN1L_ENA IN1R_ENA IN1RN/DMICDAT1 IN1RP ADC IN1LN/DMICCLK1 IN1LP IN1R_PGA_VOL [6:0] IN1_DMIC_SUP [1:0] IN1L_DMIC_DLY [5:0] IN1R_DMIC_DLY [5:0] IN1_OSR 00 = 1.536MHz 01 = 3.072MHz 10 = 6.144MHz 11 = 768kHz IN1L_VOL [7:0] IN1R_VOL [7:0] CLK DAT IN1L_HPF IN1R_HPF IN_HPF_CUT[2:0]Digital Mic Interface Figure 13 Input Signal Paths

48 Rev 4.0 ANALOGUE LINE INPUT Line inputs can be connected to the WM8281 in a similar manner to the microphone inputs described above. Single-ended and differential modes are supported on each of the six analogue input paths. The applicable mode (single -ended or differential) is selected using the IN n_MODE register s, as described later. Note that the mode is configurable for each stereo pair of inputs; the Left and Right channels of any pair of inputs are always in the same mode. The analogue line input configurations are illustrated in Figure 18 and Figure 19. Note that the microphone bias (MICBIAS) is not used for line input connections. GND Line To ADC- PGA VMID IN1xN, IN2xN, IN3xN IN1xP, IN2xP, IN3xP To ADC- PGA VMID IN1xN, IN2xN, IN3xN IN1xP, IN2xP, IN3xP Line Figure 18 Single-Ended Line Input Figure 19 Differential Line Input DIGITAL MICROPHONE INPUT Up to eight digital microphones can be connected to the WM8281. The digital microphone mode is selected using the IN n_MODE register s, as described later. Note that the mode is configurable for each stereo pair of inputs; the Left and Right channels of any pair of inputs are always in the same mode. In digital microphone mode, two channels of audio data are mult iplexed on the DMICDAT1, DMICDAT2, DMICDAT3 or DMICDAT 4 pins. Each of these stereo interfaces is clocked using the respective DMICCLK1, DMICCLK2, DMICCLK3 or DMICCLK4 pin. When digital microphone input is enabled, the WM8281 outputs a clock signal on the applicable DMICCLKn pin(s). The DMICCLK n frequency is controlled by the respective IN n_OSR register, as described in Table 1. See Table 3 for details of the INn_OSR registers. Note that, if the 768kHz DMICCLKn frequency is selected for one or more of the digital microphone input paths, then the Input Path sample rate (all input paths) is valid in the range 8kHz to 16kHz only. Note that the DMICCLK n frequencies noted in Table 1 assume that the SYSCLK frequency is a multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz (SYSCLK_FRAC=1), then the DMICCLKn frequencies will be scaled accordingly. CONDITION DMICCLKn FREQUENCY SIGNAL PASSBAND INn_OSR = 00 1.536MHz up to 20kHz INn_OSR = 01 3.072MHz up to 20kHz INn_OSR = 10 6.144MHz up to 96kHz INn_OSR = 11 768kHz up to 8kHz Table 1 DMICCLK Frequency The voltage reference for each digital microphone interface is selectable, using the IN n_DMIC_SUP registers. Each interface may be referenced to MICVDD, or to the MICBIAS1 , MICBIAS2 or MICBIAS3 levels. A pair of digital microphones is connected as illustrated in Figure 20. The microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic transmits a data bit when DM ICCLK is low. The WM8281 samples the digital microphone data at the end of each DMICCLK phase. Each microphone must tri -state its data output when the other microphone is transmitting.

50 Rev 4.0 INPUT SIGNAL PATH ENABLE The input signal paths are enabled using the register bits described in Table 2. The respective bit(s) must be enabled for analogue or digital input on the respective input path(s). The input signal paths are muted by default. It is recomm ended that de-selecting the mute should be the final step of the path enable control sequence. Similarly, the mute should be selected as the first step of the path disable control sequence. The input signal path mute functions are controlled using the register bits described in Table 4. The MICVDD power domain must be enabled when using the analogue input signal path(s). This power domain is provided using an internal Charge Pump (CP2) and LDO Regulator (LDO2). See “Charge Pumps, Regulators and Voltage Reference” for details of these circuits. The system clock, SYSCLK, must be confi gured and enabled before any audio path is enabled. The ASYNCCLK and 32kHz clock may also be required, depending on the path configuration. See “Clocking and Sample Rates” for details of the system clocks. The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the input signal paths and associated ADCs. If an attempt is made to enable an input signal path, and there are insu fficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interr upt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Register R7 69 indicate the status of each of the input signal paths. If an Underclocked Error condition occurs, then the se bits provide readback of wh ich input signal path(s) have been successfully enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R768 (0300h) Input Enables

7 IN4L_ENA 0 Input Path 4 (Left) Enable

0 = Disabled 1 = Enabled

6 IN4R_ENA 0 Input Path 4 (Right) Enable

0 = Disabled 1 = Enabled

5 IN3L_ENA 0 Input Path 3 (Left) Enable

0 = Disabled 1 = Enabled

4 IN3R_ENA 0 Input Path 3 (Right) Enable

0 = Disabled 1 = Enabled

3 IN2L_ENA 0 Input Path 2 (Left) Enable

0 = Disabled 1 = Enabled

2 IN2R_ENA 0 Input Path 2 (Right) Enable

0 = Disabled 1 = Enabled

1 IN1L_ENA 0 Input Path 1 (Left) Enable

0 = Disabled 1 = Enabled

0 IN1R_ENA 0 Input Path 1 (Right) Enable

0 = Disabled 1 = Enabled R769 (0301h) Input Enables Status

7 IN4L_ENA_STS 0 Input Path 4 (Left) Enable Status

0 = Disabled 1 = Enabled

6 IN4R_ENA_STS 0 Input Path 4 (Right) Enable Status

0 = Disabled 1 = Enabled

5 IN3L_ENA_STS 0 Input Path 3 (Left) Enable Status

0 = Disabled 1 = Enabled

Rev 4.0 51 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

4 IN3R_ENA_STS 0 Input Path 3 (Right) Enable Status

0 = Disabled 1 = Enabled

3 IN2L_ENA_STS 0 Input Path 2 (Left) Enable Status

0 = Disabled 1 = Enabled

2 IN2R_ENA_STS 0 Input Path 2 (Right) Enable Status

0 = Disabled 1 = Enabled

1 IN1L_ENA_STS 0 Input Path 1 (Left) Enable Status

0 = Disabled 1 = Enabled

0 IN1R_ENA_STS 0 Input Path 1 (Right) Enable Status

0 = Disabled 1 = Enabled Table 2 Input Signal Path Enable INPUT SIGNAL PATH SAMPLE RATE CONTROL The input signal paths may be selected as input to the digital mixers or signal processing functions within the WM8281 digital core. The sample rate for the input signal paths is configured using the IN_RATE register - see Table 23 within the “Digital Core” section. Note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. INPUT SIGNAL PATH CONFIGURATION The WM8281 supports eight input signal paths. Each pair of inputs (IN1, IN2 and IN3) can be configured as single -ended, differential, or digital microphone configuration. Note that the mode is configurable for each stereo pair of inputs; the Left and Right channels of any pair of inputs are always in the same mode. The IN4 signal path supports digital microphone input only. The input signal path configuration is selected using the IN n_MODE registers (where ‘n’ identifies th e associated input). The external circuit configurations are illustrated on the previous pages. A configurable high pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off frequency is selected using the IN_H PF_CUT register. The filter can be enabled on each path independently using the INnx_HPF bits. The analogue input signal paths (single -ended or differential) each incorporate a PGA to provide gain in the range 0dB to +31dB in 1dB steps. Note that these PGA s do not provide pop suppression functions; it is recommended that the gain should not be adjusted whilst the respective signal path is enabled. The analogue input PGA gain is controlled using the IN nL_PGA_VOL and INnR_PGA_VOL registers. Note that separate volume control is provided for the Left and Right channels of each stereo pair. When the input signal path is configured for digital microphone input, the voltage reference for the associated input/output pins is selectable using the IN n_DMIC_SUP registers - each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels. When the input signal path is configured for digital microphone input, the respective DMICCLKn frequency can be configured using the INn_OSR register bits. Note that, if a digital microphone path is selected as a source for the Rx ANC function (see Table 6), the respective DMICCLKn frequency will be 3.072MHz, regardless of the INn_OSR setting. A digital delay may be applied to any of the digital microphone input channels. This feature can be used for phase adjustment of any digital input, including directional control of multiple microphones. The delay is controlled using the INnL_DMIC_DLY and INnR_DMIC_DLY registers. The MICVDD voltage is generated by an internal Charge Pump and LDO Regulator. The MICBIAS1, MICBIAS2 and MICBIAS3 outputs are derived from MICVDD - see “Charge Pumps, Regulators and Voltage Reference”.

52 Rev 4.0 The input signal paths are configured using the register bits described in Table 3. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R780 (030Ch) HPF Control 2:0 IN_HPF_CUT [2:0]

010 Input Path HPF Select

Controls the cut-off frequency of the input path HPF circuits. 000 = 2.5Hz 001 = 5Hz 010 = 10Hz 011 = 20Hz 100 = 40Hz All other codes are Reserved R784 (0310h) IN1L Control

15 IN1L_HPF 0 Input Path 1 (Left) HPF Enable

0 = Disabled 1 = Enabled 14:13 IN1_OSR [1:0] 01 Input Path 1 DMIC Oversample Rate When digital microphone input is selected (IN1_MODE=10), this field controls the sample rate as below: 00 = 1.536MHz 01 = 3.072MHz 10 = 6.144MHz 11 = 768kHz When IN1_OSR=11, the Input Path sample rate (for all input paths) must be in the range 8kHz to 16kHz. If Input Path 1 DMIC is selected as a source for the Rx ANC function, the DMICCLK1 frequency will be set to 3.072MHz. 12:11 IN1_DMIC_SUP [1:0]

00 Input Path 1 DMIC Reference Select

(Sets the DMICDAT1 and DMICCLK1 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 10:9 IN1_MODE [1:0] 00 Input Path 1 Mode 00 = Differential (IN1xP - IN1xN) 01 = Single-ended (IN1xP) 10 = Digital Microphone 11 = Reserved 7:1 IN1L_PGA_VOL [6:0] 40h Input Path 1 (Left) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R786 (0312h) DMIC1L Control 5:0 IN1L_DMIC_DLY [5:0] 00h Input Path 1 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN1_OSR.) R788 (0314h) IN1R

15 IN1R_HPF 0 Input Path 1 (Right) HPF Enable

0 = Disabled 1 = Enabled

Rev 4.0 53 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Control 7:1 IN1R_PGA_VOL [6:0] 40h Input Path 1 (Right) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R790 (0316h) DMIC1R Control 5:0 IN1R_DMIC_DLY [5:0] 00h Input Path 1 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN1_OSR.) R792 (0318h) IN2L Control

15 IN2L_HPF 0 Input Path 2 (Left) HPF Enable

0 = Disabled 1 = Enabled 14:13 IN2_OSR [1:0] 01 Input Path 2 DMIC Oversample Rate When digital microphone input is selected (IN2_MODE=10), this field controls the sample rate as below: 00 = 1.536MHz 01 = 3.072MHz 10 = 6.144MHz 11 = 768kHz When IN2_OSR=11, the Input Path sample rate (for all input paths) must be in the range 8kHz to 16kHz. If Input Path 2 DMIC is selected as a source for the Rx ANC function, the DMICCLK2 frequency will be set to 3.072MHz. 12:11 IN2_DMIC_SUP [1:0]

00 Input Path 2 DMIC Reference Select

(Sets the DMICDAT2 and DMICCLK2 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 10:9 IN2_MODE [1:0] 00 Input Path 2 Mode 00 = Differential (IN2xP - IN2xN) 01 = Single-ended (IN2xP) 10 = Digital Microphone 11 = Reserved 7:1 IN2L_PGA_VOL [6:0] 40h Input Path 2 (Left) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R794 (031Ah) DMIC2L Control 5:0 IN2L_DMIC_DLY [5:0] 00h Input Path 2 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN2_OSR.)

54 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R796 (031Ch) IN2R Control

15 IN2R_HPF 0 Input Path 2 (Right) HPF Enable

0 = Disabled 1 = Enabled 7:1 IN2R_PGA_VOL [6:0] 40h Input Path 2 (Right) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R798 (031Eh) DMIC2R Control 5:0 IN2R_DMIC_DLY [5:0] 00h Input Path 2 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN2_OSR.) R800 (0320h) IN3L Control

15 IN3L_HPF 0 Input Path 3 (Left) HPF Enable

0 = Disabled 1 = Enabled 14:13 IN3_OSR [1:0] 01 Input Path 3 DMIC Oversample Rate When digital microphone input is selected (IN3_MODE=10), this field controls the sample rate as below: 00 = 1.536MHz 01 = 3.072MHz 10 = 6.144MHz 11 = 768kHz When IN3_OSR=11, the Input Path sample rate (for all input paths) must be in the range 8kHz to 16kHz. If Input Path 3 DMIC is selected as a source for the Rx ANC function, the DMICCLK3 frequency will be set to 3.072MHz. 12:11 IN3_DMIC_SUP [1:0]

00 Input Path 3 DMIC Reference Select

(Sets the DMICDAT3 and DMICCLK3 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 10:9 IN3_MODE [1:0] 00 Input Path 3 Mode 00 = Differential (IN3xP - IN3xN) 01 = Single-ended (IN3xP) 10 = Digital Microphone 11 = Reserved 7:1 IN3L_PGA_VOL [6:0] 40h Input Path 3 (Left) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved

Rev 4.0 55 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R802 (0322h) DMIC3L Control 5:0 IN3L_DMIC_DLY [5:0] 00h Input Path 3 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN3_OSR.) R804 (0324h) IN3R Control

15 IN3R_HPF 0 Input Path 3 (Right) HPF Enable

0 = Disabled 1 = Enabled 7:1 IN3R_PGA_VOL [6:0] 40h Input Path 3 (Right) PGA Volume (Applicable to analogue inputs only) 00h to 3Fh = Reserved 40h = 0dB 41h = 1dB 42h = 2dB … (1dB steps) 5F = 31dB 60h to 7Fh = Reserved R806 (0326h) DMIC3R Control 5:0 IN3R_DMIC_DLY [5:0] 00h Input Path 3 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN3_OSR.) R808 (0328h) IN4L Control

15 IN4L_HPF 0 Input Path 4 (Left) HPF Enable

0 = Disabled 1 = Enabled 14:13 IN4_OSR [1:0] 01 Input Path 4 DMIC Oversample Rate Controls the DMIC4 sample rate as below: 00 = 1.536MHz 01 = 3.072MHz 10 = 6.144MHz 11 = 768kHz When IN4_OSR=11, the Input Path sample rate (for all input paths) must be in the range 8kHz to 16kHz. If Input Path 4 DMIC is selected as a source for the Rx ANC function, the DMICCLK4 frequency will be set to 3.072MHz. 12:11 IN4_DMIC_SUP [1:0]

00 Input Path 4 DMIC Reference Select

(Sets the DMICDAT4 and DMICCLK4 logic levels) 00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3 R810 (032Ah) DMIC4L Control 5:0 IN4L_DMIC_DLY [5:0] 00h Input Path 4 (Left) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN4_OSR.) R812 (032Ch) IN4R Control

15 IN4R_HPF 0 Input Path 4 (Right) HPF Enable

0 = Disabled 1 = Enabled R814 (032Eh) DMIC4R Control 5:0 IN4R_DMIC_DLY [5:0] 00h Input Path 4 (Right) Digital Delay (Applicable to digital input only) LSB = 1 sample, Range is 0 to 63. (Sample rate is controlled by IN4_OSR.) Table 3 Input Signal Path Configuration

56 Rev 4.0 INPUT SIGNAL PATH DIGITAL VOLUME CONTROL A digital volume control is provided on each of the input signal paths, providing -64dB to +31.5dB gain control in 0.5dB steps. An independent mute control is also provided for each input signal path. Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. For increasing gain (or un -mute), the rate is controlled by the IN_VI_RAMP register. For decreasing gain (or mute), the rate is controlled by the IN_VD_RAMP register. Note that the IN_VI_RAMP and IN_VD_RAMP registers should not be changed while a volume ramp is in progress. The IN_VU bits control the loading of the input sign al path digital volume and mute controls. When IN_VU is set to 0, the digital volume and mute settings will be loaded into the respective control register, but will not actually change the signal path gain. The digital volume and mute settings on all of the input signal paths are updated when a 1 is written to IN_VU. This makes it possible to update the gain of multiple signal paths simultaneously. Note that, although the digital volume control registers provide 0.5dB steps, the internal circuits provide signal gain adjustment in 0.1 25dB steps. This allows a very high degree of gain control, and smooth volume ramping under all operating conditions. The digital volume control register fields are described in Table 4 and Table 5. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R777 (0309h) Input Volume Ramp 6:4 IN_VD_RAMP [2:0]

010 Input Volume Decreasing Ramp Rate

(seconds/6dB) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms This register should not be changed while a volume ramp is in progress. 2:0 IN_VI_RAMP [2:0]

010 Input Volume Increasing Ramp Rate

(seconds/6dB) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms This register should not be changed while a volume ramp is in progress. R785 (0311h) ADC Digital Volume 1L

9 IN_VU Input Signal Paths Volume and Mute

Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN1L_MUTE 1 Input Path 1 (Left) Digital Mute

0 = Un-mute 1 = Mute

Rev 4.0 57 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 IN1L_VOL [7:0] 80h Input Path 1 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R789 (0315h) ADC Digital Volume Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN1R_MUTE 1 Input Path 1 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 IN1R_VOL [7:0] 80h Input Path 1 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R793 (0319h) ADC Digital Volume 2L Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN2L_MUTE 1 Input Path 2 (Left) Digital Mute

0 = Un-mute 1 = Mute 7:0 IN2L_VOL [7:0] 80h Input Path 2 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R797 (031Dh) ADC Digital Volume Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN2R_MUTE 1 Input Path 2 (Right) Digital Mute

0 = Un-mute 1 = Mute

58 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 IN2R_VOL [7:0] 80h Input Path 2 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R801 (0321h) ADC Digital Volume 3L Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN3L_MUTE 1 Input Path 3 (Left) Digital Mute

0 = Un-mute 1 = Mute 7:0 IN3L_VOL [7:0] 80h Input Path 3 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R805 (0325h) ADC Digital Volume Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN3R_MUTE 1 Input Path 3 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 IN3R_VOL [7:0] 80h Input Path 3 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R809 (0329h) ADC Digital Volume 4L Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN4L_MUTE 1 Input Path 4 (Left) Digital Mute

0 = Un-mute 1 = Mute

Rev 4.0 59 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 IN4L_VOL [7:0] 80h Input Path 4 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) R813 (032Dh) ADC Digital Volume Writing a 1 to this bit will cause the Input Signal Paths Volume and Mute settings to be updated simultaneously

8 IN4R_MUTE 1 Input Path 4 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 IN4R_VOL [7:0] 80h Input Path 4 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 5 for volume range) Table 4 Input Signal Path Digital Volume Control

60 Rev 4.0 Input Volume Register Volume (dB) Input Volume Register Volume (dB) Input Volume Register Volume (dB) Input Volume Register Volume (dB) 00h -64.0 40h -32.0 80h 0.0 C0h Reserved 01h -63.5 41h -31.5 81h 0.5 C1h Reserved 02h -63.0 42h -31.0 82h 1.0 C2h Reserved 03h -62.5 43h -30.5 83h 1.5 C3h Reserved 04h -62.0 44h -30.0 84h 2.0 C4h Reserved 05h -61.5 45h -29.5 85h 2.5 C5h Reserved 06h -61.0 46h -29.0 86h 3.0 C6h Reserved 07h -60.5 47h -28.5 87h 3.5 C7h Reserved 08h -60.0 48h -28.0 88h 4.0 C8h Reserved 09h -59.5 49h -27.5 89h 4.5 C9h Reserved 0Ah -59.0 4Ah -27.0 8Ah 5.0 CAh Reserved 0Bh -58.5 4Bh -26.5 8Bh 5.5 CBh Reserved 0Ch -58.0 4Ch -26.0 8Ch 6.0 CCh Reserved 0Dh -57.5 4Dh -25.5 8Dh 6.5 CDh Reserved 0Eh -57.0 4Eh -25.0 8Eh 7.0 CEh Reserved 0Fh -56.5 4Fh -24.5 8Fh 7.5 CFh Reserved 10h -56.0 50h -24.0 90h 8.0 D0h Reserved 11h -55.5 51h -23.5 91h 8.5 D1h Reserved 12h -55.0 52h -23.0 92h 9.0 D2h Reserved 13h -54.5 53h -22.5 93h 9.5 D3h Reserved 14h -54.0 54h -22.0 94h 10.0 D4h Reserved 15h -53.5 55h -21.5 95h 10.5 D5h Reserved 16h -53.0 56h -21.0 96h 11.0 D6h Reserved 17h -52.5 57h -20.5 97h 11.5 D7h Reserved 18h -52.0 58h -20.0 98h 12.0 D8h Reserved 19h -51.5 59h -19.5 99h 12.5 D9h Reserved 1Ah -51.0 5Ah -19.0 9Ah 13.0 DAh Reserved 1Bh -50.5 5Bh -18.5 9Bh 13.5 DBh Reserved 1Ch -50.0 5Ch -18.0 9Ch 14.0 DCh Reserved 1Dh -49.5 5Dh -17.5 9Dh 14.5 DDh Reserved 1Eh -49.0 5Eh -17.0 9Eh 15.0 DEh Reserved 1Fh -48.5 5Fh -16.5 9Fh 15.5 DFh Reserved 20h -48.0 60h -16.0 A0h 16.0 E0h Reserved 21h -47.5 61h -15.5 A1h 16.5 E1h Reserved 22h -47.0 62h -15.0 A2h 17.0 E2h Reserved 23h -46.5 63h -14.5 A3h 17.5 E3h Reserved 24h -46.0 64h -14.0 A4h 18.0 E4h Reserved 25h -45.5 65h -13.5 A5h 18.5 E5h Reserved 26h -45.0 66h -13.0 A6h 19.0 E6h Reserved 27h -44.5 67h -12.5 A7h 19.5 E7h Reserved 28h -44.0 68h -12.0 A8h 20.0 E8h Reserved 29h -43.5 69h -11.5 A9h 20.5 E9h Reserved 2Ah -43.0 6Ah -11.0 AAh 21.0 EAh Reserved 2Bh -42.5 6Bh -10.5 ABh 21.5 EBh Reserved 2Ch -42.0 6Ch -10.0 ACh 22.0 ECh Reserved 2Dh -41.5 6Dh -9.5 ADh 22.5 EDh Reserved 2Eh -41.0 6Eh -9.0 AEh 23.0 EEh Reserved 2Fh -40.5 6Fh -8.5 AFh 23.5 EFh Reserved 30h -40.0 70h -8.0 B0h 24.0 F0h Reserved 31h -39.5 71h -7.5 B1h 24.5 F1h Reserved 32h -39.0 72h -7.0 B2h 25.0 F2h Reserved 33h -38.5 73h -6.5 B3h 25.5 F3h Reserved 34h -38.0 74h -6.0 B4h 26.0 F4h Reserved 35h -37.5 75h -5.5 B5h 26.5 F5h Reserved 36h -37.0 76h -5.0 B6h 27.0 F6h Reserved 37h -36.5 77h -4.5 B7h 27.5 F7h Reserved 38h -36.0 78h -4.0 B8h 28.0 F8h Reserved 39h -35.5 79h -3.5 B9h 28.5 F9h Reserved 3Ah -35.0 7Ah -3.0 BAh 29.0 FAh Reserved 3Bh -34.5 7Bh -2.5 BBh 29.5 FBh Reserved 3Ch -34.0 7Ch -2.0 BCh 30.0 FCh Reserved 3Dh -33.5 7Dh -1.5 BDh 30.5 FDh Reserved 3Eh -33.0 7Eh -1.0 BEh 31.0 FEh Reserved 00. -32.5 7Fh -0.5 BFh 31.5 FFh Reserved Table 5 Input Signal Path Digital Volume Range

noise reduction in a variety of different operating conditions. IN_RXANCL_SEL and IN_RXANCR_SEL registers, as described in Table 6. See “Ambient Noise Cancellation” for further details of the ANC function.

000 Right Input source for Rx ANC function

000 Left Input source for Rx ANC function

DMICDAT4 pins. This provides a flexible capability for interfacing with other devices. Table 7. Note that, if the DMICDA T1, DMICDAT2, DMICDAT3 or DMICDAT4 digital microphone input paths are disabled, then the pull-down will be disabled on the respective pin.

3 DMICDAT4_PD 0 DMICDAT4 Pull-Down Control

2 DMICDAT3_PD 0 DMICDAT3 Pull-Down Control

1 DMICDAT2_PD 0 DMICDAT2 Pull-Down Control

0 DMICDAT1_PD 0 DMICDAT1 Pull-Down Control

be supported between the available processing blocks. compression, or virtual surround sound and other audio enhancements. sample rates and/or referenced to asynchronous clock domains. DSP configuration data must be downloaded to the WM8281 each time the device is powered up. please contact your local Cirrus Logic representative for more details. cases where silence (digital mute) is not desirable. that this is described in a separate section, see “Ambient Noise Cancellation”. of the external digital interface paths is provided in Figure 23. Figure 41. The full list of digital mixer control registers is provided in the “ Register Map ” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8.

Rev 4.0 63 Silence (mute) (00h) IN1L signal path (10h) IN1R signal path (11h) IN2L signal path (12h) IN2R signal path (13h) IN3L signal path (14h) IN3R signal path (15h) IN4L signal path (16h) IN4R signal path (17h) AEC Loopback (08h) DSP DSP1 Channel 1 (68h) DSP1 Channel 2 (69h) DSP1 Channel 3 (6Ah) DSP1 Channel 4 (6Bh) DSP1 Channel 5 (6Ch) DSP1 Channel 6 (6Dh) DSP DSP2 Channel 1 (70h) DSP2 Channel 2 (71h) DSP2 Channel 3 (72h) DSP2 Channel 4 (73h) DSP2 Channel 5 (74h) DSP2 Channel 6 (75h) DSP DSP3 Channel 1 (78h) DSP3 Channel 2 (79h) DSP3 Channel 3 (7Ah) DSP3 Channel 4 (7Bh) DSP3 Channel 5 (7Ch) DSP3 Channel 6 (7Dh) DSP DSP4 Channel 1 (80h) DSP4 Channel 2 (81h) DSP4 Channel 3 (82h) DSP4 Channel 4 (83h) DSP4 Channel 5 (84h) DSP4 Channel 6 (85h) LHPF4 (63h) LHPF LHPF3 (62h) LHPF LHPF2 (61h) LHPF LHPF1 (60h) LHPF EQ4 (53h) EQ EQ3 (52h) EQ EQ2 (51h) EQ EQ1 (50h) EQ DRC 2 Right (5Bh) DRC DRC 2 Left (5Ah) DRC DRC 1 Right (59h) DRC DRC 1 Left (58h) DRC Isochronous Sample Rate Converter (ISRC) ISRC1 INT1 (A0h) ISRC1 INT2 (A1h) ISRC1 DEC1 (A4h) ISRC1 DEC2 (A5h) ISRC1 INT3 (A2h) ISRC1 INT4 (A3h) ISRC1 DEC3 (A6h) ISRC1 DEC4 (A7h) Isochronous Sample Rate Converter (ISRC) ISRC2 INT1 (A8h) ISRC2 INT2 (A9h) ISRC2 DEC1 (ACh) ISRC2 DEC2 (ADh) ISRC2 INT3 (AAh) ISRC2 INT4 (ABh) ISRC2 DEC3 (AEh) ISRC2 DEC4 (AFh) Isochronous Sample Rate Converter (ISRC) ISRC3 INT1 (B0h) ISRC3 INT2 (B1h) ISRC3 DEC1 (B4h) ISRC3 DEC2 (B5h) ISRC3 INT3 (B2h) ISRC3 INT4 (B3h) ISRC3 DEC3 (B6h) ISRC3 DEC4 (B7h) Mic Mute Mixer (0Ch) (To GPIO pin) PWM (To GPIO pin) PWM ASRC1 Left (90h) ASRC1 Right (91h) ASRC2 Left (92h) ASRC2 Right (93h) Asynchronous Sample Rate Converter (ASRC) Tone Generator 1 (04h) Tone Generator 2 (05h) Tone Generator Noise Generator (0Dh) White Noise Generator Haptic Output (06h) Haptic Signal Generator Figure 22 Digital Core - Internal Signal Processing

Rev 4.0 65 The ASRC, ISRC, and DSP Aux Input functions support selectable input sources, but do not incorporate any digital mixing. The respective input source (*_SRCn) registers are identical to those of the digital mixers. The *_SRCn registers select the input source(s) for the respective mixer or signal processing block. Note that the selected input source(s) must be configured for the same sample rate as the block(s) to which they a re connected. Sample rate conversion functions are available to support flexible interconnectivity - see “ Asynchronous Sample Rate Conver ter (ASRC) ” and “ Isochronous Sample Rate Converter (ISRC)”. A status bit associated with each of the configurable input sources provides readback for the respective signal path. If an Underclocked Error condition occurs, then these bits provide readback of which signal path(s) have been successfully enabled. The generic register definition for the digital mixers is provided in Table 8. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1600 (0640h) to R3000 (0BB8h) 15 *_STSn Valid for every digital core function input (digital mixers, DSP Aux inputs, ASRC & ISRC inputs). 0 [Digital Core function] input n status 0 = Disabled 1 = Enabled 7:1 *_VOLn Valid for every digital mixer input. 40h [Digital Core mixer] input n volume -32dB to +16dB in 1dB steps 00h to 20h = -32dB 21h = -31dB 22h = -30dB ... (1dB steps) 40h = 0dB ... (1dB steps) 50h = +16dB 51h to 7Fh = +16dB 7:0 *_SRCn Valid for every digital core function input (digital mixers, DSP Aux inputs, ASRC & ISRC inputs). 00h [Digital Core function] input n source select 00h = Silence (mute) 04h = Tone generator 1 05h = Tone generator 2 06h = Haptic generator 08h = AEC loopback 0Ch = Mic Mute Mixer 0Dh = Noise generator 10h = IN1L signal path 11h = IN1R signal path 12h = IN2L signal path 13h = IN2R signal path 14h = IN3L signal path 15h = IN3R signal path 16h = IN4L signal path 17h = IN4R signal path 20h = AIF1 RX1 21h = AIF1 RX2 22h = AIF1 RX3 23h = AIF1 RX4 24h = AIF1 RX5 25h = AIF1 RX6 26h = AIF1 RX7 27h = AIF1 RX8

66 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 28h = AIF2 RX1 29h = AIF2 RX2 2Ah = AIF2 RX3 2Bh = AIF2 RX4 2Ch = AIF2 RX5 2Dh = AIF2 RX6 30h = AIF3 RX1 31h = AIF3 RX2 38h = SLIMbus RX1 39h = SLIMbus RX2 3Ah = SLIMbus RX3 3Bh = SLIMbus RX4 3Ch = SLIMbus RX5 3Dh = SLIMbus RX6 3Eh = SLIMbus RX7 3Fh = SLIMbus RX8 50h = EQ1 51h = EQ2 52h = EQ3 53h = EQ4 58h = DRC1 Left 59h = DRC1 Right 5Ah = DRC2 Left 5Bh = DRC2 Right 60h = LHPF1 61h = LHPF2 62h = LHPF3 63h = LHPF4 68h = DSP1 channel 1 69h = DSP1 channel 2 6Ah = DSP1 channel 3 6Bh = DSP1 channel 4 6Ch = DSP1 channel 5 6Dh = DSP1 channel 6 70h = DSP2 channel 1 71h = DSP2 channel 2 72h = DSP2 channel 3 73h = DSP2 channel 4 74h = DSP2 channel 5 75h = DSP2 channel 6 78h = DSP3 channel 1 79h = DSP3 channel 2 7Ah = DSP3 channel 3 7Bh = DSP3 channel 4 7Ch = DSP3 channel 5 7Dh = DSP3 channel 6 80h = DSP4 channel 1 81h = DSP4 channel 2 82h = DSP4 channel 3 83h = DSP4 channel 4 84h = DSP4 channel 5 85h = DSP4 channel 6 90h = ASRC1 Left 91h = ASRC1 Right 92h = ASRC2 Left 93h = ASRC2 Right A0h = ISRC1 INT1 A1h = ISRC1 INT2

Rev 4.0 67 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION A2h = ISRC1 INT3 A3h = ISRC1 INT4 A4h = ISRC1 DEC1 A5h = ISRC1 DEC2 A6h = ISRC1 DEC3 A7h = ISRC1 DEC4 A8h = ISRC2 INT1 A9h = ISRC2 INT2 AAh = ISRC2 INT3 ABh = ISRC2 INT4 ACh = ISRC2 DEC1 ADh = ISRC2 DEC2 AEh = ISRC2 DEC3 AFh = ISRC2 DEC4 B0h = ISRC3 INT1 B1h = ISRC3 INT2 B2h = ISRC3 INT3 B3h = ISRC3 INT4 B4h = ISRC3 DEC1 B5h = ISRC3 DEC2 B6h = ISRC3 DEC3 B7h = ISRC3 DEC4 Table 8 Digital Core Mixer Control Registers DIGITAL CORE INPUTS The digital core comprises multiple input paths as illustrated in Figure 24. Any of these inputs may be selected as a source to the digital mixers or signal processing functions within the WM8281 digital core. Note that the outputs from other blocks within the Digita l Core may also be selected as input to the digital mixers or signal processing functions within the WM8281 digital core. Those input sources, which are not shown in Figure 24, are described separately in other sections of the “ Digital Core ” description. The bracketed numbers in Figure 24, eg. “( 10h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The sample rate for the input signal paths is configured using the applicable IN_RATE, AIFn_RATE or SLIMRXn_RATE register - see Table 23. Note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.

68 Rev 4.0 Silence (mute) (00h) AEC Loopback (08h) IN1L signal path (10h) IN1R signal path (11h) IN2L signal path (12h) IN2R signal path (13h) IN3L signal path (14h) IN3R signal path (15h) IN4L signal path (16h) IN4R signal path (17h) AIF1 RX1 (20h) AIF1 RX2 (21h) AIF1 RX3 (22h) AIF1 RX4 (23h) AIF1 RX5 (24h) AIF1 RX6 (25h) AIF1 RX7 (26h) AIF1 RX8 (27h) AIF2 RX1 (28h) AIF2 RX2 (29h) AIF2 RX3 (2Ah) AIF2 RX4 (2Bh) AIF2 RX5 (2Ch) AIF2 RX6 (2Dh) AIF3 RX1 (30h) AIF3 RX2 (31h) SLIMbus RX1 (38h) SLIMbus RX2 (39h) SLIMbus RX3 (3Ah) SLIMbus RX4 (3Bh) SLIMbus RX5 (3Ch) SLIMbus RX6 (3Dh) SLIMbus RX7 (3Eh) SLIMbus RX8 (3Fh) Figure 24 Digital Core Inputs DIGITAL CORE OUTPUT MIXERS The digital core comprises multiple output paths . The output paths associated with AIF1, AIF2 and AIF3 are illustrated in Figure 25. The output paths associated with OUT1, OUT2, OUT3, OUT4, OUT5 and OUT6 are illustrated in Figure 26. The output paths associated with the SLIMbus interface are illustrated in Figure 27. A 4-input mixer is associated with each output. The 4 input sources are selectable in each case, and independent volume control is provided for each path. The AIF1, AIF2 and AIF3 output mixer control registers (see Figure 25) are located at register addresses R1792 (700h) through to R1935 (78Fh). The OUT1, OUT2, OUT3, OUT4, OUT5 and OUT6 output mixer control registers (see Figure 26) are located at addresses R1664 (680h ) through to R1759 (6DFh). The SLIMbus output mixer control registers (see Figure 27) are located at addresses R1984 (7C0h) through to R2047 (7FFh). The full list of digital mixer control registers is provided in the “ Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input source(s) must be configured for the same sample rate as the mixer to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The sample rate for the output signal paths is configured using the applicable OUT_RATE , AIFn_RATE or SLIMTXn_RATE register - see Table 23. Note that sample rate conversion is required when routing the output signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.

Rev 4.0 69 The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output mixer paths. If an attempt is made to enable an output mixer path, and there are insufficient SYSCLK cycles to support it , then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then the se bits provide readback of which mixer(s) have been successfully enabled. AIF2TXnMIX_VOL2 AIF2TXnMIX_VOL3 AIF2TXnMIX_VOL4 AIF2TXnMIX_VOL1AIF2TXnMIX_SRC1 AIF2TXnMIX_SRC3 AIF2TXnMIX_SRC4 AIF2TXnMIX_SRC2 AIF2 TXn AIF3TXnMIX_VOL2 AIF3TXnMIX_VOL3 AIF3TXnMIX_VOL4 AIF3TXnMIX_VOL1AIF3TXnMIX_SRC1 AIF3TXnMIX_SRC3 AIF3TXnMIX_SRC4 AIF3TXnMIX_SRC2 AIF3 TXn WM8281 supports 2 AIF3 Output mixers, ie. n = 1 or 2 AIF1TXnMIX_VOL2 AIF1TXnMIX_VOL3 AIF1TXnMIX_VOL4 AIF1TXnMIX_VOL1AIF1TXnMIX_SRC1 AIF1TXnMIX_SRC3 AIF1TXnMIX_SRC4 AIF1TXnMIX_SRC2 AIF1 TXn WM8280 supports 8 AIF1 Output mixers, ie. n = 1, 2, 3, 4, 5, 6, 7 or 8 WM8280 supports 6 AIF2 Output mixers, ie. n = 1, 2, 3, 4, 5 or 6 Figure 25 Digital Core AIF Outputs

72 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R707 (02C3h) Mic noise mix control

7 MICMUTE_NOIS

E_ENA

0 Mic Mute Mixer Control

0 = Mic Mix 1 = Noise Mix

6 MICMUTE_MIX_

0 Mic Mute Mixer Enable

0 = Disabled 1 = Enabled Table 9 Mic Mute Mixer Control Registers The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded digital mixing functions. If an attempt is made to enable a MICMIX or NOISEMIX signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled, and which mixer(s) could not be enabled. 5-BAND PARAMETRIC EQUALISER (EQ) The digital core provides four EQ processing blocks as illustrated in Figure 29. A 4 -input mixer is associated with each EQ. The 4 input sources are selectable in each case, and independent volume control is provided for each path. Each EQ block supports 1 output. The EQ provides selective control of 5 frequency bands as described below. The low frequency band (Band 1) filter can be configured either as a peak filter or a shelving filter. When configured as a shelving filter, is provides adjustable gain below the Band 1 cut -off frequency. As a peak filter, it provides adjustable gain within a defined frequency band that is centred on the Band 1 frequency. The mid frequency bands (Band 2, Band 3, Band 4) filters are peak filters, which provide adjustable gain around the respective centre frequency. The high frequency band (Band 5) filter is a shelving filter, which provides adjustable gain above the Band 5 cut-off frequency. EQnMIX_VOL2 EQnMIX_VOL3 EQnMIX_VOL4 EQnMIX_VOL1EQnMIX_SRC1 EQnMIX_SRC3 EQnMIX_SRC4 EQnMIX_SRC2 EQ1 (50h) EQ2 (51h) EQ3 (52h) EQ4 (53h) EQ 5-band Equaliser WM8281 supports 4 EQ blocks, ie. n = 1, 2, 3 or 4 Figure 29 Digital Core EQ Blocks

Rev 4.0 73 The EQ1, EQ2, EQ3 and EQ4 mixer control registers (see Figure 29) are located at register addresses R2176 (880h) through to R2207 (89Fh). The full list of digital mixer control registers is provided in the “ Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective EQ processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the EQ to which they are connected. Sample rate conversion functions are available to support fle xible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The bracketed numbers in Figure 29, eg. “(50h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The sample rate for the EQ function is configured using the FX_RATE register - see Table 23. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. The EQ function supports audio sample rates in the range 8kHz to 192kHz. When the DRC is enabled, the maximum sample rate for the EQ, DRC and LHPF functions is 96kHz. Sample rate conversion is required when routing the EQ signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The control registers associated with the EQ functions are described in Table 11. The cut-off or centre frequencies for the 5 -band EQ are set using the coefficients held in the registers identified in Table 10. These coefficients are derived using tools provided in Cirrus Logic’s WISCE™ evaluation board control software ; p lease contact your local Cirrus Logic representative for more details. EQ REGISTER ADDRESSES EQ1 R3602 (0E10h) to R3620 (0E24h) EQ2 R3624 (0E28h) to R3642 (0E3Ah) EQ3 R3646 (0E3Eh) to R3664 (0E53h) EQ4 R3668 (0E54h) to R3686 (0E66h) Table 10 EQ Coefficient Registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3585 (0E01h) FX_Ctrl2 15:4 FX_STS [11:0] 00h LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3600 (0E10h) EQ1_1 15:11 EQ1_B1_GAIN [4:0]

01100 EQ1 Band 1 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ1_B2_GAIN [4:0]

01100 EQ1 Band 2 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

74 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5:1 EQ1_B3_GAIN [4:0]

01100 EQ1 Band 3 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ1_ENA 0 EQ1 Enable

0 = Disabled 1 = Enabled R3601 (0E11h) EQ1_2 15:11 EQ1_B4_GAIN [4:0]

01100 EQ1 Band 4 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ1_B5_GAIN [4:0]

01100 EQ1 Band 5 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ1_B1_MODE 0 EQ1 Band 1 Mode

0 = Shelving filter 1 = Peak filter R3602 (0E12h) to R3620 (E24h) 15:0 EQ1_B1_* EQ1_B2_* EQ1_B3_* EQ1_B4_* EQ1_B5_* EQ1 Frequency Coefficients Refer to WISCE evaluation board control software for the deriviation of these field values. R3622 (0E26h) EQ2_1 15:11 EQ2_B1_GAIN [4:0]

01100 EQ2 Band 1 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ2_B2_GAIN [4:0]

01100 EQ2 Band 2 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 5:1 EQ2_B3_GAIN [4:0]

01100 EQ2 Band 3 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ2_ENA 0 EQ2 Enable

0 = Disabled 1 = Enabled R3623 (0E27h) EQ2_2 15:11 EQ2_B4_GAIN [4:0]

01100 EQ2 Band 4 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ2_B5_GAIN [4:0]

01100 EQ2 Band 5 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ2_B1_MODE 0 EQ2 Band 1 Mode

0 = Shelving filter 1 = Peak filter R3624 (0E28h) to R3642 (E3Ah) 15:0 EQ2_B1_* EQ2_B2_* EQ2_B3_* EQ2_B4_* EQ2_B5_* EQ2 Frequency Coefficients Refer to WISCE evaluation board control software for the deriviation of these field values. R3644 (0E3Ch) EQ3_1 15:11 EQ3_B1_GAIN [4:0]

01100 EQ3 Band 1 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ3_B2_GAIN [4:0]

01100 EQ3 Band 2 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 5:1 EQ3_B3_GAIN [4:0]

01100 EQ3 Band 3 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

Rev 4.0 75 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 EQ3_ENA 0 EQ3 Enable

0 = Disabled 1 = Enabled R3645 (0E3Dh) EQ3_2 15:11 EQ3_B4_GAIN [4:0]

01100 EQ3 Band 4 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ3_B5_GAIN [4:0]

01100 EQ3 Band 5 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ3_B1_MODE 0 EQ3 Band 1 Mode

0 = Shelving filter 1 = Peak filter R3646 (0E3Eh) to R3664 (E50h) 15:0 EQ3_B1_* EQ3_B2_* EQ3_B3_* EQ3_B4_* EQ3_B5_* EQ3 Frequency Coefficients Refer to WISCE evaluation board control software for the deriviation of these field values. R3666 (0E52h) EQ4_1 15:11 EQ4_B1_GAIN [4:0]

01100 EQ4 Band 1 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ4_B2_GAIN [4:0]

01100 EQ4 Band 2 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 5:1 EQ4_B3_GAIN [4:0]

01100 EQ4 Band 3 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ4_ENA 0 EQ4 Enable

0 = Disabled 1 = Enabled R3667 (0E53h) EQ4_2 15:11 EQ4_B4_GAIN [4:0]

01100 EQ4 Band 4 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range) 10:6 EQ4_B5_GAIN [4:0]

01100 EQ4 Band 5 Gain

-12dB to +12dB in 1dB steps (see Table 12 for gain range)

0 EQ4_B1_MODE 0 EQ4 Band 1 Mode

0 = Shelving filter 1 = Peak filter R3668 (0E54h) to R3686 (E66h) 15:0 EQ4_B1_* EQ4_B2_* EQ4_B3_* EQ4_B4_* EQ4_B5_* EQ4 Frequency Coefficients Refer to WISCE evaluation board control software for the deriviation of these field values. Table 11 EQ Enable and Gain Control

path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. Purpose Input / Output” and “Interrupts” for further details. DRC or LHPF signal path(s) have been successfully enabled. Figure 30. A 4 -input mixer is associated with each DRC input channel. The 4 input sources are blocks support 2 outputs each. system, or to restrict the dynamic range of an output signal path. presence of loud impulsive noises.

Rev 4.0 77 The DRC also incorporates a Noise Gate function, which pro vides additional attenuation of very low - level input signals. This means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. A Signal Detect function is provided within the DRC; t his can be used to detect the presence of an audio signal, and used to trigger other events. The Signal Detect function can be used as an Interrupt event, or as a GPIO output, or used to trigger the Control Write Sequencer (note - DRC1 only). DRCnLMIX_VOL2 DRCnLMIX_VOL3 DRCnLMIX_VOL4 DRCnLMIX_VOL1DRCnLMIX_SRC1 DRCnLMIX_SRC3 DRCnLMIX_SRC4 DRCnLMIX_SRC2 DRC1 Left (58h) DRC2 Left (5Ah) DRC Dynamic Range Controller DRCnRMIX_VOL2 DRCnRMIX_VOL3 DRCnRMIX_VOL4 DRCnRMIX_VOL1DRCnRMIX_SRC1 DRCnRMIX_SRC3 DRCnRMIX_SRC4 DRCnRMIX_SRC2 DRC1 Right (59h) DRC2 Right (5Bh) DRC Dynamic Range Controller WM8281 supports 2 Stereo DRC blocks, ie. n = 1 or 2 Figure 30 Dynamic Range Control (DRC) Block The DRC1 and DRC2 mixer control registers (see Figure 30) are located at register addresses R2240 (8C0h) through to R2271 (08DFh). The full list of digital mixer control registers is provided in the “ Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective DRC processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the DRC to which they are connected. Sample rate conversion functions are available to sup port flexible interconnectivity - see “ Asynchronous Sample Rate Conver ter (ASRC) ” and “ Isochronous Sample Rate Conver ter (ISRC)”. The bracketed numbers in Figure 30, eg. “(58h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The sample rate for the DRC function is configured using the FX_RATE register - see Table 23. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. The DRC function supports audio sample rates in the range 8kHz to 96kHz. Higher sample rates (up to 192kHz) may be selected using FX_RATE, provided that the DRC function is disabled. Sample rate conversion is required when routing the DRC signal paths to any signal chain that is

78 Rev 4.0 asynchronous and/or configured for a different sample rate. The DRC functions are enabled using the control registers described in Table 13. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3712 (0E80h) DRC1 ctrl1

1 DRC1L_ENA 0 DRC1 (Left) Enable

0 = Disabled 1 = Enabled

0 DRC1R_ENA 0 DRC1 (Right) Enable

0 = Disabled 1 = Enabled R3721 (0E89h) DRC2 ctrl1

1 DRC2L_ENA 0 DRC2 (Left) Enable

0 = Disabled 1 = Enabled

0 DRC2R_ENA 0 DRC2 (Right) Enable

0 = Disabled 1 = Enabled Table 13 DRC Enable The following description of the DRC is applicable to each of the DRCs. The associated register control fields are described in Table 15 and Table 16 for DRC1 and DRC2 respectively. DRC Compression / Expansion / Limiting The DRC supports two different compression regions, separated by a “Knee” at a specific input amplitude. In the region above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope DRCn_LO_COMP applies. (Note that ‘n’ identifies the applicable DRC 1 or 2.) The DRC also supports a noise gate region, where low -level input signals are heavily attenuated. This function can be enabled or disabled according to the application requirements. The DRC response in this region is defined by the expansion slope DRCn_NG_EXP. For additional attenuation of signals in the noise gate region, an additional “knee” can be defined (shown as “Knee2” in Figure 31). When this kne e is enabled, this introduces an infinitely steep drop - off in the DRC response pattern between the DRCn_LO_COMP and DRCn_NG_EXP regions. The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is near - constant) is illustrated in Figure 31. DRCn_KNEE_IP (Y0) 0dB DRCn_HI_COMP DRCn_LO_COMP DRCn Input Amplitude (dB) DRCn Output Amplitude (dB) DRCn_KNEE_OP Knee1 Knee2 DRCn_KNEE2_IP DRCn_NG_EXP DRCn_KNEE2_OP Figure 31 DRC Response Characteristic

Rev 4.0 79 The slope of the DRC response is det ermined by register fields DRCn_HI_COMP and DRCn_LO_COMP. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). A slope of 0 in dicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. When the noise gate is enabled, the DRC response in this region is determined by the DRCn_NG_EXP register. A slope of 1 indicates constant gain in this region. A slope greater than 1 represents expansion (ie. a change in input amplitude produces a larger change in output amplitude). When the DRCn_KNEE2_OP knee is enabled (“Knee2” in Figure 31), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response. The DRC parameters are listed in Table 14. REF PARAMETER DESCRIPTION

1 DRCn_KNEE_IP Input level at Knee1 (dB)

2 DRCn_KNEE_OP Output level at Knee2 (dB)

3 DRCn_HI_COMP Compression ratio above Knee1

4 DRCn_LO_COMP Compression ratio below Knee1

5 DRCn_KNEE2_IP Input level at Knee2 (dB)

6 DRCn_NG_EXP Expansion ratio below Knee2

7 DRCn_KNEE2_OP Output level at Knee2 (dB)

Table 14 DRC Response Parameters The noise gate is enabled when the DRCn_NG_ENA register is set. When the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the DRCn_LO_COMP slope applies to all input signal levels below Knee1. The DRCn_KNEE2_OP knee is enabled when the DRCn_KNEE2_OP_ENA register is set. When this bit is not set, then parameter 7 above is ignored, and the Knee2 position always coincides with the low end of the DRCn_LO_COMP region. The “Knee1” point in Figure 31 is determined by register fields DRCn_KNEE_IP and DRCn_KNEE_OP. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation: Y0 = DRCn_KNEE_OP - (DRCn_KNEE_IP x DRCn_HI_COMP) Gain Limits The minimum and maximum gain applied by the DRC is set by register fields DRCn_MINGAIN, DRCn_MAXGAIN and DRCn_NG_MINGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 31. If the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. The minimum gain in the Compression regions of the DRC response is set by DRCn_MINGAIN. The mimimum gain in the Noise Gate region is set by DRCn_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal path. The maximum gain limit set by DRCn_MAXGAIN prevents quiet signals (or silence) from being excessively amplified.

80 Rev 4.0 Dynamic Characteristics The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period of time. The DRCn_ATK determines how quickly the DRC gain decreases when the signal amplitude is high. The DRCn_DCY determines how quickly the DRC gain increases when the signal amplitude is low. These register fields are described in Table 15. Note that the register defaults are suitable for general purpose microphone use. Anti-Clip Control The DRC includes an Anti -Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed -forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain att ack rate when required. The Anti-Clip feature is enabled using the DRCn_ANTICLIP bit. Note that the feed-forward processing increases the latency in the input signal path. Note that the Anti -Clip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. Quick Release Control The DRC includes a Quick -Release feature to handle short transient peaks that are not related to the intended source signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. The Quick Release feature ensures that these transients do not cause the intended signal to be masked by the longer time constant of DRCn_DCY. The Quick-Release feature is enabled by setting the DRCn_QR bit. When this bit is enabled, the DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related to the intended source signal. If the crest factor exceeds the level set by DRCn_QR_THR, then the normal decay rate (DRCn_DCY) is ignored and a faster decay rate (DRCn_QR_DCY) is used instead. Signal Activity Detect The DRC incorporates a configurable signal detect function, allowing the signal level at the DRC input to be monitored and to be used to trigger other events. This ca n be used to detect the presence of a microphone signal on an ADC or digital mic channel, or can be used to detect an audio signal received over the digital audio interface. The DRC Signal Detect function is enabled by setting DRCn_SIG_DET register bit. (Note that the respective DRCn must also be enabled.) The detection threshold is either a Peak level (Crest Factor) or an RMS level, depending on the DRCn_SIG_DET_MODE register bit. When Peak level is selected, the threshold is determined by DRCn_SIG_DET_PK, which defines the applicable Crest Factor (Peak to RMS ratio) threshold. If RMS level is selected, then the threshold is set using DRCn_SIG_DET_RMS. The DRC Signal Detect function is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The DRC Signal Detect signal can be output directly on a GPIO pin as an external indication of the Signal Detection. See “General Purpose Input / Output” to configure a GPIO pin for this function. The Control Write Sequencer can be triggered by the DRC1 Signal Detect function. This is enabled using the DRC1_WSEQ_SIG_DET_ENA register bit. See “ Control Write Sequencer ” for further details. Note that signal detection is supported on DRC1 and DRC2, but the tri ggering of the Control Write Sequencer is available on DRC1 only.

Rev 4.0 81 GPIO Outputs from DRC The Dynamic Range Control (DRC) circuit provides a number of status outputs, which can be output directly on a GPIO pin as an external indication of the DRC Status . See “ General Purpose Input / Output” to configure a GPIO pin for these functions. Each of the DRC status outputs is described below. The DRC Signal Detect flag indicates that a signal is present on the respective signal path. The threshold level for signal detection is configurable using the register fields are described in Table 15 and Table 16. The DRC Anti-Clip flag indicates that the DRC Anti -Clip function has been triggered. In this event, the DRC gain is decreasing in response to a rising s ignal level. The flag is asserted until the DRC gain stablises. The DRC Decay flag indicates that the DRC gain is increasing in response to a low level signal input. The flag is asserted until the DRC gain stabilises. The DRC Noise Gate flag indicates that the DRC Noise Gate function has been triggered, indicating that an idle condition has been detected in the signal path. The DRC Quick Release flag indicates that the DRC Quick Release function has been triggered. In this event, the DRC gain is increasing rapidly following detection of a short transient peak. The flag is asserted until the DRC gain stabilises. DRC Register Controls The DRC control registers are described in Table 15 and Table 16 for DRC1 and DRC2 respectively. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3585 (0E01h) FX_Ctrl2 15:4 FX_STS [11:0] 00h LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3712 (0E80h) DRC1 ctrl1 15:11 DRC1_SIG_DET _RMS [4:0] 00h DRC1 Signal Detect RMS Threshold. This is the RMS signal level for signal detect to be indicated when DRC1_SIG_DET_MODE=1. 00h = -30dB 01h = -31.5dB …. (1.5dB steps) 1Eh = -75dB 1Fh = -76.5dB

82 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10:9 DRC1_SIG_DET _PK [1:0]

00 DRC1 Signal Detect Peak

Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when DRC1_SIG_DET_MODE=0. 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB

8 DRC1_NG_ENA 0 DRC1 Noise Gate Enable

0 = Disabled 1 = Enabled

7 DRC1_SIG_DET

_MODE

0 DRC1 Signal Detect Mode

0 = Peak threshold mode 1 = RMS threshold mode

6 DRC1_SIG_DET 0 DRC1 Signal Detect Enable

0 = Disabled 1 = Enabled

5 DRC1_KNEE2_

OP_ENA

0 DRC1 KNEE2_OP Enable

0 = Disabled 1 = Enabled

4 DRC1_QR 1 DRC1 Quick-release Enable

0 = Disabled 1 = Enabled

3 DRC1_ANTICLI

P

1 DRC1 Anti-clip Enable

0 = Disabled 1 = Enabled

2 DRC1_WSEQ_S

IG_DET_ENA

0 DRC1 Signal Detect Write

0 = Disabled 1 = Enabled R3713 (0E81h) DRC1 ctrl2 12:9 DRC1_ATK [3:0] 0100 DRC1 Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 to 1111 = Reserved

Rev 4.0 83 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8:5 DRC1_DCY [3:0] 1001 DRC1 Gain decay rate (seconds/6dB) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms 1010 = 1.49s 1011 = 2.97s 1100 to1111 = Reserved 4:2 DRC1_MINGAIN [2:0]

100 DRC1 Minimum gain to attenuate

000 = 0dB 001 = -12dB 010 = -18dB 011 = -24dB 100 = -36dB 101 = Reserved 11X = Reserved 1:0 DRC1_MAXGAI N [1:0]

11 DRC1 Maximum gain to boost audio

signals (dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 36dB R3714 (0E82h) DRC1 ctrl3 15:12 DRC1_NG_MIN GAIN [3:0]

0000 DRC1 Minimum gain to attenuate

audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 = 36dB 1101 to 1111 = Reserved 11:10 DRC1_NG_EXP [1:0]

00 DRC1 Noise Gate slope

00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 9:8 DRC1_QR_THR [1:0]

00 DRC1 Quick-release threshold

(crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB

84 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:6 DRC1_QR_DCY [1:0]

00 DRC1 Quick-release decay rate

(seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = Reserved 5:3 DRC1_HI_COM P [2:0]

011 DRC1 Compressor slope (upper

region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved 2:0 DRC1_LO_COM P [2:0]

000 DRC1 Compressor slope (lower

region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved R3715 (0E83h) DRC1 ctrl4 10:5 DRC1_KNEE_IP [5:0]

000000 DRC1 Input signal level at the

Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC1_KNEE_O P [4:0]

00000 DRC1 Output signal at the

Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved R3716 (0E84h) DRC1 ctrl5 9:5 DRC1_KNEE2_I P [4:0]

00000 DRC1 Input signal level at the Noise

Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC1_NG_ENA = 1.

Rev 4.0 85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4:0 DRC1_KNEE2_ OP [4:0]

00000 DRC1 Output signal at the Noise

Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC1_KNEE2_OP_ENA = 1. Table 15 DRC1 Control Registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3585 (0E01h) FX_Ctrl2 15:4 FX_STS [11:0] 00h LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3721 (0E89h) DRC2 ctrl1 15:11 DRC2_SIG_DET _RMS [4:0] 00h DRC2 Signal Detect RMS Threshold. This is the RMS signal level for signal detect to be indicated when DRC2_SIG_DET_MODE=1. 00h = -30dB 01h = -31.5dB …. (1.5dB steps) 1Eh = -75dB 1Fh = -76.5dB 10:9 DRC2_SIG_DET _PK [1:0]

00 DRC2 Signal Detect Peak

Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal detect to be indicated when DRC2_SIG_DET_MODE=0. 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB

8 DRC2_NG_ENA 0 DRC2 Noise Gate Enable

0 = Disabled 1 = Enabled

86 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

7 DRC2_SIG_DET

_MODE

0 DRC2 Signal Detect Mode

0 = Peak threshold mode 1 = RMS threshold mode

6 DRC2_SIG_DET 0 DRC2 Signal Detect Enable

0 = Disabled 1 = Enabled

5 DRC2_KNEE2_

OP_ENA

0 DRC2 KNEE2_OP Enable

0 = Disabled 1 = Enabled

4 DRC2_QR 1 DRC2 Quick-release Enable

0 = Disabled 1 = Enabled

3 DRC2_ANTICLI

P

1 DRC2 Anti-clip Enable

0 = Disabled 1 = Enabled R3722 (0E8Ah) DRC2 ctrl2 12:9 DRC2_ATK [3:0] 0100 DRC2 Gain attack rate (seconds/6dB) 0000 = Reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 to 1111 = Reserved 8:5 DRC2_DCY [3:0] 1001 DRC2 Gain decay rate (seconds/6dB) 0000 = 1.45ms 0001 = 2.9ms 0010 = 5.8ms 0011 = 11.6ms 0100 = 23.25ms 0101 = 46.5ms 0110 = 93ms 0111 = 186ms 1000 = 372ms 1001 = 743ms 1010 = 1.49s 1011 = 2.97s 1100 to1111 = Reserved 4:2 DRC2_MINGAIN [2:0]

100 DRC2 Minimum gain to attenuate

000 = 0dB 001 = -12dB (default) 010 = -18dB 011 = -24dB 100 = -36dB 101 = Reserved 11X = Reserved

Rev 4.0 87 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1:0 DRC2_MAXGAI N [1:0]

11 DRC2 Maximum gain to boost audio

signals (dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 36dB R3723 (0E8Bh) DRC2 ctrl3 15:12 DRC2_NG_MIN GAIN [3:0]

0000 DRC2 Minimum gain to attenuate

audio signals when the noise gate is active. 0000 = -36dB 0001 = -30dB 0010 = -24dB 0011 = -18dB 0100 = -12dB 0101 = -6dB 0110 = 0dB 0111 = 6dB 1000 = 12dB 1001 = 18dB 1010 = 24dB 1011 = 30dB 1100 = 36dB 1101 to 1111 = Reserved 11:10 DRC2_NG_EXP [1:0]

00 DRC2 Noise Gate slope

00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 9:8 DRC2_QR_THR [1:0]

00 DRC2 Quick-release threshold

(crest factor in dB) 00 = 12dB 01 = 18dB 10 = 24dB 11 = 30dB 7:6 DRC2_QR_DCY [1:0]

00 DRC2 Quick-release decay rate

(seconds/6dB) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = Reserved 5:3 DRC2_HI_COM P [2:0]

011 DRC2 Compressor slope (upper

region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = Reserved 111 = Reserved

88 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2:0 DRC2_LO_COM P [2:0]

000 DRC2 Compressor slope (lower

region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = Reserved 11X = Reserved R3724 (0E8Ch) DRC2 ctrl4 10:5 DRC2_KNEE_IP [5:0]

000000 DRC2 Input signal level at the

Compressor ‘Knee’. 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 4:0 DRC2_KNEE_O P [4:0]

00000 DRC2 Output signal at the

Compressor ‘Knee’. 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved R3725 (0E8Dh) DRC2 ctrl5 9:5 DRC2_KNEE2_I P [4:0]

00000 DRC2 Input signal level at the Noise

Gate threshold ‘Knee2’. 00000 = -36dB 00001 = -37.5dB 00010 = -39dB … (-1.5dB steps) 11110 = -81dB 11111 = -82.5dB Only applicable when DRC2_NG_ENA = 1. 4:0 DRC2_KNEE2_ OP [4:0]

00000 DRC2 Output signal at the Noise

Gate threshold ‘Knee2’. 00000 = -30dB 00001 = -31.5dB 00010 = -33dB … (-1.5dB steps) 11110 = -75dB 11111 = -76.5dB Only applicable when DRC2_KNEE2_OP_ENA = 1. Table 16 DRC2 Control Registers

Rev 4.0 89 The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded DRC and digital mixing functions. If an attempt is made to enable a DRC signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error can be monitored using the GPIO and/or Interrupt functions. See “ General Purpose Input / Output” and “Interrupts” for further details. The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked Error condition occurs, then this register provides readback of which EQ, DRC or LHPF signal path(s) have been successfully enabled. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then the se bits provide readback of which mixer(s) have been successfully enabled. LOW PASS / HIGH PASS DIGITAL FILTER (LHPF) The digital core provides four Low Pass Filter (LPF) / High Pass Filter (HPF) processing blocks as illustrated in Figure 32. A 4 -input mixer is associated with each filter. The 4 input sources are selectable in each case, and independent volume control is provided for each path. Each Low/High Pass Filter (LHPF) block supports 1 output. The Low Pass Filter / High Pass Filter can be used to remove unwanted out -of-band noise from a signal path. Each filter can be configured either as a Low Pass filter or High Pass filter. WM8281 supports 4 LHPF blocks, ie. n = 1, 2, 3 or 4 LHPFnMIX_VOL2 LHPFnMIX_VOL3 LHPFnMIX_VOL4 LHPFnMIX_VOL1LHPFnMIX_SRC1 LHPFnMIX_SRC3 LHPFnMIX_SRC4 LHPFnMIX_SRC2 LHPF1 (60h) LHPF2 (61h) LHPF3 (62h) LHPF4 (63h) LHPF Low-Pass filter (LPF) / High-Pass filter (HPF) Figure 32 Digital Core LPF/HPF Blocks The LHPF1, LHPF2, LHPF3 and LHPF4 mixer control registers (see Figure 32) are located at register addresses R2304 (900h) through to R2335 (91Fh). The full list of digital mixer control registers is provided in the “ Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective LHPF processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the LHPF to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “ Asynchronous Sample Rate Conver ter (ASRC) ” and “ Isochronous Sample Rate Conver ter (ISRC)”. The bracketed numbers in Figure 32, eg. “(60h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The sample rate for the LHPF function is configured using the FX_RATE register - see Table 23. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. The LHPF function supports audio sample rates in the range 8kHz to 192kHz. When the DRC is enabled, the maximum sample rate for the EQ, DRC and LHPF functions is 96kHz. Sample rate conversion is required when routing the LHPF signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.

90 Rev 4.0 The control registers associated with the LHPF functions are described in Table 17. The cut -off frequencies for the L HPF blocks are set using the coefficients held in registers R 3777, R3781, R3785 and R3789 for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus Logic’s WISCE™ evaluation board control software ; p lease contact your local Cirrus Logic representative for more details. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3585 (0E01h) FX_Ctrl2 15:4 FX_STS [11:0] 00h LHPF, DRC, EQ Enable Status Indicates the status of each of the respective signal processing functions. [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 Each bit is coded as: 0 = Disabled 1 = Enabled R3776 (0EC0h) HPLPF1_

1 LHPF1_MODE 0 Low/High Pass Filter 1 Mode

0 = Low-Pass 1 = High-Pass

0 LHPF1_ENA 0 Low/High Pass Filter 1 Enable

0 = Disabled 1 = Enabled R3777 (0EC1h) HPLPF1_ 15:0 LHPF1_COEFF [15:0] 0000h Low/High Pass Filter 1 Frequency Coefficient Refer to WISCE evaluation board control software for the deriviation of this field value. R3780 (0EC4h) HPLPF2_

1 LHPF2_MODE 0 Low/High Pass Filter 2 Mode

0 = Low-Pass 1 = High-Pass

0 LHPF2_ENA 0 Low/High Pass Filter 2 Enable

0 = Disabled 1 = Enabled R3781 (0EC5h) HPLPF2_ 15:0 LHPF2_COEFF [15:0] 0000h Low/High Pass Filter 2 Frequency Coefficient Refer to WISCE evaluation board control software for the deriviation of this field value. R3784 (0EC8h) HPLPF3_

1 LHPF3_MODE 0 Low/High Pass Filter 3 Mode

0 = Low-Pass 1 = High-Pass

0 LHPF3_ENA 0 Low/High Pass Filter 3 Enable

0 = Disabled 1 = Enabled R3785 (0EC9h) HPLPF3_ 15:0 LHPF3_COEFF [15:0] 0000h Low/High Pass Filter 3 Frequency Coefficient Refer to WISCE evaluation board control software for the deriviation of this field value.

Rev 4.0 91 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3788 (0ECCh) HPLPF4_

1 LHPF4_MODE 0 Low/High Pass Filter 4 Mode

0 = Low-Pass 1 = High-Pass

0 LHPF4_ENA 0 Low/High Pass Filter 4 Enable

0 = Disabled 1 = Enabled R3789 (0ECDh) HPLPF4_ 15:0 LHPF4_COEFF [15:0] 0000h Low/High Pass Filter 4 Frequency Coefficient Refer to WISCE evaluation board control software for the deriviation of this field value. Table 17 Low Pass Filter / High Pass Filter Control The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded LHPF and digital mixing functions. If an attempt is made to enable an LHPF signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error can be monitored us ing the GPIO and/or Interrupt functions. See “ General Purpose Input / Output” and “Interrupts” for further details. The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked Error condition occurs, then this register provi des readback of which EQ, DRC or LHPF signal path(s) have been successfully enabled. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then the se bits provide readback of which mixer(s) have been successfully enabled.

92 Rev 4.0 DIGITAL CORE DSP The digital core provides four programmable DSP processing blocks as illustrated in Figure 33. Each block supports 8 inputs (Left, Right, Aux1, Aux2, … Aux6). A 4 -input mixer is associated with the Left and Right inputs, providing further expansion of the number of input paths. Each of the input sources is selectable, and independent volume control is p rovided for Left and Right input mixer channels . Each DSP block supports 6 outputs. The functionality of the DSP processing blocks is not fixed, and a wide range of audio enhancements algorithms may be performed. The procedure for configuring the WM8281 DSP functions is tailored to each customer’s application; please contact your local Cirrus Logic representative for more details. For details of the DSP Firmware requirements relating to clocking, register access, and code execution, refer to the “DSP Firmware Control” section. DSPnLMIX_VOL2 DSPnLMIX_VOL3 DSPnLMIX_VOL4 DSPnLMIX_VOL1DSPnLMIX_SRC1 DSPnLMIX_SRC3 DSPnLMIX_SRC4 DSPnLMIX_SRC2 DSPnRMIX_VOL2 DSPnRMIX_VOL3 DSPnRMIX_VOL4 DSPnRMIX_VOL1DSPnRMIX_SRC1 DSPnRMIX_SRC3 DSPnRMIX_SRC4 DSPnRMIX_SRC2 DSP n DSPnAUX1_SRC DSPnAUX3_SRC DSPnAUX4_SRC DSPnAUX2_SRC DSPnAUX5_SRC DSPnAUX6_SRC DSPn Channel 1 DSPn Channel 2 DSPn Channel 3 DSPn Channel 4 DSPn Channel 5 DSPn Channel 6 WM8281 supports 4 DSP blocks, ie. n = 1, 2, 3 or 4 DSP1 Outputs: (68h, 69h, 6Ah, 6Bh, 6Ch, 6Dh) DSP2 Outputs: (70h, 71h, 72h, 73h, 74h, 75h) DSP3 Outputs: (78h, 79h, 7Ah, 7Bh, 7Ch, 7Dh) DSP4 Outputs: (80h, 81h, 82h, 83h, 84h, 85h) Figure 33 Digital Core DSP Blocks The DSP1, DSP2 , DSP 3 and DSP4 mixer / input control registers (see Figure 33) are located at register addresses R2368 (940h) through to R2616 (A38h). The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective DSP processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the DSP to whi ch they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “ Asynchronous Sample Rate Conver ter (ASRC) ” and “ Isochronous Sample Rate Conver ter (ISRC)”. The bracketed numbers in Figure 33, eg. “(68h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The sample rate for each of the DSP functions is configured using the respective DSPn_RATE registers - see Table 23. Sample rate conversion is required when routing the DSPn signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to

Rev 4.0 93 support the commanded DSP mixing functions. If an attempt is made to enable a DSP mixer path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then the se bits provide readback of which mixer(s) have been successfully enabled. The WM8281 supports up to eight DSP Status flags as outputs from the DSP blocks. These are configurable within the DSP to provide external indication of the required function(s). The DSP Status flags can be read using the DSP_IRQn_STS registers described in Table 98 (see “Interrupts”). The DSP Status flags are inputs to the Interrupt control circuit and can be used t o trigger an interrupt event - see “Interrupts”. The DSP Status flags can be output directly on a GPIO pin as an external indication of the DSP Status. See “General Purpose Input / Output” to configure a GPIO pin for this function. The DSP_IRQn_STS fields are read -only bits. These bits can be set (or reset) by writing to the DSP_IRQn fields, as described in Table 18. This facility can be used to allow a DSP core to generate an interrupt to the host processor. The DSP interrupt registers are as serted on the rising and falling edges of the respective DSP_IRQn fields. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3393 (0D41h) ADSP2 IRQ0

1 DSP_IRQ2 0 DSP IRQ2

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ2_EINTn interrupt to the host processor.

0 DSP_IRQ1 0 DSP IRQ1

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ1_EINTn interrupt to the host processor. R3394 (0D42h) ADSP2 IRQ1

1 DSP_IRQ4 0 DSP IRQ4

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ4_EINTn interrupt to the host processor.

0 DSP_IRQ3 0 DSP IRQ3

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ3_EINTn interrupt to the host processor. R3395 (0D43h) ADSP2 IRQ2

1 DSP_IRQ6 0 DSP IRQ6

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ6_EINTn interrupt to the host processor.

0 DSP_IRQ5 0 DSP IRQ5

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ5_EINTn interrupt to the host processor.

94 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3396 (0D44h) ADSP2 IRQ3

1 DSP_IRQ8 0 DSP IRQ8

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ8_EINTn interrupt to the host processor.

0 DSP_IRQ7 0 DSP IRQ7

0 = Not asserted 1 = Asserted This bit can be set/reset by a DSP core in order to generate a DSP_IRQ7_EINTn interrupt to the host processor. Table 18 DSP Interrupts TONE GENERATOR The WM8281 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. The phase relationship between the two generators is configurable, providing flexibility in creating differential signals, or for test scenarios. Tone Generator 1 (04h) Tone Generator 2 (05h) 1kHz Tone Generator TONE1_ENA TONE2_ENA TONE_OFFSET TONE_RATE TONE1_OVD TONE1_LVL TONE2_OVD TONE2_LVL Figure 34 Digital Core Tone Generator The tone generators can be selected as input to any of the digital mixers or signal processing functions within the WM8281 digital core. The bracketed numb ers in Figure 34, eg. “(0 4h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The sample rate for the tone generators is configured using the TONE_RATE register - see Table 23. Note that sample rate conversion is required when routing the tone generator o utput(s) to any signal chain that is asynchronous and/or configured for a different sample rate. The tone generators are enabled using the TONE1_ENA and TONE2_ENA register bits as described in Table 19. The phase relationship is configured using TONE_OFFSET. The tone generators can also provide a configurable DC signal level, for use as a test signal. The DC output is selected using the TONEn_OVD register bits, and the DC signal amplitude is configured using the TONEn_LVL registers, as described in Table 19.

Rev 4.0 95 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 (0020h) Tone Generator 9:8 TONE_OFFSET [1:0]

00 Tone Generator Phase Offset

Sets the phase of Tone Generator 2 relative to Tone Generator 1 00 = 0 degrees (in phase) 01 = 90 degrees ahead 10 = 180 degrees ahead 11 = 270 degrees ahead

5 TONE2_OVD 0 Tone Generator 2 Override

0 = Disabled (1kHz tone output) 1 = Enabled (DC signal output) The DC signal level, when selected, is configured using TONE2_LVL[23:0]

4 TONE1_OVD 0 Tone Generator 1 Override

0 = Disabled (1kHz tone output) 1 = Enabled (DC signal output) The DC signal level, when selected, is configured using TONE1_LVL[23:0]

1 TONE2_ENA 0 Tone Generator 2 Enable

0 = Disabled 1 = Enabled

0 TONE1_ENA 0 Tone Generator 1 Enable

0 = Disabled 1 = Enabled R33 (0021h) Tone Generator 15:0 TONE1_LVL [23:8] 1000h Tone Generator 1 DC output level TONE1_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds R34 (0022h) Tone Generator 7:0 TONE1_LVL [7:0] 00h Tone Generator 1 DC output level TONE1_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds R35 (0023h) Tone Generator 15:0 TONE2_LVL [23:8] 1000h Tone Generator 2 DC output level TONE2_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds R36 (0024h) Tone Generator 7:0 TONE2_LVL [7:0] 00h Tone Generator 2 DC output level TONE2_LVL [23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits [19:0] contain the fractional portion. The digital core 0dBFS level corresponds Table 19 Tone Generator Control

Table 23. Note that sample rate conversion is required when routing the noise generator output to any signal chain that is asynchronous and/or configured for a different sample rate. The noise generat or is enabled using the NOISE_GEN_ENA register bit as described in Table 20. The signal level is configured using NOISE_GEN_GAIN.

5 NOISE_GEN_EN

0 Noise Generator Enable

Linear Resonant Actuator (LRA) haptic devices. programmable event profile comprising three distinct operating phases. for many different actuator components.

selection of the haptic signal generator as an input to another digital core function. *_SRCn register of the applicable output mixer to (06h). Table 23. Note that sample rate conversion is required when routing the haptic signal generator output to any signal chain that is asynchronous and/or configured for a different sample rate. The haptic signal generator is configured for an ERM or LRA actuator using the HAP_AC T register bit. and intensity of each output phase is programmable. In Continuous mode, the signal intensity is controlled using the PHASE2_INTENSITY field only. positive or negative, as selected by the *_INTENSITY registers. desirable during the final phase, to halt the physical motion of the haptic device.

4 ONESHOT_TRIG 0 Haptic One-Shot Trigger

Writing ‘1’ starts the one-shot profile (ie.

1 HAP_ACT 0 Haptic Actuator Select

98 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R145 (0091h) Haptics Control 2 14:0 LRA_FREQ [14:0] 7FFFh Haptic Resonant Frequency Selects the haptic signal frequency (LRA actuator only, HAP_ACT = 1) Haptic Frequency (Hz) = System Clock / (2 x (LRA_FREQ+1)) where System Clock = 6.144MHz or 5.6448MHz, derived by division from SYSCLK or ASYNCCLK. If HAP_RATE<1000, then SYSCLK is the clock source, and the applicable System Clock frequency is determined by SYSCLK. If HAP_RATE>=1000, then ASYNCCLK is the clock source, and the applicable System Clock frequency is determined by ASYNCCLK. Valid for Haptic Frequency in the range 100Hz to 250Hz For 6.144MHz System Clock: 77FFh = 100Hz 4491h = 175Hz 2FFFh = 250Hz For 5.6448MHz System Clock: 6E3Fh = 100Hz 3EFFh = 175Hz 2C18h = 250Hz R146 (0092h) Haptics phase 1 intensity 7:0 PHASE1_INTEN SITY [7:0] 00h Haptic Output Level (Phase 1) Selects the signal intensity of Phase 1 in one-shot mode. Coded as 2’s complement. Range is +/- Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180 degree phase shift. R147 (0093h) Haptics Control phase 1 duration 8:0 PHASE1_DURAT ION [8:0] 000h Haptic Output Duration (Phase 1) Selects the duration of Phase 1 in one- shot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms … (0.625ms steps) 1FFh = 319.375ms

Rev 4.0 99 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R148 (0094h) Haptics phase 2 intensity 7:0 PHASE2_INTEN SITY [7:0] 00h Haptic Output Level (Phase 2) Selects the signal intensity in Continuous mode or Phase 2 of one-shot mode. Coded as 2’s complement. Range is +/- Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180 degree phase shift. R149 (0095h) Haptics phase 2 duration 10:0 PHASE2_DURAT ION [10:0] 000h Haptic Output Duration (Phase 2) Selects the duration of Phase 2 in one- shot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms … (0.625ms steps) 7FFh = 1279.375ms R150 (0096h) Haptics phase 3 intensity 7:0 PHASE3_INTEN SITY [7:0] 00h Haptic Output Level (Phase 3) Selects the signal intensity of Phase 3 in one-shot mode. Coded as 2’s complement. Range is +/- Full Scale (FS). For ERM actuator, this selects the DC signal level for the haptic output. For LRA actuator, this selects the AC peak amplitude; Negative values correspond to a 180 degree phase shift. R151 (0097h) Haptics phase 3 duration 8:0 PHASE3_DURAT ION [8:0] 000h Haptic Output Duration (Phase 3) Selects the duration of Phase 3 in one- shot mode. 000h = 0ms 001h = 0.625ms 002h = 1.25ms … (0.625ms steps) 1FFh = 319.375ms R152 (0098h) Haptics Status

0 ONESHOT_STS 0 Haptic One-Shot status

0 = One-Shot event not in progress 1 = One-Shot event in progress Table 21 Haptic Signal Generator Control

Rev 4.0 101 The PWM sample rate (cycle time) is configured using the PWM_RATE register - see Table 23. Note that sample rate conversion is required when linking the PWM generators to any signal chain that is asynchronous and/or configured for a different sample rate. The PWM generators are enabled using PWM1_ENA and PWM2_ENA respectively , as described in Table 22. Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an audio signal path; a 4-input mixer is associated with each PWM generator, as illustrated in Figure 37. When the PWM n_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed ratio; in this case, the duty cycle ratio is configurable using the PWMn_LVL registers. The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, this register should be set to the highest available setting. Note that the PWM generator clock must not be set to a higher frequency than SYSCLK (if PWM_RATE<1000) or ASYNCCLK (if PWM_RATE≥1000). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R48 (0030h) PWM Drive 10:8 PWM_CLK_SEL [2:0]

000 PWM Clock Select

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only. PWM_CLK_SEL controls the resolution of the PWM generator; higher settings correspond to higher resolution. The PWM Clock must be less than or equal to SYSCLK (if PWM_RATE<1000) or less than or equal to ASYNCCLK (if PWM_RATE>=1000).

5 PWM2_OVD 0 PWM2 Generator Override

0 = Disabled (PWM duty cycle is controlled by audio source) 1 = Enabled (PWM duty cycle is controlled by PWM2_LVL).

4 PWM1_OVD 0 PWM1 Generator Override

0 = Disabled (PWM1 duty cycle is controlled by audio source) 1 = Enabled (PWM1 duty cycle is controlled by PWM1_LVL).

1 PWM2_ENA 0 PWM2 Generator Enable

0 = Disabled 1 = Enabled

0 PWM1_ENA 0 PWM1 Generator Enable

0 = Disabled 1 = Enabled R49 (0031h) PWM Drive 9:0 PWM1_LVL [9:0] 100h PWM1 Override Level Sets the PWM1 duty cycle when PWM1_OVD=1. Coded as 2’s complement. 000h = 50% duty cycle 200h = 0% duty cycle R50 (0032h) PWM Drive 9:0 PWM2_LVL [9:0] 100h PWM2 Override Level Sets the PWM2 duty cycle when PWM2_OVD=1. Coded as 2’s complement. 000h = 50% duty cycle 200h = 0% duty cycle Table 22 Pulse Width Modulation (PWM) Generator Control

102 Rev 4.0 The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the digital mixer paths. If an attempt is made to enable a PWM signal mixer path, and there are insufficient SYSCLK cycles to support it, then the attempt will be uns uccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then the se bits provide readback of which mixer(s) have been successfully enabled. SAMPLE RATE CONTROL The WM8281 supports multiple signal paths through t he digital core. Stereo full-duplex sample rate conversion is provided to allow digital audio to be routed between interfaces operating at different sample rates and/or referenced to asynchronous clock domains. Two independent clock domains are supported, referenced to SYSCLK and ASYNCCLK respectively, as described in “Clocking and Sample Rates”. Every digital signal path must be synchronised either to SYSCLK or to ASYNCCLK. Up to five different sample rates may be in use at any time on the WM8281. Three of these sample rates must be synchronised to SYSCLK; the remaining two, where required, must be synchronised to ASYNCCLK. Sample rate conversion is required when routing any audio path between digital functions that are asynchronous and/or configured for different sample rates. The Asynchronous Sample Rate Converter (ASRC) provides two stereo signal paths between the SYSCLK and ASYNCCLK domains. The ASRC is described later, and is illustrated in Figure 40. There are three Isochronous Sample Rate Converters (ISRCs). These provide four signal paths each between sample rates on the SYSCLK domain, or between sample rates on the ASYNCCLK domain . The ISRCs are described later, and are illustrated in Figure 41. The sample rate of different blocks wi thin the WM8281 digital core are controlled as illustrated in Figure 38 and Figure 39 - the *_RATE registers select the applicable sample rate for each respective group of digital functions. The *_RATE registers should not be changed if any of the *_SRC n registers associated with the respective functions is non -zero. The associate d *_SRCn registers should be cleared to 00h before writing new values to the *_RATE registers. A minimum delay of 125 µs should be allowed between clearing the *_SRC n registers and writing to the associated *_RATE registers. See Table 23 for further details.

Rev 4.0 103 Silence (mute) (00h) IN1L signal path (10h) IN1R signal path (11h) IN2L signal path (12h) IN2R signal path (13h) IN3L signal path (14h) IN3R signal path (15h) IN4L signal path (16h) IN4R signal path (17h) AEC Loopback (08h) DSP DSP1 Channel 1 (68h) DSP1 Channel 2 (69h) DSP1 Channel 3 (6Ah) DSP1 Channel 4 (6Bh) DSP1 Channel 5 (6Ch) DSP1 Channel 6 (6Dh) DSP DSP2 Channel 1 (70h) DSP2 Channel 2 (71h) DSP2 Channel 3 (72h) DSP2 Channel 4 (73h) DSP2 Channel 5 (74h) DSP2 Channel 6 (75h) DSP DSP3 Channel 1 (78h) DSP3 Channel 2 (79h) DSP3 Channel 3 (7Ah) DSP3 Channel 4 (7Bh) DSP3 Channel 5 (7Ch) DSP3 Channel 6 (7Dh) DSP DSP4 Channel 1 (80h) DSP4 Channel 2 (81h) DSP4 Channel 3 (82h) DSP4 Channel 4 (83h) DSP4 Channel 5 (84h) DSP4 Channel 6 (85h) DSP1_RATE DSP2_RATE DSP3_RATE ISRC2_FSL ISRC2_FSH IN_RATE DSP4_RATE ISRC3_FSL ISRC3_FSHISRC1_FSL ISRC1_FSH FX_RATE LHPF4 (63h) LHPF LHPF3 (62h) LHPF LHPF2 (61h) LHPF LHPF1 (60h) LHPF EQ4 (53h) EQ EQ3 (52h) EQ EQ2 (51h) EQ EQ1 (50h) EQ DRC 2 Right (5Bh) DRC DRC 2 Left (5Ah) DRC DRC 1 Right (59h) DRC DRC 1 Left (58h) DRC OUT_RATE Isochronous Sample Rate Converter (ISRC) ISRC1 INT1 (A0h) ISRC1 INT2 (A1h) ISRC1 DEC1 (A4h) ISRC1 DEC2 (A5h) ISRC1 INT3 (A2h) ISRC1 INT4 (A3h) ISRC1 DEC3 (A6h) ISRC1 DEC4 (A7h) Isochronous Sample Rate Converter (ISRC) ISRC2 INT1 (A8h) ISRC2 INT2 (A9h) ISRC2 DEC1 (ACh) ISRC2 DEC2 (ADh) ISRC2 INT3 (AAh) ISRC2 INT4 (ABh) ISRC2 DEC3 (AEh) ISRC2 DEC4 (AFh) Isochronous Sample Rate Converter (ISRC) ISRC3 INT1 (B0h) ISRC3 INT2 (B1h) ISRC3 DEC1 (B4h) ISRC3 DEC2 (B5h) ISRC3 INT3 (B2h) ISRC3 INT4 (B3h) ISRC3 DEC3 (B6h) ISRC3 DEC4 (B7h) MICMUTE_RATE Mic Mute Mixer (0Ch) (To GPIO pin) PWM (To GPIO pin) PWM PWM_RATE ASRC_RATE1 ASRC_RATE2 ASRC1 Left (90h) ASRC1 Right (91h) ASRC2 Left (92h) ASRC2 Right (93h) Asynchronous Sample Rate Converter (ASRC) Tone Generator 1 (04h) Tone Generator 2 (05h) Tone Generator TONE_RATE Noise Generator (0Dh) White Noise Generator NOISE_GEN_RATE Haptic Output (06h) Haptic Signal Generator HAP_RATE Figure 38 Digital Core Sample Rate Control (Internal Signal Processing)

104 Rev 4.0 OUT6R output OUT6L output OUT5R output OUT5L output OUT4R output OUT4L output OUT3R output OUT3L output OUT2R output OUT2L output OUT1R output OUT1L output AIF1 TX8 output AIF1 TX7 output AIF1 TX6 output AIF1 TX5 output AIF1 TX4 output AIF1 TX3 output AIF1 TX2 output AIF1 TX1 output AIF1 RX3 (22h) AIF1 RX4 (23h) AIF1 RX5 (24h) AIF1 RX6 (25h) AIF1 RX7 (26h) AIF1 RX8 (27h) AIF1 RX1 (20h) AIF1 RX2 (21h) SLIMbus TX8 output SLIMbus TX7 output SLIMbus TX6 output SLIMbus TX5 output SLIMbus TX4 output SLIMbus TX3 output SLIMbus TX2 output SLIMbus TX1 output SLIMbus RX3 (3Ah) SLIMbus RX4 (3Bh) SLIMbus RX5 (3Ch) SLIMbus RX6 (3Dh) SLIMbus RX7 (3Eh) SLIMbus RX8 (3Fh) SLIMbus RX1 (38h) SLIMbus RX2 (39h) AIF1_RATE AIF3_RATE AIF2_RATE OUT_RATE SLIMTX1_RATE SLIMTX2_RATE SLIMTX3_RATE SLIMTX4_RATE SLIMTX5_RATE SLIMTX6_RATE SLIMTX7_RATE SLIMTX8_RATE SLIMRX1_RATE SLIMRX2_RATE SLIMRX3_RATE SLIMRX4_RATE SLIMRX5_RATE SLIMRX6_RATE SLIMRX7_RATE SLIMRX8_RATE AIF3 TX2 output AIF3 TX1 output AIF3 RX1 (30h) AIF3 RX2 (31h) AIF2 TX6 output AIF2 TX5 output AIF2 TX4 output AIF2 TX3 output AIF2 TX2 output AIF2 TX1 output AIF2 RX3 (2Ch) AIF2 RX4 (2Dh) AIF2 RX5 (2Eh) AIF2 RX6 (2Fh) AIF2 RX1 (2Ah) AIF2 RX2 (2Bh) Figure 39 Digital Core Sample Rate Control (External Digital Interfaces) The input signal paths may be selected as input to the digital mixers or signal processing functions. The sample rate for the input signal paths is configured using the IN_RATE register. The output signal paths are derived from the respective output mixers. The sample rate for the output signal paths is configured using the OUT_RATE register . The sample rate of the AEC Loopback path is also set by the OUT_RATE register. The AIFn RX inputs may be selected as input to the digital mixers or signal processing functions. The AIFn TX outputs are derived from the respective output mixers. The sample rate s for d igital audio interfaces (AIF1, AIF2 and AIF3) are configured using the AIF1_RATE, AIF2_RATE and AIF3_RATE registers respectively. The SLIMbus interface supports up to 8 input channels and 8 output channels. The sample rate of each channel can be configured independently, using the SLIMTXn_RATE and SLIMRXn_RATE registers. Note that t he SLIMbus interface provides simultaneous support for SYSCLK -referenced and ASYNCCLK-referenced sample rates on different channels. For example, 48kHz and 44.1kHz SLIMbus audio paths can be simultaneously supported.

Rev 4.0 105 The EQ, LHPF and DRC funct ions can be enabled in any signal path within the digital core. The sample rate for these functions is configured using the FX_RATE register. Note that the EQ, DRC and LHPF functions must all be configured for the same sample rate. The DSPn functions can b e enabled in any signal path within the digital core. The applicable sample rates are configured using the DSP1_RATE, DSP2_RATE, DSP3_RATE and DSP4_RATE registers. The tone generators and noise generator can be selected as input to any of the digital mixer s or signal processing functions. The sample rate s for these sources are configured using the TONE_RATE and NOISE_GEN_RATE registers respectively. The haptic signal generator can be used to control an external vibe actuator, which can be driven directly by the Class D speaker output. The sample rate for the haptic signal generator is configured using the HAP_RATE register. The PWM signal generators can be modulated by an audio source, derived from the associated signal mixers. The sample rate (cycle time) f or the PWM signal generators is configured using the PWM_RATE register. The sample rate control registers are described in Table 23. Refer to the register descriptions for details of the valid selections in each case. Note that the input (ADC) and output (DAC) signal paths must always be associated with the SYSCLK clocking domain; different sample rates may be selected concurrently, but both these rates must be synchronised to SYSCLK. The control registers associated with the ASRC and ISRCs are described in Table 24 and Table 25 respectively within the following sections. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 (0020h) Tone Generator 14:11 TONE_RATE [3:0]

0000 Tone Generator Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. R48 (0030h) PWM Drive 1 14:11 PWM_RATE [3:0] 0000 PWM Frequency (sample rate) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All PWMnMIX_SRCm registers should be set to 00h before changing PWM_RATE. R112 0070h) Comfort Noise Generator 14:11 NOISE_GEN_RA TE [3:0]

0000 Noise Generator Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz.

106 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R144 0090h) Haptics Control 1 14:11 HAP_RATE [3:0] 0000 Haptic Signal Generator Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. R707 (02C3h) Mic noise mix control 14:11 MICMUTE_RATE [3:0]

0000 Mic Mute Mixer Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. R776 (0308h) Input Rate 14:11 IN_RATE [3:0] 0000 Input Signal Paths Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. If 768kHz DMIC clock rate is selected on any of the input paths (INn_OSR=11), then the Input Signal Paths sample rate is valid in the range 8kHz to 16kHz only. R1032 (0408h) Output Rate 1 14:11 OUT_RATE [3:0] 0000 Output Signal Paths Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. All OUTnxMIX_SRCm registers should be set to 00h before changing OUT_RATE. R1283 (0503h) AIF1 Rate Ctrl 14:11 AIF1_RATE [3:0] 0000 AIF1 Audio Interface Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All AIF1TXMIX_SRCn registers should be set to 00h before changing AIF1_RATE.

Rev 4.0 107 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1347 (0543h) AIF2 Rate Ctrl 14:11 AIF2_RATE [3:0] 0000 AIF2 Audio Interface Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All AIF2TXMIX_SRCn registers should be set to 00h before changing AIF2_RATE. R1411 (0583h) AIF3 Rate Ctrl 14:11 AIF3_RATE [3:0] 0000 AIF3 Audio Interface Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All AIF3TXMIX_SRCn registers should be set to 00h before changing AIF3_RATE. R1509 (05E5h) SLIMbus Rates 1 14:11 SLIMRX2_RATE [3:0]

0000 SLIMbus RX Channel 2 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. 6:3 SLIMRX1_RATE [3:0]

0000 SLIMbus RX Channel 1 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. R1510 (05E6h) SLIMbus Rates 2 14:11 SLIMRX4_RATE [3:0]

0000 SLIMbus RX Channel 4 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. 6:3 SLIMRX3_RATE [3:0]

0000 SLIMbus RX Channel 3 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz.

108 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1511 (05E7h) SLIMbus Rates 3 14:11 SLIMRX6_RATE [3:0]

0000 SLIMbus RX Channel 6 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. 6:3 SLIMRX5_RATE [3:0]

0000 SLIMbus RX Channel 5 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. R1512 (05E8h) SLIMbus Rates 4 14:11 SLIMRX8_RATE [3:0]

0000 SLIMbus RX Channel 8 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. 6:3 SLIMRX7_RATE [3:0]

0000 SLIMbus RX Channel 7 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. R1513 (05E9h) SLIMbus Rates 5 14:11 SLIMTX2_RATE [3:0]

0000 SLIMbus TX Channel 2 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX2MIX_SRCn registers should be set to 00h before changing SLIMTX2_RATE.

Rev 4.0 109 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6:3 SLIMTX1_RATE [3:0]

0000 SLIMbus TX Channel 1 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX1MIX_SRCn registers should be set to 00h before changing SLIMTX1_RATE. R1514 (05EAh) SLIMbus Rates 6 14:11 SLIMTX4_RATE [3:0]

0000 SLIMbus TX Channel 4 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX4MIX_SRCn registers should be set to 00h before changing SLIMTX4_RATE. 6:3 SLIMTX3_RATE [3:0]

0000 SLIMbus TX Channel 3 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX3MIX_SRCn registers should be set to 00h before changing SLIMTX3_RATE. R1515 (05EBh) SLIMbus Rates 7 14:11 SLIMTX6_RATE [3:0]

0000 SLIMbus TX Channel 6 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX6MIX_SRCn registers should be set to 00h before changing SLIMTX6_RATE.

110 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6:3 SLIMTX5_RATE [3:0]

0000 SLIMbus TX Channel 5 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX5MIX_SRCn registers should be set to 00h before changing SLIMTX5_RATE. R1516 (05ECh) SLIMbus Rates 8 14:11 SLIMTX8_RATE [3:0]

0000 SLIMbus TX Channel 8 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX8MIX_SRCn registers should be set to 00h before changing SLIMTX8_RATE. 6:3 SLIMTX7_RATE [3:0]

0000 SLIMbus TX Channel 7 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All SLIMTX7MIX_SRCn registers should be set to 00h before changing SLIMTX7_RATE. R3584 (0E00h) FX_Ctrl 14:11 FX_RATE [3:0] 0000 FX Sample Rate (EQ, LHPF, DRC) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. When the DRC is enabled, the maximum FX_RATE sample rate is 96kHz. All EQnMIX_SRCm, DRCnxMIX_SRCm, and LHPFnMIX_SRCm registers should be set to 00h before changing FX_RATE.

Rev 4.0 111 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4352 (1100h) DSP1 Control 1 14:11 DSP1_RATE [3:0]

0000 DSP1 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All DSP1xMIX_SRCn registers should be set to 00h before changing DSP1_RATE. R4608 (1200h) DSP2 Control 1 14:11 DSP2_RATE [3:0]

0000 DSP2 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All DSP2xMIX_SRCn registers should be set to 00h before changing DSP2_RATE. R4864 (1300h) DSP3 Control 1 14:11 DSP3_RATE [3:0]

0000 DSP3 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All DSP3xMIX_SRCn registers should be set to 00h before changing DSP3_RATE. R5120 (1400h) DSP4 Control 1 14:11 DSP4_RATE [3:0]

0000 DSP4 Sample Rate

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 4kHz to 192kHz. All DSP4xMIX_SRCn registers should be set to 00h before changing DSP4_RATE. Table 23 Digital Core Sample Rate Control

112 Rev 4.0 ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) The WM8281 supports multiple signal paths through the digital core. Two independent clock domains are supported, referenced to SYSCLK and ASYNCCLK respe ctively, as described in “ Clocking and Sample Rates”. Every digital signal path must be synchronised either to SYSCLK or to ASYNCCLK. The Asynchronous Sample Rate Conv erter (ASRC) provides two stereo signal paths between the SYSCLK and ASYNCCLK domains, as illustrated in Figure 40. The sample rate on the SYSCLK domain is selected u sing the ASRC_RATE1 register - the rate can be set equal to SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3. The sample rate on the ASYNCCLK domain is selected using the ASRC_RATE2 register - the rate can be set equal to ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2. See “Clocking and Sample Rates” for details of the sample rate control registers. The ASRC_RATE1 and ASRC_RATE2 registers should not be changed if any of the respective *_SRCn registers is non -zero. The associated *_SRC n registers should be cleared to 00h before writing new values to ASRC_RATE1 or ASRC_RATE2. A minimum delay of 125 µs should be allowed between clearing the *_SRCn registers and writing to the associated ASRC_RATE1 or ASRC_RATE2 registers. See Table 24 for further details. The ASRC supports sample rates in the range 8kHz to 48kHz only. The applicable SAMPLE_RATE_n and ASYNC_SAMPLE_RATE_n registers must each select sample rates between 8kHz and 48kHz when any ASRC path is enabled. The ASRC1 Left and ASRC1 Right paths convert from the SYSCLK domain to the ASYNCCLK domain. These paths are enabled using the ASRC1L _ENA and ASRC1R_ENA register bits respectively. The ASRC2 Left and ASRC2 Right paths convert from the ASYNCCLK domain to the SYSCLK domain. These paths are enabled using the ASRC2L_ENA and ASRC2R_ENA register bits respectively. Synchronisation (lock) between different clock domains is not instantaneous when the clocking or sample rate configurations are updated. The lock status of each ASRC path is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The ASRC Lock status of each ASRC path can be output directly on a GPIO pin as an external indication of ASRC Lock. See “ General Purpose Input / Output ” to configure a GPIO pin for this function. The WM8281 performs automatic checks to confirm that the SYSCLK or ASYNCCLK frequency is high enough to support the commanded ASRC and digital mixing functions. If an attempt is made to enable an ASRC signal path, and there are insufficient SYSCLK or ASYNCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error can be monitored using the GPIO and/or Interrupt functions. See “ General Purpose Input / Output” and “Interrupts” for further details. The status bits in Register R 3809 indicate the status of each of the ASRC signal paths. If an Underclocked Error condition occurs, then these bits provide readback of which ASRC signal path(s) have been successfully enabled. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then the se bits provide readback of which mixer(s) have been successfully enabled. The Asynchronous Sample Rate Converter (ASRC) signal paths and control registers are illustrated in Figure 40.

Rev 4.0 113 ASRC1R_ENA ASRC1L_ENAASRC1L_SRC ASRC1R_SRC ASRC1 Left (90h) ASRC1 Right (91h) ASRC2R_ENA ASRC2L_ENA ASRC2L_SRC ASRC2R_SRC ASRC2 Left (92h) ASRC2 Right (93h) ASRC_RATE1 (= SAMPLE_RATE_n) ASRC_RATE2 (= ASYNC_SAMPLE_RATE_n) The ASRC provides asynchronous conversion between the SYSCLK and ASYNCCLK CLOCK domains. ASRC_RATE1 identifies the SYSCLK-related sample rate (SAMPLE_RATE_n). ASRC_RATE2 identifies the ASYNCCLK-related sample rate (ASYNC_SAMPLE_RATE_n). Figure 40 Asynchronous Sample Rate Converters (ASRCs) The ASRC1 and ASRC2 input control registers (see Figure 40) are located at register addresses R2688 (A80h) through to R2712 (A98h). The full list of digital mixer control registers is provided in the “ Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRCn registers select the input source(s) for the respective ASRC processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the ASRC to w hich they are connected. The bracketed numbers in Figure 40, eg. “(90h)” indicate the corresponding *_SRC n register setting for selection of that signal as an input to another digital core function. The register bits associated with the ASRCs are described in Table 24. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3808 (0EE0h) ASRC_EN ABLE

3 ASRC2L_ENA 0 ASRC2 Left Enable

(Left ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled

2 ASRC2R_ENA 0 ASRC2 Right Enable

(Right ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled

1 ASRC1L_ENA 0 ASRC1 Left Enable

(Left ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled

114 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 ASRC1R_ENA 0 ASRC1 Right Enable

(Right ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled R3809 (0EE1h) ASRC_ST ATUS

3 ASRC2L_ENA_S

0 ASRC2 Left Enable Status

(Left ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled

2 ASRC2R_ENA_S

0 ASRC2 Right Enable Status

(Right ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled

1 ASRC1L_ENA_S

0 ASRC1 Left Enable Status

(Left ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled

0 ASRC1R_ENA_S

0 ASRC1 Right Enable Status

(Right ASRC channel from ASYNCCLK domain to SYSCLK domain) 0 = Disabled 1 = Enabled R3810 (0EE2h) ASRC_RA TE1 14:11 ASRC_RATE1 [3:0]

0000 ASRC Sample Rate select for SYSCLK

0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 48kHz. The ASRC_IN1L_SRC and ASRC_IN1R_SRC registers should be set to 00h before ASRC_RATE1. R3811 (0EE3h) ASRC_RA TE2 14:11 ASRC_RATE2 [3:0]

1000 ASRC Sample Rate select for

1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 48kHz. The ASRC_IN2L_SRC and ASRC_IN2R_SRC registers should be set to 00h before ASRC_RATE2. Table 24 Digital Core ASRC Control

Rev 4.0 115 ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC) The WM8281 supports multiple signal paths through the digital core. The Isochronous Sample Rate Converters (ISRCs) provide sample rate conversion between synchronised sample rates on the SYSCLK clock domain, or between synchronised sample rates on the ASYNCCLK clock domain. There are three Isochronous Sample Rate Converters (ISRCs). Each of these provides four signal paths between two different sample rates, as illustrated in Figure 41. The sample rates associated with each ISRC can be set independently. Note that the two sample rates associated with any single ISRC must both be referenced to the same clock domain (SYSCLK or ASYNCCLK). When an ISRC is used on the SYSCLK domain, then the associated sample rates may be selected from SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3. When an ISRC is used on the ASYNCCLK domain, then the associated sample rates are ASYNC_SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_2. See “Clocking and Sample Rates” for details of the sample rate control registers. Each ISRC supports sample rates in the range 8kHz to 192 kHz. The higher of the sample rates associated with each ISRC must be an integer multiple of the lower sample rate; all possible integer ratios are supported (ie. up to 24). Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where ‘n’ identifies the applicable ISRC 1, 2 or 3). Note that, in each case, the higher of the two sample rates must be selected by ISRCn_FSH. The ISRCn_FSL and ISRC n_FSH registers should not be changed if any of the respective *_S RCn registers is non -zero. The associated *_SRC n registers should be cleared to 00h before writing new values to ISRCn_FSL or ISRCn_FSH. A minimum delay of 125µs should be allowed between clearing the *_SRCn registers and writing to the associated ISRCn_FSL or ISRC n_FSH registers. See Table 25 for further details. The ISRCn ‘interpolation’ paths (increasing sample rate) are enabled using the ISRCn_INT1_ENA, ISRCn_INT2_ENA, ISRCn_INT3_ENA and ISRCn_INT4_ENA register bits. The ISRCn ‘decimation’ paths (decreasing sample rate) are enabled using the ISRCn_DEC1_ENA, ISRCn_DEC2_ENA, ISRCn_DEC3_ENA and ISRCn_DEC4_ENA register bits. A notch filter is provided in each of the ISRC paths; these are enabled using the ISRCn_NOTCH_ENA bits . The filter is configured automatically according to the applicable sample rate(s). It is recommended to enable the filter for typical applications. Disabling the filter will provide maximum ‘pass’ bandwidth, at the expense of degraded stopband attenuation. The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded ISRC and digital mixing functions. If an attempt is made to enable an ISRC signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error condition occurs, then th ese bits provide readback of which mixer(s) have been successfully enabled. The Isochronous Sample Rate Converter (ISRC) signal paths and control registers are illustrated in Figure 41.

116 Rev 4.0 WM8281 supports 3 ISRC blocks, ie. n = 1, 2 or 3 ISRCn_INT2_ENA ISRCn_INT3_ENA ISRCn_INT4_ENA ISRCn_INT1_ENAISRCnINT1_SRC ISRCnINT3_SRC ISRCnINT4_SRC ISRCnINT2_SRC ISRC1 INT1 (A0h) ISRC2 INT1 (A8h) ISRC3 INT1 (B0h) ISRC1 INT2 (A1h) ISRC2 INT2 (A9h) ISRC3 INT2 (B1h) ISRC1 INT3 (A2h) ISRC2 INT3 (AAh) ISRC3 INT3 (B2h) ISRC1 INT4 (A3h) ISRC2 INT4 (ABh) ISRC3 INT4 (B3h) ISRCn_DEC2_ENA ISRCn_DEC3_ENA ISRCn_DEC4_ENA ISRCn_DEC1_ENA ISRCnDEC1_SRC ISRCnDEC3_SRC ISRCnDEC4_SRC ISRCnDEC2_SRC ISRC1 DEC1 (A4h) ISRC2 DEC1 (ACh) ISRC3 DEC1 (B4h) ISRC1 DEC2 (A5h) ISRC2 DEC2 (ADh) ISRC3 DEC2 (B5h) ISRC1 DEC3 (A6h) ISRC2 DEC3 (AEh) ISRC3 DEC3 (B6h) ISRC1 DEC4 (A7h) ISRC2 DEC4 (AFh) ISRC3 DEC4 (B7h) ISRCn_FSL ISRCn_FSH The ISRC provides synchronous conversion between two sample rates on either the SYSCLK or ASYNCCLK domain. ISRCn_FSL identifies the lower of the two sample rates. ISRCn_FSH identifies the higher of the two sample rates. Both sample rates must be referenced to the same clock domain (SYSCLK or ASYNCCLK). Figure 41 Isochronous Sample Rate Converters (ISRCs)

Rev 4.0 117 The ISRC input control registers (see Figure 41) are located at register addresses R2816 (B00h) through to R3000 (0BB8h). The full list of digital mixer control registers is provided in the “ Register Map” section (Register R1600 through to R3000). Generic register definitions are provided in Table 8. The *_SRC regi sters select the input source(s) for the respective ISRC processing blocks. Note that the selected input source(s) must be configured for the same sample rate as the ISRC to which they are connected. The bracketed numbers in Figure 41, eg. “(A4h)” indicate the corresponding *_SRC register setting for selection of that signal as an input to another digital core function. The register bits associated with the ISRCs are described in Table 25. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3824 (0EF0h) ISRC 1 CTRL 1 14:11 ISRC1_FSH [3:0] 0000 ISRC1 High Sample Rate (Sets the higher of the ISRC1 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC1_FSH and ISRC1_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC1_DECn_SRC registers should be set to 00h before changing ISRC1_FSH. R3825 (0EF1h) ISRC 1 CTRL 2 14:11 ISRC1_FSL [3:0] 0000 ISRC1 Low Sample Rate (Sets the lower of the ISRC1 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC1_FSH and ISRC1_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC1_INTn_SRC registers should be set to 00h before changing ISRC1_FSL. R3826 (0EF2h) ISRC 1 CTRL 3

15 ISRC1_INT1_EN

A

0 ISRC1 INT1 Enable

(Interpolation Channel 1 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled

14 ISRC1_INT2_EN

A

0 ISRC1 INT2 Enable

(Interpolation Channel 2 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled

118 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

13 ISRC1_INT3_EN

A

0 ISRC1 INT3 Enable

(Interpolation Channel 3 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled

12 ISRC1_INT4_EN

A

0 ISRC1 INT4 Enable

(Interpolation Channel 4 path from ISRC1_FSL rate to ISRC1_FSH rate) 0 = Disabled 1 = Enabled

9 ISRC1_DEC1_EN

A

0 ISRC1 DEC1 Enable

(Decimation Channel 1 path from ISRC1_FSH rate to ISRC1_FSL rate) 0 = Disabled 1 = Enabled

8 ISRC1_DEC2_EN

A

0 ISRC1 DEC2 Enable

(Decimation Channel 2 path from ISRC1_FSH rate to ISRC1_FSL rate) 0 = Disabled 1 = Enabled

7 ISRC1_DEC3_EN

A

0 ISRC1 DEC3 Enable

(Decimation Channel 3 path from ISRC1_FSH rate to ISRC1_FSL rate) 0 = Disabled 1 = Enabled

6 ISRC1_DEC4_EN

A

0 ISRC1 DEC4 Enable

(Decimation Channel 4 path from ISRC1_FSH rate to ISRC1_FSL rate) 0 = Disabled 1 = Enabled

0 ISRC1_NOTCH_

0 ISRC1 Notch Filter Enable

0 = Disabled 1 = Enabled It is recommended to enable the notch filter for typical applications. R3827 (0EF3h) ISRC 2 CTRL 1 14:11 ISRC2_FSH [3:0] 0000 ISRC2 High Sample Rate (Sets the higher of the ISRC2 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC2_FSH and ISRC2_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC2_DECn_SRC registers should be set to 00h before changing ISRC2_FSH.

Rev 4.0 119 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3828 (0EF4h) ISRC 2 CTRL 2 14:11 ISRC2_FSL [3:0] 0000 ISRC2 Low Sample Rate (Sets the lower of the ISRC2 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC2_FSH and ISRC2_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC2_INTn_SRC registers should be set to 00h before changing ISRC2_FSL. R3829 (0EF5h) ISRC 2 CTRL 3

15 ISRC2_INT1_EN

A

0 ISRC2 INT1 Enable

(Interpolation Channel 1 path from ISRC2_FSL rate to ISRC2_FSH rate) 0 = Disabled 1 = Enabled

14 ISRC2_INT2_EN

A

0 ISRC2 INT2 Enable

(Interpolation Channel 2 path from ISRC2_FSL rate to ISRC2_FSH rate) 0 = Disabled 1 = Enabled

13 ISRC2_INT3_EN

A

0 ISRC2 INT3 Enable

(Interpolation Channel 3 path from ISRC2_FSL rate to ISRC2_FSH rate) 0 = Disabled 1 = Enabled

12 ISRC2_INT4_EN

A

0 ISRC2 INT4 Enable

(Interpolation Channel 4 path from ISRC2_FSL rate to ISRC2_FSH rate) 0 = Disabled 1 = Enabled

9 ISRC2_DEC1_EN

A

0 ISRC2 DEC1 Enable

(Decimation Channel 1 path from ISRC2_FSH rate to ISRC2_FSL rate) 0 = Disabled 1 = Enabled

8 ISRC2_DEC2_EN

A

0 ISRC2 DEC2 Enable

(Decimation Channel 2 path from ISRC2_FSH rate to ISRC2_FSL rate) 0 = Disabled 1 = Enabled

7 ISRC2_DEC3_EN

A

0 ISRC2 DEC3 Enable

(Decimation Channel 3 path from ISRC2_FSH rate to ISRC2_FSL rate) 0 = Disabled 1 = Enabled

6 ISRC2_DEC4_EN

A

0 ISRC2 DEC4 Enable

(Decimation Channel 4 path from ISRC2_FSH rate to ISRC2_FSL rate) 0 = Disabled 1 = Enabled

120 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 ISRC2_NOTCH_

0 ISRC2 Notch Filter Enable

0 = Disabled 1 = Enabled It is recommended to enable the notch filter for typical applications. R3830 (0EF6h) ISRC 3 CTRL 1 14:11 ISRC3_FSH [3:0] 0000 ISRC3 High Sample Rate (Sets the higher of the ISRC3 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC3_FSH and ISRC3_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC3_DECn_SRC registers should be set to 00h before changing ISRC3_FSH. R3831 (0EF7h) ISRC 3 CTRL 2 14:11 ISRC3_FSL [3:0] 0000 ISRC3 Low Sample Rate (Sets the lower of the ISRC3 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC3_FSH and ISRC3_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). All ISRC3_INTn_SRC registers should be set to 00h before changing ISRC3_FSL. R3832 (0EF8h) ISRC 3 CTRL 3

15 ISRC3_INT1_EN

A

0 ISRC3 INT1 Enable

(Interpolation Channel 1 path from ISRC3_FSL rate to ISRC3_FSH rate) 0 = Disabled 1 = Enabled

14 ISRC3_INT2_EN

A

0 ISRC3 INT2 Enable

(Interpolation Channel 2 path from ISRC3_FSL rate to ISRC3_FSH rate) 0 = Disabled 1 = Enabled

13 ISRC3_INT3_EN

A

0 ISRC3 INT3 Enable

(Interpolation Channel 3 path from ISRC3_FSL rate to ISRC3_FSH rate) 0 = Disabled 1 = Enabled

Rev 4.0 121 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

12 ISRC3_INT4_EN

A

0 ISRC3 INT4 Enable

(Interpolation Channel 4 path from ISRC3_FSL rate to ISRC3_FSH rate) 0 = Disabled 1 = Enabled

9 ISRC3_DEC1_EN

A

0 ISRC3 DEC1 Enable

(Decimation Channel 1 path from ISRC3_FSH rate to ISRC3_FSL rate) 0 = Disabled 1 = Enabled

8 ISRC3_DEC2_EN

A

0 ISRC3 DEC2 Enable

(Decimation Channel 2 path from ISRC3_FSH rate to ISRC3_FSL rate) 0 = Disabled 1 = Enabled

7 ISRC3_DEC3_EN

A

0 ISRC3 DEC3 Enable

(Decimation Channel 3 path from ISRC3_FSH rate to ISRC3_FSL rate) 0 = Disabled 1 = Enabled

6 ISRC3_DEC4_EN

A

0 ISRC3 DEC4 Enable

(Decimation Channel 4 path from ISRC3_FSH rate to ISRC3_FSL rate) 0 = Disabled 1 = Enabled

0 ISRC3_NOTCH_

0 ISRC3 Notch Filter Enable

0 = Disabled 1 = Enabled It is recommended to enable the notch filter for typical applications. Table 25 Digital Core ISRC Control

122 Rev 4.0 DSP FIRMWARE CONTROL The WM8281 digital core incorporates four DSP processing blocks, capable of running a wide range of audio enhancement functions. Different firmware configurations can be loaded onto each DSP, enabling the WM8281 to be highly customised for specific application requirements. Synchronisation of different DSPs is supported, and shared data memory space is provided for the DSP2 and DSP3 blocks; these features enable enhanced processing capabilities for the associated DSPs. Examples of the DSP functions include Virt ual Surround Sound (VSS), Multiband Compressor (MBC) , and signal enhancements such as Ez2 Hear™ . Note that it is possible to implement more than one type of audio enhancement function on a single DSP; the precise combination(s) of functions will vary from one firmware configuration to another. DSP firmware can be configured using Cirrus Logic-supplied software packages. A software programming guide can also be provided to assist users in developing their own software algorithms - please contact your local Cirrus Logic representative for further information. In order to use the DSP blocks, the required firmware configuration must first be loaded onto the device by writing the appropriate files to the WM8281 register map. The firmware configuration will comprise Program, Coefficient and Data content. In some cases, the Coefficient content must be derived using tools provided in Cirrus Logic’s WISCE™ evaluation board control software. Details of how to load the firmware configuration onto the WM8281 are described below. Note that the WISCE evaluation board control software provides support for easy loading of Program, Coefficient and Data content onto the WM8281. Please contact your local Cirrus Logic representative for more details of the WISCE evaluation board control software. After loading the DSP firmware, the DSP functions must be enabled using the ass ociated register control fields. The audio signal paths connecting to/from the DSP processing blocks are configured as described in the “ Digital Core ” section. Note that t he DSP firmware must be loaded and enabled before audio signal paths can be enabled. DSP FIRMWARE MEMORY CONTROL The DSP firmware memory is programmed by writing to the registers referenced in Table 26. Note that the DSP clock must be configured and enabled for the respective DS P block to support read/write access to these registers. The WM8281 Program, Coefficient and Data register memory space is described in Table 26. See “Register Map” for a definition of these register addresses. The shared DSP2/DSP3 memory space is implemented at two different register address locations; note that reading or writing at either address will access the same memory data. If multiple DSPs write to a shared memory address at the same time, then the address at which the collision occurred will be reported in the DSP 3_DUALMEM_COLLISION_ADDR register. Note that this field is coded in 24 -bit DSP data word units, and is defined relative to the base address of the applicable shared memory area. The DSP memory controller provides an input to the Interrupt Controller circuit. An interrupt event is triggered if a memory collision oc curs. (Note that the DSP software should be written to ensure this never happens; the interrupt is intended for development purposes only.) See “ Interrupts” for more details of the Interrupt event handling. The Program firmware parameters are formatted as 40 -bit words. For this reason, 3 x 16 -bit register addresses are required for each 40-bit word. The Coefficient and Data firmware parameters are formatted as 24 -bit words. For this reason, 2 x 16 - bit register addresses are required for each 24-bit word.

Rev 4.0 123 DESCRIPTION REGISTER ADDRESS DSP MEMORY SIZE DSP1 Program memory 10_0000h to 10_5FFFh (24576 registers) 8k x 40-bit words Coefficient memory 18_0000h to 18_1FFFh (8192 registers) 4k x 24-bit words X Data memory 19_0000h to 19_7FFFh (32768 registers) 16k x 24-bit words Y Data memory 1A_8000h to 1A_9FFFh (8192 registers) 4k x 24-bit words DSP2 Program memory 20_0000h to 20_EFFFh (61440 registers) 20k x 40-bit words Coefficient memory 28_0000h to 28_1FFFh (8192 registers) 4k x 24-bit words X Data memory 29_0000h to 29_BFFFh (49152 registers) 24k x 24-bit words X Data memory (Shared DSP2/DSP3) 2A_6000h to 2A_7FFFh (8192 registers) 4k x 24-bit words Y Data memory 2A_8000h to 2B_3FFFh (49152 registers) 24k x 24-bit words DSP3 Program memory 30_0000h to 30_EFFFh (61440 registers) 20k x 40-bit words Coefficient memory 38_0000h to 38_1FFFh (8192 registers) 4k x 24-bit words X Data memory 39_0000h to 3A_1FFFh (73728 registers) 36k x 24-bit words X Data memory (Shared DSP2/DSP3) 3A_6000h to 3A_7FFFh (8192 registers) 4k x 24-bit words Y Data memory 3A_8000h to 3B_3FFFh (49152 registers) 24k x 24-bit words DSP4 Program memory 40_0000h to 40_5FFFh (24576 registers) 8k x 40-bit words Coefficient memory 48_0000h to 48_1FFFh (8192 registers) 4k x 24-bit words X Data memory 49_0000h to 49_7FFFh (32768 registers) 16k x 24-bit words Y Data memory 4A_8000h to 4A_9FFFh (8192 registers) 4k x 24-bit words Table 26 DSP Program, Coefficient and Data Registers Clocking is required for any functionality of the DSP processing blocks, including any register read/write operations associated with DSP firmware loading. The clock source for each DSP is derived from SYSCLK, which must also be enabled. See “ Clocking and Sample Rates” for details of how to configure SYSCLK. The DSP clock frequency is selected using the DSPn_CLK_SEL register. Note that the DSP clock frequency must be less than or equal to the SYSCLK freque ncy. The frequencies must be integer - related (eg. divide by 1, 2, 3 etc.). The clock source for each DSP block is enabled using DSPn_SYS_ENA (where ‘n’ identifies the applicable DSP processing block 1, 2, 3 or 4). The clock must be enabled before (or simul taneous to) enabling the respective DSP Core or DMA channels. The clock must be disabled after (or simultaneous to) disabling the DSP Core and DMA channels. The DSPn_CLK_SEL_STS fields provide readback of the clock frequency for the respective DSP cores. T hese can be used to confirm the clock frequency, in cases where code execution has a minimum clock frequency requirement. The DSPn_CLK_SEL_STS field is only valid when the respective DSP Clock is enabled; typical typical usage of this field would be for th e DSP core itself to readback the clock status, and to take action as applicable (in particular, if the available clock does not meet the application requirements). The DSPn_RAM_RDY status bits indicate when the respective DSP firmware memory registers are ready for read/write access. The respective DSP memories should not be accessed until this bit has been set. The DSP RAM Ready flags are inputs to the Interrupt control circuit and can be used to trigger a n interrupt event - see “Interrupts”. The DSP RAM Ready flags can be output directly on a GPIO pin as an external indication of the DSP RAM Status. See “General Purpose Input / Output” to configure a GPIO pin for this function. Under default register conditions, t he DSP firmware memory contents are retained if the respective clock is disabled, and also during Hardware Reset and Software Reset ; this is selectable using the DSPn_MEM_ENA register bits, as described below. When DSPn_MEM_ENA = 1 (default), the DSP firmware memory is retained when the DSP clock is disabled (ie. when DSPn_SYS_ENA = 0). It is also retained during Hardware Reset and Software Reset, provided DCVDD is held above its reset threshold.

124 Rev 4.0 When DSPn_MEM_ENA = 0, the DSP firmware memory is disabled (and the contents lost) when DSPn_SYS_ENA = 0. It is also disabled during Hardware Reset and Software Reset. P ower consumption is reduced when the memory is disabled , but the DSP firmware must then be reloaded when required. Note that the DSP firmware memory is always cleared under Power -On Reset (POR) and ‘Sleep’ mode conditions. See the “ Applications Information” section for a summary of the WM8281 memory reset conditions. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4352 (1100h) DSP1 Control 1

4 DSP1_MEM_EN

A

1 DSP1 Memory Control

0 = DSP1 memory is cleared when DSP1_SYS_ENA=0, and during Hardware Reset or Software Reset. 1 = DSP1 memory is retained when DSP1_SYS_ENA=0. DSP1 memory is retained during Hardware Reset and Software Reset.

2 DSP1_SYS_ENA 0 DSP1 Clock Enable

0 = Disabled 1 = Enabled The DSP1 Clock must be enabled for DSP1 firmware register access, code execution, or DMA operation. The DSP1 Core must be reset (by writing DSP1_CORE_ENA=0) when disabling the DSP1 Clock. R4353 (1101h) DSP1 Clocking 1 2:0 DSP1_CLK_SEL [2:0]

000 DSP1 Clock Frequency Select

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The DSP1 Clock must be less than or equal to the SYSCLK frequency. The frequencies must also be integer-related (eg. divide by 1, 2, 3 etc.). The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX). R4356 (1104h) DSP1 Status 1

0 DSP1_RAM_RD

Y

0 DSP1 Memory Status

0 = Not ready 1 = Ready Note - DSP1 memory should not be accessed until this bit has been set.

Rev 4.0 125 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4358 (1106h) DSP1 Status 3 3:1 DSP1_CLK_SEL _STS [2:0

000 DSP1 Clock Frequency

(Read only, Only valid when the respective DSP Clock is enabled) 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX).

0 DSP1_CLK_AVAI

L

0 DSP1 Clock Availability

(Read only) 0 = No Clock 1 = Clock Available Note – this bit exists for legacy software support only; it is not recommended for future designs, as the readback may be unreliable on the latest device architectures. R4608 (1200h) DSP2 Control 1

4 DSP2_MEM_EN

A

1 DSP2 Memory Control

0 = DSP2 memory is cleared when DSP2_SYS_ENA=0, and during Hardware Reset or Software Reset. 1 = DSP2 memory is retained when DSP2_SYS_ENA=0. DSP2 memory is retained during Hardware Reset and Software Reset.

2 DSP2_SYS_ENA 0 DSP2 Clock Enable

0 = Disabled 1 = Enabled The DSP2 Clock must be enabled for DSP2 firmware register access, code execution, or DMA operation. The DSP2 Core must be reset (by writing DSP2_CORE_ENA=0) when disabling the DSP2 Clock. R4609 (1201h) DSP2 Clocking 1 2:0 DSP2_CLK_SEL [2:0]

000 DSP2 Clock Frequency Select

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The DSP2 Clock must be less than or equal to the SYSCLK frequency. The frequencies must also be integer-related (eg. divide by 1, 2, 3 etc.). The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX).

126 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4612 (1204h) DSP2 Status 1

0 DSP2_RAM_RD

Y

0 DSP2 Memory Status

0 = Not ready 1 = Ready Note - DSP2 memory should not be accessed until this bit has been set. R4614 (1206h) DSP2 Status 3 3:1 DSP2_CLK_SEL _STS [2:0

000 DSP2 Clock Frequency

(Read only, Only valid when the respective DSP Clock is enabled) 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX).

0 DSP2_CLK_AVAI

L

0 DSP2 Clock Availability

(Read only) 0 = No Clock 1 = Clock Available Note – this bit exists for legacy software support only; it is not recommended for future designs, as the readback may be unreliable on the latest device architectures. R4864 (1300h) DSP3 Control 1

4 DSP3_MEM_EN

A

1 DSP3 Memory Control

0 = DSP3 memory is cleared when DSP3_SYS_ENA=0, and during Hardware Reset or Software Reset. 1 = DSP3 memory is retained when DSP3_SYS_ENA=0. DSP3 memory is retained during Hardware Reset and Software Reset.

2 DSP3_SYS_ENA 0 DSP3 Clock Enable

0 = Disabled 1 = Enabled The DSP3 Clock must be enabled for DSP3 firmware register access, code execution, or DMA operation. The DSP3 Core must be reset (by writing DSP3_CORE_ENA=0) when disabling the DSP3 Clock.

Rev 4.0 127 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4865 (1301h) DSP3 Clocking 1 2:0 DSP3_CLK_SEL [2:0]

000 DSP3 Clock Frequency Select

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The DSP3 Clock must be less than or equal to the SYSCLK frequency. The frequencies must also be integer-related (eg. divide by 1, 2, 3 etc.). The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX). R4868 (1304h) DSP3 Status 1

0 DSP3_RAM_RD

Y

0 DSP3 Memory Status

0 = Not ready 1 = Ready Note - DSP3 memory should not be accessed until this bit has been set. R4870 (1306h) DSP3 Status 3 3:1 DSP3_CLK_SEL _STS [2:0

000 DSP3 Clock Frequency

(Read only, Only valid when the respective DSP Clock is enabled) 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX).

0 DSP3_CLK_AVAI

L

0 DSP3 Clock Availability

(Read only) 0 = No Clock 1 = Clock Available Note – this bit exists for legacy software support only; it is not recommended for future designs, as the readback may be unreliable on the latest device architectures. R4871 (1307h) DSP3 Status 4 15:0 DSP3_DUALME M_COLLISION_A DDR [15:0] 0000h DSP3 Dual Memory Collision Address In the event of a DSP3 memory access collision, this field will report the address at which the collision occurred. The address is defined relative to the base address of the shared data memory. The LSB represents one 24-bit DSP memory word.

128 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5120 (1400h) DSP4 Control 1

4 DSP4_MEM_EN

A

1 DSP4 Memory Control

0 = DSP4 memory is cleared when DSP4_SYS_ENA=0, and during Hardware Reset or Software Reset. 1 = DSP4 memory is retained when DSP4_SYS_ENA=0. DSP4 memory is retained during Hardware Reset and Software Reset.

2 DSP4_SYS_ENA 0 DSP4 Clock Enable

0 = Disabled 1 = Enabled The DSP4 Clock must be enabled for DSP4 firmware register access, code execution, or DMA operation. The DSP4 Core must be reset (by writing DSP4_CORE_ENA=0) when disabling the DSP4 Clock. R5121 (1401h) DSP4 Clocking 1 2:0 DSP4_CLK_SEL [2:0]

000 DSP4 Clock Frequency Select

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The DSP4 Clock must be less than or equal to the SYSCLK frequency. The frequencies must also be integer-related (eg. divide by 1, 2, 3 etc.). The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX). R5124 (1404h) DSP4 Status 1

0 DSP4_RAM_RD

Y

0 DSP4 Memory Status

0 = Not ready 1 = Ready Note - DSP4 memory should not be accessed until this bit has been set. R5126 (1406h) DSP4 Status 3 3:1 DSP4_CLK_SEL _STS [2:0

000 DSP4 Clock Frequency

(Read only, Only valid when the respective DSP Clock is enabled) 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX).

Rev 4.0 129 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 DSP4_CLK_AVAI

L

0 DSP4 Clock Availability

(Read only) 0 = No Clock 1 = Clock Available Note – this bit exists for legacy software support only; it is not recommended for future designs, as the readback may be unreliable on the latest device architectures. Table 27 DSP Clocking Control DSP FIRMWARE EXECUTION After the DSP firmware has been loaded, and the clocks configured, the DSP block s are enabled using the DSPn_CORE_ENA register bits. When the DSP is configured and enabled, the firmware execution can be started by writing ‘1’ to the respective DSPn_START bit. Alternative methods to trigger the firmware execution can also be configured using the DSPn_START_IN_SEL register fields. Note that t his provides the capability to synchronously trigger multiple DSP blocks. Using the DSPn_START_IN_SEL registers, the DSP firmware execution can be linked to the respective DMA function, the IRQ2 status, or to configurable ‘DSPn Start’ signals from another DSP. The ‘DSPn Start’ signals are generated within the DSP cores, enabling any of the DSP blocks to trigger code execution in another DSP. The DSPn_CORE_ENA bit must be set to ‘1’ to enable firmware execution on the respective DSP block. Note that t he usage of the DSPn_START bit may vary dependi ng on the particular software that is being executed: in some applications (eg. when an alternative trigger is selected using DSPn_START_IN_SEL), writing to the DSPn_START bit will not be required. For read/write access to the DSP firmware memory registers , the respective firmware execution must be disabled by setting the DSPn_CORE_ENA bit to ‘0’. The audio signal paths connecting to/from the DSP processing blocks are configured as described in the “ Digital Core ” section. Note that the DSP firmware must be loaded and enabled before audio signal paths can be enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4352 (1100h) DSP1 Control 1

1 DSP1_CORE_EN

A

0 DSP1 Enable

Controls the DSP1 firmware execution 0 = Disabled 1 = Enabled

0 DSP1_START DSP1 Start

Write ‘1’ to Start DSP1 firmware execution R4408 (1138h) 3:0 DSP1_START_IN _SEL [3:0] 0h DSP1 Firmware Execution control Selects the trigger for DSP1 firmware execution. 0 = DMA 3 = DSP2 Start 1 4 = DSP2 Start 2 5 = DSP3 Start 1 6 = DSP3 Start 2 7 = DSP4 Start 1 8 = DSP4 Start 2 11 = IRQ2 All other codes are Reserved. Note that the DSP1_START bit will also start the DSP1 firmware execution, regardless of this register setting.

130 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4608 (1200h) DSP2 Control 1

1 DSP2_CORE_EN

A

0 DSP2 Enable

Controls the DSP2 firmware execution 0 = Disabled 1 = Enabled

0 DSP2_START DSP2 Start

Write ‘1’ to Start DSP2 firmware execution R4664 (1238h) 3:0 DSP2_START_IN _SEL [3:0] 0h DSP2 Firmware Execution control Selects the trigger for DSP2 firmware execution. 0 = DMA 1 = DSP1 Start 1 2 = DSP1 Start 2 5 = DSP3 Start 1 6 = DSP3 Start 2 7 = DSP4 Start 1 8 = DSP4 Start 2 11 = IRQ2 All other codes are Reserved. Note that the DSP2_START bit will also start the DSP2 firmware execution, regardless of this register setting. R4864 (1300h) DSP3 Control 1

1 DSP3_CORE_EN

A

0 DSP3 Enable

Controls the DSP3 firmware execution 0 = Disabled 1 = Enabled

0 DSP3_START DSP3 Start

Write ‘1’ to Start DSP3 firmware execution R4920 (1338h) 3:0 DSP3_START_IN _SEL [3:0] 0h DSP3 Firmware Execution control Selects the trigger for DSP3 firmware execution. 0 = DMA 1 = DSP1 Start 1 2 = DSP1 Start 2 3 = DSP2 Start 1 4 = DSP2 Start 2 7 = DSP4 Start 1 8 = DSP4 Start 2 11 = IRQ2 All other codes are Reserved. Note that the DSP3_START bit will also start the DSP3 firmware execution, regardless of this register setting. R5120 (1400h) DSP4 Control 1

1 DSP4_CORE_EN

A

0 DSP4 Enable

Controls the DSP4 firmware execution 0 = Disabled 1 = Enabled

0 DSP4_START DSP4 Start

Write ‘1’ to Start DSP4 firmware execution

Rev 4.0 131 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5176 (1438h) 3:0 DSP4_START_IN _SEL [3:0] 0h DSP4 Firmware Execution control Selects the trigger for DSP4 firmware execution. 0 = DMA 1 = DSP1 Start 1 2 = DSP1 Start 2 3 = DSP2 Start 1 4 = DSP2 Start 2 5 = DSP3 Start 1 6 = DSP3 Start 2 11 = IRQ2 All other codes are Reserved. Note that the DSP4_START bit will also start the DSP4 firmware execution, regardless of this register setting. Table 28 DSP Firmware Execution DSP DIRECT MEMORY ACCESS (DMA) CONTROL Each DSP provides a multi -channel DMA function; this is configured using the registers described in Table 29. There are 8 WDMA (DSP input) and 6 RDMA (DSP output) channels for each DSP; these are enabled using the DSPn_WDMA_CHANNEL_ENABLE and DSPn_RDMA_CHANNEL_ENABLE fields. The status of each WDMA channel is indicated in DSPn_WDMA_ACTIVE_CHANNELS. The DMA can access the X data memory or Y data memory associated with the respective DSP. The applicable memory is selected using bit [15] of the respective *_START_ADDRESS register. The start address of each DMA channel is configured as described in Table 29. Note that the required address is defined relative to the base address of the selected (X data or Y data) memory. The buffer length of the DMA channels is configured using the DSPn_WDMA_BUFFER_LENGTH field. The selected buffer length applies to all enabled WDMA or RDMA channels. Note that the start address registers, and WDMA buffer length registers, are defined in 24 -bit DSP data word units. This means that the LSB of these fields represents one 24 -bit DSP memory word. (Note that this differs from the WM8281 register map layout, as described in Table 26). The parameters of a DMA channel (ie. Start Address or Offset Address) must not be changed whilst the respective DMA is enabled. All of the DMA channels must be disabled before changing the WDMA buffer length. Each DMA channel uses a twin buffer mechanism to support uninterrupted data flow through the DSP. The buffers are called ‘ping’ and ‘pong’ respectively, and are of configurable size, as noted above. Data is transferred to/from each of the buffers in turn. When the ‘ping’ input data buffer is full, the DSPn_PING_FULL bit will be asserted (set to ‘1’), and a ‘DSP Start’ signal will be generated. The ‘Start’ signal from the DMA is typically used to start Firmware execution, as noted in Table 28. Meanwhile, further DSP input data will be filling up the ‘pong’ buffer. When the ‘pong’ input buffer is full, the DSPn_PONG_FULL bit will be asserted, and another ‘DSP Start’ signal will be generated. The DSP Firmware must take care to read the input data from the applicable buffer, in accordance with the DSPn_PING_FULL and DSPn_PONG_FULL status bits. Twin buffers are also used on the DSP output (RDMA) channels. The output ‘ping’ buffers are emptied at the same time as the input ‘ping’ buffers are filled; the output ‘pong’ buffers are emptied at the same time as the input ‘pong’ buffers are filled. Further details of the DMA are provided in the software programming guide - please contact your local Cirrus Logic representative if required.

132 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4357 (1105h) DSP1 Status 2

15 DSP1_PING_FU

0 DSP1 WDMA Ping Buffer Status

0 = Not Full 1 = Full

14 DSP1_PONG_FU

0 DSP1 WDMA Pong Buffer Status

0 = Not Full 1 = Full 7:0 DSP1_WDMA_A CTIVE_CHANNE LS [7:0] 00h DSP1 WDMA Channel Status There are 8 WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as: 0 = Inactive 1 = Active R4368 (1110h) to R4375 (1117h) 15:0 DSP1_START_A DDRESS_WDMA _BUFFER_n [15:0] 0000h DSP1 WDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP1_WDMA_CHANNEL_OFFSET bit. R4384 (1120h) to R4389 (1125h) 15:0 DSP1_START_A DDRESS_RDMA _BUFFER_n [15:0] 0000h DSP1 RDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP1_RDMA_CHANNEL_OFFSET bit. R4400 (1130h) DSP1 WDMA Config 1 13:0 DSP1_WDMA_B UFFER_LENGTH [13:0] 0000h DSP1 DMA Buffer Length Selects the amount of data transferred in each WDMA channel. The LSB represents one 24-bit DSP memory word. R4401 (1131h) DSP1 WDMA Config 2 7:0 DSP1_WDMA_C HANNEL_ENABL E [7:0] 00h DSP1 WDMA Channel Enable There are 8 WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled

Rev 4.0 133 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4402 (1132h) DSP1 WDMA Offset 1 7:0 DSP1_WDMA_C HANNEL_OFFSE T [7:0] 00h DSP1 WDMA Channel Offset There are 8 WDMA channels; each bit of this field offsets the Start Address of the respective WDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R4404 (1134h) DSP1 RDMA Config 1 5:0 DSP1_RDMA_C HANNEL_ENABL E [5:0] 00h DSP1 RDMA Channel Enable There are 6 RDMA channels; each bit of this field enables the respective RDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4405 (1135h) DSP1 RDMA Offset 1 5:0 DSP1_RDMA_C HANNEL_OFFSE T [5:0] 00h DSP1 RDMA Channel Offset There are 6 RDMA channels; each bit of this field offsets the Start Address of the respective RDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R4613 (1205h) DSP2 Status 2

15 DSP2_PING_FU

0 DSP2 WDMA Ping Buffer Status

0 = Not Full 1 = Full

14 DSP2_PONG_FU

0 DSP2 WDMA Pong Buffer Status

0 = Not Full 1 = Full 7:0 DSP2_WDMA_A CTIVE_CHANNE LS [7:0] 00h DSP2 WDMA Channel Status There are 8 WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as: 0 = Inactive 1 = Active R4624 (1210h) to R4631 (1217h) 15:0 DSP2_START_A DDRESS_WDMA _BUFFER_n [15:0] 0000h DSP2 WDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP2_WDMA_CHANNEL_OFFSET bit.

134 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4640 (1220h) to R4645 (1225h) 15:0 DSP2_START_A DDRESS_RDMA _BUFFER_n [15:0] 0000h DSP2 RDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP2_RDMA_CHANNEL_OFFSET bit. R4656 (1230h) DSP2 WDMA Config 1 13:0 DSP2_WDMA_B UFFER_LENGTH [13:0] 0000h DSP2 DMA Buffer Length Selects the amount of data transferred in each WDMA channel. The LSB represents one 24-bit DSP memory word. R4657 (1231h) DSP2 WDMA Config 2 7:0 DSP2_WDMA_C HANNEL_ENABL E [7:0] 00h DSP2 WDMA Channel Enable There are 8 WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4658 (1232h) DSP2 WDMA Offset 1 7:0 DSP2_WDMA_C HANNEL_OFFSE T [7:0] 00h DSP2 WDMA Channel Offset There are 8 WDMA channels; each bit of this field offsets the Start Address of the respective WDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R4660 (1234h) DSP2 RDMA Config 1 5:0 DSP2_RDMA_C HANNEL_ENABL E [5:0] 00h DSP2 RDMA Channel Enable There are 6 RDMA channels; each bit of this field enables the respective RDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4661 (1235h) DSP2 RDMA Offset 1 5:0 DSP2_RDMA_C HANNEL_OFFSE T [5:0] 00h DSP2 RDMA Channel Offset There are 6 RDMA channels; each bit of this field offsets the Start Address of the respective RDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R4869 (1305h) DSP3 Status 2

15 DSP3_PING_FU

0 DSP3 WDMA Ping Buffer Status

0 = Not Full 1 = Full

14 DSP3_PONG_FU

0 DSP3 WDMA Pong Buffer Status

0 = Not Full 1 = Full

Rev 4.0 135 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 DSP3_WDMA_A CTIVE_CHANNE LS [7:0] 00h DSP3 WDMA Channel Status There are 8 WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as: 0 = Inactive 1 = Active R4880 (1310h) to R4887 (1317h) 15:0 DSP3_START_A DDRESS_WDMA _BUFFER_n [15:0] 0000h DSP3 WDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP3_WDMA_CHANNEL_OFFSET bit. R4896 (1320h) to R4901 (1325h) 15:0 DSP3_START_A DDRESS_RDMA _BUFFER_n [15:0] 0000h DSP3 RDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP3_RDMA_CHANNEL_OFFSET bit. R4912 (1330h) DSP3 WDMA Config 1 13:0 DSP3_WDMA_B UFFER_LENGTH [13:0] 0000h DSP3 DMA Buffer Length Selects the amount of data transferred in each WDMA channel. The LSB represents one 24-bit DSP memory word. R4913 (1331h) DSP3 WDMA Config 2 7:0 DSP3_WDMA_C HANNEL_ENABL E [7:0] 00h DSP3 WDMA Channel Enable There are 8 WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4914 (1332h) DSP3 WDMA Offset 1 7:0 DSP3_WDMA_C HANNEL_OFFSE T [7:0] 00h DSP3 WDMA Channel Offset There are 8 WDMA channels; each bit of this field offsets the Start Address of the respective WDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h

136 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4916 (1334h) DSP3 RDMA Config 1 5:0 DSP3_RDMA_C HANNEL_ENABL E [5:0] 00h DSP3 RDMA Channel Enable There are 6 RDMA channels; each bit of this field enables the respective RDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4917 (1335h) DSP3 RDMA Offset 1 5:0 DSP3_RDMA_C HANNEL_OFFSE T [5:0] 00h DSP3 RDMA Channel Offset There are 6 RDMA channels; each bit of this field offsets the Start Address of the respective RDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R5125 (1405h) DSP4 Status 2

15 DSP4_PING_FU

0 DSP4 WDMA Ping Buffer Status

0 = Not Full 1 = Full

14 DSP4_PONG_FU

0 DSP4 WDMA Pong Buffer Status

0 = Not Full 1 = Full 7:0 DSP4_WDMA_A CTIVE_CHANNE LS [7:0] 00h DSP4 WDMA Channel Status There are 8 WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as: 0 = Inactive 1 = Active R5136 (1410h) to R5143 (1417h) 15:0 DSP4_START_A DDRESS_WDMA _BUFFER_n [15:0] 0000h DSP4 WDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP4_WDMA_CHANNEL_OFFSET bit. R5152 (1420h) to R5157 (1425h) 15:0 DSP4_START_A DDRESS_RDMA _BUFFER_n [15:0] 0000h DSP4 RDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP4_RDMA_CHANNEL_OFFSET bit.

Rev 4.0 137 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5168 (1430h) DSP4 WDMA Config 1 13:0 DSP4_WDMA_B UFFER_LENGTH [13:0] 0000h DSP4 DMA Buffer Length Selects the amount of data transferred in each WDMA channel. The LSB represents one 24-bit DSP memory word. R5169 (1431h) DSP4 WDMA Config 2 7:0 DSP4_WDMA_C HANNEL_ENABL E [7:0] 00h DSP4 WDMA Channel Enable There are 8 WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R5170 (1432h) DSP4 WDMA Offset 1 7:0 DSP4_WDMA_C HANNEL_OFFSE T [7:0] 00h DSP4 WDMA Channel Offset There are 8 WDMA channels; each bit of this field offsets the Start Address of the respective WDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R5172 (1434h) DSP4 RDMA Config 1 5:0 DSP4_RDMA_C HANNEL_ENABL E [5:0] 00h DSP4 RDMA Channel Enable There are 6 RDMA channels; each bit of this field enables the respective RDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R5173 (1435h) DSP4 RDMA Offset 1 5:0 DSP4_RDMA_C HANNEL_OFFSE T [5:0] 00h DSP4 RDMA Channel Offset There are 6 RDMA channels; each bit of this field offsets the Start Address of the respective RDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h Table 29 DSP Direct Memory Access (DMA) Control DSP DEBUG SUPPORT General purpose ‘scratch’ registers are provided for each DSP. These have no assigned functio n, and can be used to assist in algorithm development. The JTAG interface provides test and debug access to the WM8281, as described in the “ JTAG Interface” section. The JTAG interface clock can be enabled independently for each DSP core, using the DSPn_DBG_CLK_ENA register bits. When using the JTAG interface to access any DSP core, the respecti ve DSPn_DBG_CLK_ENA, DSPn_SYS_ENA, and DSPn_CORE_ENA bits must all be set. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4352 (1100h) DSP1 Control 1

3 DSP1_DBG_CLK

_ENA

0 DSP1 Debug Clock Enable

0 = Disabled 1 = Enabled R4416 (1140h) DSP1 Scratch 0 15:0 DSP1_SCRATCH _0 [15:0] 0000h DSP1 Scratch Register 0

138 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4417 (1141h) DSP1 Scratch 1 15:0 DSP1_SCRATCH _1 [15:0] 0000h DSP1 Scratch Register 1 R4418 (1142h) DSP1 Scratch 2 15:0 DSP1_SCRATCH _2 [15:0] 0000h DSP1 Scratch Register 2 R4419 (1143h) DSP1 Scratch 3 15:0 DSP1_SCRATCH _3 [15:0] 0000h DSP1 Scratch Register 3 R4608 (1200h) DSP2 Control 1

3 DSP2_DBG_CLK

_ENA

0 DSP2 Debug Clock Enable

0 = Disabled 1 = Enabled R4672 (1240h) DSP2 Scratch 0 15:0 DSP2_SCRATCH _0 [15:0] 0000h DSP2 Scratch Register 0 R4673 (1241h) DSP2 Scratch 1 15:0 DSP2_SCRATCH _1 [15:0] 0000h DSP2 Scratch Register 1 R4674 (1242h) DSP2 Scratch 2 15:0 DSP2_SCRATCH _2 [15:0] 0000h DSP2 Scratch Register 2 R4675 (1243h) DSP2 Scratch 3 15:0 DSP2_SCRATCH _3 [15:0] 0000h DSP2 Scratch Register 3 R4864 (1300h) DSP3 Control 1

3 DSP3_DBG_CLK

_ENA

0 DSP3 Debug Clock Enable

0 = Disabled 1 = Enabled R4928 (1340h) DSP3 Scratch 0 15:0 DSP3_SCRATCH _0 [15:0] 0000h DSP3 Scratch Register 0 R4929 (1341h) DSP3 Scratch 1 15:0 DSP3_SCRATCH _1 [15:0] 0000h DSP3 Scratch Register 1 R4930 (1342h) DSP3 Scratch 2 15:0 DSP3_SCRATCH _2 [15:0] 0000h DSP3 Scratch Register 2 R4931 (1343h) DSP3 Scratch 3 15:0 DSP3_SCRATCH _3 [15:0] 0000h DSP3 Scratch Register 3 R5120 (1400h) DSP4 Control 1

3 DSP4_DBG_CLK

_ENA

0 DSP4 Debug Clock Enable

0 = Disabled 1 = Enabled

Rev 4.0 139 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5184 (1440h) DSP4 Scratch 0 15:0 DSP4_SCRATCH _0 [15:0] 0000h DSP4 Scratch Register 0 R5185 (1441h) DSP4 Scratch 1 15:0 DSP4_SCRATCH _1 [15:0] 0000h DSP4 Scratch Register 1 R5186 (1442h) DSP4 Scratch 2 15:0 DSP4_SCRATCH _2 [15:0] 0000h DSP4 Scratch Register 2 R5187 (1443h) DSP4 Scratch 3 15:0 DSP4_SCRATCH _3 [15:0] 0000h DSP4 Scratch Register 3 Table 30 DSP Debug Support

140 Rev 4.0 AMBIENT NOISE CANCELLATION The Cirrus Logic Ambient Noise Cancellation (ANC) processor within the WM8281 provides the capability to improve the intelligibility of a voice call by using destructive interference to reduce the acoustic energy of the ambient sound. The stereo ANC capability supports a wide variety of headset/handset applications. The ANC processor is configured using parameters that are determined during product development and downloaded to the WM8281. The configuration settings are specific to the acoustic properties of the target application. The p rimary acoustic elements in an application are typically the microphones and the speaker, but other components such as the plastics and the PCBs also have significant importance to the acoustic coefficient data. Note that the ANC configuration parameters a re application -specific, and must be recalculated following any change in the design of the acoustic elements of that application . Any mismatch between the acoustic coefficient data and the target application will give inferior ANC performance. The signal path configuration settings are adjusted during product calibration to compensate for component tolerances. Also, calibration allows DC offsets in the earpiece output path to be measured and compensated, thus reducing power consumption and minimising any p ops and clicks in the output signal path. The ANC processor employs stereo digital circuits to process the ambient noise (microphone) signals; the noise input paths (analogue or digital) are selected as described in Table 6. The selected sources are filtered and processed in accordance with the acoustic parameters programmed into the WM8281. The resulting noise cancellation signals can be mixed with the output signal pa ths using the register bits described in Table 63. Noise cancellation is applied selectively to different audio frequency bands; a low frequency limiter ensures that the ANC algorithms deliver noise reduction in the most sensitive frequency bands, without introducing distortion in other frequency bands. The ANC processor is adaptive to different ambient noise levels in order to provide the most natural sound at the headphone audio output. The stereo ANC signal processing supports a very high level of noise cancellation capability for a wide variety of headset/handset applications. It also incorporates a noise gating function, which ensures that the noise cancellation performance is optimised across a wide range of input signal conditions. Note that the ANC configuration data is lost whenever the DCVDD power domain is removed; the ANC configuration data must be downloaded to the WM8281 each time the device is powered up. The procedure for configuring the WM8281 ANC functions is tailored to each customer’s application; please contact your local Cirrus Logic representative for more details.

Rev 4.0 141 DIGITAL AUDIO INTERFACE The WM8281 provides three audio interfaces, AIF1, AFI2 and AIF3. Each of these is independently configurable on the respective transmit (TX) and receive (RX) paths. AIF1 supports up to 8 channels of input and output signal paths; AIF2 supports up to 6 channels of input and output signal paths; AIF3 supports up to 2 channels of input and output signal paths. The data source(s) for the audio interface transmit (TX) paths can be selected from any of the WM8281 input signal paths, or from the digital core processing functions. The audio interface receive (RX) paths can be selected as inputs to any of the digi tal core processing functions or digital core outputs. See “Digital Core” for details of the digital core routing options. The digital audio interfaces provide flexible connectivity for multiple processors and other audio devices. Typical connections include Applications Processor, Baseband Processor and Wireless Transceiver. Note that the SLIMbus interface also provides digit al audio input/output paths , providing options for additional interfaces. A typical configuration is illustrated in Figure 42. The audio interfaces AIF1, AIF2 and AIF3 are referenced to DBVDD1, DBVDD2 and DBVDD3 respectively, allowing the WM8281 to connect between application sub -systems on different voltage domains. Audio Interface 1 Audio Interface 2 Audio Interface 3 HDMI Device Baseband Processor Wireless Transceiver WM8281 SLIMbus interfaceApplications Processor Figure 42 Typical AIF Connections In the general case, the digital audio interface uses four pins:  TXDAT: Data output  RXDAT: Data input  BCLK: Bit clock, for synchronisation  LRCLK: Left/Right data alignment clock In master interface mode, the clock signals BCLK and LRCLK are outputs from the WM8281. In slave mode, these signals are inputs, as illustrated below. As an option, a GPIO pin can be configured as TXLRCLK, ie. the Left/Right clock for the TXDAT output. In this case, the LRCLK pin is dedicated to the RXDAT input , allowing the two sides to be clocked independently.

Rev 4.0 143 nn-1n-2321 nn-1n-2321 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK RXDAT/ TXDAT

1 BCLK

In Slave mode, the falling edge can occur anywhere in this area Figure 45 DSP Mode A Data Format nn-1n-2321 nn-1n-2321 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK RXDAT/ TXDAT

1 BCLK 1 BCLK

In Slave mode, the falling edge can occur anywhere in this area Figure 46 DSP Mode B Data Format PCM operation is supported in DSP interface mode. WM8281 data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by the WM8281 will be tre ated as Left Channel data. This data may be routed to the Left/Right playback paths using the control fields described in the “Digital Core” section. In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sa mple and the MSB of the next. nn-1n-2321 nn-1n-2321 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK RXDAT/ TXDAT Figure 47 I2S Data Format (assuming n-bit word length) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Rev 4.0 147 WM8281 Processor WM8281 or similar CODEC TXDAT LRCLK RXDAT BCLK TXDAT LRCLK RXDAT BCLK Figure 55 TDM with Processor as Master Note: The WM8281 is a 24-bit device. If the user operates the WM8281 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if necessary to the RXDAT line and the TXDAT line in TDM mode.

148 Rev 4.0 DIGITAL AUDIO INTERFACE CONTROL This section describes the configuration of the WM8281 digital audio interface paths. AIF1 supports up to 8 input signal paths and up to 8 output signal paths ; AIF2 supports up to 6 channels of input and output signal paths; AIF3 supports up to 2 channels of input and output signal paths. The digital audio interfaces AIF1, AIF2 and AIF3 can be configured as Master or Slave interfaces; mixed master/slave configurations are also possible. Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and AIF input ( RX) paths can use a common LRCLK frame clock, or can use separate LRCLK signals if required. The digital audio interface supports flexible data formats, selectable word-length, configurable timeslot allocations and TDM tri-state control. AIF SAMPLE RATE CONTROL The AIF RX inputs may be selected as input to the digital mixers or signal processing functions within the WM8281 digital core. The AIF TX outputs are derived from the respective output mixers. The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE register - see Table 23 within the “Digital Core” section. Note that sample rate conversion is required when routing the AIF paths to any signal chain that is asynchronous and/or configured for a different sample rate. AIF MASTER / SLAVE CONTROL The digital audio interfaces can operate in Master or Slave modes and also in mixed master/slave configurations. In Master mode, the BCLK and LRCLK signals are generated by the WM8281 when any of the respective digital audio interface channels is enabled. In Slave mode, these outputs are disabled by default to allow another device to drive these pins. Master mode is selected on the AIFnBCLK pin using the AIF n_BCLK_MSTR register bit. In Master mode, the AIFnBCLK signal is generated by the WM8281 when one or more AIF n channels is enabled. When the AIF n_BCLK_FRC bit is set in BCLK master mode, the AIFnBCLK signal is output at all times, including when none of the AIFn channels is enabled. The AIFnBCLK signal can be inverted in Master or Slave modes using the AIFn_BCLK_INV register. Master mode is selected on the AIFnLRCLK pin using the AIF nRX_LRCLK_MSTR register bit. In Master mode, the AIFnRXLRCLK signal is generated by the WM8281 when one or more AIF n channels is enabled. (Note that, when GPIOn is configured as AIFnTXLRCLK, then only the AIF n RX channels will cause AIFnRXLRCLK to be output.) When the AIFnRX_LRCLK_FRC bit is set in LRCLK master mode, the AIFnRXLRCLK signal is output at all times, including when none of the AIF n channels is enabled. Note that AIFnRXLRCLK is derived from AIFnBCLK, and an internal or external AIFnBCLK signal must be present to generate AIFnRXLRCLK. The AIFnRXLRCLK signal can be inverted in Master or Slave modes using the AIF nRX_LRCLK_INV register. Under default condi tions, the AIFn input (RX) and output (TX) paths both use the AIFnRXLRCLK signal as the frame synchronisation clock. The AIFn output (TX) interface can be configured to use a separate frame clock, AIFnTXLRCLK, using the AIFnTX_LRCLK_SRC bit. The AIFnTXLRCLK function, when used, must be selected on the GPIO n pin as described in the “General Purpose Input / Output” section. The AIFnTXLRCLK function can operate in Master or Slave mode, and is controlled similarly to the AIFnRXLRCLK function using the register bits described in Table 31, Table 32 and Table 33 for AIF1, AIF2 and AIF3 respectively.

Rev 4.0 149 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1280 (0500h) AIF1 BCLK Ctrl

7 AIF1_BCLK_INV 0 AIF1 Audio Interface BCLK Invert

0 = AIF1BCLK not inverted 1 = AIF1BCLK inverted

6 AIF1_BCLK_FRC 0 AIF1 Audio Interface BCLK Output Control

0 = Normal 1 = AIF1BCLK always enabled in Master mode

5 AIF1_BCLK_MST

R

0 AIF1 Audio Interface BCLK Master Select

0 = AIF1BCLK Slave mode 1 = AIF1BCLK Master mode R1281 (0501h) AIF1 Tx Pin Ctrl

3 AIF1TX_LRCLK_

1 AIF1 Audio Interface TX path LRCLK

0 = AIF1TXLRCLK 1 = AIF1RXLRCLK Note that the TXLRCLK function, when used, must be configured on a GPIO pin.

2 AIF1TX_LRCLK_I

0 AIF1 Audio Interface TX path LRCLK

0 = AIF1TXLRCLK not inverted 1 = AIF1TXLRCLK inverted

1 AIF1TX_LRCLK_

0 = Normal 1 = AIF1TXLRCLK always enabled in Master mode

0 AIF1TX_LRCLK_

0 = AIF1TXLRCLK Slave mode 1 = AIF1TXLRCLK Master mode R1282 (0502h) AIF1 Rx Pin Ctrl

2 AIF1RX_LRCLK_

0 AIF1 Audio Interface LRCLK Invert

0 = AIF1RXLRCLK not inverted 1 = AIF1RXLRCLK inverted

1 AIF1RX_LRCLK_

0 AIF1 Audio Interface LRCLK Output

0 = Normal 1 = AIF1RXLRCLK always enabled in Master mode

0 AIF1RX_LRCLK_

0 AIF1 Audio Interface LRCLK Master

0 = AIF1RXLRCLK Slave mode 1 = AIF1RXLRCLK Master mode Table 31 AIF1 Master / Slave Control

150 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1344 (0540h) AIF2 BCLK Ctrl

7 AIF2_BCLK_INV 0 AIF2 Audio Interface BCLK Invert

0 = AIF2BCLK not inverted 1 = AIF2BCLK inverted

6 AIF2_BCLK_FRC 0 AIF2 Audio Interface BCLK Output Control

0 = Normal 1 = AIF2BCLK always enabled in Master mode

5 AIF2_BCLK_MST

R

0 AIF2 Audio Interface BCLK Master Select

0 = AIF2BCLK Slave mode 1 = AIF2BCLK Master mode R1345 (0541h) AIF2 Tx Pin Ctrl

3 AIF2TX_LRCLK_

1 AIF2 Audio Interface TX path LRCLK

0 = AIF2TXLRCLK 1 = AIF2RXLRCLK Note that the TXLRCLK function, when used, must be configured on a GPIO pin.

2 AIF2TX_LRCLK_I

0 AIF2 Audio Interface TX path LRCLK

0 = AIF2TXLRCLK not inverted 1 = AIF2TXLRCLK inverted

1 AIF2TX_LRCLK_

0 = Normal 1 = AIF2TXLRCLK always enabled in Master mode

0 AIF2TX_LRCLK_

0 = AIF2TXLRCLK Slave mode 1 = AIF2TXLRCLK Master mode R1346 (0542h) AIF2 Px Pin Ctrl

2 AIF2RX_LRCLK_

0 AIF2 Audio Interface LRCLK Invert

0 = AIF2RXLRCLK not inverted 1 = AIF2RXLRCLK inverted

1 AIF2RX_LRCLK_

0 AIF2 Audio Interface LRCLK Output

0 = Normal 1 = AIF2RXLRCLK always enabled in Master mode

0 AIF2RX_LRCLK_

0 AIF2 Audio Interface LRCLK Master

0 = AIF2RXLRCLK Slave mode 1 = AIF2RXLRCLK Master mode Table 32 AIF2 Master / Slave Control

Rev 4.0 151 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1408 (0580h) AIF3 BCLK Ctrl

7 AIF3_BCLK_INV 0 AIF3 Audio Interface BCLK Invert

0 = AIF3BCLK not inverted 1 = AIF3BCLK inverted

6 AIF3_BCLK_FRC 0 AIF3 Audio Interface BCLK Output Control

0 = Normal 1 = AIF3BCLK always enabled in Master mode

5 AIF3_BCLK_MST

R

0 AIF3 Audio Interface BCLK Master Select

0 = AIF3BCLK Slave mode 1 = AIF3BCLK Master mode R1409 (0581h) AIF3 Tx Pin Ctrl

3 AIF3TX_LRCLK_

1 AIF3 Audio Interface TX path LRCLK

0 = AIF3TXLRCLK 1 = AIF3RXLRCLK Note that the TXLRCLK function, when used, must be configured on a GPIO pin.

2 AIF3TX_LRCLK_I

0 AIF3 Audio Interface TX path LRCLK

0 = AIF3TXLRCLK not inverted 1 = AIF3TXLRCLK inverted

1 AIF3TX_LRCLK_

0 = Normal 1 = AIF3TXLRCLK always enabled in Master mode

0 AIF3TX_LRCLK_

0 = AIF3TXLRCLK Slave mode 1 = AIF3TXLRCLK Master mode R1410 (0582h) AIF3 Rx Pin Ctrl

2 AIF3RX_LRCLK_

0 AIF3 Audio Interface LRCLK Invert

0 = AIF3RXLRCLK not inverted 1 = AIF3RXLRCLK inverted

1 AIF3RX_LRCLK_

0 AIF3 Audio Interface LRCLK Output

0 = Normal 1 = AIF3RXLRCLK always enabled in Master mode

0 AIF3RX_LRCLK_

0 AIF3 Audio Interface LRCLK Master

0 = AIF3RXLRCLK Slave mode 1 = AIF3RXLRCLK Master mode Table 33 AIF3 Master / Slave Control

152 Rev 4.0 AIF SIGNAL PATH ENABLE The AIF1 interface supports up to 8 input (RX) channels and up to 8 output (TX) channels. Each of these channels can be enabled or disabled using the register bits defined in Table 34. The AIF2 interface supports up to 6 input (RX) channels and up to 6 output (TX) channels. Each of these channels can be enabled or disabled using the register bits defined in Table 35. The AIF3 interface supports up to 2 input (RX) channels and up to 2 output (TX) channels. Each of these channels can be enabled or disabled using the register bits defined in Table 36. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK may also be requ ired, depending on the path configuration. See “ Clocking and Sample Rates” for details of the system clocks. The WM8281 performs automatic checks to confirm that the S YSCLK and ASYNCCLK frequencies are high enough to support the commanded signal paths and processing functions. If an attempt is made to enable an AIF signal path, and there are insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error conditions can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1305 (0519h) AIF1 Tx Enables

7 AIF1TX8_ENA 0 AIF1 Audio Interface TX Channel 8

0 = Disabled 1 = Enabled

6 AIF1TX7_ENA 0 AIF1 Audio Interface TX Channel 7

0 = Disabled 1 = Enabled

5 AIF1TX6_ENA 0 AIF1 Audio Interface TX Channel 6

0 = Disabled 1 = Enabled

4 AIF1TX5_ENA 0 AIF1 Audio Interface TX Channel 5

0 = Disabled 1 = Enabled

3 AIF1TX4_ENA 0 AIF1 Audio Interface TX Channel 4

0 = Disabled 1 = Enabled

2 AIF1TX3_ENA 0 AIF1 Audio Interface TX Channel 3

0 = Disabled 1 = Enabled

1 AIF1TX2_ENA 0 AIF1 Audio Interface TX Channel 2

0 = Disabled 1 = Enabled

0 AIF1TX1_ENA 0 AIF1 Audio Interface TX Channel 1

0 = Disabled 1 = Enabled R1306 (051Ah) AIF1 Rx Enables

7 AIF1RX8_ENA 0 AIF1 Audio Interface RX Channel 8

0 = Disabled 1 = Enabled

Rev 4.0 153 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

6 AIF1RX7_ENA 0 AIF1 Audio Interface RX Channel 7

0 = Disabled 1 = Enabled

5 AIF1RX6_ENA 0 AIF1 Audio Interface RX Channel 6

0 = Disabled 1 = Enabled

4 AIF1RX5_ENA 0 AIF1 Audio Interface RX Channel 5

0 = Disabled 1 = Enabled

3 AIF1RX4_ENA 0 AIF1 Audio Interface RX Channel 4

0 = Disabled 1 = Enabled

2 AIF1RX3_ENA 0 AIF1 Audio Interface RX Channel 3

0 = Disabled 1 = Enabled

1 AIF1RX2_ENA 0 AIF1 Audio Interface RX Channel 2

0 = Disabled 1 = Enabled

0 AIF1RX1_ENA 0 AIF1 Audio Interface RX Channel 1

0 = Disabled 1 = Enabled Table 34 AIF1 Signal Path Enable REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1369 (0559h) AIF2 TX Enables

5 AIF2TX6_ENA 0 AIF2 Audio Interface TX Channel 6

0 = Disabled 1 = Enabled

4 AIF2TX5_ENA 0 AIF2 Audio Interface TX Channel 5

0 = Disabled 1 = Enabled

3 AIF2TX4_ENA 0 AIF2 Audio Interface TX Channel 4

0 = Disabled 1 = Enabled

2 AIF2TX3_ENA 0 AIF2 Audio Interface TX Channel 3

0 = Disabled 1 = Enabled

1 AIF2TX2_ENA 0 AIF2 Audio Interface TX Channel 2

0 = Disabled 1 = Enabled

0 AIF2TX1_ENA 0 AIF2 Audio Interface TX Channel 1

0 = Disabled 1 = Enabled

154 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1370 (055Ah) AIF2 RX Enables

5 AIF2RX6_ENA 0 AIF2 Audio Interface RX Channel 6

0 = Disabled 1 = Enabled

4 AIF2RX5_ENA 0 AIF2 Audio Interface RX Channel 5

0 = Disabled 1 = Enabled

3 AIF2RX4_ENA 0 AIF2 Audio Interface RX Channel 4

0 = Disabled 1 = Enabled

2 AIF2RX3_ENA 0 AIF2 Audio Interface RX Channel 3

0 = Disabled 1 = Enabled

1 AIF2RX2_ENA 0 AIF2 Audio Interface RX Channel 2

0 = Disabled 1 = Enabled

0 AIF2RX1_ENA 0 AIF2 Audio Interface RX Channel 1

0 = Disabled 1 = Enabled Table 35 AIF2 Signal Path Enable REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1433 (0599h) AIF3 TX Enables

1 AIF3TX2_ENA 0 AIF3 Audio Interface TX Channel 2

0 = Disabled 1 = Enabled

0 AIF3TX1_ENA 0 AIF3 Audio Interface TX Channel 1

0 = Disabled 1 = Enabled R1434 (059Ah) AIF3 RX Enables

1 AIF3RX2_ENA 0 AIF3 Audio Interface RX Channel 2

0 = Disabled 1 = Enabled

0 AIF3RX1_ENA 0 AIF3 Audio Interface RX Channel 1

0 = Disabled 1 = Enabled Table 36 AIF3 Signal Path Enable

Rev 4.0 155 AIF BCLK AND LRCLK CONTROL The AIFnBCLK frequency is selected by the AIF n_BCLK_FREQ register . For each value of this register, the actual frequency depends upon whether AIF n is configured for a 48kHz -related sample rate or a 44.1kHz-related sample rate, as described below. If AIFn_RATE<1000 (see Table 23), then AIFn is referenced to the SYSCLK clocking domain and the applicable frequency depends upon the SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3 registers. If AIFn_RATE≥1000, then AIF n is referenced to the ASYNCCLK clocking domain and the applicable frequency depends upon the ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2 registers. The selected AIFnBCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable. See “Clocking and Sample Rates ” for details of SYSCLK and ASYNCCLK domains, and the associated control registers. The AIFnRXLRCLK frequency is controlled relative to AIFnBCLK by the AIFnRX_BCPF divider. Under default conditions, the AIFn input (RX) and output (TX) paths both use the AIFnRXLRCLK signal as the frame synchronisation clock. The AIFn output (TX) interface can be configured to use a separate frame clock, AIFnTXLRCLK, using the AIF nTX_LRCLK_SRC bit, as described in Table 31, Table 32 and Table 33 for AIF1, AIF2 and AIF3 respectively. When the GPIOn pin is configured as AIFnTXLRCLK, then the AIFnTXLRCLK frequency is controlled relative to AIFnBCLK by the AIFnTX_BCPF divider. See “General Purpose Input / Output ” for details of how to configure the GPIO1, GPIO2 or GPIO3 pins. Note that the BCLK rate must be configured in Master or Slave modes, using the AIFn_BCLK_FREQ registers. The LRCLK rate(s) only require to be configured in Master mode.

156 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1280 (0500h) AIF1 BCLK Ctrl 4:0 AIF1_BCLK_FRE Q [4:0]

01100 AIF1BCLK Rate

00000 = Reserved 00001 = Reserved 00010 = 64kHz (58.8kHz) 00011 = 96kHz (88.2kHz) 00100 = 128kHz (117.6kHz) 00101 = 192kHz (176.4kHz) 00110 = 256kHz (235.2kHz) 00111 = 384kHz (352.8kHz) 01000 = 512kHz (470.4kHz) 01001 = 768kHz (705.6kHz) 01010 = 1.024MHz (940.8kHz) 01011 = 1.536MHz (1.4112MHz) 01100 = 2.048MHz (1.8816MHz) 01101 = 3.072MHz (2.8824MHz) 01110 = 4.096MHz (3.7632MHz) 01111 = 6.144MHz (5.6448MHz) 10000 = 8.192MHz (7.5264MHz) 10001 = 12.288MHz (11.2896MHz) 10010 = 24.576MHz (22.5792MHz) The frequencies in brackets apply for 44.1kHz-related sample rates only. If AIF1_RATE<1000, then AIF1 is referenced to SYSCLK and the 44.1kHz- related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF1_RATE>=1000, then AIF1 is referenced to ASYNCCLK and the 44.1kHz-related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. The AIF1BCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable. R1285 (0505h) AIF1 Tx BCLK Rate 12:0 AIF1TX_BCPF [12:0] 0040h AIF1TXLRCLK Rate This register selects the number of BCLK cycles per AIF1TXLRCLK frame. AIF1TXLRCLK clock = AIF1BCLK / AIF1TX_BCPF Integer (LSB = 1), Valid from 8..8191 R1286 (0506h) AIF1 Tx BCLK Rate 12:0 AIF1RX_BCPF [12:0] 0040h AIF1RXLRCLK Rate This register selects the number of BCLK cycles per AIF1RXLRCLK frame. AIF1RXLRCLK clock = AIF1BCLK / AIF1RX_BCPF Integer (LSB = 1), Valid from 8..8191 Table 37 AIF1 BCLK and LRCLK Control

Rev 4.0 157 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1344 (0540h) AIF2 BCLK Ctrl 4:0 AIF2_BCLK_FRE Q [4:0]

01100 AIF2BCLK Rate

00000 = Reserved 00001 = Reserved 00010 = 64kHz (58.8kHz) 00011 = 96kHz (88.2kHz) 00100 = 128kHz (117.6kHz) 00101 = 192kHz (176.4kHz) 00110 = 256kHz (235.2kHz) 00111 = 384kHz (352.8kHz) 01000 = 512kHz (470.4kHz) 01001 = 768kHz (705.6kHz) 01010 = 1.024MHz (940.8kHz) 01011 = 1.536MHz (1.4112MHz) 01100 = 2.048MHz (1.8816MHz) 01101 = 3.072MHz (2.8824MHz) 01110 = 4.096MHz (3.7632MHz) 01111 = 6.144MHz (5.6448MHz) 10000 = 8.192MHz (7.5264MHz) 10001 = 12.288MHz (11.2896MHz) 10010 = 24.576MHz (22.5792MHz) The frequencies in brackets apply for 44.1kHz-related sample rates only. If AIF2_RATE<1000, then AIF2 is referenced to SYSCLK and the 44.1kHz- related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF2_RATE>=1000, then AIF2 is referenced to ASYNCCLK and the 44.1kHz-related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. The AIF2BCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable. R1349 (0545h) AIF2 Tx BCLK Rate 12:0 AIF2TX_BCPF [12:0] 0040h AIF2TXLRCLK Rate This register selects the number of BCLK cycles per AIF2TXLRCLK frame. AIF2TXLRCLK clock = AIF2BCLK / AIF2TX_BCPF Integer (LSB = 1), Valid from 8..8191 R1350 (0546h) AIF2 Rx BCLK Rate 12:0 AIF2RX_BCPF [12:0] 0040h AIF2RXLRCLK Rate This register selects the number of BCLK cycles per AIF2RXLRCLK frame. AIF2RXLRCLK clock = AIF2BCLK / AIF2RX_BCPF Integer (LSB = 1), Valid from 8..8191 Table 38 AIF2 BCLK and LRCLK Control

158 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1408 (0580h) AIF3 BCLK Ctrl 4:0 AIF3_BCLK_FRE Q [4:0]

01100 AIF3BCLK Rate

00000 = Reserved 00001 = Reserved 00010 = 64kHz (58.8kHz) 00011 = 96kHz (88.2kHz) 00100 = 128kHz (117.6kHz) 00101 = 192kHz (176.4kHz) 00110 = 256kHz (235.2kHz) 00111 = 384kHz (352.8kHz) 01000 = 512kHz (470.4kHz) 01001 = 768kHz (705.6kHz) 01010 = 1.024MHz (940.8kHz) 01011 = 1.536MHz (1.4112MHz) 01100 = 2.048MHz (1.8816MHz) 01101 = 3.072MHz (2.8824MHz) 01110 = 4.096MHz (3.7632MHz) 01111 = 6.144MHz (5.6448MHz) 10000 = 8.192MHz (7.5264MHz) 10001 = 12.288MHz (11.2896MHz) 10010 = 24.576MHz (22.5792MHz) The frequencies in brackets apply for 44.1kHz-related sample rates only. If AIF3_RATE<1000, then AIF3 is referenced to SYSCLK and the 44.1kHz- related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF3_RATE>=1000, then AIF3 is referenced to ASYNCCLK and the 44.1kHz-related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. The AIF3BCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable. R1413 (0585h) AIF3 Tx BCLK Rate 12:0 AIF3TX_BCPF [12:0] 0040h AIF3TXLRCLK Rate This register selects the number of BCLK cycles per AIF3TXLRCLK frame. AIF3TXLRCLK clock = AIF3BCLK / AIF3TX_BCPF Integer (LSB = 1), Valid from 8..8191 R1414 (0586h) AIF3 Rx BCLK Rate 12:0 AIF3RX_BCPF [12:0] 0040h AIF3RXLRCLK Rate This register selects the number of BCLK cycles per AIF3RXLRCLK frame. AIF3RXLRCLK clock = AIF3BCLK / AIF3RX_BCPF Integer (LSB = 1), Valid from 8..8191 Table 39 AIF3 BCLK and LRCLK Control

Rev 4.0 159 AIF DIGITAL AUDIO DATA CONTROL The register bits controlling the audio data format, word lengths and slot configurations for AIF1, AIF2 and AIF3 are described in Table 40, Table 41 and Table 42 respectively. Note that Left -Justified and DSP -B modes are valid in Master mode only (ie. BCLK and LRCLK are outputs from the WM8281). The AIFn Slot Length is the number of BCLK cycles in one timeslot within the overall LRCLK frame. The Word Length is the number of valid data bits within each timeslot. (If the word length is less than the slot length, then there will be unused BCLK cycles at the end of each timeslot.) The AIF n word length and slot length is independently selectable for the input (RX) and output (TX) paths. For each AIF input (RX) and AIF output (TX) channel, the position of the audio data sample within the LRCLK frame is configurable. The _SLOT registers define the timeslot position of the audio sample for the associated audio channel. Valid selections are Slot 0 upwards. The timeslots are numbered as illustrated in Figure 49 through to Figure 52. Note that, in DSP modes, the timeslots are ordered consecutively from the start of the LRCLK frame. In I2S and Left -Justified modes, the even -numbered timeslots are arranged in the first half of the LRCLK frame, and the odd-numbered timeslots are arranged in the second half of the frame. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1284 (0504h) AIF1 Format 2:0 AIF1_FMT [2:0] 000 AIF1 Audio Interface Format 000 = DSP Mode A 001 = DSP Mode B 010 = I2S mode 011 = Left Justified mode Other codes are Reserved R1287 (0507h) AIF1 Frame Ctrl 13:8 AIF1TX_WL [5:0] 18h AIF1 TX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 7:0 AIF1TX_SLOT_L EN [7:0] 18h AIF1 TX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 R1288 (0508h) AIF1 Frame Ctrl 13:8 AIF1RX_WL [5:0] 18h AIF1 RX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 7:0 AIF1RX_SLOT_L EN [7:0] 18h AIF1 RX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 R1289 (0509h) to R1296 (0510h) 5:0 AIF1TX1_SLOT [5:0] 0h AIF1 TX Channel n Slot position Defines the TX timeslot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 5:0 AIF1TX2_SLOT [5:0] 5:0 AIF1TX3_SLOT [5:0] 5:0 AIF1TX4_SLOT [5:0] 5:0 AIF1TX5_SLOT [5:0] 5:0 AIF1TX6_SLOT [5:0] 5:0 AIF1TX7_SLOT [5:0] 5:0 AIF1TX8_SLOT [5:0] R1297 (0511h) to R1304 5:0 AIF1RX1_SLOT [5:0] 0h AIF1 RX Channel n Slot position Defines the RX timeslot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 5:0 AIF1RX2_SLOT [5:0] 5:0 AIF1RX3_SLOT [5:0]

160 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION (0518h) 5:0 AIF1RX4_SLOT [5:0] 5:0 AIF1RX5_SLOT [5:0] 5:0 AIF1RX6_SLOT [5:0] 5:0 AIF1RX7_SLOT [5:0] 5:0 AIF1RX8_SLOT [5:0] Table 40 AIF1 Digital Audio Data Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1348 (0544h) AIF2 Format 2:0 AIF2_FMT [2:0] 000 AIF2 Audio Interface Format 000 = DSP Mode A 001 = DSP Mode B 010 = I2S mode 011 = Left Justified mode Other codes are Reserved R1351 (0547h) AIF2 Frame Ctrl 13:8 AIF2TX_WL [5:0] 18h AIF2 TX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 7:0 AIF2TX_SLOT_L EN [7:0] 18h AIF2 TX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 R1352 (0548h) AIF2 Frame Ctrl 13:8 AIF2RX_WL [5:0] 18h AIF2 RX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 7:0 AIF2RX_SLOT_L EN [7:0] 18h AIF2 RX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 R1353 (0549h) to R1358 (054Eh) 5:0 AIF2TX1_SLOT [5:0] 0h AIF2 TX Channel n Slot position Defines the TX timeslot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 5:0 AIF2TX2_SLOT [5:0] 5:0 AIF2TX3_SLOT [5:0] 5:0 AIF2TX4_SLOT [5:0] 5:0 AIF2TX5_SLOT [5:0] 5:0 AIF2TX6_SLOT [5:0]

Rev 4.0 161 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1361 (0551h) to R1366 (0556h) 5:0 AIF2RX1_SLOT [5:0] 0h AIF2 RX Channel n Slot position Defines the RX timeslot position of the Channel n audio sample Integer (LSB=1); Valid from 0 to 63 5:0 AIF2RX2_SLOT [5:0] 5:0 AIF2RX3_SLOT [5:0] 5:0 AIF2RX4_SLOT [5:0] 5:0 AIF2RX5_SLOT [5:0] 5:0 AIF2RX6_SLOT [5:0] Table 41 AIF2 Digital Audio Data Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1412 (0584h) AIF3 Format 2:0 AIF3_FMT [2:0] 000 AIF3 Audio Interface Format 000 = DSP Mode A 001 = DSP Mode B 010 = I2S mode 011 = Left Justified mode Other codes are Reserved R1415 (0587h) AIF3 Frame Ctrl 13:8 AIF3TX_WL [5:0] 18h AIF3 TX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 7:0 AIF3TX_SLOT_L EN [7:0] 18h AIF3 TX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 R1416 (0588h) AIF3 Frame Ctrl 13:8 AIF3RX_WL [5:0] 18h AIF3 RX Word Length (Number of valid data bits per slot) Integer (LSB = 1); Valid from 16 to 32 7:0 AIF3RX_SLOT_L EN [7:0] 18h AIF3 RX Slot Length (Number of BCLK cycles per slot) Integer (LSB = 1); Valid from 16 to 128 R1417 (0589h) AIF3 Frame Ctrl 5:0 AIF3TX1_SLOT [5:0] 0h AIF3 TX Channel 1 Slot position Defines the TX timeslot position of the Channel 1 audio sample Integer (LSB=1); Valid from 0 to 63 R1418 (058Ah) AIF3 Frame Ctrl 5:0 AIF3TX2_SLOT [5:0] 1h AIF3 TX Channel 2 Slot position Defines the TX timeslot position of the Channel 2 audio sample Integer (LSB=1); Valid from 0 to 63 R1425 (0591h) AIF3 Frame Ctrl 5:0 AIF3RX1_SLOT [5:0] 0h AIF3 RX Channel 1 Slot position Defines the RX timeslot position of the Channel 1 audio sample Integer (LSB=1); Valid from 0 to 63 R1426 (0592h) AIF3 Frame Ctrl 5:0 AIF3RX2_SLOT [5:0] 1h AIF3 RX Channel 2 Slot position Defines the RX timeslot position of the Channel 2 audio sample Integer (LSB=1); Valid from 0 to 63 Table 42 AIF3 Digital Audio Data Control

162 Rev 4.0 AIF TDM AND TRI-STATE CONTROL The AIFn output pins are tri-stated when the AIFn_TRI register is set. Note that, when a GPIOn pin is configured as a GPIO, this pin is not affected by the respective AIFn_TRI register. See “ General Purpose Input / Output” to configure the GPIO pins. Under default conditions, the AIFnTXDAT output is held a t logic 0 when t he WM8281 is not transmitting data (ie. during timeslots that are not enabled for output by the WM8281). When the AIFnTX_DAT_TRI register is set, the WM8281 tri-states the respective AIFnTXDAT pin when not transmitting data, allowing other devices to drive the AIFnTXDAT connection. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1281 (0501h) AIF1 Tx Pin Ctrl

5 AIF1TX_DAT_TR

I

0 AIF1TXDAT Tri-State Control

0 = Logic 0 during unused timeslots 1 = Tri-stated during unused timeslots R1283 (0503h) AIF1 Rate Ctrl

6 AIF1_TRI 0 AIF1 Audio Interface Tri-State Control

0 = Normal 1 = AIF1 Outputs are tri-stated Note that the GPIO1 pin is only tri-stated by this register when it is configured as AIF1TXLRCLK. Table 43 AIF1 TDM and Tri-State Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1345 (0541h) AIF2 Tx Pin Ctrl

5 AIF2TX_DAT_TR

I

0 AIF2TXDAT Tri-State Control

0 = Logic 0 during unused timeslots 1 = Tri-stated during unused timeslots R1347 (0543h) AIF2 Rate Ctrl

6 AIF2_TRI 0 AIF2 Audio Interface Tri-State Control

0 = Normal 1 = AIF2 Outputs are tri-stated Note that the GPIO2 pin is only tri-stated by this register when it is configured as AIF2TXLRCLK. Table 44 AIF2 TDM and Tri-State Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1409 (0581h) AIF3 Tx Pin Ctrl

5 AIF3TX_DAT_TR

I

0 AIF3TXDAT Tri-State Control

0 = Logic 0 during unused timeslots 1 = Tri-stated during unused timeslots R1411 (0583h) AIF3 Rate Ctrl

6 AIF3_TRI 0 AIF3 Audio Interface Tri-State Control

0 = Normal 1 = AIF3 Outputs are tri-stated Note that the GPIO3 pin is only tri-stated by this register when it is configured as AIF3TXLRCLK. Table 45 AIF3 TDM and Tri-State Control

Rev 4.0 163 AIF DIGITAL PULL-UP AND PULL-DOWN The WM8281 provides integrated pull -up and pull -down resistors on each of the AIFnLRCLK, AIFnBCLK and AIFnRXDAT pins. This provides a flexible capability for interfacing with other devices. Each of the pull -up and pull -down resistors can be confi gured independently using the register bits described in Table 46, Table 47 and Table 48. When the pull -up and pull -down resistors are both enabled, the WM8281 provides a ‘bus keeper’ function on the respective pin. The bus keeper function holds the logic level unchanged whenever the pin is undriven (eg. if the signal is tri-stated). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3107 (0C23h) Misc Pad Ctrl 4

5 AIF1LRCLK_PU 0 AIF1LRCLK Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF1LRCLK_PD and AIF1LRCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF1LRCLK pin.

4 AIF1LRCLK_PD 0 AIF1LRCLK Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF1LRCLK_PD and AIF1LRCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF1LRCLK pin.

3 AIF1BCLK_PU 0 AIF1BCLK Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF1BCLK_PD and AIF1BCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF1BCLK pin.

2 AIF1BCLK_PD 0 AIF1BCLK Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF1BCLK_PD and AIF1BCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF1BCLK pin.

1 AIF1RXDAT_PU 0 AIF1RXDAT Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF1RXDAT_PD and AIF1RXDAT_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF1RXDAT pin.

0 AIF1RXDAT_PD 0 AIF1RXDAT Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF1RXDAT_PD and AIF1RXDAT_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF1RXDAT pin. Table 46 AIF1 Digital Pull-Up and Pull-Down Control

164 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3108 (0C24h) Misc Pad Ctrl 5

5 AIF2LRCLK_PU 0 AIF2LRCLK Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF2LRCLK_PD and AIF2LRCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF2LRCLK pin.

4 AIF2LRCLK_PD 0 AIF2LRCLK Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF2LRCLK_PD and AIF2LRCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF2LRCLK pin.

3 AIF2BCLK_PU 0 AIF2BCLK Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF2BCLK_PD and AIF2BCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF2BCLK pin.

2 AIF2BCLK_PD 0 AIF2BCLK Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF2BCLK_PD and AIF2BCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF2BCLK pin.

1 AIF2RXDAT_PU 0 AIF2RXDAT Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF2RXDAT_PD and AIF2RXDAT_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF2RXDAT pin.

0 AIF2RXDAT_PD 0 AIF2RXDAT Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF2RXDAT_PD and AIF2RXDAT_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF2RXDAT pin. Table 47 AIF2 Digital Pull-Up and Pull-Down Control

Rev 4.0 165 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3109 (0C25h) Misc Pad Ctrl 6

5 AIF3LRCLK_PU 0 AIF3LRCLK Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF3LRCLK_PD and AIF3LRCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF3LRCLK pin.

4 AIF3LRCLK_PD 0 AIF3LRCLK Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF3LRCLK_PD and AIF3LRCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF3LRCLK pin.

3 AIF3BCLK_PU 0 AIF3BCLK Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF3BCLK_PD and AIF3BCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF3BCLK pin.

2 AIF3BCLK_PD 0 AIF3BCLK Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF3BCLK_PD and AIF3BCLK_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF3BCLK pin.

1 AIF3RXDAT_PU 0 AIF3RXDAT Pull-Up Control

0 = Disabled 1 = Enabled Note - when AIF3RXDAT_PD and AIF3RXDAT_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF3RXDAT pin.

0 AIF3RXDAT_PD 0 AIF3RXDAT Pull-Down Control

0 = Disabled 1 = Enabled Note - when AIF3RXDAT_PD and AIF3RXDAT_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the AIF3RXDAT pin. Table 48 AIF3 Digital Pull-Up and Pull-Down Control

166 Rev 4.0 SLIMBUS INTERFACE The SLIMbus protocol is highly configurable and adaptable, supporting multiple audio signal paths, and mixed sample rates simultaneously. It also supports control messaging and associated communications between devices. SLIMBUS DEVICES The SLIMbus components comprise different device classes (Manager, Framer, Interface, Generic). Each component on the bus has an Interface Device, which provides bus management servi ces for the respective component. One or more components on the bus will provide Manager and Framer Device functions; the Manager has the capabilities to administer the bus, whilst the Framer is responsible for driving the CLK line and for driving the DATA required to establish the Frame Structure on the bus. Note that only one Manager and one Framer Device will be active at any time . The Framer function can be transferred between Devices when required. Generic Devices provide the basic SLIMbus functionalit y for the associated Port(s), and for the Transport Protocol by which audio signal paths are established on the bus. SLIMBUS FRAME STRUCTURE The SLIMbus bit stream is formatted within a defined structure of Cells, Slots, Subframes, Frames, and Superframes:  A single data bit is known as a Cell  4 Cells make a Slot  192 Slots make a Frame  8 Frames make a Superframe The bit stream structure is configurable to some extent, but the Superframe definition always comprises 1536 slots. The transmitted/received bit r ate is not fixed; it can be configured according to system requirements, and can be changed dynamically without interruption to active audio paths. The SLIMbus CLK frequency (also the bus bit rate) is defined by a Root Frequency (RF) and a Clock Gear (CG). In the top Clock Gear (Gear 10), the CLK frequency is equal to the Root Frequency. Each reduction in the Clock Gear halves the CLK frequency, and doubles the duration of the Superframe. The SLIMbus bandwidth will typically comprise Control space (for bus messages, synchronisation etc.) and Data space (for audio paths). The precise allocation is configurable, and can be entirely Control space, if required. The Subframe definition comprises the number of Slots per Subframe (6, 8, 24 or 32 Slots), and the number of these Slots (per Subframe) allocated as Control space. The applicable combination of Subframe length and Control space width are defined by the Subframe Mode (SM) parameter. The SLIMbus Frame always comprises 192 Slots, regardless of the Subframe d efinition. A number of Slots are allocated to Control space, as noted above; the remaining Slots are allocated to Data space. Some of the Control space is required for Framing Information and for the Guide Channel (described below); the remainder of the Control space are allocated to the Message Channel. CONTROL SPACE Framing Information is provided in Slots 0 and 96 of every Frame. Slot 0 contains a 4 -bit synchronisation code; Slot 96 contains the 32 -bit Framing Information, transmitted 4 bits at a time over the 8 Frames that make up the SLIMbus Superframe. The Clock Gear, Root Frequency, Subframe configuration, along with some other parameters, are encoded within the Framing Information. The Guide Channel occupies two Slots within Frame 0. This provides t he necessary information for a SLIMbus component to acquire and verify the frame synchronisation. The Guide Channel occupies the first two Control space Slots within the first Frame of the bit stream, excluding the Framing Information Slots. Note that the exact Slot allocation will depend upon the applicable Subframe mode.

Rev 4.0 167 The Message Channel is allocated all of the Control space not used by the Framing Information or the Guide Channel. The Message Channel enables SLIMbus devices to communicate with each ot her, using a priority-based mechanism defined in the MIPI specification. Messages may be broadcast to all devices on the bus, or can be addressed to specific devices using their allocated Logical Address (LA) or Enumeration Address (EA) . Note that, device -specific messages are directed to a particular device (ie. Manager, Framer, Interface or Generic) within a component on the bus. DATA SPACE The Data space can be organised into a maximum of 256 Data Channels. Each Channel, identified by a unique Channel Number (CN) , is a stream of one or more contiguous Slots, organised in a consistent data structure that repeats at a fixed interval. A Data Channel is defined by its Segment Length (SL) (number of contiguous Slots allocated), Segment Interval (spacing between the first Slots of successive Segments), and Segment Offset (the Slot Number of the first allocated Slot within the Superframe). The Segment Interval and Segment Offset are collecti vely defined by a Segment Distribution (SD) , by which the SLIMbus Manager may configure (or re-configure) any Data Channel. Each Segment may comprise TAG, AUX and DATA portions. Any of these portions may be 0 -length; the exact composition depends on the Transport Protocol (TP) for the associated Channel (see below). The DATA portion must be wide enough to accommodate one full word of the Data Channel contents (data words cannot be spread across multiple segments). The Segment Interval for each Data Channel represents the minimum spacing between consecutive data samples for that Channel. (Note - the minimum spacing applies if every allocated segment is populated with new data; in many cases, additional bandwidth is allocated, as described below, and not every allocated segment is used.) The Segment Interval gives rise to Segment Windows for each Data Channel, aligned to the start of every Superframe. The Segment Window boundaries define the times within which each new data sample must be buffered, ready for tr ansmission - adherence to these fixed boundaries allows Slot allocations to be moved within a Segment Window, without altering the signal latency. The Segment Interval may be either shorter or longer than the Frame length, but there is always an integer nu mber of Segment Windows per Superframe. The Transport Protocol (TP) defines the flow control or handshaking method used by the Ports associated with a Data Channel. The applicable flow control mode(s) depend on the relationship between the audio sample rat e (flow rate) and the SLIMbus CLK frequency. If the two rates are synchronised and integer -related, then no flow control is needed; in other cases, the flow may be regulated by the use of a ‘Presence’ bit. The Presence bit can either be set by the source D evice (‘pushed’ protocol), or by the sink Device (‘pulled’ protocol). The Data Channel structure is defined in terms of the Transport Protocol (TP) , Segment Distribution (SD), and the Segment Length (SL) parameters. Each of these is described above. The Da ta Channel content definition includes a Presence Rate (PR) parameter (describing the nominal sample rate for the audio channel) and a Frequency Locked (FL) bit (identifying whether the data source is synchronised to the SLIMbus CLK). The Data Length (DL) parameter defines the size of each data sample (number of Slots). The Auxiliary Bits Format (AF) and Data Type (DT) parameters provide support for non-PCM encoded data channels; the Channel Link (CL) parameter is an indicator that channel CN is related to the previous channel, CN-1. For a given Root Frequency and Clock Gear, the Segment Length (SL) and Segment Distribution (SD) parameters define the amount of SLIMbus bandwidth that is allocated to a given Data Channel. The minimum bandwidth requirements of a Data Channel are represented by the Presence Rate (PR) and Data Length (DL) parameters. The allocated SLIMbus bandwidth must be equal to or greater than the bandwidth of the data to be transferred.

168 Rev 4.0 The Segment Interval defines the repetition rate of the SLIMbus Slots allocated to consecutive data samples for a given Data Channel. The Presence Rate (PR) is the nominal sample rate of the audio path. The Segment Rate (determined by the Segment Interval value) must be equal to or greater than the Presence Rat e for a given data channel. The following constraints must be observed, when configuring a SLIMbus channel:  If Pushed or Pulled Transport Protocol is selected, the Segment Rate must be greater than the Presence Rate, to ensure that samples are not dropped as a result of clock drift.  If Isochronous Transport Protocol is selected, the Segment Rate must be equal to the Presence Rate. Isochronous Transport Protocol should only be selected if the data source is frequency -locked to the SLIMbus CLK (ie. the data s ource is synchronised to the SLIMbus Framer device). SLIMBUS CONTROL SEQUENCES This section describes the messages and general protocol associated with most aspects of the SLIMbus system. Note that the SLIMbus specification permits some flexibility in Core Message support for different components. See “SLIMbus Interface Control” for details of which message(s) are supported on each of the SLIMbus devices that are present on the WM8281. DEVICE MANAGEMENT & CONFIGURATION This section describes the SLIMbus messages associated with configuring all devices on the SLIMbus interface. When the SLIMbus interface starts up, it is required that one (and only one) of the components provides the Manager and Framer Device functions. Other devices can request connection to the bus after they have gained synchronisation. The REPORT_PRESENT (DC, DCV) message may be issued by devices attempting to connect to the bus. The payload of this message contains the Device Class (DC) and Device Class Version (DCV) parameters, describing the type of device that is attempting to connect. This message may be issued autonomously by the connecting device, or else in response to a REQUEST_SELF_ANNOUNCEMENT message from the Manager Device. After positively acknowledging the REPORT_PRESENT message, the Manager Device will then issue the ASSIGN_LOGICAL_ADDRESS (LA) message to allow the other device to connect to the bus. The payload of this message contains the Logical Address (LA) parameter only; this is the unique address by which the connected device will send and receive SLIMbus messages. The device is then said to be ‘enumerated’. Once a device has been successfully connected to the bus, the Logical Address (LA) parameter can be changed at any time using the CHANGE_LOGICAL_ADDRESS (LA) message. The RESET_DEVICE message commands an individual SLIMbus device to perform its reset procedure. As part of the reset, all associated ports will be reset, and any associated Data Channels will be cancelled. Note that, if the RESET_DEVICE command is issued to an Interface Device, it will cause a Component Reset (ie. all Devices within the associa ted component are reset). Under a Component Reset, every associated Device will release its Logical Address, and the Component will become disconnected from the bus. INFORMATION MANAGEMENT A memory map of Information Elements is defined for each Device. T his is arranged in 3 x 1kByte blocks, comprising Core Information elements, Device Class -specific Information elements, and User Information elements respectively, as described in the MIPI specification. Note that the contents of the User Information portion for each WM8281 SLIMbus Device are reserved. Read/Write access is implemented using the messages described below. Specific elements within the Information Map are identified using the Element Code (EC) parameter. In the case of Read access, a unique Transaction ID (TID) is assigned to each message relating to a particular read/write request. The REQUEST_INFORMATION (TID, EC) message is used to instruct a device to respond with the indicated information. The payload of this message contains the Transaction ID (TID) and the Element Code (EC).

Rev 4.0 169 The REQUEST_CLEAR_INFORMATION (TID, EC, CM) message is used to instruct a device to respond with the indicated information, and also to clear all, or parts, of the same information slice. The payload of this message co ntains the Transaction ID (TID), Element Code (EC), and Clear Mask (CM). The Clear Mask field is used to select which element(s) are to be cleared as part of the instruction. The REPLY_INFORMATION (TID, I S) message is used to provide readback of a requeste d parameter. The payload of this message contains the Transaction ID (TID) and the Information Slice (IS). The Information Slice byte(s) contain the value of the requested parameter. The CLEAR_INFORMATION (EC, CM) message is used to clear all, or parts, of the indicated information slice. The payload of this message contains the Element Code (EC) and Clear Mask (CM). The Clear Mask field is used to select which element(s) are to be cleared as part of the instruction. The REPORT_INFORMATION (EC, IS) message is used to inform other devices about a change in a specified element in the Information Map. The payload of this message contains the Element Code (EC) and the Information Slice ( IS). The Information Slice byte(s) contain the new value of the applicable parameter. VALUE MANAGEMENT (INCLUDING REGISTER ACCESS) A memory map of Value Elements is defined for each Device. This is arranged in 3 x 1kByte blocks, comprising Core Value elements, Device Class -specific Value elements, and User Value elements respectively, as described in the MIPI specification. These elements are typically parameters used to configure Device behaviour. The User Value elements of the Interface Device are used on WM8281 to support Read/Write access to the Register Map. Details of how to access specific registers are described in the “ SLIMbus Interface Control” section. Note that, with the exception of the User Value elements of the Interface Device, the contents of the User Value portion for each WM8281 SLIMbus Device are reserved. Read/Write access is implemented using the messages described below. Specific elements within the Value Map are identified using the Element Code (EC) parameter. I n the case of Read access, a unique Transaction ID (TID) is assigned to each message relating to a particular read/write request. The REQUEST_VALUE (TID, EC) message is used to instruct a device to respond with the indicated information. The payload of thi s message contains the Transaction ID (TID) and the Element Code (EC). The REPLY_VALUE (TID, VS) message is used to provide readback of a requested parameter. The payload of this message contains the Transaction ID (TID) and the Value Slice (VS). The Value Slice byte(s) contain the value of the requested parameter. The CHANGE_VALUE (EC, VU) message is used to write data to a specified element in the Value Map. The payload of this message contains the Element Code (EC) and the Value Update (VU). The Value Update byte(s) contain the new value of the applicable parameter. FRAME & CLOCKING MANAGEMENT This section describes the S LIMbus messages associated with changing the Frame or Clocking configuration. One or more configuration messages may be issued as part of a Reconfiguration Sequence; all of the updated parameters become active at once, when the Reconfiguration boundary is reached. The BEGIN_RECONFIGURATION message is issued to define a Reconfiguration Boundary point: subsequent NEXT_* messages will become active at the first valid Superframe boundary following receipt of the RECONFIGURE_NOW message. (A valid boundary must be at least two Slots after the end of the RECONFIGURE_NOW message.) Both of these messages have no payload content. The NEXT_ACTIVE_FRAMER (LAIF, NCo, NCi) message is used to select a new device as the active Framer. The payload of this message includes the Logical Address, Incoming Framer (LAIF) . Two other fields (NCo, NCi) define the number of clock cycles for which the CLK line shall b e inactive during the handover. The NEXT_SUBFRAME_MODE (SM) and NEXT_CLOCK_GEAR (CG) messages are used to re - configure the SLIMbus clocking or framing definition. The payload of each is the respective Subframe Mode (SM) or Clock Gear (CG) respectively.

170 Rev 4.0 The NEXT_PAUSE_CLOCK (RT) message instructs the active Framer to pause the bus. The payload of the message contains the Restart Time (RT), which indicates whether the interruption is to be of a specified time and/or phase duration. The NEXT_RESET_BUS message instructs all components on the bus to be reset. In this case, all Devices on the bus are reset and are disconnected from the bus. Subsequent re -connection to the bus follows the same process as when the bus is first initialised. The NEXT_SHUTDOWN_BUS message instructs all devices that the bus is to be shut down. DATA CHANNEL CONFIGURATION This section describes the procedure for configuring a SLIMbus Data Channel. Note that the Manager Device is responsible for allocating the available bandwidth as required for each Data Channel. The CONNECT_SOURCE (PN, CN) and CONNECT_SINK (PN, CN) messages are issued to the respective devices, defining the Port(s) between which a Data Channel is to be established. Note that multiple destinations (sinks) can be c onfigured for a channel , if required . The payload of each message contains the Port Number (PN) and the Channel Number (CN) parameters. The BEGIN_RECONFIGURATION message is issued to define a Reconfiguration Boundary point: subsequent NEXT_* messages will become active at the first valid Superframe boundary following receipt of the RECONFIGURE_NOW message. (A valid boundary must be at least two Slots after the end of the RECONFIGURE_NOW message.) The NEXT_DEFINE_CHANNEL (CN, TP, SD, SL) message informs the associated devices of the structure of the Data Channel. The payload of this message contains the Channel Number (CN) , Transport Protocol (TP), Segment Distribution (SD), and the Segment Length (SL) parameters for the Data Channel. The NEXT_DEFINE_CONTENT (CN, FL, PR, AF, DT, CL, DL) , or CHANGE_CONTENT (CN, FL, PR, AF, DT, CL, DL) message provides more detailed information about the Data Channel contents. The payload of this message contains the Channel Number (CN), Frequency Locked (FL) , Presence Rate (PR) , Auxiliary Bits Format (AF) , Data Type (DT) , Channel Link (CL) , and Data Length (DL) parameters. The NEXT_ACTIVATE_CHANNEL (CN) message instructs the channel to be activated at the next Reconfiguration boundary. The payload of this message contains the Channel Number (CN) only. The RECONFIGURE_NOW message completes the Reconfiguration sequence, causing all of the ‘NEXT_’ messages since the BEGIN_RECONFIGURATION to become active at the next valid Superframe boundary. (A valid boundary must be at least two S lots after the end of the RECONFIGURE_NOW message.) Active channels can be reconfigured using the CHANGE_CONTENT, NEXT_DEFINE_CONTENT, or NEXT_DEFINE_CHANNEL messages. Note that these changes can be effected without interrupting the data channel; the NEXT_DEFINE_CHANNEL, for example, may be used to change a Segment Distribution, in order to reallocate the SLIMbus bandwidth. An active channel can be paused using the NEXT_DEACTIVATE_CHANNEL message, and re - instated using the NEXT_ACTIVATE_CHANNEL message. Data channels can be disconnected using the DISCONNECT_PORT or NEXT_REMOVE_CHANNEL messages. These messages provide equivalent functionality, but use different parameters (PN or CN respectively) to identify the affected signal path.

Rev 4.0 171 SLIMBUS INTERFACE CONTROL The WM8281 features a MIPI-compliant SLIMbus interface, providing 8 channels of audio input and 8 channels of audio output. Mixed audio sample rates are supported on the SLIMbus interface . The SLIMbus interface also supports read/write access to the WM8281 control registers. The SLIMbus interface on WM8281 comprises a Generic Device, Framer Device, and Interface Device. A maximum of 16 Ports can be configured, providing up to 8 input (RX) channels and up to 8 output (TX) channels. The audio paths associated with the SLIMbus interface are described in the “Digital Core” section. The SLIMbus interface supports read/write access to the WM8281 control registers, as described later in this section. The SLIMbus clocking rate and channel allocations are controlled by the Manager Device. The Message Channel and Data Channel bandwidth may be dynamically adjusted according to the application requirements. Note that the Manag er Device functions are not implemented on the WM8281, and these bandwidth allocation requirements are outside the scope of this datasheet. SLIMBUS DEVICE PARAMETERS The SLIMbus interface on the WM8281 comprises three Devices. The Enumeration Address of each Device within the SLIMbus interface is derived from the parameters noted in Table 49. DESCRIPTION MANUFACTURER ID PRODUCT CODE DEVICE ID INSTANCE VALUE ENUMERATION ADDRESS Generic 0x012F 0x5110 0x00 0x00 012F_5110_0000 Framer 0x012F 0x5110 0x55 0x00 012F_5110_5500 Interface 0x012F 0x5110 0x7F 0x00 012F_5110_7F00 Table 49 SLIMbus Device Parameters SLIMBUS MESSAGE SUPPORT The SLIMbus interface on the WM8281 supports bus messages as noted in Table 50. Additional notes regarding SLIMbus message support are noted below, and also in Table 51. MESSAGE CODE MC[6:0] DESCRIPTION GENERIC FRAMER INTERFACE Device Management Messages 0x01 REPORT_PRESENT (DC, DCV) S S S 0x02 ASSIGN_LOGICAL_ADDRESS (LA) D D D 0x04 RESET_DEVICE () D D D 0x08 CHANGE_LOGICAL_ADDRESS (LA) D D D 0x09 CHANGE_ARBITRATION_PRIORITY (AP) 0x0C REQUEST_SELF_ANNOUNCEMENT () D D D 0x0F REPORT_ABSENT () Data Channel Management Messages 0x10 CONNECT_SOURCE (PN, CN) D 0x11 CONNECT_SINK (PN, CN) D 0x14 DISCONNECT_PORT (PN) D 0x18 CHANGE_CONTENT (CN, FL, PR, AF, DT, CL, DL) D Information Management Messages 0x20 REQUEST_INFORMATION (TID, EC) D D D 0x21 REQUEST_CLEAR_INFORMATION (TID, EC, CM) D D D 0x24 REPLY_INFORMATION (TID, IS) S S S 0x28 CLEAR_INFORMATION (EC, CM) D D D 0x29 REPORT_INFORMATION (EC, IS) S

172 Rev 4.0 MESSAGE CODE MC[6:0] DESCRIPTION GENERIC FRAMER INTERFACE Reconfiguration Messages 0x40 BEGIN_RECONFIGURATION () D D D 0x44 NEXT_ACTIVE_FRAMER (LAIF, NCo, NCi) D 0x45 NEXT_SUBFRAME_MODE (SM) D D 0x46 NEXT_CLOCK_GEAR (CG) D 0x47 NEXT_ROOT_FREQUENCY (RF) D 0x4A NEXT_PAUSE_CLOCK (RT) D 0x4B NEXT_RESET_BUS () D 0x4C NEXT_SHUTDOWN_BUS () D 0x50 NEXT_DEFINE_CHANNEL (CN, TP, SD, SL) D 0x51 NEXT_DEFINE_CONTENT (CN, FL, PR, AF, DT, CL, DL) D 0x54 NEXT_ACTIVATE_CHANNEL (CN) D 0x55 NEXT_DEACTIVATE_CHANNEL (CN) D 0x58 NEXT_REMOVE_CHANNEL (CN) D 0x5F RECONFIGURE_NOW () D D D Value Management Messages 0x60 REQUEST_VALUE (TID, EC) D 0x61 REQUEST_CHANGE_VALUE (TID, EC, VU) 0x64 REPLY_VALUE (TID, VS) S 0x68 CHANGE_VALUE (EC, VU) D Table 50 SLIMbus Message Support S = supported as a Source Device only. D = supported as a Destination Device only. The WM8281 SLIMbus component must be reset prior to scheduling a Hardware Reset or Power -On Reset. This can be achieved using the RESET_DEVICE message (issued to the WM8281 Interface Device), or else using the NEXT_RESET_BUS message. PARAMETER CODE DESCRIPTION COMMENTS AF Auxiliary Bits Format CG Clock Gear CL Channel Link CM Clear Mask WM8281 does not fully support this function. The CM bytes of the REQUEST_CLEAR_INFORMATION or CLEAR_INFORMATION messages must not be sent to WM8281 Devices. When either of these messages is received, all bits within the specified Information Slice will be cleared. CN Channel Number DC Device Class DCV Device Class Variation DL Data Length DT Data Type WM8281 supports the following DT codes: 0h - Not indicated 1h - LPCM audio Note that 2’s complement PCM can be supported with DT=0h. EC Element Code FL Frequency Locked IS Information Slice LA Logical Address

Rev 4.0 173 PARAMETER CODE DESCRIPTION COMMENTS LAIF Logical Address, Incoming Framer NCi Number of Incoming Framer Clock Cycles NCo Number of Outgoing Framer Clock Cycles PN Port Number Note that the Port Numbers of the WM8281 SLIMbus paths are register-configurable, as described in Table 52. PR Presence Rate Note that the Presence Rate must be the same as the Sample Rate selected for the associated WM8281 SLIMbus path. RF Root Frequency WM8281 supports the following RF codes as Active Framer: 1h - 24.576MHz 2h - 22.5792MHz All codes are supported when WM8281 is not the Active Framer. RT Restart Time WM8281 supports the following RT codes: 0h -Fast Recovery 2h - Unspecified Delay When either of these values is specified, the WM8281 will resume toggling the CLK line within four cycles of the CLK line frequency. SD Segment Distribution Note that any data channels that are assigned the same SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n value must also be assigned the same Segment Interval. SL Segment Length SM Subframe Mode All SM codes are supported. Note that, if subframe mode 0, 16, or 21 is selected, there is a risk of bus synchronisation being lost following a RECONFIGURE_NOW() message, and audio/data channels may be corrupted. It is recommended to use other subframe modes in order to avoid this occurrence. If subframe mode 0, 16, or 21 is selected, suitable error handling should be incorporated to detect any loss of data. TID Transaction ID TP Transport Protocol WM8281 supports the following TP codes for TX channels: 0h - Isochronous Protocol 1h - Pushed Protocol WM8281 supports the following TP codes for RX channels: 0h - Isochronous Protocol 2h - Pulled Protocol VS Value Slice VU Value Update Table 51 SLIMbus Parameter Support

174 Rev 4.0 SLIMBUS PORT NUMBER CONTROL The WM8281 SLIMbus interface supports up to 8 input (RX) channels and up to 8 output (TX) channels. The SLIMbus port numbers for these audio channels are configurable using the registers described in Table 52. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1490 (05D2h) SLIMbus RX Ports0 13:8 SLIMRX2_PORT _ADDR [5:0]

1 SLIMbus RX Channel n Port number

Valid from 0..63 5:0 SLIMRX1_PORT _ADDR [5:0] R1491 (05D3h) SLIMbus RX Ports1 13:8 SLIMRX4_PORT _ADDR [5:0] 5:0 SLIMRX3_PORT _ADDR [5:0] R1492 (05D4h) SLIMbus RX Ports2 13:8 SLIMRX6_PORT _ADDR [5:0] 5:0 SLIMRX5_PORT _ADDR [5:0] R1493 (05D5h) SLIMbus RX Ports3 13:8 SLIMRX8_PORT _ADDR [5:0] 5:0 SLIMRX7_PORT _ADDR [5:0] R1494 (05D6h) SLIMbus TX Ports0 13:8 SLIMTX2_PORT _ADDR [5:0]

9 SLIMbus TX Channel n Port number

Valid from 0..63 5:0 SLIMTX1_PORT _ADDR [5:0] R1495 (05D7h) SLIMbus TX Ports1 13:8 SLIMTX4_PORT _ADDR [5:0] 5:0 SLIMTX3_PORT _ADDR [5:0] R1496 (05D8h) SLIMbus TX Ports2 13:8 SLIMTX6_PORT _ADDR [5:0] 5:0 SLIMTX5_PORT _ADDR [5:0] R1497 (05D9h) SLIMbus TX Ports3 13:8 SLIMTX8_PORT _ADDR [5:0] 5:0 SLIMTX7_PORT _ADDR [5:0] Table 52 SLIMbus Port Number Control SLIMBUS SAMPLE RATE CONTROL The SLIMbus RX inputs may be selected as input to the digital mixers or signal processing functions within the WM8281 digital core. The SLIMbus TX outputs are derived from the respective outpu t mixers. The sample rate for each SLIMbus channel is configured using the SLIMRXn_RATE and SLIMTXn_RATE registers - see Table 23 within the “Digital Core” section. Note that the SLIMbus interface provides simultaneous support for S YSCLK-referenced and ASYNCCLK-referenced sample rates on different channels. For example, 48kHz and 44.1kHz SLIMbus audio paths can be simultaneously supported. Sample rate conversion is required when routing the SLIMbus paths to any signal chain that is asynchronous and/or configured for a different sample rate.

Rev 4.0 175 SLIMBUS SIGNAL PATH ENABLE The SLIMbus interface supports up to 8 input (RX) channels and up to 8 output (TX) channels. Each of these channels can be enabled or disabled using the register bits defined in Table 53. Note that the SLIMbus audio channels can only be supported when the corresponding ports have been enabled by the Manager Device (ie. in addition to setting the respective enable bits) . The status bits in Registers R1527 and R1528 indicate the status of each of the SLIMbus ports. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK may also be req uired, depending on the path configuration. See “ Clocking and Sample Rates” for details of the system clocks. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1525 (05F5h) SLIMbus RX Channel Enable

7 SLIMRX8_ENA 0 SLIMbus RX Channel n Enable

0 = Disabled 1 = Enabled

6 SLIMRX7_ENA 0

5 SLIMRX6_ENA 0

4 SLIMRX5_ENA 0

3 SLIMRX4_ENA 0

2 SLIMRX3_ENA 0

1 SLIMRX2_ENA 0

0 SLIMRX1_ENA 0

(05F6h) SLIMbus TX Channel Enable

7 SLIMTX8_ENA 0 SLIMbus TX Channel n Enable

0 = Disabled 1 = Enabled

6 SLIMTX7_ENA 0

5 SLIMTX6_ENA 0

4 SLIMTX5_ENA 0

3 SLIMTX4_ENA 0

2 SLIMTX3_ENA 0

1 SLIMTX2_ENA 0

0 SLIMTX1_ENA 0

(05F7h) SLIMbus RX Port Status

7 SLIMRX8_PORT_STS 0 SLIMbus RX Channel n Port Status

(Read only) 0 = Disabled 1 = Configured and active

6 SLIMRX7_PORT_STS 0

5 SLIMRX6_PORT_STS 0

4 SLIMRX5_PORT_STS 0

3 SLIMRX4_PORT_STS 0

2 SLIMRX3_PORT_STS 0

1 SLIMRX2_PORT_STS 0

0 SLIMRX1_PORT_STS 0

(05F8h) SLIMbus TX Port Status

7 SLIMTX8_PORT_STS 0 SLIMbus TX Channel n Port Status

(Read only) 0 = Disabled 1 = Configured and active

6 SLIMTX7_PORT_STS 0

5 SLIMTX6_PORT_STS 0

4 SLIMTX5_PORT_STS 0

3 SLIMTX4_PORT_STS 0

2 SLIMTX3_PORT_STS 0

1 SLIMTX2_PORT_STS 0

0 SLIMTX1_PORT_STS 0

Table 53 SLIMbus Signal Path Enable

176 Rev 4.0 SLIMBUS CONTROL REGISTER ACCESS Control register access is supported via the SLIMbus interface. Full read/write access to all registers is possible, via the “User Value Elements” portion of the Value Map. Register Write operations are implemented using the “CHANGE_VALUE” message. A maximum of two messages may be required, depending on circ umstances: the first “CHANGE_VALUE” message selects the register page ( bits [23:8] of the Control Register address); the second message contains the data and bits [7:0] of the register address. The first message may be omitted if the register page is unchanged from the previous Read or Write operation. The associated parameters are described in Table 54 and Table 55, for the generic case of writing the value 0xVVVV to control register address 0xYYYYZZ. Write Message 1 – CHANGE_VALUE PARAMETER VALUE DESCRIPTION Source Address 0xSS ‘SS’ is the 8-bit Logical Address of the message source. This could be any active device on the bus, but is typically the Manager Device (0xFF). Destination Address 0xLL ‘LL’ is the 8-bit Logical Address of the message destination (ie. the WM8281 SLIMbus Interface Device). The value is assigned by the SLIMbus Manager Device. Access Mode 0b1 Selects Byte-based access mode. Byte Address 0x800 Identifies the User Value element for selecting the Control Register page address. Slice Size 0b001 Selects 2-byte slice size Value Update 0xYYYY ‘YYYY’ is bits [23:8] of the applicable Control Register address. Table 54 Register Write Message (1) Write Message 2 – CHANGE_VALUE PARAMETER VALUE DESCRIPTION Source Address 0xSS ‘SS’ is the 8-bit Logical Address of the message source. This could be any active device on the bus, but is typically the Manager Device (0xFF). Destination Address 0xLL ‘LL’ is the 8-bit Logical Address of the message destination (ie. the WM8281 SLIMbus Interface Device). The value is assigned by the SLIMbus Manager Device. Access Mode 0b1 Selects Byte-based access mode. Byte Address 0xUUU Specifies the Value Map address, calculated as 0xA00 + (2 x 0xZZ), where ‘ZZ’ is bits [7:0] of the applicable Control Register address. Slice Size 0b001 Selects 2-byte slice size Value Update 0xVVVV ‘VVVV’ is the 16-bit data to be written. Table 55 Register Write Message (2) Note that t he first message may be omitted if its contents are unchanged from the previous CHANGE_VALUE message sent to the WM8281.

Rev 4.0 177 Register Read operations are implemented using the “CHANGE_VALUE” and “REQUEST_VALUE” messages. A maximum of two messages may be requi red, depending on circumstances: the “CHANGE_VALUE” message selects the register page ( bits [23:8] of the Control Register address); the “REQUEST_VALUE” message contains bits [7:0] of the register address. The first message may be omitted if the register page is unchanged from the previous Read or Write operation. The associated parameters are described in Table 56 and Table 57, for the generic case of reading the contents of control register address 0xYYYYZZ. Read Message 1 – CHANGE_VALUE PARAMETER VALUE DESCRIPTION Source Address 0xSS ‘SS’ is the 8-bit Logical Address of the message source. This could be any active device on the bus, but is typically the Manager Device (0xFF). Destination Address 0xLL ‘LL’ is the 8-bit Logical Address of the message destination (ie. the WM8281 SLIMbus Interface Device). The value is assigned by the SLIMbus Manager Device. Access Mode 0b1 Selects Byte-based access mode. Byte Address 0x800 Identifies the User Value element for selecting the Control Register page address. Slice Size 0b001 Selects 2-byte slice size Value Update 0xYYYY ‘YYYY’ is bits [23:8] of the applicable Control Register address. Table 56 Register Read Message (1) Read Message 2 – REQUEST_VALUE PARAMETER VALUE DESCRIPTION Source Address 0xSS ‘SS’ is the 8-bit Logical Address of the message source. This could be any active device on the bus, but is typically the Manager Device (0xFF). Destination Address 0xLL ‘LL’ is the 8-bit Logical Address of the message destination (ie. the WM8281 SLIMbus Interface Device). The value is assigned by the SLIMbus Manager Device. Access Mode 0b1 Selects Byte-based access mode. Byte Address 0xUUU Specifies the Value Map address, calculated as 0xA00 + (2 x 0xZZ), where ‘ZZ’ is bits [7:0] of the applicable Control Register address. Slice Size 0b001 Selects 2-byte slice size Transaction ID 0xTTTT ‘TTTT’ is the 16-bit Transaction ID for the message. The value is assigned by the SLIMbus Manager Device. Table 57 Register Read Message (2) Note that t he first message may be omitted if its contents are unchanged from the previous CHANGE_VALUE message sent to the WM8281. The WM8281 will respond to the Register Read commands in accordance with the normal SLIMbus protocols. Note that the WM8281 assumes that sufficient Control Space Slots are available in which to provide its response before the next REQUEST_VALUE message is received. The WM8281 response is made using a REPLY_VALUE message; the SLIMbus Manager should wait until the REPLY_VALUE message has be en received before sending the next REQUEST_VALUE message. If additional REQUEST_VALUE message(s) are received before the WM8281 response has been made, then the earlier REQUEST_VALUE message(s) will be ignored (ie. only the last REQUES T_VALUE message will be serviced).

178 Rev 4.0 SLIMBUS CLOCKING CONTROL The clock frequency of the SLIMbus interface is not fixed, and may be set according to the application requirements. The clock frequency can be reconfigured dynamically as required. The WM8281 SLIMbus interface includes a Framer Device. When configured as the active Framer, the SLIMbus clock (SLIMCLK) is an output from the WM8281. At other times, SLIMCLK is an input. The Framer function can be transferred from one device to another; this is kno wn as Framer Handover, and is controlled by the Manager Device. The supported Root Frequencies in Active Framer mode are 24.576MHz or 22.5792MHz only. At other times, the supported Root Frequencies are as defined in the MIPI Alliance specification for SLIMbus. Under normal operating conditions, the SLIMbus interface operates w ith a fixed Root Frequency (RF); dynamic updates to the bus rate are applied using a selectable Clock Gear (CG) function. The Root Frequency and the Clock Gear setting are co ntrolled by the Manager Device; these parameters are transmitted in every SLIMbus superframe to all devices on the bus. In Gear 10 (the highest Clock Gear setting), the SLIMCLK input (or output) frequency is equal to the Root Frequency. In lower gears, the SLIMCLK frequency is reduced by increasing powers of 2. The Clock Gear definition is shown in Table 58. Note that 24.576MHz Root Frequency is an example only; other frequencies are also supported. CLOCK GEAR DESCRIPTION SLIMCLK FREQUENCY (assuming 24.576MHz Root Frequency) 10 Divide by 1 24.576MHz 9 Divide by 2 12.288MHz 8 Divide by 4 6.144MHz 7 Divide by 8 3.072MHz 6 Divide by 16 1.536MHz

5 Divide by 32 768kHz

4 Divide by 64 384kHz

3 Divide by 128 192kHz

2 Divide by 256 96kHz

1 Divide by 512 48kHz

Table 58 SLIMbus Clock Gear Selection When the WM8281 is the active Framer, the SLIMCLK output is synchronised to the SYSCLK or ASYNCCLK system clock, as selected by the SLIMCLK_SRC register bit. The applicable system clock must be enabled, and configured at the S LIMbus Root Frequency, whenever the WM8281 is the active Framer. See “ Clocking and Sample Rates ” for details of the SYSCLK and ASYNCCLK system clocks. When the WM8281 is not configured as the active Framer device, then t he SLIMCLK input can be used to provide a reference source for the Frequency Locked Loops (FLLs). The frequency of this reference is controlled using the SLIMCLK_REF_GEAR register, as described in Table 59. The SLIMbus clock reference is generated using an adaptive divider on the SLIMCLK input. The divider automatically adapts to the SLIMbus Clock Gear (CG). Note that, if the Clock Gear (CG) on the bus is lower than the SLIMCLK_REF_GEAR, then the selected reference frequency cannot be supported, and the SLIMbus clock reference is disabled. The SLIMbus clock reference is selected as input to the FLLs using the FL Ln_REFCLK_SRC registers. See “Clocking and Sample Rates” for details of system clocking and the FLLs.

Rev 4.0 179 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1507 (05E3h) SLIMbus Framer Ref Gear

4 SLIMCLK_SRC 0 SLIMbus Clock source

Selects the SLIMbus reference clock in Active Framer mode. 0 = SYSCLK 1 = ASYNCCLK Note that the applicable clock must be enabled, and configured at the SLIMbus Root Frequency, in Active Framer mode. 3:0 SLIMCLK_REF_ GEAR [3:0] 4h SLIMbus Clock Reference control. Sets the SLIMbus reference clock relative to the SLIMbus Root Frequency (RF). 0h = Clock stopped 1h = Gear 1 (RF / 512) 2h = Gear 2 (RF / 256) 3h = Gear 3 (RF / 128) 4h = Gear 4 (RF / 64) 5h = Gear 5 (RF / 32) 6h = Gear 6 (RF / 16) 7h = Gear 7 (RF / 8) 8h = Gear 8 (RF / 4) 9h = Gear 9 (RF / 2) Ah = Gear 10 (RF) All other codes are Reserved Table 59 SLIMbus Clock Reference Control

180 Rev 4.0 OUTPUT SIGNAL PATH The WM8281 provides six stereo pairs of audio output signal paths. These outputs comprise ground - referenced headphone drivers, differential speaker drivers and digital output interfaces suitable for external speaker drivers. The output signal paths are summarised in Table 60. SIGNAL PATH DESCRIPTIONS OUTPUT PINS OUT1L, OUT1R Ground-referenced headphone output HPOUT1L, HPOUT1R OUT2L, OUT2R Ground-referenced headphone output HPOUT2L, HPOUT2R OUT3L, OUT3R Ground-referenced headphone output HPOUT3L, HPOUT3R OUT4L, OUT4R Differential speaker output SPKOUTLN, SPKOUTLP, SPKOUTRP, SPKOUTRN OUT5L, OUT5R Digital speaker (PDM) output SPKDAT1, SPKCLK1 OUT6L, OUT6R Digital speaker (PDM) output SPKDAT2, SPKCLK2 Table 60 Output Signal Path Summary The analogue output paths incorporate high performance 24-bit sigma-delta DACs. Under default conditions, the headphone drivers provide a stereo, single -ended output. A mono mode is also available on each headphone output pair, providing a differential (BTL) configuration. The ground-referenced headphone output paths incorporate a common mode feedback path for rejection of system -related noise. These outputs support direct connection to headphone loads, with no requirement for AC coupling capacitors. The speaker output paths are configured to drive a stereo pair of differential (BTL) outputs. The Class D design offers high efficiency at large signal levels. W ith a suitable choice of external speaker, the Class D output can drive loudspeakers directly, without any additional filter components. The digital output paths provide two stereo Pulse Density Modulation (PDM) output interface s, for connection to external audio devices. A total of four digital output channels are provided. Digital volume control is available on all outputs (analogue and digital), with programmable ramp control for smooth, glitch-free operation. A configurable noise gate function is available on each of the output signal paths. Any of the output signal paths may be selected as input to the Acoustic Echo Cancellation (AEC) loopback path. The WM8281 incorporates thermal protection functions, and als o provides short -circuit detection on the Class D speaker and headphone output paths. For further details, refer to the “ Thermal Shutdown and Short Circuit Protection” section. The WM8281 output signal paths are illustrated in Figure 56. Note that a phase inversion is present in the Class D output (OUT4) path, as shown below.

Rev 4.0 181 OUT6L output OUT6R output AEC Loopback input OUT6_OSR 0 = Normal mode 1 = High Performance SPK2_MUTE_ENDIAN SPK2_MUTE_SEQ SPK2L_MUTE SPK2R_MUTE PDM Output Driver SPKCLK2 SPKDAT2 SPK2_FMT OUT6L_ENA OUT6R_ENA Digital Core ANC Processor Noise Cancelling outputs (Left/Right) OUT5L output OUT5R output OUT5_OSR 0 = Normal mode 1 = High Performance OUT4L output OUT4R output SPKOUTLP SPKOUTLN SPKOUTRP SPKOUTRN OUT3L output OUT3R output HPOUT3L OUT2L output OUT2R output HPOUT2L OUT1L output OUT1R output HPOUT1L SPK1_MUTE_ENDIAN SPK1_MUTE_SEQ SPK1L_MUTE SPK1R_MUTE PDM Output Driver SPKCLK1 SPKDAT1 SPK1_FMT OUT5L_ENA OUT5R_ENA Mute Sequence Mute Sequence HPOUT1R HPOUT2R HPOUT3R OUT6R_ANC_SRC OUT5R_ANC_SRC OUT4R_ANC_SRC OUT3R_ANC_SRC OUT2R_ANC_SRC OUT1R_ANC_SRC OUT1_MONO OUT2_MONO OUT3_MONO OUT6L_ANC_SRC OUT5L_ANC_SRC OUT4L_ANC_SRC OUT3L_ANC_SRC OUT2L_ANC_SRC OUT1L_ANC_SRC AEC_LOOPBACK_ENA AEC_LOOPBACK_SRC [1:0] OUT6L_VOL [6:0] OUT6R_VOL [6:0] OUT5L_VOL [6:0] OUT5R_VOL [6:0] OUT4L_VOL [6:0] OUT4R_VOL [6:0] OUT3L_VOL [6:0] OUT3R_VOL [6:0] OUT2L_VOL [6:0] OUT2R_VOL [6:0] OUT1L_VOL [6:0] OUT1R_VOL [6:0] DAC DAC SPKOUTL_ENA SPKOUTR_ENA DAC DAC DAC DAC DAC DAC HP3L_ENA HP2L_ENA HP1L_ENA HP1R_ENA HP2R_ENA HP3R_ENA Figure 56 Output Signal Paths

182 Rev 4.0 OUTPUT SIGNAL PATH ENABLE The output signal paths are enabled using the register bits described in Table 61. The respective bit(s) must be enabled for analogue or digital output on the respective output path(s). The output signal paths are muted by default. It is recommended that de -selecting the mute should be the final step of the path enable control sequence. Similarly, the mute should be selected as the first step of the path dis able control sequence. The output signal path mute functions are controlled using the register bits described in Table 64. The supply rails for outputs (OUT1, OUT2 and OUT3) are generated using an integrated dual -mode Charge Pump, CP1. The Charge Pump is enabled automatically by the WM8281 when required by the output drivers . See the “ Charge Pump s, Regulators and Voltage Reference ” section for further details. The WM8281 schedules a pop -suppressed control sequence to enable or disable the OUT1, OUT2 OUT3 and OUT4 signal paths. This is automatically managed in response to setting the respective HPnx_ENA or SPKOUTx_ENA register bits. See “Control Write Sequencer” for further details. The headphone output (OUT1, OUT2, OUT3) enable cont rol sequences are inputs to the Interrupt circuit, and can be used to trigger an Interrupt event when a sequence completes. See “ Interrupts” for further details. The headphone output (OUT1, OUT2, OUT3) enable control sequences can also generate a GPIO output, providing an external indication of the sequence status. See “ General Purpose Input / Output ” to configure a GPIO pin for this function. The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK may also be required, depending on the path configuration. See “ Clocking and Sample Rates” for details of the system clocks. The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output signal paths and associated DACs. If a n attempt is made to enable an out put signal path, and there are insufficient SYSCLK cycles to support it, then the a ttempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The status bits in Register R1025 and R1030 indicate the status of each of the output signal paths. If an Underclocked Error condition occurs, then the se bits provide readback of which signal path(s) have been successfully enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1024 (0400h) Output Enables 1

11 OUT6L_ENA 0 Output Path 6 (Left) Enable

0 = Disabled 1 = Enabled

10 OUT6R_ENA 0 Output Path 6 (Right) Enable

0 = Disabled 1 = Enabled

9 OUT5L_ENA 0 Output Path 5 (Left) Enable

0 = Disabled 1 = Enabled

8 OUT5R_ENA 0 Output Path 5 (Right) Enable

0 = Disabled 1 = Enabled

7 SPKOUTL_ENA 0 Output Path 4 (Left) Enable

0 = Disabled 1 = Enabled

6 SPKOUTR_ENA 0 Output Path 4 (Right) Enable

0 = Disabled 1 = Enabled

Rev 4.0 183 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

5 HP3L_ENA 0 Output Path 3 (Left) Enable

0 = Disabled 1 = Enabled

4 HP3R_ENA 0 Output Path 3 (Right) Enable

0 = Disabled 1 = Enabled

3 HP2L_ENA 0 Output Path 2 (Left) Enable

0 = Disabled 1 = Enabled

2 HP2R_ENA 0 Output Path 2 (Right) Enable

0 = Disabled 1 = Enabled

1 HP1L_ENA 0 Output Path 1 (Left) Enable

0 = Disabled 1 = Enabled

0 HP1R_ENA 0 Output Path 1 (Right) Enable

0 = Disabled 1 = Enabled R1025 (0401h) Output Status 1

11 OUT6L_ENA_ST

S

0 Output Path 6 (Left) Enable Status

0 = Disabled 1 = Enabled

10 OUT6R_ENA_ST

S

0 Output Path 6 (Right) Enable Status

0 = Disabled 1 = Enabled

9 OUT5L_ENA_ST

S

0 Output Path 5 (Left) Enable Status

0 = Disabled 1 = Enabled

8 OUT5R_ENA_ST

S

0 Output Path 5 (Right) Enable Status

0 = Disabled 1 = Enabled

7 OUT4L_ENA_ST

S

0 Output Path 4 (Left) Enable Status

0 = Disabled 1 = Enabled

6 OUT4R_ENA_ST

S

0 Output Path 4 (Right) Enable Status

0 = Disabled 1 = Enabled R1030 (0406h) Raw Output Status 1

5 OUT3L_ENA_ST

S

0 Output Path 3 (Left) Enable Status

0 = Disabled 1 = Enabled

4 OUT3R_ENA_ST

S

0 Output Path 3 (Right) Enable Status

0 = Disabled 1 = Enabled

3 OUT2L_ENA_ST

S

0 Output Path 2 (Left) Enable Status

0 = Disabled 1 = Enabled

2 OUT2R_ENA_ST

S

0 Output Path 2 (Right) Enable Status

0 = Disabled 1 = Enabled

1 OUT1L_ENA_ST

S

0 Output Path 1 (Left) Enable Status

0 = Disabled 1 = Enabled

0 OUT1R_ENA_ST

S

0 Output Path 1 (Right) Enable Status

0 = Disabled 1 = Enabled Table 61 Output Signal Path Enable

184 Rev 4.0 OUTPUT SIGNAL PATH SAMPLE RATE CONTROL The output signal paths are derived from the respective output mixers within the WM8281 digital core. The sample rate for the output signal paths is configured using the OUT_RATE register - see Table 23 within the “Digital Core” section. Note that sample rate conversion is required when routing the output signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. OUTPUT SIGNAL PATH CONTROL The SPKCLKn frequency of the PDM output paths (OUT5 and OUT6) is controlled by the respective OUTn_OSR register, as described in Table 62. When the OUT n_OSR bit is set, the audio performance is improved, but power consumption is also increased. Note that the SPKCLK n frequencies noted in Table 62 assume that the SYSCLK frequency is a multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz (SYSCLK_FRAC=1), then the SPKCLKn frequencies will be scaled accordingly. CONDITION SPKCLKn FREQUENCY OUTn_OSR = 0 3.072MHz OUTn_OSR = 1 6.144MHz Table 62 SPKCLK Frequency The WM8281 incorporates a stereo Ambient Noise Cancellation (ANC) processor which can provide noise reduction in many different operating conditions. The noise cancellation signals can be mixed into any of the output signal paths using the _ANC_SRC registers, as described in Table 63. See “Ambient Noise Cancellation” for further details of the ANC function. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1040 (0410h) Output Path Config 1L 11:10 OUT1L_ANC_SR C [1:0]

00 OUT1L ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1044 (0414h) Output Path Config 1R 11:10 OUT1R_ANC_SR C [1:0]

00 OUT1R ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1048 (0418h) Output Path Config 2L 11:10 OUT2L_ANC_SR C [1:0]

00 OUT2L ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1052 (041Ch) Output Path Config 2R 11:10 OUT2R_ANC_SR C [1:0]

00 OUT2R ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1056 (0420h) Output Path Config 3L 11:10 OUT3L_ANC_SR C [1:0]

00 OUT3L ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved

Rev 4.0 185 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1062 (0426h) DAC Volume Limit 3R 11:10 OUT3R_ANC_SR C [1:0]

00 OUT3R ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1064 (0428h) Output Path Config 4L 11:10 OUT4L_ANC_SR C [1:0]

00 OUT4L ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1068 (042Ch) Output Path Config 4R 11:10 OUT4R_ANC_SR C [1:0]

00 OUT4R ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1072 (0430h) Output Path Config 5L

13 OUT5_OSR 0 Output Path 5 Oversample Rate

0 = Normal mode 1 = High Performance mode 11:10 OUT5L_ANC_SR C [1:0]

00 OUT5L ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1076 (0434h) Output Path Config 5R 11:10 OUT5R_ANC_SR C [1:0]

00 OUT5R ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1080 (0438h) Output Path Config 6L

13 OUT6_OSR 0 Output Path 6 Oversample Rate

0 = Normal mode 1 = High Performance mode 11:10 OUT6L_ANC_SR C [1:0]

00 OUT6L ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved R1084 (043Ch) Output Path Config 6R 11:10 OUT6R_ANC_SR C [1:0]

00 OUT6R ANC Source Select

00 = Disabled 01 = ANC Left Channel 10 = ANC Right Channel 11 = Reserved Table 63 Output Signal Path Control

186 Rev 4.0 OUTPUT SIGNAL PATH DIGITAL VOLUME CONTROL A digital volume control is provided on each of the output signal paths, providing -64dB to +31.5dB gain control in 0.5dB steps. An independent mute control is also provided for each output signal path. Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. For increasin g gain (or un -mute), the rate is controlled by the OUT_VI_RAMP register. For decreasing gain (or mute), the rate is controlled by the OUT_VD_RAMP register. Note that the OUT_VI_RAMP and OUT_VD_RAMP registers should not be changed while a volume ramp is in progress. The OUT_VU bits control the loading of the output signal path digital volume and mute controls. When OUT_VU is set to 0, the digital volume and mute settings will be loaded into the respective control register, but will not actually change the si gnal path gain. The digital volume and mute settings on all of the output signal paths are updated when a 1 is written to OUT_VU. This makes it possible to update the gain of multiple signal paths simultaneously. Note that, although the digital volume cont rol registers provide 0.5dB steps, the internal circuits provide signal gain adjustment in 0.1 25dB steps. This allows a very high degree of gain control, and smooth volume ramping under all operating conditions. The digital volume control register fields are described in Table 64 and Table 65. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1033 (0409h) Output Volume Ramp 6:4 OUT_VD_RAMP [2:0]

010 Output Volume Decreasing Ramp Rate

(seconds/6dB) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms This register should not be changed while a volume ramp is in progress. 2:0 OUT_VI_RAMP [2:0]

010 Output Volume Increasing Ramp Rate

(seconds/6dB) 000 = 0ms 001 = 0.5ms 010 = 1ms 011 = 2ms 100 = 4ms 101 = 8ms 110 = 15ms 111 = 30ms This register should not be changed while a volume ramp is in progress. R1041 (0411h) DAC Digital Volume 1L

9 OUT_VU Output Signal Paths Volume Update

Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT1L_MUTE 1 Output Path 1 (Left) Digital Mute

0 = Un-mute 1 = Mute

Rev 4.0 187 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 OUT1L_VOL [7:0] 80h Output Path 1 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1045 (0415h) DAC Digital Volume Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT1R_MUTE 1 Output Path 1 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT1R_VOL [7:0] 80h Output Path 1 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1049 (0419h) DAC Digital Volume 2L Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT2L_MUTE 1 Output Path 2 (Left) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT2L_VOL [7:0] 80h Output Path 2 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1053 (041Dh) DAC Digital Volume Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT2R_MUTE 1 Output Path 2 (Right) Digital Mute

0 = Un-mute 1 = Mute

188 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 OUT2R_VOL [7:0] 80h Output Path 2 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1057 (0421h) DAC Digital Volume 3L Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT3L_MUTE 1 Output Path 3 (Left) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT3L_VOL [7:0] 80h Output Path 3 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1061 (0425h) DAC Digital Volume Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT3R_MUTE 1 Output Path 3 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT3R_VOL [7:0] 80h Output Path 3 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1065 (0429h) DAC Digital Volume 4L Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT4L_MUTE 1 Output Path 4 (Left) Digital Mute

0 = Un-mute 1 = Mute

Rev 4.0 189 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 OUT4L_VOL [7:0] 80h Output Path 4 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1069 (042Dh) DAC Digital Volume Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT4R_MUTE 1 Output Path 4 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT4R_VOL [7:0] 80h Output Path 4 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1073 (0431h) DAC Digital Volume 5L Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT5L_MUTE 1 Output Path 5 (Left) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT5L_VOL [7:0] 80h Output Path 5 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1077 (0435h) DAC Digital Volume Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT5R_MUTE 1 Output Path 5 (Right) Digital Mute

0 = Un-mute 1 = Mute

190 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 OUT5R_VOL [7:0] 80h Output Path 5 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1081 (0439h) DAC Digital Volume 6L Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT6L_MUTE 1 Output Path 6 (Left) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT6L_VOL [7:0] 80h Output Path 6 (Left) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) R1085 (043Dh) DAC Digital Volume Writing a 1 to this bit will cause the Output Signal Paths Volume and Mute settings to be updated simultaneously

8 OUT6R_MUTE 1 Output Path 6 (Right) Digital Mute

0 = Un-mute 1 = Mute 7:0 OUT6R_VOL [7:0] 80h Output Path 6 (Right) Digital Volume -64dB to +31.5dB in 0.5dB steps 00h = -64dB 01h = -63.5dB … (0.5dB steps) 80h = 0dB … (0.5dB steps) BFh = +31.5dB C0h to FFh = Reserved (See Table 65 for volume range) Table 64 Output Signal Path Digital Volume Control

Rev 4.0 191 Output Volume Register Volume (dB) Output Volume Register Volume (dB) Output Volume Register Volume (dB) Output Volume Register Volume (dB) 00h -64.0 40h -32.0 80h 0.0 C0h Reserved 01h -63.5 41h -31.5 81h 0.5 C1h Reserved 02h -63.0 42h -31.0 82h 1.0 C2h Reserved 03h -62.5 43h -30.5 83h 1.5 C3h Reserved 04h -62.0 44h -30.0 84h 2.0 C4h Reserved 05h -61.5 45h -29.5 85h 2.5 C5h Reserved 06h -61.0 46h -29.0 86h 3.0 C6h Reserved 07h -60.5 47h -28.5 87h 3.5 C7h Reserved 08h -60.0 48h -28.0 88h 4.0 C8h Reserved 09h -59.5 49h -27.5 89h 4.5 C9h Reserved 0Ah -59.0 4Ah -27.0 8Ah 5.0 CAh Reserved 0Bh -58.5 4Bh -26.5 8Bh 5.5 CBh Reserved 0Ch -58.0 4Ch -26.0 8Ch 6.0 CCh Reserved 0Dh -57.5 4Dh -25.5 8Dh 6.5 CDh Reserved 0Eh -57.0 4Eh -25.0 8Eh 7.0 CEh Reserved 0Fh -56.5 4Fh -24.5 8Fh 7.5 CFh Reserved 10h -56.0 50h -24.0 90h 8.0 D0h Reserved 11h -55.5 51h -23.5 91h 8.5 D1h Reserved 12h -55.0 52h -23.0 92h 9.0 D2h Reserved 13h -54.5 53h -22.5 93h 9.5 D3h Reserved 14h -54.0 54h -22.0 94h 10.0 D4h Reserved 15h -53.5 55h -21.5 95h 10.5 D5h Reserved 16h -53.0 56h -21.0 96h 11.0 D6h Reserved 17h -52.5 57h -20.5 97h 11.5 D7h Reserved 18h -52.0 58h -20.0 98h 12.0 D8h Reserved 19h -51.5 59h -19.5 99h 12.5 D9h Reserved 1Ah -51.0 5Ah -19.0 9Ah 13.0 DAh Reserved 1Bh -50.5 5Bh -18.5 9Bh 13.5 DBh Reserved 1Ch -50.0 5Ch -18.0 9Ch 14.0 DCh Reserved 1Dh -49.5 5Dh -17.5 9Dh 14.5 DDh Reserved 1Eh -49.0 5Eh -17.0 9Eh 15.0 DEh Reserved 1Fh -48.5 5Fh -16.5 9Fh 15.5 DFh Reserved 20h -48.0 60h -16.0 A0h 16.0 E0h Reserved 21h -47.5 61h -15.5 A1h 16.5 E1h Reserved 22h -47.0 62h -15.0 A2h 17.0 E2h Reserved 23h -46.5 63h -14.5 A3h 17.5 E3h Reserved 24h -46.0 64h -14.0 A4h 18.0 E4h Reserved 25h -45.5 65h -13.5 A5h 18.5 E5h Reserved 26h -45.0 66h -13.0 A6h 19.0 E6h Reserved 27h -44.5 67h -12.5 A7h 19.5 E7h Reserved 28h -44.0 68h -12.0 A8h 20.0 E8h Reserved 29h -43.5 69h -11.5 A9h 20.5 E9h Reserved 2Ah -43.0 6Ah -11.0 AAh 21.0 EAh Reserved 2Bh -42.5 6Bh -10.5 ABh 21.5 EBh Reserved 2Ch -42.0 6Ch -10.0 ACh 22.0 ECh Reserved 2Dh -41.5 6Dh -9.5 ADh 22.5 EDh Reserved 2Eh -41.0 6Eh -9.0 AEh 23.0 EEh Reserved 2Fh -40.5 6Fh -8.5 AFh 23.5 EFh Reserved 30h -40.0 70h -8.0 B0h 24.0 F0h Reserved 31h -39.5 71h -7.5 B1h 24.5 F1h Reserved 32h -39.0 72h -7.0 B2h 25.0 F2h Reserved 33h -38.5 73h -6.5 B3h 25.5 F3h Reserved 34h -38.0 74h -6.0 B4h 26.0 F4h Reserved 35h -37.5 75h -5.5 B5h 26.5 F5h Reserved 36h -37.0 76h -5.0 B6h 27.0 F6h Reserved 37h -36.5 77h -4.5 B7h 27.5 F7h Reserved 38h -36.0 78h -4.0 B8h 28.0 F8h Reserved 39h -35.5 79h -3.5 B9h 28.5 F9h Reserved 3Ah -35.0 7Ah -3.0 BAh 29.0 FAh Reserved 3Bh -34.5 7Bh -2.5 BBh 29.5 FBh Reserved 3Ch -34.0 7Ch -2.0 BCh 30.0 FCh Reserved 3Dh -33.5 7Dh -1.5 BDh 30.5 FDh Reserved 3Eh -33.0 7Eh -1.0 BEh 31.0 FEh Reserved 3Fh -32.5 7Fh -0.5 BFh 31.5 FFh Reserved Table 65 Output Signal Path Digital Volume Range

192 Rev 4.0 OUTPUT SIGNAL PATH DIGITAL VOLUME LIMIT A digital limit control is provided on each of the output signal paths . Any signal which exceeds the applicable limit will be clipped at that level. The limit control is implemented in the digital domain, before the output path DACs. For typical applications, a limit of 0dBFS is recommended for the analogue output paths (OUT1, OUT2, OUT3 and OUT4). The digital speaker outputs (OUT5 and OUT6) can handle signal levels up to +3dBFS; a maximum setting of +3dBFS is recommended for these output paths. Caution is advised when selecting other limits, as the output signal may clip in the digital and/or analogue stages of the respective signal path(s) The digital limit register fields are described in Table 66 and Table 67. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1042 (0412h DAC Volume Limit 1L 7:0 OUT1L_VOL_LIM [7:0] 81h Output Path 1 (Left) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1046 (0416h DAC Volume Limit 1R 7:0 OUT1R_VOL_LI M [7:0] 81h Output Path 1 (Right) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1050 (041Ah DAC Volume Limit 2L 7:0 OUT2L_VOL_LIM [7:0] 81h Output Path 2 (Left) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range)

Rev 4.0 193 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1054 (041Eh DAC Volume Limit 2R 7:0 OUT2R_VOL_LI M [7:0] 81h Output Path 2 (Right) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1058 (0422h DAC Volume Limit 3L 7:0 OUT3L_VOL_LIM [7:0] 81h Output Path 3 (Left) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1062 (0426h DAC Volume Limit 3R 7:0 OUT3R_VOL_LI M [7:0] 81h Output Path 3 (Right) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1066 (042Ah DAC Volume Limit 4L 7:0 OUT4L_VOL_LIM [7:0] 81h Output Path 4 (Left) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range)

194 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1070 (042Eh DAC Volume Limit 4R 7:0 OUT4R_VOL_LI M [7:0] 81h Output Path 4 (Right) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1074 (0432h DAC Volume Limit 5L 7:0 OUT5L_VOL_LIM [7:0] 81h Output Path 5 (Left) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1078 (0436h DAC Volume Limit 5R 7:0 OUT5R_VOL_LI M [7:0] 81h Output Path 5 (Right) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) R1082 (043Ah DAC Volume Limit 6L 7:0 OUT6L_VOL_LIM [7:0] 81h Output Path 6 (Left) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range)

Rev 4.0 195 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1086 (043Eh DAC Volume Limit 6R 7:0 OUT6R_VOL_LI M [7:0] 81h Output Path 6 (Right) Digital Limit -6dBFS to +6dBFS in 0.5dB steps 00h to 73h = Reserved 74h = -6.0dBFS 75h = -5.5dBFS … (0.5dB steps) 80h = 0.0dBFS … (0.5dB steps) 8Bh = +5.5dBFS 8Ch = +6.0dBFS 8Dh to FFh = Reserved (see Table 67 for limit range) Table 66 Output Signal Path Digital Limit Control OUTnL_VOL_LIM[7:0], OUTnR_VOL_LIM[7:0] LIMIT (dBFS) 00h to 73h Reserved 74h -6.0 75h -5.5 76h -5.0 77h -4.5 78h -4.0 79h -3.5 7Ah -3.0 7Bh -2.5 7Ch -2.0 7Dh -1.5 7Eh -1.0 7Fh -0.5 80h 0.0 81h +0.5 82h +1.0 83h +1.5 84h +2.0 85h +2.5 86h +3.0 87h +3.5 88h +4.0 89h +4.5 8Ah +5.0 8Bh +5.5 8Ch +6.0 8Dh to FFh Reserved Table 67 Output Signal Path Digital Limit Range

196 Rev 4.0 OUTPUT SIGNAL PATH NOISE GATE CONTROL The WM8281 provides a digital noise gate function for each of the output signal paths. The noise gate ensures best noise performance when the signal path is idle. When the noise gate is enabled, and the applicable signal level is below the noise gate thres hold, then the noise gate is activated, causing the signal path to be muted. The noise gate function is enabled using the NGATE_ENA register, as described in Table 68. For each output path, the noise gate may be associated with one or more of the signal path threshold detection functions using the _NGATE_SRC register fields. When more than one signal thres hold is selected, then the output path noise gate is only activated (ie. muted) when all of the respective signal thresholds are satisfied. For example, if the OUT1L noise gate is associated with the OUT1L and OUT1R signal paths, then the OUT1L signal path will only be muted if both the OUT1L and OUT1R signal levels are below the respective thresholds. The noise gate threshold (the signal level below which the noise gate is activated) is set using NGATE_THR. Note that, for each output path, the noise gate t hreshold represents the signal level at the respective output pin(s) - the threshold is therefore independent of the digital volume and PGA gain settings. Note that, although there is only one noise gate threshold level (NGATE_THR), each of the output path noise gates may be activated independently, according to the respective signal content and the associated threshold configuration(s). To prevent erroneous triggering, a time delay is applied before the gate is activated; the noise gate is only activated (ie. muted) when the output levels are below the applicable signal level threshold(s) for longer than the noise gate ‘hold time’. The ‘hold time’ is set using the NGATE_HOLD register. When the noise gate is activated, the WM8281 gradually attenuates the res pective signal path at the rate set by the OUT_VD_RAMP register (see Table 64). When the noise gate is de -activated, the output volume increases at the rate set by the OUT_VI_RAMP register. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1043 (0413h) Noise Gate Select 1L 11:0 OUT1L_NGATE_ SRC [11:0] 001h Output Signal Path Noise Gate Source Enables one of more signal paths as inputs to the respective noise gate. If more than one signal path is enabled as an input, the noise gate is only activated (ie. muted) when all of the respective signal thresholds are satisfied. [11] = OUT6R [10] = OUT6L [9] = OUT5R [8] = OUT5L [7] = OUT4R [6] = OUT4L [5] = OUT3R [4] = OUT3L [3] = OUT2R [2] = OUT2L [1] = OUT1R [0] = OUT1L Each bit is coded as: 0 = Disabled 1 = Enabled R1047 (0417h) Noise Gate Select 1R 11:0 OUT1R_NGATE_ SRC [11:0] 002h R1051 (041Bh) Noise Gate Select 2L 11:0 OUT2L_NGATE_ SRC [11:0] 004h R1055 (041Fh) Noise Gate Select 2R 11:0 OUT2R_NGATE_ SRC [11:0] 008h R1059 (0423h) Noise Gate Select 3L 11:0 OUT3L_NGATE_ SRC [11:0] 010h R1063 (0427h) Noise Gate Select 3R 11:0 OUT3R_NGATE_ SRC [11:0] 020h

Rev 4.0 197 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1067 (042Bh) Noise Gate Select 4L 11:0 OUT4L_NGATE_ SRC [11:0] 040h R1071 (042Fh) Noise Gate Select 4R 11:0 OUT4R_NGATE_ SRC [11:0] 080h R1075 (0433h) Noise Gate Select 5L 11:0 OUT5L_NGATE_ SRC [11:0] 100h R1079 (0437h) Noise Gate Select 5R 11:0 OUT5R_NGATE_ SRC [11:0] 200h R1083 (043Bh) Noise Gate Select 6L 11:0 OUT6L_NGATE_ SRC [11:0] 400h R1087 (043Fh) Noise Gate Select 6R 11:0 OUT6R_NGATE_ SRC [11:0] 800h R1112 (0458h) Noise Gate Control 5:4 NGATE_HOLD [1:0]

00 Output Signal Path Noise Gate Hold Time

(delay before noise gate is activated) 00 = 30ms 01 = 120ms 10 = 250ms 11 = 500ms 3:1 NGATE_THR [2:0]

000 Output Signal Path Noise Gate Threshold

000 = -60dB 001 = -66dB 010 = -72dB 011 = -78dB 100 = -84dB 101 = -90dB 110 = -96dB 111 = -102dB

0 NGATE_ENA 0 Output Signal Path Noise Gate Enable

0 = Disabled 1 = Enabled Table 68 Output Signal Path Noise Gate Control

When configured with suitable DSP firmware, the WM8281 can provide an integrated AEC capability. the required signal processing algorithms. Figure 56. The AEC Loopback signal can be selected as input to any of the digital mixers wi thin the register - see Table 23 within the “Digital Core” section. for the Transmit Path AEC function is selected using the AEC_LOOPBACK_SRC register. “General Purpose Input / Output” and “Interrupts” for further details.

0000 Input source for Tx AEC function

1 AEC_ENA_STS 0 Transmit (Tx) Path AEC Control Status

0 AEC_LOOPBAC

0 Transmit (Tx) Path AEC Control

Rev 4.0 199 HEADPHONE OUTPUTS AND MONO MODE The headphone drivers can provide a mono differential (BTL) output; this is ideal for driving an earpiece or hearing aid coil. The mono differential (BTL) configuration is selected using the OUTn_MONO register bits. When the OUTn_MONO bit is set, then the respective Right channel output is an inverted copy of the Left channel outp ut signal; this creates a differential output between the r espective OUTnL and OUTnR signal paths. The Left and Right channel output drivers must both be enabled in Mono mode; both channels should be enabled simultaneously using the register bits described in Table 61. The mono (BTL) signal paths are illustrated in Figure 56. Note that, in mono configuration, the effective gain of the signal path is increased by 6dB. The OUT1L and OUT1R output signal paths are associated with the analogue outputs HPOUT1L and HPOUT1R respectively. The OUT2L and OUT2R output signal paths are associated with the analogue outputs HPOUT2L and HPOUT2R respectively. The OUT3L and OUT3R output signal paths are associated with the analogue outputs HPOUT3L and HPOUT3R respectively. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1040 (0410h) Output Path Config 1L

12 OUT1_MONO 0 Output Path 1 Mono Mode

(Configures HPOUT1L and HPOUT1R as a mono differential output.) 0 = Disabled 1 = Enabled The gain of the signal path is increased by 6dB in differential (mono) mode. R1048 (0418h) Output Path Config 2L

12 OUT2_MONO 0 Output Path 2 Mono Mode

(Configures HPOUT2L and HPOUT2R as a mono differential output.) 0 = Disabled 1 = Enabled The gain of the signal path is increased by 6dB in differential (mono) mode. R1056 (0420h) Output Path Config 3L

12 OUT3_MONO 0 Output Path 3 Mono Mode

(Configures HPOUT3L and HPOUT3R as a mono differential output.) 0 = Disabled 1 = Enabled The gain of the signal path is increased by 6dB in differential (mono) mode. Table 70 Headphone Driver Mono Mode Control The headphone driver outputs HPOUT1L, HPOUT1R, HPOUT2L , HPOUT2R, HPOUT3L a nd HPOUT3R are suitable for direct connection to external headphones and earpieces. The outputs are ground-referenced, eliminating any requirement for AC coupling capacitors. The headphone outputs incorporate a common mode, or ground loop, feedback path wh ich provides rejection of system-related ground noise. The feedback pins must be connected to ground for normal operation of the headphone outputs. Note that the feedback pins should be connected to GND close to the respective headphone jack, as illustrated in Figure 57. In mono (differential) mode, the feedback pin(s) should be connected to the ground plane that is physically closest to the earpiece output PCB tracks. The ground feedback path for HPOUT1L and HPOUT1R is provided via the HPOUT1FB1 or HPOUT1FB2 pins; the applicable connection must be selected using the ACCDET_SRC register, as described in Table 71. The ground feedback path for HPOUT2L and HPOUT2R is provided via the HPOUT2 FB pin. No register configuration is required for the HPOUT2FB connection. The ground feedback path for HPOUT3L and HPOUT3R is provided via the HPOUT3FB pin. No

200 Rev 4.0 register configuration is required for the HPOUT3FB connection. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R659 (0293h) Accessory Detect Mode 1

13 ACCDET_SRC 0 Accessory Detect / Headphone Feedback

0 = Accessory detect on MICDET1, Headphone ground feedback on HPOUT1FB1 1 = Accessory detect on MICDET2, Headphone ground feedback on HPOUT1FB2 Table 71 Headphone Output (HPOUT1) Ground Feedback Control Earpiece The HPOUT1FB1 or HPOUT1FB2 pin is selected by the ACCDET_SRC register bit. WM8281 HPOUT1L HPOUT1R HPOUT1FB1 HPOUT2L HPOUT2R HPOUT2FB HPOUT1FB2 HPOUT3L HPOUT3R HPOUT3FB Each headphone output can support stereo (single- ended) or mono (differential) output. The illustration shows the configuration for a typical application. Figure 57 Headphone and Earpiece Connection SPEAKER OUTPUTS (ANALOGUE) The speaker driver outputs SPKOUTLP, SPKOUTLN, SPKOUTRP and SPKOUTRN provide two differential (BTL) outputs suitable for direct connection to external loudspeakers. The integrated Class D speaker driver provides high efficiency at large signal levels. The speaker driver signal paths incorporate a boost function which shifts the signal levels between the AVDD and SPKVDD voltage domains. The boost is pre -configured (+12dB) for the recommended AVDD and SPKVDD operating voltages (see “Recommended Operating Conditions”). Ultra-low leakage and high PSRR allow the speaker supply SPKVDD to be connected directly to a lithium battery. Note that SPKVDDL powers the Left Speaker driver, and SPKVDD R powers the Right Speaker driver; it is assumed that SPKVDDL = SPKVDDR = SPKVDD. Note that SYSCLK must be pres ent and enabled when using the Class D speaker output; see “Clocking and Sample Rates” for details of SYSCLK and the associated register control fields. The OUT4L and OUT4R output signal paths are associated with the analogue outputs SPKOUTLP, SPKOUTLN, SPKOUTRP and SPKOUTRN. The Class D speaker output is a pulse width modulated signal, and requires external filtering in order to recreate the audio signal. With a suitable choice of external speakers, the speakers themselves can provide the necessary filtering. See “ Applications Information” for further information on Class D speaker connections. The external speaker connection is illustrated in Figure 58, assuming suitable speakers are chosen to provide the PWM filtering.

202 Rev 4.0 When the OUT6L or OUT6R output signal path is enabled, the PDM interface clock signal is output on the SPKCLK2 pin. The output signal paths support normal and high performance operati ng modes, as described in the “Output Signal Path ” section. The SPKCLK n frequency is set according to the operating mode of the relevant output path , as described in Table 72. The OUT 5_OSR and OUT6_OSR register bit s are defined in Table 63. Note that the SPKCLK n frequencies noted in Table 72 and Table 73 assume that the S YSCLK frequency is a multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz (SYSCLK_FRAC=1), then the SPKCLKn frequencies will be scaled accordingly. OUT5_OSR DESCRIPTION SPKCLK1 FREQUENCY 0 Normal mode 3.072MHz 1 High Performance mode 6.144MHz Table 72 SPKCLK1 Frequency OUT6_OSR DESCRIPTION SPKCLK2 FREQUENCY 0 Normal mode 3.072MHz 1 High Performance mode 6.144MHz Table 73 SPKCLK2 Frequency The PDM output channels can be independently muted. When muted, the default output on each channel is a DSD -compliant silent stream (0110_1001b). The mute output code can be programmed to other values if required, using the SPK n_MUTE_SEQ register fields. The mute output code can be transmitted MSB-first or LSB-first; this is selectable using the SPKn_MUTE_ENDIAN register. Note that the PDM Mute function is not a soft -mute; the audio output is interrupted immediately when the PDM mute is asserted. It is recommended to use the Output Signal Path mute function before applying the PDM mute. See Table 64 for details of the OUTnL_MUTE and OUTnR_MUTE registers. The PDM output interface registers are described in Table 74. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1168 (0490h) PDM SPK1 CTRL 1

13 SPK1R_MUTE 0 PDM Speaker Output 1 (Right) Mute

0 = Audio output (OUT5R) 1 = Mute Sequence output

12 SPK1L_MUTE 0 PDM Speaker Output 1 (Left) Mute

0 = Audio output (OUT5L) 1 = Mute Sequence output

8 SPK1_MUTE_EN

0 PDM Speaker Output 1 Mute Sequence

0 = Mute sequence is LSB first 1 = Mute sequence output is MSB first 7:0 SPK1_MUTE_SE Q [7:0] 69h PDM Speaker Output 1 Mute Sequence Defines the 8-bit code that is output on SPKDAT1 (left) or SPKDAT1 (right) when muted. R1169 (0491h) PDM SPK1 CTRL 2

0 SPK1_FMT 0 PDM Speaker Output 1 timing format

0 = Mode A (PDM data is valid at the rising/falling edges of SPKCLK1) 1 = Mode B (PDM data is valid during the high/low phase of SPKCLK1) R1170 (0492h) PDM SPK2 CTRL 1

13 SPK2R_MUTE 0 PDM Speaker Output 2 (Right) Mute

0 = Audio output (OUT6R) 1 = Mute Sequence output

12 SPK2L_MUTE 0 PDM Speaker Output 2 (Left) Mute

0 = Audio output (OUT6L) 1 = Mute Sequence output

Rev 4.0 203 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

8 SPK2_MUTE_EN

0 PDM Speaker Output 2 Mute Sequence

0 = Mute sequence is LSB first 1 = Mute sequence output is MSB first 7:0 SPK2_MUTE_SE Q [7:0] 69h PDM Speaker Output 2 Mute Sequence Defines the 8-bit code that is output on SPKDAT2 (left) or SPKDAT2 (right) when muted. R1171 (0493h) PDM SPK2 CTRL 2

0 SPK2_FMT 0 PDM Speaker Output 2 timing format

0 = Mode A (PDM data is valid at the rising/falling edges of SPKCLK2) 1 = Mode B (PDM data is valid during the high/low phase of SPKCLK2) Table 74 Digital Speaker (PDM) Output Control The digital speaker (PDM) outputs SPKDAT n and SPKCLKn are intended for direct connection to a compatible external speaker driver. A typical configuration is illustrated in Figure 60. WM8281 Speaker Driver Speaker Driver Right Left Speaker Driver Speaker Driver Left Right SPKCLK1 SPKDAT1 SPKCLK2 SPKDAT2 Figure 60 Digital Speaker (PDM) Connection

204 Rev 4.0 EXTERNAL ACCESSORY DETECTION The WM8281 provides external accessory detection functions whi ch can sense the presence and impedance of external components. This can be used to detect the insertion or removal of an external headphone or headset, and to provide an indication of key/button push events. Jack insertion is detected using the JACKDET pi n, which must be connected to a switch contact within the jack socket. An Interrupt event is generated whenever a jack insertion or jack removal event is detected. The jack detect function can also be used to trigger a Wake-Up transition (ie. exit from Sleep mode) and/or to trigger the Control Write Sequencer. Suppression of pops and clicks caused by jack insertion or removal is provided using t he MICDET clamp function . This function can also be used to trigger interrupt events, a Wake -Up transition (ie. exit from Sleep mode) and/or to trigger the Control Write Sequencer. The integrated General Purpose Switch can be synchronised with the MICDET clamp, to provide additional pop suppression capability. Microphones, push -buttons and other accessories can be det ected via the MICDET1 or MICDET2 pins. The presence of a microphone, and the status of a hookswitch can be detected. This feature can also be used to detect push-button operation. Headphone impedance can be detected via the HPDETL and HPDETR pins; this can be used to set different gain levels or other configuration settings according to the type of load connected. For example, different settings may be applicable to Headphone or Line output loads. The MICVDD power domain must be enabled when using the Microphone Detect function. (Note that MICVDD is not required for the Jack Detect or Headphone Detect functions.) The MICVDD power domain is provided using an internal Charge Pump (CP2) and LDO Regulator (LDO2). See “ Charge Pumps, Regulators and Voltage Reference” for details of these circuits. The internal 32kHz clock must be present and enabled when using the jack insertion or accessory detection functions; see “ Clocking and Sample Rates ” for details of the internal 32kHz clock and associated register control fields. JACK DETECT The WM8281 provides support for jack insertion switch detection. The jack insertion status can be read using the relevant register status bit. A jack insertion or removal can also be used to trigger an interrupt (IRQ) event or to trigger the Control Write Sequencer. When the WM8281 is in the low -power Sleep mode (see “ Low Power Sleep Configuration ”), the jack detect function can be used as a ‘wake -up’ input; a typical use case is where an applicatio n is idle in standby mode until a headphone or headset jack is inserted. Jack insertion and removal is detected using the JACKDET pin. The recommended external connection circuit is illustrated in Figure 61. The jack detect feature is enabled using JD1_ENA; the jack insertion status can be read using the JD1_STS register. The JACKDET input de-bounce is selected using the JD1_DB register, as described in Table 75. Note that the de -bounce circuit uses the 32kHz clock, which must be enabled whenever input de -bounce functions are required. Note that the Jack Detect signal, JD1, can be used as an input to the MICDET Clamp function. This provides additional functionality relating to jack insertion or jack removal events. An Interrupt Request (IRQ) event is generated whenever a jack insertion or jack removal is detected (see “Interrupts”). Separate ‘mask’ bits are provided to enable IRQ events on the rising and/or falling edge of the JD1 status. The Control Write Sequencer can be tri ggered by a jack insertion or jack removal detection. This is enabled using register bits described in the “Low Power Sleep Configuration” section. The control registers associated with the Jack Detect function are described in Table 75.

Rev 4.0 205 REGISTER ADDRESS BIT LABEL DEFAUL T (02D3h) Jack detect analogue

0 JD1_ENA 0 JACKDET enable

0 = Disabled 1 = Enabled R3413 (0D55h) AOD IRQ Raw Status

0 JD1_STS 0 JACKDET input status

0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET pin is pulled ‘low’ on Jack insertion.) R3414 (0D56h) Jack detect debounce

0 JD1_DB 0 JACKDET input de-bounce

0 = Disabled 1 = Enabled Table 75 Jack Detect Control A recommended connection circuit, including headphone output on HPOUT1 and microphone connections, is shown in Figure 61. See “ Applications Information” for details of recommended external components. WM8281 HPOUT1L HPOUT1R HPOUT1FB1 JACKDET MICDET1 Note: The illustrated circuit assumes the jack insertion switch contacts are closed when jack is inserted. * Note that the Right analogue mic channel is recommended with the external accessory detect function (jack insertion switch) MICBIASn 2.2k (+/-2%) C * INnRP Figure 61 Jack Detect and External Accessory Connections The internal comparator circuit used to detect the JACKDET status is illustrated in Figure 62. The threshold voltages for the jack detect circuit are noted in the “ Electrical Characteristics”. Note that separate thresholds are defined for jack insertion and jack removal. JACKDET - reference AVDD Jack Detect logic 1M (jack insertion switch) Note: The illustrated circuit assumes the jack insertion switch contacts are closed when jack is inserted. Figure 62 Jack Detect Comparator

Rev 4.0 207 In applications where a large decoupling capacitance is present on the MICBIAS output, the MICDET Clamp function alone may be unable to discharge the capacitor sufficiently to eliminate pops and clicks associated with jack insertion and removal. In this ca se, it may be desirable to use the General Purpose Switch within the WM8281 to provide isolation from the MICBIAS output; an example circuit is shown in Figure 64. The General Purpose Switch is configured using SW1_MODE. This register allows the switch to be disabled, enabled, or synchronised to the MICDET Clamp status, as described in Table 76. For jack pop suppression, it is recommended to set SW1_MODE=11. In this case, the switch contacts are open whenever the MICDET Clamp is active, and the switch contacts are closed whenever the MICDET Clamp is inactive. Normal accessory funct ions are supported when the switch contacts (GPSWA and GPSWB) are closed, and the MICDET Clamp is inactive. Ground clamping of MICDET, and isolation of MICBIAS are achieved when the switch contacts are open, and the MICDET Clamp is active. Note that the MI CDET Clamp function must also be configured appropriately when using this method of pop suppression control. HPOUT1FB1/ MICDET2 MICDET1/ HPOUT1FB2 MICBIASn C * INnRP GPSWA GPSWB C * Note: The Jack plug is shown partially removed, with the MICDET1 pin in contact with the headphone load. * see note General Purpose Switch Control SW1_MODE WM8281 MICDET Clamp Control MICD_CLAMP_MODE MICD_CLAMP_STS MICD_CLAMP_DB When the MICDET Clamp is active in the configuration shown, the MICDET1 pin is grounded via the headphone jack ground connection. * Note that the Right analogue mic channel is recommended with the external accessory detect function Figure 64 General Purpose Switch circuit

208 Rev 4.0 The control registers associated with the MICDET C lamp and General Purpose Switch functions are described in Table 76. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R674 (02A2h) Micd Clamp control 3:0 MICD_CLAMP_M ODE [3:0]

0000 MICDET Clamp Mode

0h = Disabled 1h = Active (MICDET1 and MICDET2 are shorted together) 2h = Reserved 3h = Reserved 4h = Active when JD1=0 5h = Active when JD1=1 6h = Active when GP5=0 7h = Active when GP5=1 8h = Active when JD1=0 or GP5=0 9h = Active when JD1=0 or GP5=1 Ah = Active when JD1=1 or GP5=0 Bh = Active when JD1=1 or GP5=1 Ch = Active when JD1=0 and GP5=0 Dh = Active when JD1=0 and GP5=1 Eh = Active when JD1=1 and GP5=0 Fh = Active when JD1=1 and GP5=1 R3096 (0C18h) GP Switch 1 1:0 SW1_MODE [1:0] 00 General Purpose Switch control 00 = Disabled (open) 01 = Enabled (closed) 10 = Enabled when MICDET Clamp is active 11 = Enabled when MICDET Clamp is not active R3413 (0D55h) AOD IRQ Raw Status

3 MICD_CLAMP_S

0 MICDET Clamp status

0 = Clamp not active 1 = Clamp active R3414 (0D56h) Jack detect debounce

3 MICD_CLAMP_D

B

0 MICDET Clamp de-bounce

0 = Disabled 1 = Enabled Table 76 MICDET Clamp and General Purpose Switch control MICROPHONE DETECT The WM8281 microphone detection circuit measures the impedance of an external load connected to one of the MICDET pins. This feature can be used to detect the presence of a microphone, and the status of the associated hookswitch. It can also be used to detect push -button status or the connection of other external accessories. The microphone detection circuit measures the impedance connected to MICDET1 or MICDET2. In the discrete measurement mode (ACCDET_MODE=000), the function reports whether the measured impedance l ies within one of 8 pre -defined levels. In the ADC measurement mode (ACCDET_MODE=111), a more specific result is provided in the form of a 7-bit ADC output. The microphone detection circuit typically uses one of the MICBIAS outputs as a reference. The WM8281 will automatically enable the appropriate MICBIAS when required in order to perform the detection function; this allows the detection function to be supported in low -power standby operating conditions. Note that the MICVDD power domain must be enabled when using the microphone detection function. This power domain is provided using an internal Charge Pump (CP2) and LDO Regulator (LDO2). See “Charge Pumps, Regulators and Voltage Reference” for details of these circuits. To select microphone detection on one of the MICDET pin s, the ACCDET_MODE register must be set to 000 or 111 (depending on the desired measurement mode) . The ACCDET_MODE register is defined in Table 77.

Rev 4.0 209 The WM8281 can only support one headphone or microphone detection function at any time. When the detection function is not in use, it is recommended to set ACCDET_MODE=000. The microphone detection circuit can be enabled on the MICDET1 pin or the MICDET2 pin, selected by the ACCDET_SRC register. The microphone detection circuit uses MICVDD, MICBIAS1, MICBIAS2 or MICBIAS3 as a reference. The applicable source is configured using the MICD_BIAS_SRC register. When ACCDET_MODE is set to 000 or 111 , then Microphone detection is enabled by setting MICD_ENA. When microphone detection is enabled, the WM8281 performs a number of measurements in order to determine the MICDET impedance. The measurement process is repeated at a cyclic rate controlled by MICD_RATE. (The MICD_RATE register selects the delay between completion of one measurement and the start of th e next .) When the microphone detection result has settled, the WM8281 indicates valid data by setting the MICD_VALID bit. When the discrete measurement mode is selected (ACCDET_MODE=000) , the measured impedance is only deemed valid after more than one suc cessive measurement has produced the same result. The MICD_DBTIME register provides control of the de -bounce period; this can be either 2 measurements or 4 measurements. When the microphone detection result has settled (ie. after the applicable de -bounce p eriod), the WM8281 indicates valid data by setting the MICD_VALID bit. The measured impedance is indicated using the MICD_LVL and MICD_STS register bits, as described in Table 77. The MICD_VALID bit, when set, remains asserted for as long as the microphone detection function is enabled (ie. while MICD_ENA = 1). If the detected impedance changes, then the MICD_LVL and MICD_STS fields will change, but the MICD_VALID bit will remain set, indicating valid data at all times. The 8 pre-defined impedance levels (including the ‘no accessory detected’ level) allow detection of a typical microphone and up to 6 push -buttons. Each measurement level can be enabled or disabled independently; this provides flexibility according to the required thresholds, and offers a faster measurement time in some applications. The MICD_LVL_SEL register is described in detail later in this section. Note that the impedance levels quoted in the MICD_LV L description assume that a microphone (475Ω to 30kΩ impedance) is also present on the MICDET pin. The limits quoted in the “ Electrical Characteristics” refer to the c ombined effective impedance on the MICDET pin. Typical external components are described in the “Applications Information” section. When the ADC measurement mode is selected (ACCDET_MODE=111), the detection function must be disabled before the measurement can be read. When the WM8281 indicates valid data (MICD_VALID=1), the detection must be disabled by setting MICD_ENA=0. The ADC measurement mode generates two output results, contained within the MICDET_ADCVAL and MICDET_ADCVAL_DIFF registers. These registers contain the most recent measurement value (MICDET_ADCVAL) and the measurement difference value (MICDET_ADCVAL_DIFF). The difference value indicates the difference between the latest measurement and the previous measurement; this can be used to determine whether the measurement is stable and reliable. Note that the MICDET_ADCVAL and MICDET_ADCVAL_DIFF registers do not follow a linear coding. The appropriate test con dition for accepting the measurement value (or for re -scheduling the measurement) will vary depending on the application requirements, and depending on the expected impedance value. The microphone detection function is an input to the Interrupt control circuit and can be used to trigger an Interrupt event every time an accessory insertion, removal or impedance change is detected. See “Interrupts” for further details. The microphone detection function can also generate a GPIO output, providing an external indication of the microphone detection. This GPIO output is pulsed every time an accessory insertion, removal or impedance change is detected. See “ General Purpose Input / Output ” to configure a GPIO pin for this function. The register fields associated with Microphone Detection (or other accessories) are described in

Table 77. The external circuit configuration is illustrated in Figure 65.

13 ACCDET_SRC 0 Accessory Detect / Headphone

000 Accessory Detect Mode Select

0001 Mic Detect Bias Startup Delay

Rev 4.0 211 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5:4 MICD_BIAS_SRC [1:0]

00 Accessory Detect (MICDET) reference

00 = MICVDD 01 = MICBIAS1 10 = MICBIAS2 11 = MICBIAS3

1 MICD_DBTIME 1 Mic Detect De-bounce

0 = 2 measurements 1 = 4 measurements Only valid when ACCDET_MODE=000.

0 MICD_ENA 0 Mic Detect Enable

0 = Disabled 1 = Enabled R676 (02A4h) Mic Detect 2 7:0 MICD_LVL_SEL [7:0] 1001_ 1111 Mic Detect Level Select (enables Mic/Accessory Detection in specific impedance ranges) [7] = Enable >475 ohm detection [6] = Not used - must be set to 0 [5] = Not used - must be set to 0 [4] = Enable 375 ohm detection [3] = Enable 155 ohm detection [2] = Enable 73 ohm detection [1] = Enable 40 ohm detection [0] = Enable 18 ohm detection Note that the impedance values quoted assume that a microphone (475ohm- 30kohm) is also present on the MICDET pin. Only valid when ACCDET_MODE=000. R677 (02A5h) Mic Detect 3 10:2 MICD_LVL [8:0] 0_0000_ 0000 Mic Detect Level (indicates the measured impedance) [8] = >475 ohm, <30k ohm [7] = Not used [6] = Not used [5] = 375 ohm [4] = 155 ohm [3] = 73 ohm [2] = 40 ohm [1] = 18 ohm [0] = <3 ohm Note that the impedance values quoted assume that a microphone (475ohm- 30kohm) is also present on the MICDET pin. Only valid when ACCDET_MODE=000.

1 MICD_VALID 0 Mic Detect Data Valid

0 = Not Valid 1 = Valid

0 MICD_STS 0 Mic Detect Status

0 = No Mic/Accessory present (impedance is >30k ohm) 1 = Mic/Accessory is present (impedance is <30k ohm) Only valid when ACCDET_MODE=000. R683 02ABh Mic Detect 4 15:8 MICDET_ADCVA L_DIFF [7:0] 00h Mic Detect ADC Level (Difference) Only valid when ACCDET_MODE=111. 6:0 MICDET_ADCVA L [6:0] 00h Mic Detect ADC Level Only valid when ACCDET_MODE=111.

212 Rev 4.0 Table 77 Microphone Detect Control The external connections for the Microphone Detect circuit are illustrated in Figure 65. In typical applications, it can be used to detect a microphone or button press. Note that, when using the Microphone Detect circuit, it is recommended to use one of the Right channel analogue microphone input paths, to ensure best immunity to electrical transients arising from the external accessory. The voltage reference for the microphone detection is configured using the MICD_BIAS_SRC register, as described in Table 77. The microphone detection function will automatically enable the applicable reference when required for MICDET impedance measurement. If the selected reference (MICBIAS1, MICBIAS2 or MICBIAS3) is not already enabled (ie. if MICBn_ENA = 0, where n is 1, 2 or 3 as appropriate), then the applicable MICBIAS source will be enabled for short periods of time only, every time the impedance measurement is scheduled. To allow time for the MICBIAS source to start -up, a time delay is applied before the measur ement is performed; this is configured using the MICD_BIAS_STARTTIME register, as described in Table 77. The MICD_BIAS_STARTTIME register should be set to 16ms or more if MICBn_RATE = 1 (pop -free start-up / shut -down). The MICD_BIAS_STARTTIME register should be set to 0.25ms or more if MICBn_RATE = 0 (fast start-up / shut-down). If the selected reference is not enabled continuously (ie. if MICB n_ENA = 0), then the appli cable MICBIAS discharge bit (MICBn_DISCH) should be set to 0. The MICBIAS sources are configured using the registers described in the “Charge Pumps, Regulators and Voltage Reference” section. MICDET1 Accessory / Button Detect AGND MICDET2 Detection pin selected by ACCDET_SRC (MICDET1 or MICDET2) Microphone/Accessory detection selected by ACCDET_MODE Analogue Input C INnx Microphone Supply selected by MICD_BIAS_SRC (MICVDD, MICBIAS1, MICBIAS2, MICBIAS3) MICBIAS3 MICBIAS2 MICBIAS1 MICVDD LDO2 Regulator External accessories :- 2.2k (+/-2%) MicrophoneHookswitch / button 1button 2 Figure 65 Microphone and Accessory Detect Interface When the discrete measurement mode is selected (ACCDET_MODE=000), the MICD_LVL_SEL [7:0] register bits allow each of the im pedance measurement levels to be enabled or disabled independently. This allows the function to be tailored to the particular application requirements. If one or more bits within the MICD_LVL_SEL register is set to 0, then the corresponding impedance level will be disabled. Any measured impedance which lies in a disabled level will be reported as the next lowest, enabled level. For example, the MICD_LVL_SEL [2] bit enables the detection of impedances around 73 . If MICD_LVL_SEL [2] = 0, then an external imp edance of 73  will not be indicated as 73  but will be indicated as 40; this would be reported in the MICD_LVL register as MICD_LVL [2] = 1. With all measurement levels enabled, the WM8281 can detect the presence of a typical microphone

Rev 4.0 213 and up to 6 push-buttons. The microphone detect function is specifically designed to detect a video accessory (typical 75) load if required. See “Applications Information” for ty pical recommended external components for microphone, video or push-button accessory detection. The accuracy of the microphone detect function is assured whenever the connected load is within the applicable limits specified in the “ Electrical Characteristics ”. It is required that a 2.2k  (2%) resistor must also be connected between MICDET and the selected MICBIAS reference; note that different resistor values will lead to inaccuracy in the impedance measurement. Note that the connection of a microphone will change the measured impedance on the MICDET pin; see “Applications Information” for recommended components for typical applications. The measurement time varies between 100 s and 500s according to the impedance of the external load. A high impedance will be measured faster than a low impedance. The timing of the microphone detect function is illustrated in Figure 66. Two different cases are shown, according to whether MICBIAS n is enabled periodically by the impedance measurement function (MICBn_ENA=0), or is enabled at all times (MICBn_ENA=1). MICBn_ENA=0 : MICBIASn is enabled periodically for measurement function Measurement time (100us to 500us) MICD_RATE (0ms to 512ms; 0.25ms default)MICD_BIAS_STARTTIME (0ms to 512ms; 0.25ms default) time MICBn_ENA=1 : MICBIASn is enabled constantly MICD_RATE (0ms to 512ms; 0.25ms default) time Measurement time (100us to 500us) Figure 66 Microphone and Accessory Detect Timing

214 Rev 4.0 HEADPHONE DETECT The WM8281 headphone detection circuit measures the impedance of an external headphone load. This feature can be used to set different gain levels or to apply other configuration settings according to the type of load connected. Separate monitor pins are provided for headphone detection on the left and right channels of HPOUT1. Headphone detection can be enabled on the HPDETL pin or the HPDETR pin. Under recommended configuration, these pins provide measurement of the HPOUT1L and HPOUTR loads respectively. The headphone detect function can also be enabled on the MICDET1 pin or the M ICDET2 pin. Note that, in this configuration, any MICBIAS output that is connected to the selected MICDET pin must be disabled and floating (MICBn_ENA=0, MICBn_DISCH=0). The applicable headphone detection pin is selected using the ACCDET_MODE register. Whe n MICDETn is selected (ACCDET_MODE=100), the applicable MICDETn pin is determined by the ACCDET_SRC register, as described in Table 80. The WM8281 can only support on e headphone or microphone detection function at any time. When the detection function is not in use, it is recommended to set ACCDET_MODE=000. Headphone detection on the selected channel is commanded by writing a ‘1’ to the HP_POLL register bit. The impedance measurement range is configured using the HP_IMPEDANCE_RANGE register. This register should be set in accordance with the expected load impedance. Note that a number of separate measurements (for different impedance ranges) are typically required in order to determine the load impedance; the recommended control sequence is described below. Note that setting the HP_IMPEDANCE_RANGE register is not required for detection on the MICDETn pins (ACCDET_MODE=100). Note also that the impedance measurement range , and measurement accuracy, in this mode are different to the HPDETL and HPDETR measurement modes. For correct operation, the respective output driver(s) must be disabled when headphone detection is commanded on HPOUT1L or HPOUT1R. The applicable driver(s) must also be configured with additional register settings; the requirements are detailed in Table 78. The HP1L_ENA and HP1R_ENA register bits are defined in Table 61. The other associated register bits are defined in Table 80. Note that, when configuring the HP1x_FLWR, HP1x_SHRTI , HP1x_SHRTO and HP1_TST_CAP_SEL, care is required not to change the value of other bits in the register, which may have changed from the default setting. Accordingly, a ‘read -modify-write’ sequence is required to implement this. The applicable headphone output(s) configuration must be maintained until after the headphone detection has completed. For normal headphone driver operation, the HP1_TST_CAP_SEL register must be restored to its default value. (The other register bits noted in Table 78 will be configured automatically when HPOUT is enabled or disabled.) DESCRIPTION REQUIREMENT HPOUT1L Impedance measurement HP1L_ENA = 0 HP1L_FLWR = 0, HP1L_SHRTI = 0, HP1L_SHRTO = 1 HP1_TST_CAP_SEL = 01 HPOUT1R Impedance measurement HP1R_ENA = 0 HP1R_FLWR = 0, HP1R_SHRTI = 0, HP1R_SHRTO = 1 HP1_TST_CAP_SEL = 01 Note that the output driver(s) must be disabled (HP1x_ENA=0) before setting the other control bits. Table 78 Output Configuration for Headphone Detect When headphone detection is commanded, the WM8281 uses an adjustable current source to determine the connected impedance . A sweep of measurement currents is applied. The rate of this sweep can be adjusted using the HP_CLK_DIV and HP_RATE registers . To avoid audible clicks, the default step size should always be used (HP_RATE = 0). The timing of the current source ramp is also controlled by the HP_HOLDTIME register. It is recommended that the default setting (001b) be used for this parameter.

Rev 4.0 215 The headphone detection process will typically comprise a number of separate measurements (for different impedance ranges). Completion of each measurement is indicated by the HP_DONE register bit. When this bit is set, the measurement result can be read from the HP_DACVAL register, and subsequently decoded as described below. C0 + (C1 × Offset) (HP_DACVAL + 1.5) C2 C3 (1 + (C4 × Gradient)) C5Impedance (Ω) = The associated parameters for decoding the measurement result are defined in Table 79. The applicable values are dependent on the HP_IMPEDANCE_RANGE setting in each case. The ‘Offset’ and ‘Gradient’ values are derived from register fields which are factory-calibrated for each device. PARAMETER HP_IMPEDANCE_ RANGE=00 HP_IMPEDANCE_ RANGE=01 HP_IMPEDANCE_ RANGE=10 HP_IMPEDANCE_ RANGE=11 C0 1.007 1.007 9.696 100.684 C1 -0.0072 -0.0072 -0.0795 -0.9494 C2 4003 7975 7300 7300 C3 69.3 69.6 62.9 63.2 C4 0.0055 0.0055 0.0055 0.0055 C5 0.25 0.25 0.25 0.25 Offset HP_OFFSET_01 + HP_OFFSET_DIFF_00 HP_OFFSET_01 HP_OFFSET_01 + HP_OFFSET_DIFF_10 HP_OFFSET_01 + HP_OFFSET_DIFF_11 Gradient HP_GRADIENT_0X HP_GRADIENT_0X HP_GRADIENT_1X HP_GRADIENT_1X Table 79 Headphone Measurement Decode parameters Note that, to achieve the specified measurement accuracy, the above equation must be calculated to an accuracy of at least 5 decimal places throughout. The impedance measurement result is valid when 169 ≤ HP_DACVAL ≤ 1019. (In case of any contradiction with the HP_IMPEDANCE_RANGE description, the HP_DACVAL validity takes precedence.) If the external impedance is entirely unknown (ie. it could lie in any of the HP_IMPEDANCE_RANGE regions), then it is recommended to test initially with HP_IMPEDANCE_RANGE=00. If the resultant HP_DACVAL is < 169, then the impedance is higher than the selected measurement range, so the test should be scheduled again, after incrementing HP_IMPEDANCE_RANGE. Each measurement is triggered by writing ‘1’ to the HP_POLL bit. Completion of each measurement is indicated by the HP_DONE register bit. Note that, after the HP_DONE bit has been asserted, it will remain asserted until the next measurement has been commanded. A simpler, but less accura te, procedure for headphone impedance measurement is also supported, using the HP_LVL register. When the HP_DONE bit is set, indicating completion of a measurement, the impedance can be read directly from the HP_LVL field, provided that the value lies with in the range of the applicable HP_IMPEDANCE_RANGE setting. Note that, for detection using one of the MICDETn pins, the HP_LVL field is the only supported readback option. The HP_IMPEDANCE_RANGE field is not valid for detection on the MICDETn pins. See Table 80 for further description of the HP_LVL field. The headphone detection function is an input to the Interrupt control circuit and can be used to trigger an Interrupt event on completion of the headphone detection - see “Interrupts”. The headphone detection function can also generate a GPIO output, providing an external indicatio n of the headphone detection. See “ General Purpose Input / Output ” to configure a GPIO pin for this function. The register fields associated with Headphone Detection a re described in Table 80. The external

216 Rev 4.0 circuit configuration is illustrated in Figure 67. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R135 (0087h) HP Detect Calibration 15:14 HP_OFFSET_DIF F_11 [1:0] Headphone Detect Calibration field. Signed integer, -7 to +7. LSB=1. Default value is factory-set per device. Note that HP_OFFSET_DIFF_11 is a 4- bit field, and is split across R135 and R136 register addresses. 13:10 HP_OFFSET_DIF F_10 [3:0] Headphone Detect Calibration field. Signed integer, -7 to +7. LSB=1. Default value is factory-set per device. 9:4 HP_OFFSET_01 [5:0] Headphone Detect Calibration field. Signed integer, -31 to +31. LSB=1. Default value is factory-set per device. 3:0 HP_OFFSET_DIF F_00 [3:0] Headphone Detect Calibration field. Signed integer, -7 to +7. LSB=1. Default value is factory-set per device. R136 (0088h) HP Detect Calibration 15:14 HP_OFFSET_DIF F_11 [3:2] Headphone Detect Calibration field. Signed integer, -7 to +7. LSB=1. Field is split across 2 registers. Default value is factory-set per device. Note that HP_OFFSET_DIFF_11 is a 4- bit field, and is split across R135 and R136 register addresses. 13:7 HP_GRADIENT_ 1X [6:0] Headphone Detect Calibration field. Default value is factory-set per device. 6:0 HP_GRADIENT_ 0X [6:0] Headphone Detect Calibration field. Default value is factory-set per device. R549 (0225h) HP Ctrl 1L

2 HP1L_FLWR 1 HPOUT1L Voltage Follower mode

0 = Disabled 1 = Enabled This bit must be set to 0 when the Headphone Detection function is enabled on HPOUT1L. This bit is configured automatically when HPOUT1L is enabled or disabled.

1 HP1L_SHRTI 1 HPOUT1L Input Clamp

0 = Disabled 1 = Enabled This bit must be set to 0 when the Headphone Detection function is enabled on HPOUT1L. This bit is configured automatically when HPOUT1L is enabled or disabled.

0 HP1L_SHRTO 0 HPOUT1L Output Clamp

0 = Enabled 1 = Disabled This bit must be set to 1 when the Headphone Detection function is enabled on HPOUT1L. This bit is configured automatically when HPOUT1L is enabled or disabled.

Rev 4.0 217 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R550 (0226h) HP Ctrl 1R

2 HP1R_FLWR 1 HPOUT1R Voltage Follower mode

0 = Disabled 1 = Enabled This bit must be set to 0 when the Headphone Detection function is enabled on HPOUT1R. This bit is configured automatically when HPOUT1R is enabled or disabled.

1 HP1R_SHRTI 1 HPOUT1R Input Clamp

0 = Disabled 1 = Enabled This bit must be set to 0 when the Headphone Detection function is enabled on HPOUT1R. This bit is configured automatically when HPOUT1R is enabled or disabled.

0 HP1R_SHRTO 0 HPOUT1R Output Clamp

0 = Enabled 1 = Disabled This bit must be set to 1 when the Headphone Detection function is enabled on HPOUT1R. This bit is configured automatically when HPOUT1R is enabled or disabled. R659 (0293h) Accessory Detect Mode 1 0 = Accessory detect on MICDET1, Headphone ground feedback on HPOUT1FB1 1 = Accessory detect on MICDET2, Headphone ground feedback on HPOUT1FB2 2:0 ACCDET_MODE [2:0]

00 Accessory Detect Mode Select

000 = Microphone detect (MICDETn, discrete mode) 001 = Headphone detect (HPDETL) 010 = Headphone detect (HPDETR) 011 = Reserved 100 = Headphone detect (MICDETn) 101 = Reserved 110 = Reserved 111 = Microphone detect (MICDETn, ADC mode) Note that the MICDETn measurements are implemented on either the MICDET1 or MICDET2 pins, depending on the ACCDET_SRC register bit. R667 (029Bh) Headphone Detect 1 10:9 HP_IMPEDANCE _RANGE [1:0]

00 Headphone Detect Range

00 = 4 ohms to 30 ohms 01 = 8 ohms to 100 ohms 10 = 100 ohms to 1k ohms 11 = 1k ohms to 10k ohms Only valid when ACCDET_MODE=001 or ACCDET_MODE=010.

218 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:5 HP_HOLDTIME [2:0]

001 Headphone Detect Hold Time

(Selects the hold time between ramp up and ramp down of the headphone detect current source. The clock cycle rate is set by HP_CLK_DIV.) 000 = 1 clock cycle 001 = 4 clock cycles 010 = 16 clock cycles 011 = 64 clock cycles 100 = 256 clock cycles 101 = 512 clock cycles 110 = 768 clock cycles 111 =1024 clock cycles 4:3 HP_CLK_DIV [1:0]

01 Headphone Detect Clock Rate

(Selects the clocking rate of the headphone detect adjustable current source.) 00 = 32kHz 01 = 16kHz 10 = 8kHz 11 = 4kHz

1 HP_RATE 0 Headphone Detect Ramp Rate

0 = Normal rate 1 = Fast rate

0 HP_POLL 0 Headphone Detect Enable

Write 1 to start HP Detect function R668 (029Ch) Headphone Detect 2

15 HP_DONE 0 Headphone Detect Status

0 = HP Detect not complete 1 = HP Detect done 14:0 HP_LVL [14:0] 0000h Headphone Detect Level LSB = 0.5ohm 8 = 4ohm or less 9 = 4.5 ohm 10 = 5 ohm 11 = 5.5 ohm 20,000 = 10k ohm or more When ACCDET_MODE=001 or 010, this field is valid from 4ohm to10k ohm. When ACCDET_MODE=100, this field is valid from 400ohm to 6k ohm. Note that, when ACCDET_MODE=001 or 010, the HP_LVL readback is only valid within the range selected by HP_IMPEDANCE_RANGE. If HP_LVL reports a value outside the selected range, then the range should be adjusted and the measurement repeated. A result of 0 ohms may be reported if the measurement is less than the minimum value for the selected range. R669 (029Dh) Headphone Detect Test 9:0 HP_DACVAL [9:0] 000h Headphone Detect Level (Coded as integer, LSB=1. See separate description for full decode information.)

Rev 4.0 219 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1188 (04A4h) HP Test Ctrl 1:0 HP1_TST_CAP_ SEL [1:0]

11 This field must be set to 01 when the

Headphone Detection function is enabled on HPOUTL or HPOUTR. This field must be set to 11 (default) at all other times. Table 80 Headphone Detect Control MICDET1/HPOUT1FB2 Headphone Detect / Impedance measurement Headphone Detect selected by ACCDET_MODE HPDETL HPDETR HPOUT1L HPOUT1R 4.7 4.7 MICDET1/HPOUT1FB2 or HPOUT1FB1/MICDET2 selected by ACCDET_SRC (Note: HPOUT1FB* ground connection close to headset jack) HPOUT1FB1/MICDET2 Figure 67 Headphone Detect Interface The external connections for the Headphone Detect circuit are illustrated in Figure 67. Note that only the HPOUT1L or HPOUT1R headphone outputs should be connected to HPDETL or HPDETR pins - impedance measurement is not supported on HPOUT2L, HPOUT2R, HPOUT3L or HPOUT3R. Note that, where external resistors are connected in series with the headphone load, as illustrated, it is recommended that the HPDET n connection is to the headphone side of the resistors. If the HPDETn connection is made to the WM8281 ‘end’ of these resistors, this will lead to a corresponding offset in the measured impedance. Under default conditions, the measurement time varies between 17ms and 61ms according to the impedance of the external load. A high impedance will be measured faster than a low impedance.

220 Rev 4.0 LOW POWER SLEEP CONFIGURATION The WM8281 supports a low -power ‘Sleep’ mode, where most functions are disabled, and power consumption is minimised. A selectable ‘Wake -Up’ event can be configured to return the device to full operation and/or execute a specific response to the particular Wake-Up condition. A Wake -Up event is triggered via hardware input pin(s); in typical applications, these inputs are associated with jack insert (via the JACKDET analogue input) or external push -button detection (via the GPIO5 digital input). A Wake-Up transition can also be triggered using the LDOENA pin to enable LDO1 (assuming that DCVDD is supplied by LDO1). The WM8281 enters Sleep mode when LDO1 is disabled, causing the DCVDD supply to be removed. The AVDD, DBVDD1, and LDOVDD supplies must be present throughout the Sleep mode duration. Note that it is assumed that DCVDD is supplied by LDO1; see the “ Charge Pumps, Regulators and Voltage Reference” for specific control requirements where DCVDD is not powered from LDO1. SLEEP MODE The WM8281 enters Sleep mode when LDO1 is disabled , causing the DCVDD supply to be removed . (LDO1 can be controlled using the LDO1_ENA register bit, or using the LDOENA pin; both of these controls must be de-asserted to disable the LDO. Note that, under certain circumstances - see “Write Sequence Control ” below - the LDO is controlled by writing to the _T RIG_STS register fields. ) The AVDD, DBVDD1, and LDOVDD supplies must be present throughout the Sleep mode ; under these conditions, and with LDO1 disabled, most of the Digital Core (and control registers) are held in reset. For correct Sleep mode behaviour, the following register configuration is required before entering the Sleep mode:  Write the value A210h to Register R13056 (3300h), and write 050Ch to Register R13057 (3301h). Note that SYSCLK must be enabled when writing to these registers. These register writes only need to be executed once, at any suitable opportunity after Power -Up; it is not necessary to repeat these register writes before each Sleep transition.  Write the value 0Bh to the LDO1_VSEL field in Register R528 (0210h). This register write is required before every Sleep transition, and must be scheduled as the last register write before whichever final action is used to command the WM8281 to Sleep mode . See “Charge Pumps, Regulators and Voltage Reference” for details of the LDO1_VSEL field. Note that it is assumed that DCVDD is supplied by LDO1; see the “ Charge Pumps, Regulators and Voltage Reference” for specific control requirements where DCVDD is not powered from LDO1. The system clocks (SYSCLK, ASYNCCLK) are not required in Sleep mode, and the external clock inputs (MCLKn) may be stopped, except as described below. If de-bounce is enabled on any of the configured Wake -Up signals (JACKDET or GPIO5), then the 32kHz clock must be active during Sleep mode (see “ Clocking and Sample Rates”). The 32kHz clock must be derived from the MCLK2 pin in this case. The 32kHz clock must be configured using CLK_32K_ENA and CLK_32K_SRC before Sleep mode is entered. The MCLK2 frequency limit in Sleep mode (see “ Signal Timing Requirements ”) must be observed before entering Sleep mode, and maintained until after Wake-Up. Selected functions and control registers are maintained via an ‘Always-On’ internal supply domain in Sleep mode. The ‘Always -On’ control registers are listed in Table 81. These registers are maintained (ie. not reset) in Sleep mode. The CLK32K_ENA and CLK_32K_SRC registers are maintained in Sleep mode, but are reset to default values on Wake-Up. The WM8281 can be configured to enable the 32kHz clock (derived from MCLK2) automatically on Wake -Up; this may typically be required in a pplications where the 32kHz clock has been maintained in Sleep mode. To enable the 32kHz clock on Wake -Up, write the value C100h to Register R14202 (337Ah), and write 0041h to Register R14203 (3 37Bh). Note that SYSCLK must be enabled when writing to these registers. Note that the Control Interface is not supported in Sleep mode. Read/Write access to the ‘Always -On’ registers is not possible in Sleep mode.

Rev 4.0 221 REGISTER ADDRESS LABEL REFERENCE 40h WKUP_MICD_CLAMP_FALL See Table 84 WKUP_MICD_CLAMP_RISE WKUP_GP5_FALL WKUP_GP5_RISE WKUP_JD1_FALL WKUP_JD1_RISE 41h WSEQ_ENA_MICD_CLAMP_FAL L See Table 85 WSEQ_ENA_MICD_CLAMP_RIS E WSEQ_ENA_GP5_FALL WSEQ_ENA_GP5_RISE WSEQ_ENA_JD1_FALL WSEQ_ENA_JD1_RISE 66h WSEQ_MICD_CLAMP_RISE_IND EX See “Control Write Sequencer” 67h WSEQ_MICD_CLAMP_FALL_IND EX 68h WSEQ_GP5_RISE_INDEX 69h WSEQ_GP5_FALL_INDEX 6Ah WSEQ_JD1_RISE_INDEX 6Bh WSEQ_JD1_FALL_INDEX 100h CLK_32K_ENA See “Clocking and Sample Rates” See note above. CLK_32K_SRC 210h LDO1_VSEL See “Charge Pumps, Regulators and Voltage Reference” LDO1_DISCH LDO1_ENA 02A2h MICD_CLAMP_MODE See “External Accessory Detection” 02D3h JD1_ENA See “External Accessory Detection” 0C04h GP5_DIR See “General Purpose Input / Output” GP5_PU GP5_PD GP5_POL GP5_OP_CFG GP5_DB GP5_LVL GP5_FN 0C0Fh IRQ_POL See “Interrupts” IRQ_OP_CFG 0C10h GP_DBTIME See “General Purpose Input / Output” 0C18h SW1_MODE 0C20h LDO1ENA_PD See “Charge Pumps, Regulators and Voltage Reference” LDO1ENA_PU MCLK2_PD See “Clocking and Sample Rates” RESET_PU See “Hardware Reset, Software Reset, Wake-Up, and Device ID” RESET_PD 0C39h IRQ_DRV_STR See “Applications Information” GPIO5_DRV_STR 0D0Fh IM_IRQ1 See “Interrupts” 0D1Fh IM_IRQ2 0D50h MICD_CLAMP_FALL_TRIG_STS See Table 83 MICD_CLAMP_RISE_TRIG_STS

222 Rev 4.0 REGISTER ADDRESS LABEL REFERENCE GP5_FALL_TRIG_STS GP5_RISE_TRIG_STS JD1_FALL_TRIG_STS JD1_RISE_TRIG_STS 0D51h MICD_CLAMP_FALL_EINT1 See “Interrupts” MICD_CLAMP_RISE_EINT1 GP5_FALL_EINT1 GP5_RISE_EINT1 JD1_FALL_EINT1 JD1_RISE_EINT1 0D52h MICD_CLAMP_FALL_EINT2 See “Interrupts” MICD_CLAMP_RISE_EINT2 GP5_FALL_EINT2 GP5_RISE_EINT2 JD1_FALL_EINT2 JD1_RISE_EINT2 0D53h IM_MICD_CLAMP_FALL_EINT1 See “Interrupts” IM_MICD_CLAMP_RISE_EINT1 IM_GP5_FALL_EINT1 IM_GP5_RISE_EINT1 IM_JD1_FALL_EINT1 IM_JD1_RISE_EINT1 0D54h IM_MICD_CLAMP_FALL_EINT2 See “Interrupts” IM_MICD_CLAMP_RISE_EINT2 IM_GP5_FALL_EINT2 IM_GP5_RISE_EINT2 IM_JD1_FALL_EINT2 IM_JD1_RISE_EINT2 0D56h MICD_CLAMP_DB See “External Accessory Detection” JD1_DB 3000h to 31FFh WSEQ_DATA_WIDTHn See “Control Write Sequencer” WSEQ_ADDRn WSEQ_DELAYn WSEQ_DATA_STARTn WSEQ_DATAn Table 81 Sleep Mode ‘Always-On’ Control Registers The ‘Always-On’ digital input / output pins are listed in Table 82. All other digital input pins will have no effect in Sleep mode. The IRQ¯¯¯ output is normally de-asserted in Sleep mode. Note that, in Sleep mode, the IRQ¯¯¯ output can only be asserted in response to the JD1 or GP5 control signals (these described in the following section). If the IRQ¯¯¯ output is asse rted in Sleep mode, it can only be de-asserted after a Wake-Up transition. PIN NAME DESCRIPTION REFERENCE LDOENA Enable pin for LDO1 See “Charge Pumps, Regulators and Voltage Reference” RESET¯¯¯¯¯¯ Digital Reset input (active low) See “Hardware Reset, Software Reset, Wake-Up, and Device ID” MCLK2 Master clock 2 See “Clocking and Sample Rates” GPIO5 General Purpose pin GPIO5 See “General Purpose Input / Output” IRQ¯¯¯ Interrupt Request (IRQ) output See “Interrupts” Table 82 Sleep Mode ‘Always-On’ Digital Input Pins

Rev 4.0 223 A Wake-Up transition is triggered using the JD1 or GP5 control signals (defined below). It is assumed that DCVDD is supplied by LDO1. The AVDD, DBVDD1 and LDOVDD supplies must be present throughout the Sleep mode duration . See “ Charge Pump s, Regulators and Voltage Reference” for specific control requirements where DCVDD is not powered from LDO1. Note that a logic ‘1’ applied to the LDOENA pin will also cause a Wake -Up transition. In this event, however, the configurable Wake-Up events (described below) are not applicable. SLEEP CONTROL SIGNALS - JD1, GP5, MICDET CLAMP The internal control signals JD1 and GP5 are provided to support the low -power Sleep mode. The MICDET Clamp status is controlled by a selectable logic function, derived from JD1 and/or GP5. A rising or falling edge of these signals can be used to trigger a Wake-Up transition (ie. exit from Sleep mode). The JD1, GP5 and MICDET Clamp status signals can also be used to trigger the Control Write Sequencer and/or the Interrupt Controller. Note that it is possible to enable more than one response from these contr ol signals. For example, a particular edge transition could trigger a Wake-Up transition, and also a Control Write Sequence. The JD1, GP5 and MICDET Clamp status signals are described in this section. The Wake -Up, Write Sequencer, and Interrupt actions are described in the sections that follow. The JD1 signal is derived from the Jack Detect function (see “ External Accessory Detection ”). This input can be used to trigger Wake-Up or other actions in response to a jack insertion or jack removal detection. When the JD1 signal is enabled, it indicates the status of the JACKDET input pin. See Table 75 for details of the associated control registers. The GP5 signal is derived from the GPIO5 input pin (see “General Purpose Input / Output”). This input can be used to trigger Wake -Up or other actions in response to a logic level input detected on the GPIO5 pin. When using the GP5 signal, the GPIO5 pin must be configured as a GPIO input (GP5_DIR=1, GP5_FN=01h). An internal pull-up or pull-down resistor may be enabled on the GPIO5 pin if required. The GPIO pin control registers are defined in Table 86. The MICDET Clamp status is controlled by the JD1 and/or GP5 signals (see “ External Accessory Detection”). The configurable logic provides flexibility in selecting the appropriate condi tions for activating the MICDET Clamp. The clamp status can be used to trigger Wake -Up or other actions in response to a jack insertion or jack removal detection. The MICDET Clamp function is configured using the MICD_CLAMP_MODE register, as described in Table 76. Whenever a rising or falling edge is detected on JD1, GP5 or MICDET Clamp status, the WM8281 will assert the respective trigger status (_TRIG_STS) bit. The trigger status bits are latching fields and, once they are set, they are not reset until a ‘1’ is written to the respective register bit(s). The JD1, GP5 and MICDET Clamp trigger status bits are described in Table 83. The trigger status bits can be used to control Wake -Up and Write Sequencer actions. The JD1, GP5 and MICDET Clamp signals are inputs to the Interrupt Controller. Each of these functions is d escribed in the following sections.

224 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3408 (0D50h) AOD wkup and trig

7 MICD_CLAMP_FALL_

TRIG_STS

0 MICDET Clamp Trigger Status

(Falling edge triggered) Note: Cleared when a ‘1’ is written

6 MICD_CLAMP_RISE_

TRIG_STS (Rising edge triggered) Note: Cleared when a ‘1’ is written

5 GP5_FALL_TRIG_STS 0 GP5 Trigger Status

(Falling edge triggered) Note: Cleared when a ‘1’ is written

4 GP5_RISE_TRIG_STS 0 GP5 Trigger Status

(Rising edge triggered) Note: Cleared when a ‘1’ is written

3 JD1_FALL_TRIG_STS 0 JD1 Trigger Status

(Falling edge triggered) Note: Cleared when a ‘1’ is written

2 JD1_RISE_TRIG_STS 0 JD1 Trigger Status

(Rising edge triggered) Note: Cleared when a ‘1’ is written Table 83 JD1, GP5 and MICDET Clamp Trigger Status Registers Note that the de -bounce function on all inputs (including JD1, GP5 and MICDET Clamp status) use the 32kHz clock (see “ Clocking and Sample Rates ”). The 32kHz clock must be enabled whenever input de-bounce functions are required. Note that the MCLK2 input pin is on the ‘Always -On’ domain, and is supported in Sleep m ode. (MCLK1 input is not supported in Sleep mode.) If input de -bounce is enabled in Sleep mode, the 32kHz clock must use MCLK2 (direct) input as its source (CLK_32K_SRC = 01). WAKE-UP TRANSITION A Wake -Up transition (exit from Sleep) can be associated wit h any of the JD1, GP5 or MICDET Clamp trigger status bits. This is selected using the register bits described in Table 84. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R64 (0040h) Wake Control

7 WKUP_MICD_CLAMP

_FALL

0 MICDET Clamp (Falling) Wake-Up

0 = Disabled 1 = Enabled

6 WKUP_MICD_CLAMP

_RISE

0 MICDET Clamp (Rising) Wake-Up

0 = Disabled 1 = Enabled

5 WKUP_GP5_FALL 0 GP5 (Falling) Wake-Up Select

0 = Disabled 1 = Enabled

4 WKUP_GP5_RISE 0 GP5 (Rising) Wake-Up Select

0 = Disabled 1 = Enabled

3 WKUP_JD1_FALL 0 JD1 (Falling) Wake-Up Select

0 = Disabled 1 = Enabled

2 WKUP_JD1_RISE 0 JD1 (Rising) Wake-Up Select

0 = Disabled 1 = Enabled Table 84 JD1, GP5 and MICDET Clamp Wake-Up Control Registers

Rev 4.0 225 When a valid ‘Wake-Up’ event is detected, the WM8281 will enable LDO1 (and DCVDD), and a user - configurable Boot Sequence is executed (see “ Hardware Reset, S oftware Reset , Wake -Up, and Device ID”). Note that the trigger status (_TRIG_STS) bits are latching fields. Care is required when resetting these bits, to ensure the intended device behaviour - resetting the _TRIG_STS register(s) may cause LDO1 (and DCVDD) to be disabled. For normal device operation following a ‘Wake -Up’ transition, the LDO1_ENA register must be set (or the LDOENA pin asserted) before the _TRIG_STS bit(s) are reset. (Note that further options are described in the next section.) For recommended use of the Sleep / Wake -Up functions, it is assumed that DCVDD is powered from the output of LDO1 (see “Charge Pumps, Regulators and Voltage Reference”). If DCVDD is powered externally (not from LDO1), then the JD1, GP5 and MICDET Clamp inputs cannot trigger a Wake -Up transition directly; a Wake -Up transition will only occur by re -application of DCVDD. In this configuration, the JD1, GP5 or MICDET Clamp inputs can provide a signal to the host processor, via the IRQ¯¯¯ output; if a Wake -Up transition is required, this can be implemented by the host processor controlling the DCVDD supply. If DCVDD is powered externally, then the WKUP_* control bits described in Table 84 must be held at 0 at all times. WRITE SEQUENCE CONTROL A Control Write Seq uence can be associated with any of the JD1, GP5 or MICDET Clamp trigger status bits. This is selected using the register bits described in Table 85. Note that the JD1 , GP5 and MICDET Clamp trigger status bits can be used to trigger the Control Write Sequencer at any time. This feature may be used during normal operation, or immediately following a Wake-Up transition. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R65 (0041h) Sequence Control

7 WSEQ_ENA_MICD_C

LAMP_FALL

0 MICDET Clamp (Falling) Write

0 = Disabled 1 = Enabled

6 WSEQ_ENA_MICD_C

LAMP_RISE

0 MICDET Clamp (Rising) Write

0 = Disabled 1 = Enabled

5 WSEQ_ENA_GP5_FA

0 GP5 (Falling) Write Sequencer

0 = Disabled 1 = Enabled

4 WSEQ_ENA_GP5_RIS

E

0 GP5 (Rising) Write Sequencer

0 = Disabled 1 = Enabled

3 WSEQ_ENA_JD1_FAL

L

0 JD1 (Falling) Write Sequencer

0 = Disabled 1 = Enabled

2 WSEQ_ENA_JD1_RIS

E

0 JD1 (Rising) Write Sequencer

0 = Disabled 1 = Enabled Table 85 JD1, GP5 and MICDET Clamp Write Sequencer Control Registers

226 Rev 4.0 When a valid ‘Write Sequencer’ control event is detected, the respective control sequence will be scheduled. See “Control Write Sequencer” for further details. Note that the trigger status (_TRIG_STS) bits are latching fields. Care is requ ired when resetting these bits, to ensure the intended device behaviour - resetting the _TRIG_STS register(s) may cause LDO1 (and DCVDD) to be disabled. A valid clock (SYSCLK) must be enabled whenever a Control Write Sequence is scheduled. If the JD1, GP5 or MICDET Clamp trigger status bits are associated with the Control Write Sequencer (using the register bits in Table 85) and also configured as Wake -Up events (using the register bits in Table 84), then the Boot Sequence must be programmed to configure and enable SYSCLK. (Note that the default SYSCLK frequency must be used in this case.) The Boot Sequence (see “ Hardware Reset, S oftware Reset, Wake-Up, and Device ID ”) is scheduled as part of the Wake -Up transitio n, and provides the capability to configure SYSCLK (and other register settings) prior to the Control Write Sequencer being triggered. Note that, if the Control Write Sequencer is triggered during normal operation, then SYSCLK will typically be already available, and no additional requirements will apply. To return to Sleep mode following a Wake -Up / Write Sequence, the last step of the control sequence must be to write ‘1’ to the applicable trigger status bit(s). The _TRIG_STS bit(s) will be reset, LDO1 will be disabled, and the WM8281 will be in Sleep mode. (The LDO1_ENA bit must be set to 0, and the LDOENA pin must not be asserted.) To remain ‘On’ at the end of a Wake -up / Write Sequence, the control sequence must write ‘1’ to the LDO1_ENA bit before resetting the trigger status bit(s). Alternatively, the host processor should assert the LDOENA pin before resetting the trigger status bit(s). When the Control Write Sequencer is triggered during normal operation, it can be programmed to select the Sleep mode by writing ‘0’ to the LDO1_ENA bit. (The LDOENA pin must not be asserted.) See “Charge Pumps, Regulators and Voltage Reference” for details of the LDO1_ENA control bit. INTERRUPT CONTROL An Interrupt Request (IRQ) event can be associated with the JD1, GP5 or MICDET Clamp signals. Separate ‘mask’ bits are provided to enable IRQ events on the rising and/or falling edges of each signal. See “Interrupts” for further details.

Rev 4.0 227 GENERAL PURPOSE INPUT / OUTPUT The WM8281 provides a number of GPIO functions to enable interfacing and detection of external hardware and to provide logic outputs to other devices. The GPIO input functions can be used to generate an Interrupt (IRQ) event. The GPIO and Interrupt circuits support the following functions:  Digital audio interface function (AIFnTXLRCLK)  Logic input / Button detect (GPIO input)  Logic ‘1’ and logic ‘0’ output (GPIO output)  Interrupt (IRQ) status output  DSP Status Flag (DSP IRQn) and RAM status output  Clock output  Frequency Locked Loop (FLL) status output  Frequency Locked Loop (FLL) Clock output  Pulse Width Modulation (PWM) Signal output  Headphone Detection status output  Microphone / Accessory Detection status output  Headphone Enable status output  Boot Sequence status output  Asynchronous Sample Rate Converter (ASRC) Lock status and Configuration Error output  Isochronous Sample Rate Converter (ISRC) Configuration Error output  Over-Temperature, Short Circuit Protection, and Speaker Shutdown status output  Dynamic Range Control (DRC) status output  Control Write Sequencer status output  Control Interface Error status output  Clocking Error status output Note that the GPIO pins are referenced to different power domains (DBVDD1, DBVDD2 or DBVDD3), as noted in the “Pin Description” section. The GPIO4 function shares the same pin as CIF1MISO (see “ Control Interface”). The GPIO4 function is enabled by setting SPI_GPIO = 0, as described in Table 113. In addition to the functions described in this section, th e GPIO5 pin can be configured as an input to the Control Write Sequencer (see “ Control Write Sequencer ”). See also Table 85 for details of the associated register control fields. The GPIO5 pin is one of the ‘Always On’ digital input / output pins and can be used as a ‘Wake -Up’ input in the low -power ‘Sleep’ mode. The GPIO5 pin can also be used as an input to the MICDET Clamp function, supporting additional functionality relating to jack insertion or jack removal events See “Low Power Sleep Configuration” for further details. The WM8281 also incorporates a General Purpose Switch feature, which can be used as a controllable analogue switch; details of this are provided at the end of this “ General Purpose Input / Output” section.

228 Rev 4.0 GPIO CONTROL For each GPIO, the selected function is determined by the GP n_FN field, where n identifies the GPIO pin (1, 2, 3, 4 or 5). The pin direction, set by GP n_DIR, must be set according to function selected by GPn_FN. When a pin is configured as a GPIO input (GP n_DIR = 1, GP n_FN = 01h), the logic level at the pin can be read from the respective GP n_LVL bit. Note that GP n_LVL is not affected by the GP n_POL bit. A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin by setting the respective GP n_DB bit. The de-bounce circuit uses the 32kHz clock, which must be enabled whenever input de -bounce functions are required. The de -bounce time is configurable using the GP_DBTIME register. See “ Clocking and Sample Rates ” for further details of the WM8281 clocking configuration. Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt event. An interrupt event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling. Integrated pull -up and pull -down resistors are provided on each of the GPIO pins; these can be configured independently using the GPn_PU and GPn_PD fields. Note that, if GP n_PU and GPn_PD are both set for any GPIO pin, then the pull-up and pull-down will be disabled. When a pin is configured as a GPIO output (GPn_DIR = 0, GP n_FN = 01h), its level can be set to logic 0 or logic 1 using the GP n_LVL field. Note that the GPn_LVL registers are ‘write only’ when the respective GPIO pin is configured as an output. When a pin is configured as an output (GP n_DIR = 0), the polarity can be inverted using the GPn_POL bit. When GPn_POL = 1, then the selected output function is inverted. In th e case of Logic Level output (GP n_FN = 01h), the external output will be the opposite logic level to GP n_LVL when GPn_POL = 1. A GPIO output can be either CMOS driven or Open Drain. This is selected on each pin using the respective GPn_OP_CFG bit. The register fields that control the GPIO pins are described in Table 86.

Rev 4.0 229 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3072 (0C00h) GPIO1 CTRL to R3076 (0C04h) GPIO5 CTRL

15 GPn_DIR 1 GPIOn Pin Direction

0 = Output 1 = Input

14 GPn_PU 0 GPIOn Pull-Up Enable

0 = Disabled 1 = Enabled

13 GPn_PD 1 GPIOn Pull-Down Enable

0 = Disabled 1 = Enabled 11 GPn_LVL 0 GPIOn level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level. For output functions only, when GPn_POL is set, the register is the opposite logic level to the external pin. Note that the GPn_LVL register is ‘write only’ when GPn_DIR=0.

10 GPn_POL 0 GPIOn Output Polarity Select

0 = Non-inverted (Active High) 1 = Inverted (Active Low)

9 GPn_OP_CFG 0 GPIOn Output Configuration

0 = CMOS 1 = Open Drain

8 GPn_DB 1 GPIOn Input De-bounce

0 = Disabled 1 = Enabled 6:0 GPn_FN [6:0] 01h GPIOn Pin Function (see Table 87 or Table 88 for details) R3088 (0C10h) GPIO Debounce Config 15:12 GP_DBTIME [3:0]

0001 GPIO Input de-bounce time

0h = 100us 1h = 1.5ms 2h = 3ms 3h = 6ms 4h = 12ms 5h = 24ms 6h = 48ms 7h = 96ms 8h = 192ms 9h = 384ms Ah = 768ms Bh to Fh = Reserved Note: n is a number (1, 2, 3, 4 or 5) that identifies the individual GPIO. Table 86 GPIO Control

230 Rev 4.0 GPIO FUNCTION SELECT The available GPIO functions for GPIO pins 1, 2, 3 and 4 are described in Table 87. A subset of these functions is available for GPIO5, as described in Table 88. The function of each GPIO is set using the GP n_FN register, where n identifies the GPIO pin ( 1, 2, 3, 4 or 5). Note that the respective GP n_DIR must also be set according to whether the func tion is an input or output. GPn_FN DESCRIPTION COMMENTS 00h GPIO1 - AIF1TXLRCLK GPIO2 - AIF2TXLRCLK GPIO3 - AIF3TXLRCLK GPIO4 - Reserved Alternate Audio Interface connections for AIF1, AIF2 and AIF3 01h Button detect input / Logic level output GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL. GPn_DIR = 1: Button detect or logic level input. 02h IRQ1 Output Interrupt (IRQ1) output 0 = IRQ1 not asserted 1 = IRQ1 asserted 03h IRQ2 Output Interrupt (IRQ2) output 0 = IRQ2 not asserted 1 = IRQ2 asserted 04h OPCLK Clock Output Configurable clock output derived from SYSCLK 05h FLL1 Clock Clock output from FLL1 06h FLL2 Clock Clock output from FLL2 08h PWM1 Output Configurable Pulse Width Modulation output PWM1 09h PWM2 Output Configurable Pulse Width Modulation output PWM2 0Ah SYSCLK Underclocked Error Indicates that an unsupported clocking configuration has been attempted 0 = Normal 1 = SYSCLK underclocking error 0Bh ASYNCCLK Underclocked Error Indicates that an unsupported clocking configuration has been attempted 0 = Normal 1 = ASYNCCLK underclocking error 0Ch FLL1 Lock Indicates FLL1 Lock status 0 = Not locked 1 = Locked 0Dh FLL2 Lock Indicates FLL2 Lock status 0 = Not locked 1 = Locked 0Fh FLL1 Clock OK Indicates FLL1 Clock OK status 0 = FLL1 Clock output is not active 1 = FLL1 Clock output is active 10h FLL2 Clock OK Indicates FLL2 Clock OK status 0 = FLL2 Clock output is not active 1 = FLL2 Clock output is active 12h Headphone detect Indicates Headphone Detection status 0 = Headphone Detect not complete 1 = Headphone Detect complete 13h Microphone detect Microphone Detect (MICDET accessory) IRQ output A single 31s pulse is output whenever an accessory insertion, removal or impedance change is detected.

Rev 4.0 231 GPn_FN DESCRIPTION COMMENTS 15h Write Sequencer status Indicates Write Sequencer status A short pulse is output when the Write Sequencer has completed all scheduled sequences. 16h Control Interface Address Error Indicates Control Interface Address error 0 = Normal 1 = Control Interface Address error 17h ADC Overflow Error Indicates an overflow condition in the input signal paths 0 = Normal 1 = ADC overflow error 18h ADC CIC Error Indicates a CIC error condition in the input signal paths 0 = Normal 1 = ADC CIC error 19h ADC FIFO Error Indicates a FIFO error condition in the input signal paths 0 = Normal 1 = ADC FIFO error 1Ah ASRC1 Lock Indicates ASRC1 Lock status 0 = Not locked 1 = Locked 1Bh ASRC2 Lock Indicates ASRC2 Lock status 0 = Not locked 1 = Locked 1Ch ASRC Configuration Error Indicates ASRC configuration error 0 = ASRC configuration OK 1 = ASRC configuration error 1Dh DRC1 Signal Detect Indicates DRC1 Signal Detect status 0 = Signal threshold not exceeded 1 = Signal threshold exceeded 1Eh DRC1 Anti-Clip Active Indicates DRC1 Anti-Clip status 0 = Anti-Clip is not active 1 = Anti-Clip is active 1Fh DRC1 Decay Active Indicates DRC1 Decay status 0 = Decay is not active 1 = Decay is active 20h DRC1 Noise Gate Active Indicates DRC1 Noise Gate status 0 = Noise Gate is not active 1 = Noise Gate is active 21h DRC1 Quick Release Active Indicates DRC1 Quick Release status 0 = Quick Release is not active 1 = Quick Release is active 22h DRC2 Signal Detect Indicates DRC2 Signal Detect status 0 = Signal threshold not exceeded 1 = Signal threshold exceeded 23h DRC2 Anti-Clip Active Indicates DRC2 Anti-Clip status 0 = Anti-Clip is not active 1 = Anti-Clip is active 24h DRC2 Decaying Indicates DRC2 Decay status 0 = Decay is not active 1 = Decay is active 25h DRC2 Noise Gate Active Indicates DRC2 Noise Gate status 0 = Noise Gate is not active 1 = Noise Gate is active 26h DRC2 Quick Release Active Indicates DRC2 Quick Release status 0 = Quick Release is not active 1 = Quick Release is active 27h Mixer Dropped Sample Error Indicates a dropped sample in the digital core mixers 0 = Normal 1 = Mixer dropped sample error

232 Rev 4.0 GPn_FN DESCRIPTION COMMENTS 2Bh Speaker Overheat Shutdown Indicates Shutdown Temperature status 0 = Temperature is below shutdown level 1 = Temperature is above shutdown level 2Ch Speaker Overheat Warning Indicates Warning Temperature status 0 = Temperature is below warning level 1 = Temperature is above warning level 2Dh Underclocked Error Indicates insufficient SYSCLK or ASYNCCLK cycles for one or more of the selected signal paths or signal processing functions. Increasing the SYSCLK or ASYNCCLK frequency (as applicable) should allow the selected configuration to be supported. 0 = Normal 1 = Underclocked error 2Eh Overclocked Error Indicates that an unsupported device configuration has been attempted, as the clocking requirements of the requested configuration exceed the device limits. 0 = Normal 1 = Overclocked error 2Fh HP1L Status HPOUT1L Enable Status A short pulse is output when the HPOUT1L Enable control sequence has completed. 30h HP1R Status HPOUT1R Enable Status A short pulse is output when the HPOUT1R Enable control sequence has completed. 31h HP2L Status HPOUT2L Enable Status A short pulse is output when the HPOUT2L Enable control sequence has completed. 32h HP2R Status HPOUT2R Enable Status A short pulse is output when the HPOUT2R Enable control sequence has completed. 33h HP3L Status HPOUT3L Enable Status A short pulse is output when the HPOUT3L Enable control sequence has completed. 34h HP3R Status HPOUT3R Enable Status A short pulse is output when the HPOUT3R Enable control sequence has completed. 35h DSP IRQ1 Flag DSP Status flag (DSP_IRQ1) output 0 = DSP_IRQ1 not asserted 1 = DSP_IRQ1 asserted 36h DSP IRQ2 Flag DSP Status flag (DSP_IRQ2) output 0 = DSP_IRQ2 not asserted 1 = DSP_IRQ2 asserted 37h DSP IRQ3 Flag DSP Status flag (DSP_IRQ3) output 0 = DSP_IRQ3 not asserted 1 = DSP_IRQ3 asserted 38h DSP IRQ4 Flag DSP Status flag (DSP_IRQ4) output 0 = DSP_IRQ4 not asserted 1 = DSP_IRQ4 asserted 39h DSP IRQ5 Flag DSP Status flag (DSP_IRQ5) output 0 = DSP_IRQ5 not asserted 1 = DSP_IRQ5 asserted 3Ah DSP IRQ6 Flag DSP Status flag (DSP_IRQ6) output 0 = DSP_IRQ6 not asserted 1 = DSP_IRQ6 asserted 3Bh DSP IRQ7 Flag DSP Status flag (DSP_IRQ7) output 0 = DSP_IRQ6 not asserted 1 = DSP_IRQ6 asserted

Rev 4.0 233 GPn_FN DESCRIPTION COMMENTS 3Ch DSP IRQ8 Flag DSP Status flag (DSP_IRQ8) output 0 = DSP_IRQ6 not asserted 1 = DSP_IRQ6 asserted 3Dh OPCLK Async Clock Output Configurable clock output derived from ASYNCCLK 44h Boot Done Boot Status A short pulse is output when the Boot Sequence has completed. 45h DSP1 RAM Ready DSP1 RAM Status 0 = Not ready 1 = Ready 46h DSP2 RAM Ready DSP2 RAM Status 0 = Not ready 1 = Ready 47h DSP3 RAM Ready DSP3 RAM Status 0 = Not ready 1 = Ready 48h DSP4 RAM Ready DSP4 RAM Status 0 = Not ready 1 = Ready 4Bh SYSCLK_ENA Status SYSCLK_ENA Status 0 = SYSCLK_ENA is enabled 1 = SYSCLK_ENA is disabled 4Ch ASYNC_CLK_ENA Status ASYNC_CLK_ENA Status 0 = ASYNC_CLK_ENA is enabled 1 = ASYNC_CLK_ENA is disabled 4Dh ISRC1 Configuration Error Indicates ISRC1 configuration error 0 = ISRC configuration OK 1 = ISRC configuration error 4Eh ISRC2 Configuration Error Indicates ISRC2 configuration error 0 = ISRC configuration OK 1 = ISRC configuration error 4Fh ISRC3 Configuration Error Indicates ISRC3 configuration error 0 = ISRC configuration OK 1 = ISRC configuration error 53h HPOUT1L Short Circuit Status (Negative side) HPOUT1L Short Circuit status 0 = Normal 1 = Short Circuit detected 54h HPOUT1R Short Circuit Status (Negative side) HPOUT1R Short Circuit status 0 = Normal 1 = Short Circuit detected 55h HPOUT1L Short Circuit Status (Positive side) HPOUT1L Short Circuit status 0 = Normal 1 = Short Circuit detected 56h HPOUT1R Short Circuit Status (Positive side) HPOUT1R Short Circuit status 0 = Normal 1 = Short Circuit detected 57h HPOUT2L Short Circuit Status (Negative side) HPOUT2L Short Circuit status 0 = Normal 1 = Short Circuit detected 58h HPOUT2R Short Circuit Status (Negative side) HPOUT2R Short Circuit status 0 = Normal 1 = Short Circuit detected 59h HPOUT2L Short Circuit Status (Positive side) HPOUT2L Short Circuit status 0 = Normal 1 = Short Circuit detected 5Ah HPOUT2R Short Circuit HPOUT2R Short Circuit status

234 Rev 4.0 GPn_FN DESCRIPTION COMMENTS Status (Positive side) 0 = Normal 1 = Short Circuit detected 5Bh HPOUT3L Short Circuit Status (Negative side) HPOUT3L Short Circuit status 0 = Normal 1 = Short Circuit detected 5Ch HPOUT3R Short Circuit Status (Negative side) HPOUT3R Short Circuit status 0 = Normal 1 = Short Circuit detected 5Dh HPOUT3L Short Circuit Status (Positive side) HPOUT3L Short Circuit status 0 = Normal 1 = Short Circuit detected 5Eh HPOUT3R Short Circuit Status (Positive side) HPOUT3R Short Circuit status 0 = Normal 1 = Short Circuit detected 5Fh SPKOUTL Short Circuit Status SPKOUTL Short Circuit status 0 = Normal 1 = Short Circuit detected 60h SPKOUTR Short Circuit Status SPKOUTR Short Circuit status 0 = Normal 1 = Short Circuit detected 61h Speaker Shutdown Status Speaker Shutdown Status 0 = Normal 1 = Speaker Shutdown completed (due to Overheat Temperature or Short Circuit condition) Table 87 GPIO Function Select (GPIO1, GPIO2, GPIO3, GPIO4) GPn_FN DESCRIPTION COMMENTS 00h Reserved 01h Button detect input / Logic level output GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL. GPn_DIR = 1: Button detect or logic level input. 02h IRQ1 Output Interrupt (IRQ1) output 0 = IRQ1 not asserted 1 = IRQ1 asserted 03h IRQ2 Output Interrupt (IRQ2) output 0 = IRQ2 not asserted 1 = IRQ2 asserted 04h OPCLK Clock Output Configurable clock output derived from SYSCLK 05h FLL1 Clock Clock output from FLL1 06h FLL2 Clock Clock output from FLL2 07h Reserved 08h PWM1 Output Configurable Pulse Width Modulation output PWM1 09h PWM2 Output Configurable Pulse Width Modulation output PWM2 3Dh OPCLK Async Clock Output Configurable clock output derived from ASYNCCLK Table 88 GPIO Function Select (GPIO5)

Rev 4.0 235 DIGITAL AUDIO INTERFACE FUNCTION (AIFnTXLRCLK) GPn_FN = 00h. The WM8281 provides three digital audio interfaces (AIF1, AIF2 and AIF3). Under default conditions, the input (RX) and output (TX) paths of each interface use the respective AIFnRXLRCLK signal as the frame synchronisation clock. If desired, the outpu t (TX) interface can be configured to use a separate frame clock, AIFnTXLRCLK, using the AIFnTX_LRCLK_SRC registers as described in “Digital Audio Interface Control”. The AIFnTXLRCLK function is selected on the respective GPIO pin by setting the GPIO registers as described in “GPIO Control”. BUTTON DETECT (GPIO INPUT) GPn_FN = 01h. Button detect functionality can be selected on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. The same functionality can be used to support a Jack Detect input function. It is recommended to enable the GPIO input de -bounce feature when using GPIOs as but ton input or Jack Detect input. The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable de-bounce controls. Note that GPn_LVL is not affected by the GPn_POL bit. The de -bounced GPIO signals are also inputs to the Interrupt control circuit. An interrupt event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bits are latched once set; it can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) GPn_FN = 01h. The WM8281 can be programmed to drive a logic high or logic low level on a GPIO pin by selecting the “GPIO Output” function as described in “GPIO Control”. The output logic level is selected using the respective GP n_LVL bit. Note that the GPn_LVL registers are ‘write only’ when the respective GPIO pin is configured as an output. The polarity of the GPIO output can be inverted using the GP n_POL registers. If GP n_POL=1, then the external output will be the opposite logic level to GPn_LVL. INTERRUPT (IRQ) STATUS OUTPUT GPn_FN = 02h, 03h. The WM8281 has an Interrupt Controller which can be used to indicate when any selected Interrupt events occur. An interrupt can be generated by any of the events described throughout the GPIO function definition above . Individual interrupts may be masked in order to configure the Interrupt as required. See “Interrupts” for further details. The Interrupt Controller supports two separate Interrupt Request (IRQ) outputs. The IRQ1 or IRQ2 status may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. Note that the IRQ1 status is output on the IRQ¯¯¯ pin at all times.

236 Rev 4.0 DSP STATUS FLAG (DSP IRQn) OUTPUT GPn_FN = 35h, 36h, 37h, 38h, 39h, 3A, 3Bh, 3Ch, 45h, 46h, 47h, 48h. The WM8281 supports up to eight DSP Status flags as outputs from the DSP blocks. These are configurable within the DSP to provide external indication of the required function(s). Status flags indicating the DSPn RAM status (where ‘n’ is 1, 2, 3 or 4) are also suppo rted. See “Digital Core” for more details of the DSP blocks. The DSP Status and DSP RAM Ready flags may be output directly on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. The DSP Status and DSP RAM Ready outputs are described in Table 89. The DSP Status flags are inputs to the Interrupt Controller circuit. An interrupt event is triggered on the rising edge of the DSP Status (DSP_IRQn) flags or DSP RAM Ready flags . The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling. GPN_FN DESCRIPTION COMMENTS 35h DSP Status (DSP_IRQ1) External indication of DSP_IRQ1_STS 36h DSP Status (DSP_IRQ2) External indication of DSP_IRQ2_STS 37h DSP Status (DSP_IRQ3) External indication of DSP_IRQ3_STS 38h DSP Status (DSP_IRQ4) External indication of DSP_IRQ4_STS 39h DSP Status (DSP_IRQ5) External indication of DSP_IRQ5_STS 3Ah DSP Status (DSP_IRQ6) External indication of DSP_IRQ6_STS 3Bh DSP Status (DSP_IRQ7) External indication of DSP_IRQ7_STS 3Ch DSP Status (DSP_IRQ8) External indication of DSP_IRQ8_STS 45h DSP1 RAM Ready Indicates DSP1 RAM Ready status 46h DSP2 RAM Ready Indicates DSP2 RAM Ready status 47h DSP3 RAM Ready Indicates DSP3 RAM Ready status 48h DSP4 RAM Ready Indicates DSP4 RAM Ready status Table 89 DSP Status and RAM Ready Indications OPCLK AND OPCLK_ASYNC CLOCK OUTPUT GPn_FN = 04h, 3Dh. A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. The OPCLK frequency is controlled by OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled using the OPCLK_ENA register, as described in Table 90. A clock output (OPCLK _ASYNC) derived from ASYNCCLK can be output on a GPIO pin. Th e OPCLK_ASYNC frequency is controlled by OPCLK_ ASYNC_DIV and OPCLK_ASYNC_SEL . The OPCLK_ASYNC output is enabled using the OPCLK_ASYNC_ENA register It is recommended to disable the clock output (OPCLK_ENA=0 or OPCLK_ASYNC_ENA=0) before making any change to the respective OPCLK_DIV, OPCLK_SEL, OPCLK_ASYNC_DIV or OPCLK_ASYNC_SEL registers. The OPCLK or OPCLK_ASYNC Clock outputs can be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The OPCLK_ASYNC source frequency cannot be higher than the ASYNCCLK frequency. The maximum output frequency supported for GPIO output is noted in the “Electrical Characteristics”. See “Clocking and Sample Rates” for more details of the system clocks (SYSCLK and ASYNCCLK).

Rev 4.0 237 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R329 (0149h) Output system clock

15 OPCLK_ENA 0 OPCLK Enable

0 = Disabled 1 = Enabled 7:3 OPCLK_DIV [4:0] 00h OPCLK Divider 00h = Divide by 1 01h = Divide by 1 02h = Divide by 2 03h = Divide by 3 1Fh = Divide by 31 2:0 OPCLK_SEL [2:0] 000 OPCLK Source Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related SYSCLK rates only (ie. SAMPLE_RATE_n = 01XXX). The OPCLK Source Frequency must be less than or equal to the SYSCLK frequency. R330 (014Ah) Output async clock

15 OPCLK_ASYNC_

0 OPCLK_ASYNC Enable

0 = Disabled 1 = Enabled 7:3 OPCLK_ASYNC_ DIV [4:0] 00h OPCLK_ASYNC Divider 00h = Divide by 1 01h = Divide by 1 02h = Divide by 2 03h = Divide by 3 1Fh = Divide by 31 2:0 OPCLK_ASYNC_ SEL [2:0]

000 OPCLK_ASYNC Source Frequency

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related ASYNCCLK rates only (ie. ASYNC_SAMPLE_RATE_n = 01XXX). The OPCLK_ASYNC Source Frequency must be less than or equal to the ASYNCCLK frequency. Table 90 OPCLK and OPCLK_ASYNC Control

238 Rev 4.0 FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT GPn_FN = 0Ch, 0Dh, 0Fh, 10h. The WM8281 supports FLL status flags, which may be used to control other events. See “ Clocking and Sample Rates” for more details of the FLL. The ‘FLL Clock OK’ signal s indicate that the respective FLL has started up and is providing an output clock. The ‘FLL Lock’ signals indicate whether FLL Lock has been achieved. The FLL Clock OK and FLL Lock signals may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The FLL Clock OK and FLL Lock signal s are inputs to the Interrupt Controller circuit. An interrupt event is triggered on the rising and falling edges of these signals. The associated interrupt bit s are latched once set; they can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT GPn_FN = 05h, 06h. Clock outputs derived from the FLLs may be output on a GPIO pin. The GPIO output from each FLLn (where ‘n’ is 1 or 2 ) is controlled by the respective FLLn_GPCLK_DIV and FLLn_GPCLK_ENA registers, as described in Table 91. It is recommended to disable t he clock output (FLLn_GPCLK_ENA=0) before making any change to the respective FLLn_GPCLK_DIV register. Note that the FLLn_GPCLK_DIV and FLLn_GPCLK_ENA registers affect the GPIO outputs only; they do not affect the FLL frequency. The maximum output frequency supported for GPIO output is noted in the “Electrical Characteristics”. The Frequency Locked Loop (FLL) Clock outputs may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. See “Clocking and Sample Rates ” for more details of the WM8281 system clocking and for details of how to configure the FLLs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R394 (018Ah) FLL1 GPIO Clock 7:1 FLL1_GPCLK_DI V [6:0] 06h FLL1 GPIO Clock Divider 00h to 06h= Divide by 6 07h = Divide by 7 08h = Divide by 8 09h = Divide by 9 7Fh = Divide by 127 (FGPIO = FVCO / FLL1_GPCLK_DIV)

0 FLL1_GPCLK_EN

A

0 FLL1 GPIO Clock Enable

0 = Disabled 1 = Enabled R426 (01AAh) FLL2 GPIO Clock 7:1 FLL2_GPCLK_DI V [6:0] 06h FLL2 GPIO Clock Divider 00h to 06h= Divide by 6 07h = Divide by 7 08h = Divide by 8 09h = Divide by 9 7Fh = Divide by 127 (FGPIO = FVCO / FLL2_GPCLK_DIV)

0 FLL2_GPCLK_EN

A

0 FLL2 GPIO Clock Enable

0 = Disabled 1 = Enabled Table 91 FLL Clock Output Control

Rev 4.0 239 PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT GPn_FN = 08h, 09h. The WM8281 incorporates two Pulse Width Modulation ( PWM) signal generators which can be enabled as GPIO outputs. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. The Pulse Width Modulation (PWM) outputs may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. See “Digital Core” for details of how to configure the PWM signal generators. Note that the PWM output should always be disabled (PWMn_ENA=0, as described in Table 22) whenever the system clock, SYSCLK, is disabled. Failure to do this may result in a persistent logic ‘1’ DC output from the PWM generator. See “ Clocking and Sample Rates” for details of system clocking and the associated control requirements. HEADPHONE DETECTION STATUS OUTPUT GPn_FN = 12h. The WM8281 provides a headphone detection circuit on the HPDETL and HPDETR pins to measure the impedance of an external load connected to the headphone outputs. See “ External Accessory Detection” for further details. A logic signal from the headphone detection circuit may be ou tput directly on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. This logic signal is set low when a Headphone Detect measurement is triggered, and is set high when the Headphone Detect function has completed. A rising edge indicates completion of a Headphone Detect measurement. The headphone detection circuit is also an input to the Interrupt control circuit . An inte rrupt event is triggered whenever a headphone detection measurement has completed . Note that the HPDET_EINT flag is also asserted when the headphone detection is initiated. The associated interrupt bit is latched once set; it can be polled at any time or u sed to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. MICROPHONE / ACCESSORY DETECTION STATUS OUTPUT GPn_FN = 13h. The WM8281 provides an impedance measurement circuit on the MICDET n pins to detect the connection of a microphone or other external accessory. See “ External Accessory Detection ” for further details. A logic signal from the microphone detect circuit may be output directly on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. This logic signal is set high for a pulse duration of 31s whenever an accessory insertion, removal or impedance change is detected. The microphone detection circuit is also an input to the Interrupt control circuit . An interrupt event is triggered whenever an accessory insertion, removal or impedance change is detected . The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling. HEADPHONE ENABLE STATUS OUTPUT GPn_FN = 2Fh, 30h, 31h, 32h, 33h, 34h. Whenever a headphone output path is enabled or disabled, a pop -suppression control sequence is triggered. Status outputs indicating the progress of these sequences are provided. Note that this provides See “Output Signal Path” for details of the Output Enable functions. A logic signal from the Headphone Enable control functions may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a short pulse duration (approx. 100ns) whenever the respective control sequence has completed. The headphone control sequence status outputs are described in Table 92. The Headphone Enable control sequences also provide inputs to the Interrupt control circuit . An interrupt event is triggered on completion of the respective control sequence. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

240 Rev 4.0 GPN_FN DESCRIPTION COMMENTS 2Fh HPOUT1L Enable Status A short pulse is output when the respective control sequence has completed. 30h HPOUT1R Enable Status 31h HPOUT2L Enable Status 32h HPOUT2R Enable Status 33h HPOUT3L Enable Status 34h HPOUT3R Enable Status Table 92 Headphone Enable Status Indications BOOT DONE STATUS OUTPUT GPn_FN = 44h. The WM8281 executes a user -configurable Boot Sequence following Power -On Reset (POR), Hardware Reset, Software Reset or Wake -Up (from Sleep mode) . Control register writes should not be attempted while the Boot Sequence is running. For details of the Boot Sequence, see “Control Write Sequencer”. The BOOT_DONE_STS register bit (see Table 128) indicate s the status of the Boot Sequence. (When BOOT_DONE_STS=1, then the Boot Sequence is complete.) A logic signal from the Boot Sequence function may be output directly on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. This logic signal is set high for a short pulse duration (approx. 100ns) when the Boot Sequence has completed. To output this signal, the Boot Sequence must be programmed to configure a GPIO pin for this function. Note that, under default register conditions, completion of the Boot Sequence is indicated via the Interrupt circuit. The BOOT_DONE_STS signal is also an input to the Interrupt Controller circuit. An interrupt event is triggered on the rising edge of this signal. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT GPn_FN = 1Ah, 1Bh. The WM8281 maintains a flag indicating the lock status of the Asynchronous Sample Rate Converters (ASRCs), which may be used to control other events if required. See “ Digital Core” for more details of the ASRCs. The ASRC Lock signals may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The ASRC Lock signals are inputs to the Interrupt control circuit. An interrupt event is triggered on the rising and falling edges of the ASRC Lock signals. The associated interrupt bits ar e latched once set; they can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. ASYNCHRONOUS SAMPLE RATE CONVERTE R (ASRC) CONFIGURATI ON ERROR STATUS OUTPUT GPn_FN = 1Ch. The WM8281 performs automatic checks to confirm that the ASRCs are configured with valid settings. Invalid settings include conditions where one of the associated sample rates is higher than 48kHz . If an invalid ASRC configuration is detected, this can be indicated using the GPIO and/or Interrupt functions. The ASRC Configuration Error signal may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The ASRC Configuration Error signal is an input to the Interrupt Controller circuit. An interrupt event is triggered on the rising edge of the ASRC Configuration Error signal. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling.

Rev 4.0 241 ISOCHRONOUS SAMPLE RATE CONVERTER ( ISRC) CONFIGURATION E RROR STATUS OUTPUT GPn_FN = 4Dh, 4Eh, 4Fh. The WM8281 performs automatic checks to confirm that the ISRCs are configured with valid s ettings. Invalid settings include conditions where an invalid combination of sample rates is configured. If an invalid ISRC configuration is detected, this can be indicated using the GPIO and/or Interrupt functions. The ISRC Configuration Error signal may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The ISRC Configuration Error signals are inputs to the Interrupt Controller circuit. An interrupt event is triggered on the rising edge of the ISRC Configuration Error signals. The associated interrupt bit s are latched once set; they can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT GPn_FN = 2Bh, 2Ch, 53h, 54h, 55h, 56h, 57h, 58h, 59h, 5Ah, 5Bh, 5Ch, 5Dh, 5Eh, 5Fh, 60h, 61h. The WM8281 incorporates a temperature sensor which detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The temperature status may be output directly on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. A GPIO pin can be used to indicate either an Overheat Warning Temperature event or an Overheat Shutdown Temperature event. The WM8281 provides short circuit protection on the Class D speaker outputs, and on each of the headphone output paths. The status of each of the short circuit detection circuits may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. Note that two short circuit indications are implemented for each headphone output channel (relating to detection in the positive and negative output voltage regions respectively); if either of these indications is asserted, then a short circuit condition exists in the respective output path. If the Overheat Shutdown Temperature is exceeded, or if a short circuit is detected on the Class D speaker outputs, then the Class D speaker outputs will automatically be disabled in order to protect the device. When the speaker driver shutdown is complete, the Speaker Shutdown signal will be asserted. The speaker driver shutdown status can also be output directly on a GPIO pin. The Overtemperature, Short Circuit protection, and Speaker Shutdown status flags are inputs to the Interrupt control circuit. An interrupt event may be triggered on the applicable edges of these signals. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

242 Rev 4.0 DYNAMIC RANGE CONTROL (DRC) STATUS OUTPUT GPn_FN = 1Dh, 1Eh, 1Fh, 20h, 21h, 22h, 23h, 24h, 25h, 26h. The Dynamic Range Control (DRC) circuits provide status outputs, which may be used to control other events if required. The DRC status flags may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The DRC status outputs are described in Table 93. See “Digital Core” for more details of the DRC. GPN_FN DESCRIPTION COMMENTS 1Dh DRC1 Signal Detect Indicates a signal is present on the respective DRC path. The threshold level is configurable (see Table 15). 1Eh DRC1 Anti-Clip Active Indicates the DRC anti-clip function has been triggered; the DRC gain is decreasing in response to a rising signal level. 1Fh DRC1 Decay Active Indicates that the DRC gain is increasing in response to a low-level signal input. 20h DRC1 Noise Gate Active Indicates that the DRC noise gate has been triggered; an idle signal condition has been detected. 21h DRC1 Quick Release Active Indicates that the DRC quick-release function has been triggered; the DRC gain is increasing rapidly following detection of a short transient peak. 22h DRC2 Signal Detect Description as above. 23h DRC2 Anti-Clip Active Description as above. 24h DRC2 Decay Active Description as above. 25h DRC2 Noise Gate Active Description as above. 26h DRC2 Quick Release Active Description as above. Table 93 Dynamic Range Control (DRC) Status Indications CONTROL WRITE SEQUENCER STATUS OUTPUT GPn_FN = 15h. The WM8281 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write operations in response to a simple trigger event. See “ Control Write Sequencer ” for details of the Control Write Sequencer. The WSEQ_BUSY register bit (see Table 121) indicates the status of the Control Write Sequencer . When WSEQ_BUSY=1, this indicates that one or more Write Sequence operations are in progress or are queued for sequential execution. A logic signal from the Write Sequencer function may be output directly on a GPIO pin by setting the respective GPIO registers as described in “ GPIO Control ”. This logic signal is set high for a short pulse duration (approx. 100ns) whenever the Write Sequencer has completed all scheduled sequences, and there are no more pending operations The Write Sequencer status is an input to the Interrupt control circuit . An interrupt event is triggered on completion of a Control Sequence. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling.

Rev 4.0 243 CONTROL INTERFACE ERROR STATUS OUTPUT GPn_FN = 16h. The WM8281 is controlled by writing to registers through a 2-wire (I2C) or 4 -wire (SPI) serial control interface, as described in the “ Control Interface ” section. The SLIMbus interface also supports read/write access to the control registers, as described in the “SLIMbus Interface Control” section. The WM8281 performs automatic checks to confirm if a register access is successful. Register access will be unsuccessful if an invalid register address is selected. Read/write access to the DSP firmware memory will be unsuccessful if the associated clocking is not enabled. If an invalid or unsuccessful register operation is attempted, this can be indicated using the GPIO and/or Interrupt functions. The C ontrol Interface Error signal may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The Control Interface Error signal is an input to the Interrupt Controller circuit. An interrupt event is triggered on the rising edge of the Control Interface Error signal. The associated interrupt bit is latched once set; it can be polled at any time or used to con trol the IRQ signal. See “ Interrupts” for more details of the Interrupt event handling. SYSTEM CLOCKS ENABLE STATUS OUTPUT GPn_FN = 4Bh, 4Ch. The WM8281 requires a s ystem clock (SYSCLK) for its internal functions and to support the input/output signal paths. The WM8281 can support two independent clock domains, with selected functions referenced to the ASYNCCLK clock domain. See “ Clocking and Sample Rates” for details of these clocks. The SYSCLK_ENA and ASYNC_CLK_ENA registers (see Table 101) control the SYSCLK and ASYNCCLK signals respectively. When ‘0’ is written to these registers, the host processor must wait until the WM8281 has shut down the associated functions before issuing any other register write commands. The SYSCLK Enable and ASYNCCLK Enable status may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The SYSCLK Enable and ASYNCCLK Enable signals are inputs to the Interrupt Controller circuit. An interrupt event is triggered when the respective clock functions have been shut down . The associated interrupt bit is latched once set; it can be polled a t any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event handling.

244 Rev 4.0 CLOCKING ERROR STATUS OUTPUT GPn_FN = 0Ah, 0Bh, 17h, 18h, 19h, 27h, 2Dh, 2Eh. The WM8281 performs automatic checks to confirm that the system clocks are correctly configured according to the commanded functionality. An invalid configuration is one where there are insufficient clock cycles to support the digital processing required by the commanded signal paths. An Underclocked Error condition is where there are insufficient clock cycles for the requested functionality, and increasing the SYSCLK or ASYNCCLK frequency (as applicable) should allow the selected configuration to be supported. An Overclocked Error condition is where the requested functionality cannot be supported, as the clocking requirements of the requested configuration exceed the device limits. The system clocks (SYSCLK and, where applicable, ASYNCCLK) must be enabled before any signal path is enabled. If an attempt is made to enable a signal path, and there are insufficient clock cycles to support that path, then the attempt will be unsuccessful . Note that any signal paths that are already active will not be affected under these circumstances. The Clocking Error signals may be output directly on a GPIO pin by setting the respective GPIO registers as described in “GPIO Control”. The Clocking Error conditions are described in Table 94. The Clocking Error signals are inputs to the Interrupt Controller circuit. An interrupt event is triggered on the rising and falling edges of the Clocking Error signals. The associated interrupt bit s are latched once set; they can be polled at any time or used to control the IR Q signal. See “ Interrupts” for more details of the Interrupt event handling. GPN_FN DESCRIPTION COMMENTS 0Ah SYSCLK Underclocked Indicates insufficient SYSCLK cycles for the commanded functionality. 0Bh ASYNCCLK Underclocked Indicates insufficient ASYNCCLK cycles for the commanded functionality. 17h ADC Overflow Error Indicates an overflow condition in the input signal paths. 18h ADC CIC Error Indicates a CIC error condition in the input signal paths. 19h ADC FIFO Error Indicates a FIFO error condition in the input signal paths. 27h Mixer Dropped Sample Error Indicates a dropped sample in the digital core mixer function. 2Dh Underclocked Error Indicates insufficient SYSCLK or ASYNCCLK cycles for one or more of the selected signal paths or signal processing functions. Increasing the SYSCLK or ASYNCCLK frequency (as applicable) should allow the selected configuration to be supported. Status bits associated with specific sub-systems provide further de-bug capability. The INnx_ENA_STS bits in register R769 indicate the status of each of the input (analogue or digital microphone) signal paths. The OUTnx_ENA_STS bits in registers R1025 and R1030 indicate the status of each of the output (Headphone, Speaker or PDM) signal paths. The ASRCnx_ENA_STS bits in register R3809 indicate the status of each of the ASRC signal paths. The FX_STS field in register R3585 indicates the status of each of the Effects (EQ, DRC or LHPF) signal paths. The *MIX_STSn fields in registers R1600 to R3000 indicate the status of each of the Digital Core mixer signal paths. The ISRCn and AIFn functions are also inputs to the Underclocked Error status indication, but there are no specific _STS register bits associated with these. 2Eh Overclocked Error Indicates that an unsupported device configuration has been attempted, as the clocking requirements of the requested configuration exceed the device limits. Table 94 Clocking Error Status Indications

Rev 4.0 245 GENERAL PURPOSE SWITCH The WM8281 provides a General Purpose Switch, which can be used as a controllable analogue switch for external functions. The switch is implemented between the GPSWA and GPSWB pins. Note that this feature is entirely independent to the GPIOn pins. The General Purpose Switch is configured using SW1_MODE. This register allows the switch to be disabled, enabled, or synchronised to the MICDET Clamp status, as described in Table 95. The switch is a bi -directional analogue switch, offering flexibility in the potential circuit applications. Refer to the “Absolute Maximum Ratings” and “Electrical Characteristics” for further details. The switch can be used in conjunction with the MICDET Clamp function, in order suppress pops and clicks associated with jack insertion and removal. An example circuit is shown in Figure 64, within the “External Accessory Detection ” section. Note that the MICDET Clamp function must also be configured appropriately when using this method of pop suppression control. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3096 (0C18h) GP Switch 1 1:0 SW1_MODE [1:0] 00 General Purpose Switch control 00 = Disabled (open) 01 = Enabled (closed) 10 = Enabled when MICDET Clamp is active 11 = Enabled when MICDET Clamp is not active Table 95 General Purpose Switch control

246 Rev 4.0 INTERRUPTS The Interrupt Controller has multiple inputs. These include the Jack Detect and GPIO input pins, DSP_IRQn flags, headphone / accessory detection, FLL / ASRC Lock detection, and Clocking configuration error indications. (See Table 96, Table 97 and Table 98 for a full definition of the Interrupt Controller inputs.) Any combination of these input s can be used to trigger an Interrupt Request (IRQ) event. The Interrupt Controller supports two sets of interrupt registers. This allows two separate Interrupt Request (IRQ) outputs to be generated, and for each IRQ to report a different set of input or s tatus conditions. For each Interrupt Request (IRQ1 and IRQ2) output, there is an Interrupt register field associated with each of the interrupt inputs. These fields are asserted whenever a logic edge is detected on the respective input. Some inputs are tri ggered on rising edges only; some are triggered on both edges . Separate rising and falling interrupt registers are provided for the JD1 and GP5 signals. The Interrupt register fields for IRQ1 are described in Table 96. The Interrupt register fields for IRQ 2 are described in Table 97. The Interrupt flags can be polled at any time, or else in response to the Interrupt Request (IRQ) output being signalled via the IRQ¯¯¯ pin or a GPIO pin. All of the Interrupts are edge-triggered, as noted above. Many of these are triggered on both the rising and falling edges and, therefore, the Interrupt registers cannot indicate which edge has been detected. The “Raw Status” fields described in Table 98 provide readback of the current value of the corresponding inputs to the Interrupt Controller. Note that the status of any GPIO inputs can be read using the GPn_LVL registers, as described in Table 86. The UNDERCLOCKED_STS and OVERCLOCKED_STS registers represent the logical ‘OR’ of status flags from multiple sub -systems. The status bits in registers R3364 to R3366 (see Table 98) provide readback of these lower -level signals. See “ Clocking and Sample Rates ” for a description of the Underclocked and Overclocked Error conditions. Individual mask bits can enable or disable different functions from the Interrupt controller. The mask bits are described in Table 96 (for IRQ1) and Table 97 (for IRQ2). Note that a masked interrupt input will not assert the corresponding interrupt register field, and will not cause the associated Interrupt Request (IRQ) output to be asserted. The Interrupt Request (IRQ) outputs represent the logical ‘OR’ of the associated inte rrupt registers. (IRQ1 is derived from the _EINT1 registers; IRQ2 is derived from the _EINT2 registers) . The Interrupt register fields are latching fields and, once they are set, they are not reset until a ‘1’ is written to the respective register bit(s). The Interrupt Request (IRQ) outputs are not reset until each of the associated interrupts has been reset. A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin using the register bits described in Table 86. The GPIO de-bounce circuit uses the 32kHz clock, which must be enabled whenever the GPIO de-bounce function is required. A de -bounce circuit is always enabl ed on the FLL status inputs; either the 32kHz clock, or the SYSCLK signal, must be enabled to trigger an Interrupt from the FLL status inputs. Note that the “Raw Status” fields (described in Table 98), are valid without clocking, and can be used to provide FLL status readback when system clocks are not available. The IRQ outputs can be globally masked using the IM_IRQ1 and IM_IRQ2 register bits. When not masked, the IRQ status can be read from IRQ1_STS and IRQ2_STS for the respective IRQ outputs. The IRQ1 output is provided externally on the IRQ¯¯¯ pin. Under default conditions, this output is ‘Active Low’. The polarity can be inverted using the IRQ_POL regi ster. The IRQ¯¯¯ output can be either CMOS driven or Open Drain; this is selected using the IRQ_OP_CFG register. Note that the IRQ¯¯¯ output is referenced to the DBVDD1 power domain. The IRQ2 status can be used to trigger DSP firm ware execution - see “DSP Firmware Control ”. This allows the DSP firmware execution to be linked to external events (eg. Jack detection, or GPIO input), or to any of the status conditions flagged by the Interrupt registers. The IRQ1 and IRQ2 signals may be output on a GPIO pin - see “General Purpose Input / Output”. The WM8281 Interrupt Controller circuit is illustrated in Figure 68. (Note that not all interrupt inputs are shown.) The associated control fields are described in Table 96, Table 97 and Table 98. Note that, under default register condit ions, the ‘Boot Done’ status is the only un -masked interrupt source; a falling edge on the IRQ¯¯¯ pin will indicate completion of the Boot Sequence.

Rev 4.0 247 IM_xxx_EINT1 IM_xxx_EINT1 IM_GP1_EINT1 IM_FLL1_LOCK_EINT1 IM_DRC1_SIG_DET_EINT1 IM_UNDERCLOCKED_EINT1 xxx_EINT1 xxx_EINT1 GP1_EINT1 FLL1_LOCK_EINT1 DRC1_SIG_DET_EINT1 UNDERCLOCKED_EINT1 IM_IRQ1 IRQ1_STS De-bouncing & Edge detection xxx_STS xxx_STS GP1_LVL FLL1_LOCK_STS DRC1_SIG_DET_STS UNDERCLOCKED_STS IM_xxx_EINT2 IM_xxx_EINT2 IM_GP1_EINT2 IM_FLL1_LOCK_EINT2 IM_DRC1_SIG_DET_EINT2 IM_UNDERCLOCKED_EINT2 xxx_EINT2 xxx_EINT2 GP1_EINT2 FLL1_LOCK_EINT2 DRC1_SIG_DET_EINT2 UNDERCLOCKED_EINT2 IM_IRQ2 IRQ2_STS Note: not all available interrupt sources are shown Figure 68 Interrupt Controller REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3087 (0C0Fh) IRQ CTRL

10 IRQ_POL 1 IRQ Output Polarity Select

0 = Non-inverted (Active High) 1 = Inverted (Active Low)

9 IRQ_OP_CFG 0 IRQ Output Configuration

0 = CMOS 1 = Open Drain R3328 (0D00h) Interrupt Status 1

3 GP4_EINT1 0 GPIO4 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

2 GP3_EINT1 0 GPIO3 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

1 GP2_EINT1 0 GPIO2 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

0 GP1_EINT1 0 GPIO1 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. R3329 (0D01h) Interrupt Status 2

11 DSP4_RAM_RD

Y_EINT1

0 DSP4 RAM Ready Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

10 DSP3_RAM_RD

Y_EINT1

0 DSP3 RAM Ready Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

248 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

9 DSP2_RAM_RD

Y_EINT1

0 DSP2 RAM Ready Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

8 DSP1_RAM_RD

Y_EINT1

0 DSP1 RAM Ready Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

7 DSP_IRQ8_EINT

0 DSP IRQ8 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

6 DSP_IRQ7_EINT

0 DSP IRQ7 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

5 DSP_IRQ6_EINT

0 DSP IRQ6 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

4 DSP_IRQ5_EINT

0 DSP IRQ5 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

3 DSP_IRQ4_EINT

0 DSP IRQ4 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

2 DSP_IRQ3_EINT

0 DSP IRQ3 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

1 DSP_IRQ2_EINT

0 DSP IRQ2 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

0 DSP_IRQ1_EINT

0 DSP IRQ1 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. R3330 (0D02h) Interrupt Status 3

15 SPK_OVERHEA

T_WARN_EINT1

0 Speaker Overheat Warning Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

14 SPK_OVERHEA

T_EINT1

0 Speaker Overheat Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

13 HPDET_EINT1 0 Headphone Detect Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

12 MICDET_EINT1 0 Microphone / Accessory Detect Interrupt

(Detection event triggered) Note: Cleared when a ‘1’ is written.

11 WSEQ_DONE_EI

0 Write Sequencer Done Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

10 DRC2_SIG_DET

_EINT1

0 DRC2 Signal Detect Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

9 DRC1_SIG_DET

_EINT1

0 DRC1 Signal Detect Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

8 ASRC2_LOCK_E

0 ASRC2 Lock Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

Rev 4.0 249 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

7 ASRC1_LOCK_E

0 ASRC1 Lock Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

6 UNDERCLOCKE

D_EINT1

0 Underclocked Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

5 OVERCLOCKED

_EINT1

0 Overclocked Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

3 FLL2_LOCK_EIN

0 FLL2 Lock Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

2 FLL1_LOCK_EIN

0 FLL1 Lock Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

1 CLKGEN_ERR_E

0 SYSCLK Underclocked Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

0 CLKGEN_ERR_A

SYNC_EINT1

0 ASYNCCLK Underclocked Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written. R3331 (0D03h) Interrupt Status 4

12 CTRLIF_ERR_EI

0 Control Interface Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

11 MIXER_DROPPE

D_SAMPLE_EIN Mixer Dropped Sample Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written.

10 ASYNC_CLK_EN

A_LOW_EINT1

0 ASYNC_CLK_ENA Interrupt

(Triggered on ASYNCCLK shut-down) Note: Cleared when a ‘1’ is written.

9 SYSCLK_ENA_L

OW_EINT1

0 SYSCLK_ENA Interrupt

(Triggered on SYSCLK shut-down) Note: Cleared when a ‘1’ is written.

8 ISRC1_CFG_ER

R_EINT1

0 ISRC1 Configuration Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

7 ISRC2_CFG_ER

R_EINT1

0 ISRC2 Configuration Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

6 ISRC3_CFG_ER

R_EINT1

0 ISRC3 Configuration Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

5 HP3R_DONE_EI

0 HPOUT3R Enable Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

4 HP3L_DONE_EI

0 HPOUT3L Enable Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

3 HP2R_DONE_EI

0 HPOUT2R Enable Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

2 HP2L_DONE_EI

0 HPOUT2L Enable Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

250 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

1 HP1R_DONE_EI

0 HPOUT1R Enable Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

0 HP1L_DONE_EI

0 HPOUT1L Enable Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written. R3332 (0D04h) Interrupt Status 5

8 BOOT_DONE_EI

0 Boot Done Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

5 ADC_OVERFLO

W_EINT1

0 ADC Overflow Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

4 ADC_FIFO_OU_

0 ADC FIFO Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

3 ASRC_CFG_ER

R_EINT1

0 ASRC Configuration Error Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

1 FLL2_CLOCK_O

K_EINT1

0 FLL2 Clock OK Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

0 FLL1_CLOCK_O

K_EINT1

0 FLL1 Clock OK Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. R3333 (0D05h) Interrupt Status 6

15 DSP_SHARED_

WR_COLL_EINT

0 DSP Shared Memory Collision Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

14 SPK_SHUTDOW

N_EINT1

0 Speaker Shutdown Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

13 SPKOUTR_SHO

RT_EINT1

0 SPKOUTR Short Circuit Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

12 SPKOUTL_SHO

RT_EINT1

0 SPKOUTL Short Circuit Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

11 HP3R_SC_NEG_

0 HPOUT3R Short Circuit Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

10 HP3R_SC_POS_

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

9 HP3L_SC_NEG_

0 HPOUT3L Short Circuit Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

8 HP3L_SC_POS_

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

7 HP2R_SC_NEG_

0 HPOUT2R Short Circuit Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

6 HP2R_SC_POS_

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

Rev 4.0 251 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

5 HP2L_SC_NEG_

0 HPOUT2L Short Circuit Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

4 HP2L_SC_POS_

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

3 HP1R_SC_NEG_

0 HPOUT1R Short Circuit Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

2 HP1R_SC_POS_

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

1 HP1L_SC_NEG_

0 HPOUT1L Short Circuit Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

0 HP1L_SC_POS_

(Rising edge triggered) Note: Cleared when a ‘1’ is written. R3336 (0D08h) to R3341 (0D0Dh) IM_* (see note) For each *_EINT1 interrupt register in R3328 to R3333, a corresponding mask bit (IM_*) is provided in R3336 to R3341. The mask bits are coded as: 0 = Do not mask interrupt 1 = Mask interrupt Note : The BOOT_DONE_EINT1 interrupt is ‘0’ (un-masked) by default; all other interrupts are ‘1’ (masked) by default. R3343 (0D0Fh) Interrupt Control 0 IM_IRQ1 0 IRQ1 Output Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. R3409 (0D51h) AOD IRQ1

7 MICD_CLAMP_F

ALL_EINT1

0 MICDET Clamp Interrupt

(Falling edge triggered) Note: Cleared when a ‘1’ is written.

6 MICD_CLAMP_R

ISE_EINT1 (Rising edge triggered) Note: Cleared when a ‘1’ is written.

5 GP5_FALL_EINT

0 GP5 Interrupt

(Falling edge triggered) Note: Cleared when a ‘1’ is written.

4 GP5_RISE_EINT

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

3 JD1_FALL_EINT

0 JD1 Interrupt

(Falling edge triggered) Note: Cleared when a ‘1’ is written.

2 JD1_RISE_EINT

(Rising edge triggered) Note: Cleared when a ‘1’ is written. R3411 (0D53h) AOD IRQ Mask IRQ1 IM_* 1 For each *_EINT1 interrupt register in R3409, a corresponding mask bit (IM_*) is provided in R3411. The mask bits are coded as: 0 = Do not mask interrupt 1 = Mask interrupt Table 96 Interrupt 1 Control Registers

252 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3344 (0D10h) IRQ2 Status 1

3 GP4_EINT2 0 GPIO4 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

2 GP3_EINT2 0 GPIO3 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

1 GP2_EINT2 0 GPIO2 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

0 GP1_EINT2 0 GPIO1 Interrupt

(Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. R3345 (0D11h) IRQ2 Status 2 Y_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. Y_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. Y_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. Y_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. R3346 (0D12h) IRQ2 Status 3 T_WARN_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. T_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

Rev 4.0 253 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

13 HPDET_EINT2 0 Headphone Detect Interrupt

(Rising edge triggered) Note: Cleared when a ‘1’ is written.

12 MICDET_EINT2 0 Microphone / Accessory Detect Interrupt

(Detection event triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. _EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. _EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. D_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. _EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. SYNC_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. R3347 (0D13h) IRQ2 Status 4 (Rising edge triggered) Note: Cleared when a ‘1’ is written. D_SAMPLE_EIN Mixer Dropped Sample Interrupt (Rising edge triggered) Note: Cleared when a ‘1’ is written. A_LOW_EINT2 (Triggered on ASYNCCLK shut-down) Note: Cleared when a ‘1’ is written. OW_EINT2 (Triggered on SYSCLK shut-down) Note: Cleared when a ‘1’ is written. R_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written.

254 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. R_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. R3348 (0D14h) IRQ2 Status 5 (Rising edge triggered) Note: Cleared when a ‘1’ is written. W_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. R_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written. K_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. K_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. R3349 (0D15h) IRQ2 Status 6 WR_COLL_EINT (Rising edge triggered) Note: Cleared when a ‘1’ is written. N_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. RT_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written. RT_EINT2 (Rising and falling edge triggered) Note: Cleared when a ‘1’ is written.

Rev 4.0 255 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. R3352 (0D18h) to R3357 (0D1Dh) IM_* (see note) For each *_EINT2 interrupt register in R3344 to R3349, a corresponding mask bit (IM_*) is provided in R3352 to R3357. The mask bits are coded as: 0 = Do not mask interrupt 1 = Mask interrupt Note : The BOOT_DONE_EINT2 interrupt is ‘0’ (un-masked) by default; all other interrupts are ‘1’ (masked) by default. R3359 (0D1Fh) IRQ2 Control 0 IM_IRQ2 0 IRQ2 Output Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. R3410 (0D52h) AOD IRQ2 ALL_EINT2 (Falling edge triggered) Note: Cleared when a ‘1’ is written. ISE_EINT2 (Rising edge triggered) Note: Cleared when a ‘1’ is written.

256 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION (Falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. (Falling edge triggered) Note: Cleared when a ‘1’ is written. (Rising edge triggered) Note: Cleared when a ‘1’ is written. R3412 (0D54h) AOD IRQ Mask IRQ2 IM_* 1 For each *_EINT2 interrupt register in R3410, a corresponding mask bit (IM_*) is provided in R3412. The mask bits are coded as: 0 = Do not mask interrupt 1 = Mask interrupt Table 97 Interrupt 2 Control Registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3360 (0D20h) Interrupt Raw Status Y_STS

0 DSP4 RAM Status

0 = Not ready 1 = Ready Y_STS

0 DSP3 RAM Status

0 = Not ready 1 = Ready Y_STS

0 DSP2 RAM Status

0 = Not ready 1 = Ready Y_STS

0 DSP1 RAM Status

0 = Not ready 1 = Ready

7 DSP_IRQ8_STS 0 DSP IRQ8 Status

0 = Not asserted 1 = Asserted

6 DSP_IRQ7_STS 0 DSP IRQ7 Status

0 = Not asserted 1 = Asserted

5 DSP_IRQ6_STS 0 DSP IRQ6 Status

0 = Not asserted 1 = Asserted

4 DSP_IRQ5_STS 0 DSP IRQ5 Status

0 = Not asserted 1 = Asserted

3 DSP_IRQ4_STS 0 DSP IRQ4 Status

0 = Not asserted 1 = Asserted

2 DSP_IRQ3_STS 0 DSP IRQ3 Status

0 = Not asserted 1 = Asserted

1 DSP_IRQ2_STS 0 DSP IRQ2 Status

0 = Not asserted 1 = Asserted

Rev 4.0 257 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 DSP_IRQ1_STS 0 DSP IRQ1 Status

0 = Not asserted 1 = Asserted R3361 (0D21h) Interrupt Raw Status T_WARN_STS

0 Speaker Overheat Warning Status

0 = Normal 1 = Warning temperature exceeded T_STS

0 Speaker Overheat Status

0 = Normal 1 = Shutdown temperature exceeded

11 WSEQ_DONE_S

0 Write Sequencer Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed) _STS

0 DRC2 Signal Detect Status

0 = Normal 1 = Signal detected _STS

0 DRC1 Signal Detect Status

0 = Normal 1 = Signal detected

8 ASRC2_LOCK_S

0 ASRC2 Lock Status

0 = Not locked 1 = Locked

7 ASRC1_LOCK_S

0 ASRC1 Lock Status

0 = Not locked 1 = Locked D_STS

0 Underclocked Error Status

0 = Normal 1 = Underclocked Error _STS

0 Overclocked Error Status

0 = Normal 1 = Overclocked Error

3 FLL2_LOCK_ST

S

0 FLL2 Lock Status

0 = Not locked 1 = Locked

2 FLL1_LOCK_ST

S

0 FLL1 Lock Status

0 = Not locked 1 = Locked

1 CLKGEN_ERR_S

0 SYSCLK Underclocked Error Status

0 = Normal 1 = Underclocked Error SYNC_STS

0 ASYNCCLK Underclocked Error Status

0 = Normal 1 = Underclocked Error R3362 (0D22h) Interrupt Raw Status

12 CTRLIF_ERR_ST

S

0 Control Interface Error Status

0 = Normal 1 = Control Interface Error D_SAMPLE_STS Mixer Dropped Sample Status 0 = Normal 1 = Dropped Sample Error A_LOW_STS

0 ASYNC_CLK_ENA Status

0 = ASYNC_CLK_ENA is enabled 1 = ASYNC_CLK_ENA is disabled When a ‘0’ is written to ASYNCCLK_ENA, then no other control register writes should be attempted until ASYNC_CLK_ENA_LOW_STS=1.

258 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION OW_STS

0 SYSCLK_ENA Status

0 = SYSCLK_ENA is enabled 1 = SYSCLK_ENA is disabled When a ‘0’ is written to SYSCLK_ENA, then no other control register writes should be attempted until SYSCLK_ENA_LOW_STS=1. R_STS 0 = Normal 1 = Configuration Error R_STS 0 = Normal 1 = Configuration Error R_STS 0 = Normal 1 = Configuration Error

5 HP3R_DONE_ST

S

0 HPOUT3R Enable Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed)

4 HP3L_DONE_ST

S

0 HPOUT3L Enable Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed)

3 HP2R_DONE_ST

S

0 HPOUT2R Enable Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed)

2 HP2L_DONE_ST

S

0 HPOUT2L Enable Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed)

1 HP1R_DONE_ST

S

0 HPOUT1R Enable Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed)

0 HP1L_DONE_ST

S

0 HPOUT1L Enable Status

0 = Busy (sequence in progress) 1 = Idle (sequence completed) R3363 (0D23h) Interrupt Raw Status

8 BOOT_DONE_S

0 Boot Status

0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. W_STS

0 ADC Overflow Status

0 = Normal 1 = ADC Overflow

0 ADC FIFO Status

0 = Normal 1 = ADC FIFO Error R_STS 0 = Normal 1 = Configuration Error K_STS 0 = FLL2 Clock is not OK 1 = FLL2 Clock is OK K_STS 0 = FLL1 Clock is not OK 1 = FLL1 Clock is OK R3364 (0D24h)

13 PWM_OVERCLO

CKED_STS

0 Indicates an Overclocked Error condition

for each respective sub-system.

Rev 4.0 259 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Interrupt Raw Status

12 FX_CORE_OVE

RCLOCKED_ST S

0 The bits are coded as:

0 = Normal 1 = Overclocked The OVERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted.

10 DAC_SYS_OVE

RCLOCKED_ST S

9 DAC_WARP_OV

ERCLOCKED_S TS

8 ADC_OVERCLO

CKED_STS

7 MIXER_OVERCL

OCKED_STS

6 AIF3_ASYNC_O

VERCLOCKED_ STS

5 AIF2_ASYNC_O

VERCLOCKED_ STS

4 AIF1_ASYNC_O

VERCLOCKED_ STS

3 AIF3_SYNC_OV

ERCLOCKED_S TS

2 AIF2_SYNC_OV

ERCLOCKED_S TS

1 AIF1_SYNC_OV

ERCLOCKED_S TS

0 PAD_CTRL_OVE

RCLOCKED_ST S R3365 (0D25h) Interrupt Raw Status

15 SLIMBUS_SUBS

YS_OVERCLOC KED_STS for each respective sub-system. The bits are coded as: 0 = Normal 1 = Overclocked The OVERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted.

14 SLIMBUS_ASYN

C_OVERCLOCK ED_STS

13 SLIMBUS_SYNC

_OVERCLOCKE D_STS

12 ASRC_ASYNC_S

YS_OVERCLOC KED_STS

11 ASRC_ASYNC_

WARP_OVERCL OCKED_STS

10 ASRC_SYNC_SY

S_OVERCLOCK ED_STS

9 ASRC_SYNC_W

ARP_OVERCLO CKED_STS

8 DSP4_OVERCL

OCKED_STS

7 DSP3_OVERCL

OCKED_STS

260 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

5 DSP2_OVERCL

OCKED_STS

3 DSP1_OVERCL

OCKED_STS

2 ISRC3_OVERCL

OCKED_STS

1 ISRC2_OVERCL

OCKED_STS

0 ISRC1_OVERCL

OCKED_STS R3366 (0D26h) Interrupt Raw Status

10 AIF3_UNDERCL

OCKED_STS

0 Indicates an Underclocked Error

condition for each respective sub- system. The bits are coded as: 0 = Normal 1 = Overclocked The UNDERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted.

9 AIF2_UNDERCL

OCKED_STS

8 AIF1_UNDERCL

OCKED_STS

7 ISRC3_UNDERC

LOCKED_STS

6 ISRC2_UNDERC

LOCKED_STS

5 ISRC1_UNDERC

LOCKED_STS

4 FX_UNDERCLO

CKED_STS

3 ASRC_UNDERC

LOCKED_STS

2 DAC_UNDERCL

OCKED_STS

1 ADC_UNDERCL

OCKED_STS

0 MIXER_UNDERC

LOCKED_STS R3368 (0D28h) Interrupt Raw Status N_STS

0 Speaker Shutdown Status

0 = Normal 1 = Speaker Shutdown completed (due to Overheat Temperature or Short Circuit condition) RT_STS

0 SPKOUTR Short Circuit Status

0 = Normal 1 = Short Circuit detected RT_STS

0 SPKOUTL Short Circuit Status

0 = Normal 1 = Short Circuit detected

0 HPOUT3R Short Circuit Status

0 = Normal 1 = Short Circuit detected 0 = Normal 1 = Short Circuit detected

0 HPOUT3L Short Circuit Status

0 = Normal 1 = Short Circuit detected 0 = Normal 1 = Short Circuit detected

Rev 4.0 261 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 HPOUT2R Short Circuit Status

0 = Normal 1 = Short Circuit detected 0 = Normal 1 = Short Circuit detected

0 HPOUT2L Short Circuit Status

0 = Normal 1 = Short Circuit detected 0 = Normal 1 = Short Circuit detected

0 HPOUT1R Short Circuit Status

0 = Normal 1 = Short Circuit detected 0 = Normal 1 = Short Circuit detected

0 HPOUT1L Short Circuit Status

0 = Normal 1 = Short Circuit detected 0 = Normal 1 = Short Circuit detected R3392 (0D40h) Interrupt Pin Status

1 IRQ2_STS 0 IRQ2 Status

IRQ2_STS is the logical ‘OR’ of all unmasked _EINT2 interrupts. 0 = Not asserted 1 = Asserted

0 IRQ1_STS 0 IRQ1 Status

IRQ1_STS is the logical ‘OR’ of all unmasked _EINT1 interrupts. 0 = Not asserted 1 = Asserted R3413 (0D55h) AOD IRQ Raw Status 0 = Clamp not active 1 = Clamp active

2 GP5_STS 0 GP5 Status

0 = Not asserted 1 = Asserted 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET pin is pulled ‘low’ on Jack insertion.) Table 98 Interrupt Status

262 Rev 4.0 CLOCKING AND SAMPLE RATES The WM8281 requires a clock reference for its internal functions and also for the input (ADC) paths, output (DAC) paths and digital audio interfaces. Under typical clocking configurations, all commonly- used audio sample rates can be derived directly from the external reference; for additional flexibility, the WM8281 incorporates two Frequency Locked Loop (FLL) circuits to perform frequency conversion and filtering. External clock signals may be connected via MCLK1 and MCLK2. (These inputs are referenced to the DBVDD1 power domain.) In AIF Slave modes, the BCLK signals may be used as a reference for the system clocks. The SLIMbus interface can provide the clock reference, when used as the input to one of the FLLs. To avoid audible glitches, all clock configurations must be set up before enabling playback. SYSTEM CLOCKING The WM8281 supports two independent clock domains, referenced to the SYSCLK and ASYNCCLK system clocks respectively. Up to five different sample rates may be independently selected for specific audio in terfaces and other input/output signal paths. Each selected sample rate must be synchronised either to SYSCLK or to ASYNCCLK, as described later. The two system clocks are independent (ie. not synchronised). Stereo full -duplex sample rate conversion is sup ported, allowing asynchronous audio data to be mixed and to be routed between independent interfaces. See “Digital Core” for further details. Each subsystem within the WM8281 digital core is clocked at a dynamically -controlled rate, limited by the SYSCLK (or ASYNCCLK) frequency, as applicable. For maximum signal mixing and processing capacity, it is recommended that the highest possible SYSCLK and ASYNCCLK frequencies are configured. SAMPLE RATE CONTROL The WM8281 supports two independent clock domains , referenced to SYSCLK and ASYNCCLK respectively. Different sample rates may be selected for each of the audio interfaces (AIF1, AIF2, AIF3 , SLIMbus), and for the input (ADC) and output (DAC) paths. Each of these must be referenced either to SYSCLK or to ASYNCCLK. (Note that the SLIMbus interface supports multiple sample rates, selected independently for each input or output channel.) The WM8281 can support a maximum of five different sample rates at any time. The supported sample rates range from 4kHz to 192kHz. Up to three different sample rates can be selected using the SAMPLE_RATE_1, SAMPLE_RATE_2 and SAMPLE_RATE_3 registers. These must each be numerically related to ea ch other and to the SYSCLK frequency (further details of these requirements are provided in Table 99 and the accompanying text). The remaining two sample rates can be selected using the ASYNC_SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_2 registers. These sample rates must be numerically related to each other and to the ASYNCCLK frequency (further details of these requirements are provided i n Table 100 and the accompanying text), Each of the audio interfaces, input paths and output paths is associated with one of the sample rates selected by the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n registers. Note that if any two interfaces are operating at the same sample rate, but are not synchronised, then one of these must be referenced to the ASYNCCLK domain, and the other to the SYSCLK domain. Note that, when any of the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n registers is written to, the activation of the new setting is automatically synchronised by the WM8281 to ensure continuity of all active signal paths. The SAMPLE_RATE_n_STS and ASYNC_SAMPLE_RATE_n_STS registers provide readback of the sample rate selections that have been implemented.

Rev 4.0 263 There are some restrictions to be observed regarding the sample rate control configuration, as noted below:  The input (ADC / Digital Microphone ) and output (DAC) signal paths must always be associated with the SYSCLK clocking domain.  All external clock references (MCLK input or Slave mode AIF input) must be within 1% of the applicable register setting(s).  The input (ADC / DMIC) sample rate is valid from 8kHz to 192kHz . If 768kHz DMI C clock rate is selected, then the supported sample rate is valid from 8kHz to 16kHz only.  The output (DAC) sample rate is valid from 8kHz to 192kHz.  The Mic Mute mixer sample rate is valid from 8kHz to 192kHz.  The Effects (EQ, DRC, LHPF) sample rate is va lid from 8kHz to 192kHz. When the DRC is enabled, the maximum sample rate for these functions is 96kHz.  The Tone Generator sample rate is valid from 8kHz to 192kHz.  The Haptic Signal Generator sample rate is valid from 8kHz to 192kHz.  The Asynchronous Samp le Rate Converter ( ASRC) supports sample rates 8kHz to 48kHz. The associated SYSCLK and ASYNCLK sample rates must both be 8kHz to 48kHz.  The Isochronous Sample Rate Converters (ISRCs) support sample rates 8kHz to 192kHz. For each ISRC, the higher sample rate must be an integer multiple of the lower rate. AUTOMATIC SAMPLE RATE DETECTION The WM8281 supports automatic sample rate detection on the digital audio interfaces (AIF1, AIF2 and AIF3). Note that this is only possible when the respective interface is operating in Slave mode (ie. when LRCLK and BCLK are inputs to the WM8281). Automatic sample rate detection is enabled using the RATE_EST_ENA register bit. The LRCLK input pin selected for sample rate detection is set using the LRCLK_SRC register. Up to f our audio sample rates can be configured for automatic detection; these sample rates are selected using the SAMPLE_RATE_DETECT_n registers. Note that the function will only detect sample rates that match one of the SAMPLE_RATE_DETECT_n registers. If one of the selected audio sample rates is detected on the selected LRCLK input, then a Control Write Sequence will be triggered. A unique sequence of actions may be programmed for each of the detected sample rates. Note that the applicable control sequences must be programmed by the user for each detection outcome. See “Control Write Sequencer” for further details. The TRIG_ON_STARTUP register controls whether the sample rat e detection circuit responds to the initial detection of the applicable interface (ie. when the AIFn interface starts up). When TRIG_ON_STARTUP=0, then the detection circuit will only respond (ie. trigger the Control Write Sequencer) to a change in the det ected sample rate - the initial sample rate detection will be ignored. (Note that the ‘initial sample rate detection’ is the first detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n registers.) When TRIG_ON_STARTUP=1 , then the detectio n circuit will trigger the Control Write Sequencer whenever a selected sample rate is detected, including when the AIF interface starts up, or when the sample rate detection is first enabled. As described above, setting TRIG_ON_STARTUP=0 is designed to inh ibit any response to the initial detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n registers. Note that, if the LRCLK_SRC setting is changed, or if the detection function is disabled and re -enabled, then a subsequent detection of a ma tching sample rate may trigger the Control Write Sequencer, regardless of the TRIG_ON_STARTUP setting.

264 Rev 4.0 There are some restrictions to be observed regarding the automatic sample rate detection , as noted below:  The same sample rate must not be selected on m ore than one of the SAMPLE_RATE_DETECT_n registers.  Sample rates 192kHz and 176.4kHz must not be selected concurrently.  Sample rates 96kHz and 88.2kHz must not be selected concurrently. The control registers associated with the automatic sample rate detection function are described in Table 101. SYSCLK AND ASYNCCLK CONTROL The SYSCLK and ASYNCCLK clocks may be provided directly from external inputs (MCLK , or slave mode BCLK inputs) . Alternatively, the SYSCLK and ASYNCCLK clocks can be derived using the integrated FLL(s), with MCLK, BCLK, LRCLK or SLIMCLK as a reference. The required SYSCLK frequenc y is dependent on the SAMPLE_RATE_n registers. Table 99 illustrates the valid SYSCLK frequencies for every supported sample rate. The SYSCLK_FREQ and SYSCLK_FRAC regis ters are used to identify the applicable SYSCLK frequency. It is recommended that the highest possible SYSCLK frequency is selected. The chosen SYSCLK frequency must be valid for all of the SAMPLE_RATE_n registers . It follows that all of the SAMPLE_RATE_n registers must select numerically-related values, ie. all from the same cell as represented in Table 99. Sample Rate SAMPLE_RATE_n SYSCLK Frequency SYSCLK_FREQ SYSCLK_FRAC 12kHz 24kHz 48kHz 96kHz 192kHz 4kHz 8kHz 16kHz 32kHz 01h 02h 03h 04h 05h 10h 11h 12h 13h 6.144MHz, 12.288MHz, 24.576MHz, 49.152MHz, 73.728MHz, 98.304MHz, or 147.456MHz 000, 001, 010, 011, 100, 101, or 110 11.025kHz 22.05kHz 44.1kHz 88.2kHz 176.4kHz 09h 0Ah 0Bh 0Ch 0Dh 5.6448MHz, 11.2896MHz, 22.5792MHz, 45.1584MHz, 67.7376MHz, 90.3168MHz, or 135.4752MHz 000, 001, 010, 011, 100, 101, or 110 Note that each of the SAMPLE_RATE_n registers must select a sample rate value from the same group in the two lists above. Table 99 SYSCLK Frequency Selection The required ASYNCCLK frequency is dependent on the ASYNC_SAMPLE_RATE_n registers. Table 100 illustrates the valid ASYNCCLK frequencies for every supported sample rate. The ASYNC_CLK_FREQ register is used to identify the applicable ASYNCCLK frequency. It is recommended that the highest possible ASYNCCLK frequency is selected. Note that, if all the sample rates in the system are synchronised to SYSCLK, then the ASYNCCLK may not be required at all. In this case, the ASYNCCLK should be disabled (see Table 101), and the associated register values are not important.

Rev 4.0 265 Sample Rate ASYNC_SAMPLE_RATE_n ASYNCCLK Frequency ASYNC_CLK_FREQ 12kHz 24kHz 48kHz 96kHz 192kHz 4kHz 8kHz 16kHz 32kHz 01h 02h 03h 04h 05h 10h 11h 12h 13h 6.144MHz, 12.288MHz, 24.576MHz, or 49.152MHz 000, 001, 010, or 011 11.025kHz 22.05kHz 44.1kHz 88.2kHz 176.4kHz 09h 0Ah 0Bh 0Ch 0Dh 5.6448MHz, 11.2896MHz, 22.5792MHz or 45.1584MHz 000, 001, 010, or 011 Note that each of the ASYNC_SAMPLE_RATE_n registers must select a sample rate value from the same group in the two lists above. Table 100 ASYNCCLK Frequency Selection The WM8281 supports automatic clocking configuration. The programmable dividers associated with the ADCs, DACs and all DSP functions are configured automatically, with values determined from the SYSCLK_FREQ, SAMPLE_RATE_n, ASYNC_CLK_FREQ and ASYNC_SAMPLE_RATE_n fields. Note that the digital audio interface (AIF) clocking rates must be configured separately. The sample rates of each AIF, the input (ADC) paths, output (DAC) paths and DSP functions are selected as described in the respective sections. Stereo full -duplex sample rate conversion is supported in multiple configurations to allow digital audio to be routed between interfaces and for asynchronous audio data to be mixed. See “Digital Core” for further details. The SYSCLK_SRC register is used to select the SYSCLK source , as described in Table 101. The source may be MCLK n, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant FLL must be enabled and configured, as described later. The SYSCLK_FREQ and SYSCLK_FRAC registers are set according to the frequency of the selected SYSCLK source. The SYSCLK-referenced circuits within the digital core are clocked at a dynamically -controlled rate, limited by the SYSCLK frequency itself. For maximum signal mixing and processing capacity, it is recommended that the highest possible SYSCLK frequency is configured. The SAMPLE_RATE_n registers are set according to the sample rate(s) that are required by one or more of the WM8281 audio interfaces. The WM8281 supports sample rates ranging from 4kHz to 192kHz. The SYSCLK signal is enabled by the register bit SYSCLK_ENA. The applicable clock source (MCLKn, AIFnBCLK or FLLn) must be enabled before setting SYSCLK_ENA=1. This bit should be set to 0 when reconfiguring the clock sources (see below for additional requirements when setting SYSCLK_ENA=0). When disabling SYSCLK, note that all of the input, output or digital core functions associated with the SYSCLK clock domain must be disabled before setting SYSCLK_ENA=0. When ‘0’ is written to SYSCLK_ENA, the host processor must wait until the WM8281 has shut down the associated functions before issuing any other r egister write commands. The SYSCLK Enable status can be polled via the SYSCLK_ENA_LOW_STS bit (see Table 98), or else monitored using the Interrupt or GPIO functions. The SYSCLK Enable status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The corresponding Interrupt eve nt indicates that the WM8281 has shut down the SYSCLK functions and is ready to accept register write commands. The SYSCLK Enable status can be output directly on a GPIO pin as an external indication of the SYSCLK status. See “General Purpose Input / Output” to configure a GPIO pin for this function.

266 Rev 4.0 The required control sequence for disabling SYSCLK is summarised below:  Disable all SYSCLK-associated functions (inputs, outputs, digital core)  Set SYSCLK_ENA = 0  Wait until SYSCLK_ENA_LOW = 1 (or wait for the corresponding IRQ/GPIO event) The ASYNC_CLK_SRC register is used to select the ASYNCCLK source, as described in Table 101. The source may be MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant FLL must be enabled and configured, as described later. The ASYNC_CLK_FREQ register is set according to the frequency of the selected ASYNCCLK source. The ASYNCCLK -referenced circuits within the digital core are clocked at a dynamically -controlled rate, limited by the ASYNCCLK frequency itself. For m aximum signal mixing and processing capacity, it is recommended that the highest possible ASYNCCLK frequency is configured. The ASYNC_SAMPLE_RATE_n registers are set according to the sample rate(s) of any audio interface that is not synchronised to the SYSCLK clock domain. The ASYNCCLK signal is enabled by the register bit ASYNC_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK or FLLn) must be enabled before setting ASYNC_CLK_ENA=1. This bit should be set to 0 when reconfiguring the clock sources (see below for additional requirements when setting ASYNC_CLK_ENA=0). When disabling ASYNCCLK, note that all of the input, output or digital core functions associated with the ASYNCCLK clock domain must be disabled before setting ASYNC_CLK_ENA=0. When ‘0’ is wr itten to ASYNC_CLK_ENA, the host processor must wait until the WM8281 has shut down the associated functions before issuing any other register write commands. The ASYNCCLK Enable status can be polled via the ASYNC_CLK_ENA_LOW_STS bit (see Table 98), or else monitored using the Interrupt or GPIO functions. The ASYNCCLK Enable status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The corresponding Interrupt event indicates that the WM8281 has shut down the ASYNCCLK functions and is ready to accept register write commands. The ASYNCCLK Enable status can be output directly on a GPIO pin as an external indication of the ASYNCCLK status. See “General Purpose Input / Output” to configure a GPIO pin for this function. The required control sequence for disabling ASYNCCLK is summarised below:  Disable all ASYNCCLK-associated functions (inputs, outputs, digital core)  Set ASYNCCLK_ENA = 0  Wait until ASYNCCLK_ENA_LOW = 1 (or wait for the corresponding IRQ/GPIO event) The SYSCLK (and ASYNCCLK, when applicable) clocks must be configured and enabled before any audio path is enabled. The WM8281 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies are high enoug h to support the commanded signal paths and processing functions. If an attempt is made to enable a signal path or processing function, and there are insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that an y signal paths that are already active will not be affected under these circumstances.) An Underclocked Error condition is where there are insufficient clock cycles for the requested functionality, and increasing the SYSCLK or ASYNCCLK frequency (as applic able) should allow the selected configuration to be supported. An Overclocked Error condition is where the requested functionality cannot be supported, as the clocking requirements of the requested configuration exceed the device limits. The SYSCLK Underclocked condition, ASYNCCLK Underclocked condition , and other Clocking Error conditions can be monitored using the GPIO and/or Interrupt functions. See “ General Purpose Input / Output” and “Interrupts” for further details.

Rev 4.0 267 MISCELLANEOUS CLOCK CONTROLS The WM8281 requires a 32kHz clock for miscellaneous de -bounce functions. This can be generated automatically from SYSCLK, or may be input directly as MCLK1 or MCLK2. The 32kHz clock source is selected using the CLK_32K_SRC register. The 32kHz clock is enabled using the CLK_32K_ENA register. The 32kHz clock can be maintained in Sleep mode, if required for de -bouncing any of the configured Wake-Up signals (eg. JACKDET or GPIO5). Note that the 32kHz clock must be derived from the MCLK2 pin in this case (CLK_32K_SRC=01). See “ Low Power Sleep Configuration ” for more details of the Sleep mode. A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. A clock output (OPCLK _ASYNC) derived from ASYNCCLK can be output on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. The WM8281 provides integrated pull-down resistors on the MCLK1 and MCLK2 pins. This provides a flexible capability for interfacing with other devices. The clocking scheme for the WM8281 is illustrated in Figure 69.

268 Rev 4.0 MCLK2 MCLK1 SYSCLK SYSCLK_ENA SAMPLE_RATE_1 [4:0] SYSCLK_FRAC AIF1BCLK AIF2BCLK AIF3BCLK FLL1_REFCLK_SRC FLL2_REFCLK_SRC SAMPLE_RATE_2 [4:0] SAMPLE_RATE_3 [4:0] ASYNC_SAMPLE_RATE_2 [4:0] ASYNC_CLK_FREQ [2:0] CLK_32K_SRC 32k Clock Divider (Auto) Divider OPCLK OPCLK_SEL OPCLK_DIV CLK_32K_ENA SYSCLK_FREQ [2:0] FLL1 ASYNC_CLK_ENA OPCLK_ENA ASYNCCLK Divider OPCLK_ASYNC OPCLK_ASYNC_SEL OPCLK_ASYNC_DIV OPCLK_ASYNC_ENA Automatic Clocking Control FLLn, AIFnRXLRCLK, and SLIMCLK can also be selected as FLLn input reference. Divider FLL1_GPCLK_DIV GPIO output FLL1_GPCLK_ENA SYSCLK_SRC ASYNC_CLK_SRC FLL2_OUTDIV FLL1_OUTDIV FLL2 Divider GPIO output FLL2_GPCLK_DIV FLL2_GPCLK_ENA Divider Divider ASYNC_SAMPLE_RATE_1 [4:0] Figure 69 System Clocking

Rev 4.0 269 The WM8281 clocking control registers are described in Table 101. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R256 (0100h) Clock 32k

6 CLK_32K_ENA 0 32kHz Clock Enable

0 = Disabled 1 = Enabled 1:0 CLK_32K_SRC [1:0] 10 32kHz Clock Source 00 = MCLK1 (direct) 01 = MCLK2 (direct) 10 = SYSCLK (automatically divided) 11 = Reserved R257 (0101h) System Clock 1

15 SYSCLK_FRAC 0 SYSCLK Frequency

0 = SYSCLK is a multiple of 6.144MHz 1 = SYSCLK is a multiple of 5.6448MHz 10:8 SYSCLK_FREQ [2:0]

101 SYSCLK Frequency

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) 100 = 73.728MHz (67.7376MHz) 101 = 98.304MHz (90.3168MHz) 110 = 147.456MHz (135.4752MHz) 111 = Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX).

6 SYSCLK_ENA 0 SYSCLK Control

0 = Disabled 1 = Enabled SYSCLK should only be enabled after the applicable clock source has been configured and enabled. Set this bit to 0 when reconfiguring the clock sources. 3:0 SYSCLK_SRC [3:0]

0100 SYSCLK Source

0000 = MCLK1 0001 = MCLK2 0100 = FLL1 0101 = FLL2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK All other codes are Reserved

270 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R258 (0102h) Sample rate 1 4:0 SAMPLE_RATE_ 1 [4:0]

10001 Sample Rate 1 Select

00h = None 01h = 12kHz 02h = 24kHz 03h = 48kHz 04h = 96kHz 05h = 192kHz 09h = 11.025kHz 0Ah = 22.05kHz 0Bh = 44.1kHz 0Ch = 88.2kHz 0Dh = 176.4kHz 10h = 4kHz 11h = 8kHz 12h = 16kHz 13h = 32kHz All other codes are Reserved R259 (0103h) Sample rate 2 4:0 SAMPLE_RATE_ 2 [4:0]

10001 Sample Rate 2 Select

Register coding is same as SAMPLE_RATE_1. R260 (0104h) Sample rate 3 4:0 SAMPLE_RATE_ 3 [4:0]

10001 Sample Rate 3 Select

Register coding is same as SAMPLE_RATE_1. R266 (010Ah) Sample rate 1 status 4:0 SAMPLE_RATE_ 1_STS [4:0]

00000 Sample Rate 1 Status

(Read only) Register coding is same as SAMPLE_RATE_1. R267 (010Bh) Sample rate 2 status 4:0 SAMPLE_RATE_ 2_STS [4:0]

00000 Sample Rate 2 Status

(Read only) Register coding is same as SAMPLE_RATE_1. R268 (010Ch) Sample rate 3 status 4:0 SAMPLE_RATE_ 3_STS [4:0]

00000 Sample Rate 3 Status

(Read only) Register coding is same as SAMPLE_RATE_1. R274 (0112h) Async clock 1 10:8 ASYNC_CLK_FR EQ [2:0]

011 ASYNCCLK Frequency

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. ASYNC_SAMPLE_RATE_n = 01XXX).

6 ASYNC_CLK_EN

A

0 ASYNCCLK Control

0 = Disabled 1 = Enabled ASYNCCLK should only be enabled after the applicable clock source has been configured and enabled. Set this bit to 0 when reconfiguring the clock sources.

Rev 4.0 271 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3:0 ASYNC_CLK_SR C [3:0]

0101 ASYNCCLK Source

0000 = MCLK1 0001 = MCLK2 0010 = Reserved 0011 = Reserved 0100 = FLL1 0101 = FLL2 0111 = Reserved 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1011 to 1111 = Reserved All other codes are Reserved R275 (0113h) Async sample rate 1 4:0 ASYNC_SAMPL E_RATE_1 [4:0]

10001 ASYNC Sample Rate 1 Select

00h = None 01h = 12kHz 02h = 24kHz 03h = 48kHz 04h = 96kHz 05h = 192kHz 09h = 11.025kHz 0Ah = 22.05kHz 0Bh = 44.1kHz 0Ch = 88.2kHz 0Dh = 176.4kHz 10h = 4kHz 11h = 8kHz 12h = 16kHz 13h = 32kHz All other codes are Reserved R276 (0114h) Async sample rate 2 4:0 ASYNC_SAMPL E_RATE_2 [4:0]

10001 ASYNC Sample Rate 2 Select

Register coding is same as ASYNC_SAMPLE_RATE_1. R283 (011Bh) Async sample rate 1 status 4:0 ASYNC_SAMPL E_RATE_1_STS [4:0]

00000 ASYNC Sample Rate 1 Status

(Read only) Register coding is same as ASYNC_SAMPLE_RATE_1. R284 (011Ch) Async sample rate 2 status 4:0 ASYNC_SAMPL E_RATE_2_STS [4:0]

00000 ASYNC Sample Rate 2 Status

(Read only) Register coding is same as ASYNC_SAMPLE_RATE_1. R329 (0149h) Output system clock 0 = Disabled 1 = Enabled 7:3 OPCLK_DIV [4:0] 00h OPCLK Divider 00h = Divide by 1 01h = Divide by 1 02h = Divide by 2 03h = Divide by 3 1Fh = Divide by 31

272 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2:0 OPCLK_SEL [2:0]

000 OPCLK Source Frequency

000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related SYSCLK rates only (ie. SAMPLE_RATE_n = 01XXX). The OPCLK Source Frequency must be less than or equal to the SYSCLK frequency. R330 (014Ah) Output async clock 0 = Disabled 1 = Enabled 7:3 OPCLK_ASYNC_ DIV [4:0] 00h OPCLK_ASYNC Divider 00h = Divide by 1 01h = Divide by 1 02h = Divide by 2 03h = Divide by 3 1Fh = Divide by 31 2:0 OPCLK_ASYNC_ SEL [2:0] 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related ASYNCCLK rates only (ie. ASYNC_SAMPLE_RATE_n = 01XXX). The OPCLK_ASYNC Source Frequency must be less than or equal to the ASYNCCLK frequency. R338 (0152h) Rate Estimator

4 TRIG_ON_STAR

0 Automatic Sample Rate Detection Start-

0 = Do not trigger Write Sequence on initial detection 1 = Always trigger the Write Sequencer on sample rate detection 3:1 LRCLK_SRC [2:0]

000 Automatic Sample Rate Detection source

000 = AIF1RXLRCLK 001 = AIF1TXLRCLK 010 = AIF2RXLRCLK 011 = AIF2TXLRCLK 100 = AIF3RXLRCLK 101 = AIF3TXLRCLK 110 = Reserved 111 = Reserved

0 RATE_EST_ENA 0 Automatic Sample Rate Detection control

0 = Disabled 1 = Enabled R339 (0153h) Rate Estimator 4:0 SAMPLE_RATE_ DETECT_A [4:0] 00h Automatic Detection Sample Rate A (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n.

Rev 4.0 273 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R340 (0154h) Rate Estimator 4:0 SAMPLE_RATE_ DETECT_B [4:0] 00h Automatic Detection Sample Rate B (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R341 (0155h) Rate Estimator 4:0 SAMPLE_RATE_ DETECT_C [4:0] 00h Automatic Detection Sample Rate C (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R342 (0156h) Rate Estimator 4:0 SAMPLE_RATE_ DETECT_D [4:0] 00h Automatic Detection Sample Rate D (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R3104 (0C20h) Misc Pad Ctrl 1

13 MCLK2_PD 0 MCLK2 Pull-Down Control

0 = Disabled 1 = Enabled R3105 (0C21h) Misc Pad Ctrl 2

12 MCLK1_PD 0 MCLK1 Pull-Down Control

0 = Disabled 1 = Enabled Table 101 Clocking Control In AIF Slave modes, it is important to ensure the applicable clock domain (SYSCLK or ASYNCCLK) is synchronised with the associated external LRCLK. This can be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by selecting th e external BCLK or LRCL K signal as a reference input to one of the FLL s, as a source for SYSCLK or ASYNCCLK. If the AIF clock domain is not synchronised with the LRCLK, then clicks arising from dropped or repeated audio samples will occur, due to the inherent tolerances of multi ple, asynchronous, system clocks. See “Applications Information” for further details on valid clocking configurations.

274 Rev 4.0 BCLK AND LRCLK CONTROL The digital audio interf aces (AIF1, AIF2 and AIF3 ) use BCLK and LRCLK signals for synchronisation. In master mode, these are output signals, generated by the WM8281. In slave mode, these are input signals to the WM8281. It is also possible to support mixed master/slave operation. The BCLK and LRCLK signals are controlled as illustrated in Figure 70. See the “ Digital Audio Interface Control” section for further details of the relevant control registers. Note that the BCLK and LRCLK signals are synchronised to SYSCLK or ASYNCLK, depending upon the applicable clocking domain for the respective interface. See “Digital Core” for further details. AIF1_BCLK_FREQ [4:0] f/N AIF1BCLK AIF1LRCLK AIF1RX_BCPF [12:0] f/N GPIO1 (AIF1TXLRCLK) AIF1TX_BCPF [12:0] SYSCLK MASTER MODE CLOCK OUTPUTS f/N AIF1_BCLK_MSTR AIF1RX_LRCLK_MSTR AIF1TX_LRCLK_MSTR AIF2_BCLK_FREQ [4:0] f/N AIF2BCLK AIF2LRCLK AIF2RX_BCPF [12:0] f/N GPIO2 (AIF2TXLRCLK) AIF2TX_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF2_BCLK_MSTR AIF2RX_LRCLK_MSTR AIF2TX_LRCLK_MSTR AIF3_BCLK_FREQ [4:0] f/N AIF3BCLK AIF3LRCLK AIF3RX_BCPF [12:0] f/N GPIO3 (AIF3TXLRCLK) AIF3TX_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF3_BCLK_MSTR AIF3RX_LRCLK_MSTR AIF3TX_LRCLK_MSTR ASYNCCLK The clock reference for each AIF is SYSCLK or ASYNCCLK AIFn is clocked from SYSCLK if AIFn_RATE < 1000 AIFn is clocked from ASYNCCLK if AIFn_RATE >= 1000 (see note below) (see note below) (see note below) Figure 70 BCLK and LRCLK Control CONTROL INTERFACE CLOCKING Register map access is possible with or without a system clock . Clocking is provided from SYSCLK , when available; the SYSCLK_SRC register selects the applicable SYSCLK source. See “Control Interface” for further details of control register access.

Rev 4.0 275 FREQUENCY LOCKED LOOP (FLL) Two integrated FLLs are provided to support the clocking requirements of the WM8281. These can be enabled and configured independently according to the available reference clocks and the application requirements. The reference clock may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz). The FLL is tolerant of jitter and may be used to generate a stable output clock from a less stable input reference. The FLL characteristics are summarised in “ Electrical Characteristics ”. Note that the FLL can be used to generate a free -running clock in the abs ence of an external reference source. This is described in the “ Free-Running FLL Mode” section below . Configurable spread-spectrum modulation can be applied to the FLL outputs, to control EMI effects. Each of the FLLs comprises two sub -systems - the ‘main’ loop and the ‘synchroniser’ loop; these can be used together to maintain best frequency accuracy and noise (jitter) performance across multiple use-cases. The two-loop design enables the FLL to synchronise effectively to an input clock that may be intermittent or noisy, whilst also achieving the performance benefits of a stable clock reference that may be asynchronous to the audio data. The main loop takes a constant a nd stable clock reference as its input. For best performance, a high frequency (eg. 12.288MHz) reference is recommended. The main FLL loop will free -run without any clock reference if the input signal is removed; it can also be configured to initiate an ou tput in the absence of any reference signal. The synchroniser loop takes a separate clock reference as its input. The synchroniser input may be intermittent (eg. during voice calls only). The FLL uses the synchroniser input, when available, as the frequency reference. To achieve the designed performance advantage, the synchroniser input must be synchronous with the audio data. Note that, if only a single clock input reference is used, this must be configured as the main FLL input reference. The synchroniser should be disabled in this case. The synchroniser loop should only be used when the main loop clock reference is present. If the input reference to the main FLL is intermittent , or may be interrupted unexpectedly, then the synchroniser should be disabled. The FLL is enabled using the FLL n_ENA register bit (where n = 1 or 2 for the corresponding FLL) . The FLL Synchroniser is enabled using the FLLn_SYNC_ENA register bit. Note that the other FLL registers should be configured before enabling the FLL; the FLL n_ENA and FLLn_SYNC_ENA register bits should be set as the final step of the FLLn enable sequence. The FLL supports configurable free -running operation, using the FLL n_FREERUN register bits described in the next section. Note that , once the FLL output has been established, the FLL will always free-run when the input reference clock is stopped, regardless of the FLLn_FREERUN bits. To disable the FLL while the input reference clock has stopped, the respective FLL n_FREERUN bit must be set to ‘1’, before setting the FLLn_ENA bit to ‘0’. When changing FLL settings, it is recommended that the digital circuit be disabled via FLL n_ENA and then re -enabled after the other register settings have been updated. When changing the input reference frequency FREF, it is recommended that the FLL be reset by setting FLLn_ENA to 0. Note that some of the FLL configuration registers can be updated while the FLL is enabled, as described below. As a general rule, however, it is recommended to configure the FLL (and FLL Synchroniser, if applicable), before setting the corresponding _ENA register bit(s). The FLL configuration requirements are illustrated in Figure 71.

276 Rev 4.0 MCLK2 MCLK1 FLLn_REFCLK_SRC (270MHz ≤ Fvco ≤ 312MHz) FVCO FOUTDivide by FLLn_OUTDIV Divide by 2, 3 .. 7 FLLn_ENA (FLL Enable) FLLn, AIFnBCLK, AIFnRXLRCLK Divide by 1, 2, 4 or 8 Divide by FLLn_REFCLK_DIV FREF < 13.5MHz FREF Multiply by N.K Multiply by FLLn_FRATIO Multiply by 1, 2, 3 … 16 Main FLL path FLLn_SYNCCLK_SRC N.K = FLLn_N + FLLn_THETA FLLn_LAMBDA N.K (Sync) = FLLn_SYNC_N + FLLn_SYNC_THETA FLLn_SYNC_LAMBDA FLLn_SYNC_ENA (FLL Synchroniser Enable) SLIMCLK SLIMCLK_REF_GEAR Automatic Divider Divide by FLLn_SYNCCLK_DIV Divide by 1, 2, 4 or 8 FSYNC < 13.5MHz FSYNC Multiply by N.K (Sync) Multiply by FLLn_SYNC_ FRATIO Multiply by 1, 2, 4, 8 or 16 FLL Synchroniser path FGPIO Divide by 7, 8 .. 127 Divide by FLLn_GPCLK_DIV Figure 71 FLL Configuration The procedure for configuring the FLL is described below. Note that the configuration of the main FLL path and the FLL Synchroniser path are very similar. One or both paths must be configured, depending on the application requirements:  If a single clock input reference is used, then only the main FLL path should be used.  If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly, then only the main FLL path should be used.  If two clock input references are used, then the constant or low-noise clock is configured on the main FLL path, and the high-accuracy clock is configured on the FLL synchroniser path. Note that the synchroniser input must be synchronous with the audio data. The following description is applicable to FLL1 and FLL2. The associated register control fields are described in Table 106 and Table 107 respectively. The main input reference is selected using FLLn_REFCLK_SRC. The synchroniser input reference is selected using FLLn_SYNCCLK_SRC. The available options in each case comprise MCLK1, MCLK2, SLIMCLK, AIFnBCLK, AIFnRXLRCLK, or the output from another FLL. The SLIMCLK reference is controlled by an adaptive divider on the external SLIMCLK input. The divider automatically adapts to the SLIMbus Clock Gear, to provide a constant reference frequency for the FLL. See “SLIMbus Interface Control” for details. The FLL n_REFCLK_DIV field controls a programmable divider on the main input reference. T he FLLn_SYNCCLK_DIV field controls a programmable divider on the synchroniser input reference. Each input can be divided by 1, 2, 4 or 8. These registers should be set to bring each reference down to 13.5MHz or below. For best performance, it is recommende d that the highest possible frequency - within the 13.5MHz limit - should be selected. (Note that additional guidelines also apply, as described below.) The FLL output frequency , relative to the main input reference FREF, is directly determined from FLLn_FRATIO, FLLn_OUTDIV and the real number represented by N.K. The integer value , N, is held in the FLL n_N register field. The fractional portion, K, is determined by the ratio FLLn_THETA / FLLn_LAMBDA.

Rev 4.0 277 The FLL output frequency is generated according to the following equation: FOUT = (FVCO / FLLn_OUTDIV) The FLL operating frequency, FVCO is set according to the following equation: FVCO = (FREF x 3 x N.K x FLLn_FRATIO) FREF is the input frequency, as determined by FLLn_REFCLK_DIV. When the FLL output is selected as the SYSCLK or ASYNCCLK source, then FVCO must be exactly 294.912MHz (for 48kHz-related sample rates) or 270.9504MHz (for 44.1kHz-related sample rates). Note that the output frequencies that do not lie on or between the frequencies quoted above cannot be guaranteed across the full range of device operating conditions. In order to follow the above requirements for F VCO, the value of FLL n_OUTDIV should be selected according to the desired output F OUT. The divider, FLLn_OUTDIV, must be set so that F VCO is in the range 270MHz to 295MHz. The available divisions are integers from 2 to 7. Some typical settings of FLLn_OUTDIV are noted in Table 102. OUTPUT FREQUENCY FOUT FLLn_OUTDIV

45 MHz to 52 MHz 110 (divide by 6)

67.5 MHz to 78 MHz 100 (divide by 4)

90 MHz to 104 MHz 011 (divide by 3)

135 MHz to 150 MHz 010 (divide by 2)

Table 102 Selection of FLLn_OUTDIV The FLLn_FRATIO field selects the frequency division ratio of the FLL input. The FLL n_GAIN field is used to optimise the FLL, according to the input frequency. As a general guide, these fields should be selected as described in Table 103. (Note that additional guidelines also apply, as described below.) REFERENCE FREQUENCY FREF FLLn_FRATIO FLLn_GAIN 1MHz - 13.5MHz 0h (divide by 1) 4h (16x gain) 256kHz - 1MHz 1h (divide by 2) 2h (4x gain) 128kHz - 256kHz 3h (divide by 4) 0h (1x gain) 64kHz - 128kHz 7h (divide by 8) 0h (1x gain) Less than 64kHz Fh (divide by 16) 0h (1x gain) Table 103 Selection of FLLn_FRATIO and FLLn_GAIN In order to determine the remaining FLL parameters, the FLL operating frequency, F VCO, must be calculated, as given by the following equation: FVCO = (FOUT x FLLn_OUTDIV) The value of N.K can then be determined as follows: N.K = FVCO / (FLLn_FRATIO x 3 x FREF) Note that, in the above equations: FLLn_OUTDIV is the FOUT clock ratio. FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. FLLn_FRATIO is the FVCO clock ratio (1, 2, 3 … 16).

278 Rev 4.0 If the above equation s produce an integer value for N.K, then the value of FLLn_FRATIO should be adjusted to a different, odd -number division (eg. divide by 3), and the value of N.K re -calculated. A non-integer value of N.K is recommended for best performance of the FLL. (If possible, the FLLn_FRATIO value should be decreased to the nearest alternative odd -number division. If a suitable lower value does not exist, FLL n_FRATIO should be increased to the nearest odd -number divisio n instead.) After the value of FLLn_FRATIO has been determined, the input frequency, FREF, must be compared with the maximum frequency limit noted in Table 104. If t he input frequency (after division by FLLn_REFCLK_DIV) is higher than the applicable limit, then the FLLn_REFCLK_DIV division ratio should be increased, and the value of N.K re -calculated. (Note that the same value of FLLn_FRATIO as already calculated should be used, when deriving the new value of N.K.) FLLn_FRATIO REFERENCE FREQUENCY FREF - MAXIMUM VALUE 0h (divide by 1) 11.5 MHz 1h (divide by 2) 6.144 MHz 2h (divide by 3) 3h (divide by 4) 3.072 MHz 4h (divide by 5) 5h (divide by 6) 2.8224 MHz 6h (divide by 7) 7h (divide by 8) 1.536 MHz 8h (divide by 9) 9h (divide by 10) Ah (divide by 11) Bh (divide by 12) Ch (divide by 13) Dh (divide by 14) Eh (divide by 15) Fh (divide by 16) 768 kHz Table 104 Maximum FLL input frequency (function of FLLn_FRATIO) The value of N is held in the FLLn_N register field. The value of K is determined by the ratio FLLn_THETA / FLLn_LAMBDA. The FLLn_N, FLLn_THETA and FLLn_LAMBDA fields are all coded as integers (LSB = 1). If the FLL n_N or FLL n_THETA registers are updated while the FLL is enabled (FLL n_ENA=1), then the new values will only be effective when a ‘1’ is written to the FLL n_CTRL_UPD bit. This makes it possible to update the two registers simultaneously, without disabling the FLL. Note that, when the FLL is disabled (FLLn_ENA=0), then the FLLn_N and FLLn_THETA registers can be updated without writing to the FLLn_CTRL_UPD bit. The values of FLLn_THETA and FLLn_LAMBDA can be calculated as described later.

Rev 4.0 279 A similar procedure applies for the deriviation of the FLL Synchroniser parameters - assuming that this function is used. The FLLn_SYNC_FRATIO field selects the frequency division ratio of the FLL synchroniser input. The FLLn_GAIN and FLL n_SYNC_DFSAT fields are used to optimise the FLL, according to the input frequency. These fields should be set as described in Table 105. Note that the FLLn_SYNC_FRATIO register coding is not the same as the FLLn_FRATIO register. SYNCHRONISER FREQUENCY FSYNC FLLn_SYNC_FRATIO FLLn_SYNC_GAIN FLLn_SYNC_DFSAT 1MHz - 13.5MHz 0h (divide by 1) 4h (16x gain) 0 (wide bandwidth) 256kHz - 1MHz 1h (divide by 2) 2h (4x gain) 0 (wide bandwidth) 128kHz - 256kHz 2h (divide by 4) 0h (1x gain) 0 (wide bandwidth) 64kHz - 128kHz 3h (divide by 8) 0h (1x gain) 1 (narrow bandwidth) Less than 64kHz 4h (divide by 16) 0h (1x gain) 1 (narrow bandwidth) Table 105 Selection of FLLn_SYNC_FRATIO, FLLn_SYNC_GAIN, FLLn_SYNC_DFSAT The FLL operating frequency, FVCO, is the same frequency calculated as described above. The value of N.K (Sync) can then be determined as follows: N.K (Sync) = FVCO / (FLLn_SYNC_FRATIO x 3 x FSYNC) Note that, in the above equations: FSYNC is the synchroniser input frequency, after division by FLL n_SYNCCLK_DIV, where applicable. FLLn_SYNC_FRATIO is the FVCO clock ratio (1, 2, 4, 8 or 16). The value of N (Sync) is held in the FLLn_SYNC_N register field. The value of K (Sync) is determined by the ratio FLLn_SYNC_THETA / FLLn_SYNC_LAMBDA. The FLL n_SYNC_N, FLL n_SYNC_THETA and FLL n_SYNC_LAMBDA fields are all coded as integers (LSB = 1). In Fractional Mode (FLLn_THETA > 0 ), the register fields FLL n_THETA and FLL n_LAMBDA can be calculated as described below. Note that an equivalent procedure is also used to derive the FLL n_SYNC_THETA and FLLn_SYNC_LAMBDA register values from the corresponding synchroniser parameters. Calculate GCD(FLL) using the ‘Greatest Common Denominator’ function: GCD(FLL) = GCD(FLLn_FRATIO x FREF, FVCO / 3) where GCD(x, y) is the greatest common denominator of x and y FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. Next, calculate FLLn_THETA and FLLn_LAMBDA using the following equations: FLLn_THETA = ((FVCO / 3) - (FLL_N x FLLn_FRATIO x FREF)) / GCD(FLL) FLLn_LAMBDA = (FLLn_FRATIO x FREF) / GCD(FLL) Note that, in Fractional Mode, the values of FLL n_THETA and FLL n_LAMBDA must be co -prime (ie. not divisible by any common integer). The calculation above ensures that the values will be co-prime. The value of K must be a fraction less than 1 (ie. FLLn_THETA must be less than FLLn_LAMBDA).

280 Rev 4.0 The FLL control registers are described in Table 106 and Table 107. Example settings for a variety of reference frequencies and output frequencies are shown in Table 110. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R369 (0171h) FLL1 Control 1

0 FLL1_ENA 0 FLL1 Enable

0 = Disabled 1 = Enabled This should be set as the final step of the FLL1 enable sequence, ie. after the other FLL registers have been configured. R370 (0172h) FLL1 Control 2

15 FLL1_CTRL_UP

D

0 FLL1 Control Update

Write ‘1’ to apply the FLL1_N and FLL1_THETA register settings. (Only valid when FLL1_ENA=1) 9:0 FLL1_N [9:0] 008h FLL1 Integer multiply for FREF (LSB = 1) If updated while the FLL is enabled, the new value is only effective when a ‘1’ is written to FLL1_CTRL_UPD. R371 (0173h) FLL1 Control 3 15:0 FLL1_THETA [15:0] 0018h FLL1 Fractional multiply for FREF This field sets the numerator (multiply) part of the FLL1_THETA / FLL1_LAMBDA ratio. Coded as LSB = 1. If updated while the FLL is enabled, the new value is only effective when a ‘1’ is written to FLL1_CTRL_UPD. R372 (0174h) FLL1 Control 4 15:0 FLL1_LAMBDA [15:0] 007Dh FLL1 Fractional multiply for FREF This field sets the denominator (dividing) part of the FLL1_THETA / FLL1_LAMBDA ratio. Coded as LSB = 1. R373 (0175h) FLL1 Control 5 11:8 FLL1_FRATIO [3:0] 0h FLL1 FVCO clock divider 0h = 1 1h = 2 2h = 3 3h = 4 Fh = 16 3:1 FLL1_OUTDIV [2:0]

011 FLL1 FOUT clock divider

000 = Reserved 001 = Reserved 010 = Divide by 2 011 = Divide by 3 100 = Divide by 4 101 = Divide by 5 110 = Divide by 6 111 = Divide by 7 (FOUT = FVCO / FLL1_OUTDIV) R374 (0176h) FLL1 Control 6 7:6 FLL1_REFCLK_ DIV [1:0]

00 FLL1 Clock Reference Divider

00 = 1 01 = 2 10 = 4 11 = 8 MCLK (or other input reference) must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired.

Rev 4.0 281 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3:0 FLL1_REFCLK_S RC

0000 FLL1 Clock source

0000 = MCLK1 0001 = MCLK2 0011 = SLIMCLK 0100 = FLL1 0101 = FLL2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1100 = AIF1RXLRCLK 1101 = AIF2RXLRCLK 1110 = AIF3RXLRCLK All other codes are Reserved R377 (0179h) FLL1 Control 7 5:2 FLL1_GAIN [3:0] 0000 FLL1 Gain 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256 R385 (0181h) FLL1 Synchroni ser 1

0 FLL1_SYNC_EN

A

0 FLL1 Synchroniser Enable

0 = Disabled 1 = Enabled This should be set as the final step of the FLL1 synchroniser enable sequence, ie. after the other synchroniser registers have been configured. R386 (0182h) FLL1 Synchroni ser 2 9:0 FLL1_SYNC_N [9:0] 000h FLL1 Integer multiply for FSYNC (LSB = 1) R387 (0183h) FLL1 Synchroni ser 3 15:0 FLL1_SYNC_TH ETA [15:0] 0000h FLL1 Fractional multiply for FSYNC This field sets the numerator (multiply) part of the FLL1_SYNC_THETA / FLL1_SYNC_LAMBDA ratio. Coded as LSB = 1. R388 (0184h) FLL1 Synchroni ser 4 15:0 FLL1_SYNC_LA MBDA [15:0] 0000h FLL1 Fractional multiply for FSYNC This field sets the denominator (dividing) part of the FLL1_SYNC_THETA / FLL1_SYNC_LAMBDA ratio. Coded as LSB = 1. R389 (0185h) FLL1 Synchroni ser 5 10:8 FLL1_SYNC_FR ATIO [2:0]

000 FLL1 Synchroniser FVCO clock divider

000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16

282 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R390 (0186h) FLL1 Synchroni ser 6 7:6 FLL1_SYNCCLK _DIV [1:0]

00 FLL1 Synchroniser Clock Reference

00 = 1 01 = 2 10 = 4 11 = 8 MCLK (or other input reference) must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. 3:0 FLL1_SYNCCLK _SRC

0000 FLL1 Synchroniser Clock source

0000 = MCLK1 0001 = MCLK2 0011 = SLIMCLK 0100 = FLL1 0101 = FLL2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1100 = AIF1RXLRCLK 1101 = AIF2RXLRCLK 1110 = AIF3RXLRCLK All other codes are Reserved R391 (0187h) FLL1 Synchroni ser 7 5:2 FLL1_SYNC_GAI N [3:0]

0000 FLL1 Synchroniser Gain

0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256

0 FLL1_SYNC_DF

1 FLL1 Synchroniser Bandwidth

0 = Wide bandwidth 1 = Narrow bandwidth Table 106 FLL1 Register Map REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R401 (0191h) FLL2 Control 1

0 FLL2_ENA 0 FLL2 Enable

0 = Disabled 1 = Enabled This should be set as the final step of the FLL2 enable sequence, ie. after the other FLL registers have been configured. R402 (0192h) FLL2 Control 2

15 FLL2_CTRL_UP

D

0 FLL2 Control Update

Write ‘1’ to apply the FLL2_N and FLL2_THETA register settings. (Only valid when FLL2_ENA=1) 9:0 FLL2_N [9:0] 008h FLL2 Integer multiply for FREF (LSB = 1) If updated while the FLL is enabled, the new value is only effective when a ‘1’ is written to FLL2_CTRL_UPD.

Rev 4.0 283 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R403 (0193h) FLL2 Control 3 15:0 FLL2_THETA [15:0] 0018h FLL2 Fractional multiply for FREF This field sets the numerator (multiply) part of the FLL2_THETA / FLL2_LAMBDA ratio. Coded as LSB = 1. If updated while the FLL is enabled, the new value is only effective when a ‘1’ is written to FLL2_CTRL_UPD. R404 (0194h) FLL2 Control 4 15:0 FLL2_LAMBDA [15:0] 007Dh FLL2 Fractional multiply for FREF This field sets the denominator (dividing) part of the FLL2_THETA / FLL2_LAMBDA ratio. Coded as LSB = 1. R405 (0195h) FLL2 Control 5 11:8 FLL2_FRATIO [3:0] 0h FLL2 FVCO clock divider 0h = 1 1h = 2 2h = 3 3h = 4 Fh = 16 3:1 FLL2_OUTDIV [2:0]

110 FLL2 FOUT clock divider

000 = Reserved 001 = Reserved 010 = Divide by 2 011 = Divide by 3 100 = Divide by 4 101 = Divide by 5 110 = Divide by 6 111 = Divide by 7 (FOUT = FVCO / FLL2_OUTDIV) R406 (0196h) FLL2 Control 6 7:6 FLL2_REFCLK_ DIV [1:0]

00 FLL2 Clock Reference Divider

00 = 1 01 = 2 10 = 4 11 = 8 MCLK (or other input reference) must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. 3:0 FLL2_REFCLK_S RC

0000 FLL2 Clock source

0000 = MCLK1 0001 = MCLK2 0011 = SLIMCLK 0100 = FLL1 0101 = FLL2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1100 = AIF1RXLRCLK 1101 = AIF2RXLRCLK 1110 = AIF3RXLRCLK All other codes are Reserved

284 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R409 (0199h) FLL2 Control 7 5:2 FLL2_GAIN [3:0] 0000 FLL2 Gain 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256 R417 (01A1h) FLL2 Synchroni ser 1

0 FLL2_SYNC_EN

A

0 FLL2 Synchroniser Enable

0 = Disabled 1 = Enabled This should be set as the final step of the FLL2 synchroniser enable sequence, ie. after the other synchroniser registers have been configured. R418 (01A2h) FLL2 Synchroni ser 2 9:0 FLL2_SYNC_N [9:0] 000h FLL2 Integer multiply for FSYNC (LSB = 1) R419 (01A3h) FLL2 Synchroni ser 3 15:0 FLL2_SYNC_TH ETA [15:0] 0000h FLL2 Fractional multiply for FSYNC This field sets the numerator (multiply) part of the FLL2_SYNC_THETA / FLL2_SYNC_LAMBDA ratio. Coded as LSB = 1. R420 (01A4h) FLL2 Synchroni ser 4 15:0 FLL2_SYNC_LA MBDA [15:0] 0000h FLL2 Fractional multiply for FSYNC This field sets the denominator (dividing) part of the FLL2_SYNC_THETA / FLL2_SYNC_LAMBDA ratio. Coded as LSB = 1. R421 (01A5h) FLL2 Synchroni ser 5 10:8 FLL2_SYNC_FR ATIO [2:0]

000 FLL2 Synchroniser FVCO clock divider

000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 R422 (01A6h) FLL2 Synchroni ser 6 7:6 FLL2_SYNCCLK _DIV [1:0]

00 FLL2 Synchroniser Clock Reference

00 = 1 01 = 2 10 = 4 11 = 8 MCLK (or other input reference) must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired.

Rev 4.0 285 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3:0 FLL2_SYNCCLK _SRC

0000 FLL2 Synchroniser Clock source

0000 = MCLK1 0001 = MCLK2 0011 = SLIMCLK 0100 = FLL1 0101 = FLL2 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1100 = AIF1RXLRCLK 1101 = AIF2RXLRCLK 1110 = AIF3RXLRCLK All other codes are Reserved R423 (01A7h) FLL2 Synchroni ser 7 5:2 FLL2_SYNC_GAI N [3:0]

0000 FLL2 Synchroniser Gain

0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 to 1111 = 256

0 FLL2_SYNC_DF

1 FLL2 Synchroniser Bandwidth

0 = Wide bandwidth 1 = Narrow bandwidth Table 107 FLL2 Register Map FREE-RUNNING FLL MODE The FLL can generate a clock signal even when no external reference is available. This may be because the normal input reference has been interrupted , or may be during a standby or start-up period when no initial reference clock is available. Free-running FLL mode is enabled using the FLLn_FREERUN register. (Note that FLLn_ENA must also be enabled in Free-running FLL mode.) In Free -running FLL mode, the normal feedback mechanism of the FLL is halted, and the FLL oscillates independently of the external input reference(s). If the FLL was previously operating normal ly, (with an input refe rence clock ), then the FLL output frequency will remain unchanged when Free -running FLL mode is enabled. The FLL output will be independent of the input reference while operating in free-running mode with FLLn_FREERUN=1. The main FLL loop will always conti nue to free-run if the input reference clock is stopped (regardless of the FLLn_FREERUN setting). If FLLn_FREERUN=0, the FLL will re -lock to the input reference whenever it is available. In free -running mode, (with FLLn_FREERUN=1), the FLL integrator value (part of the feedback mechanism) can be commanded directly using the FLLn_FRC_INTEG_VAL register. The integrator value in this register is applied to the FLL when a ‘1’ is written to the FLLn_FRC_INTEG_UPD bit. If the FLL is started up in free -running mode, (ie. it was not previously running), then the default value of FLLn_FRC_INTEG_VAL will be applied. The FLL integrator value (part of the feedback mechanism) can be read from the FLLn_INTEG register; the value of this field may be stored for later use. Note that the readback value of the FLLn_INTEG register is only valid when FLLn_FREERUN=1, and the FLLn_INTEG_VALID bit is set. The FLL integrator setting does not ensure a specific output frequency for the FLL across all devices and operating conditions; some level of variation will apply. The free-running FLL clock may be selected as the SYSCLK source or ASYNCCLK source as shown Figure 69.

286 Rev 4.0 The control registers applicable to Free-running FLL mode are described in Table 108. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R369 (0171h) FLL1 Control 1

1 FLL1_FREERUN 1 FLL1 Free-Running Mode Enable

0 = Disabled 1 = Enabled The FLL feedback mechanism is halted in Free-Running mode, and the latest integrator setting is maintained R375 (0177h) FLL1 Loop Filter Test

15 FLL1_FRC_INTE

G_UPD

0 Write ‘1’ to apply the

FLL1_FRC_INTEG_VAL setting. (Only valid when FLL1_FREERUN=1) 11:0 FLL1_FRC_INTE G_VAL [11:0] 281h FLL1 Forced Integrator Value R376 (0178h) FLL1 NCO Test 0

15 FLL1_INTEG_VA

0 FLL1 Integrator Valid

Indicates if the FLL1_INTEG register is valid 0 = Not valid 1 = Valid 11:0 FLL1_INTEG [11:0] 000h FLL1 Integrator Value (Read-only) Indicates the current FLL1 integrator setting. Only valid when FLL1_INTEG_VALID = 1. R401 (0191h) FLL2 Control 1

1 FLL2_FREERUN 1 FLL2 Free-Running Mode Enable

0 = Disabled 1 = Enabled The FLL feedback mechanism is halted in Free-Running mode, and the latest integrator setting is maintained R407 (0197h) FLL2 Loop Filter Test

15 FLL2_FRC_INTE

G_UPD FLL2_FRC_INTEG_VAL setting. (Only valid when FLL2_FREERUN=1) 11:0 FLL2_FRC_INTE G_VAL [11:0] 000h FLL2 Forced Integrator Value R408 (0198h) FLL2 NCO Test 0

15 FLL2_INTEG_VA

0 FLL2 Integrator Valid

Indicates if the FLL2_INTEG register is valid 0 = Not valid 1 = Valid 11:0 FLL2_INTEG [11:0] 000h FLL2 Integrator Value (Read-only) Indicates the current FLL2 integrator setting. Only valid when FLL2_INTEG_VALID = 1. Table 108 Free-Running FLL Mode Control

Rev 4.0 287 SPREAD SPECTRUM FLL CONTROL The WM8281 can apply modulation to the FLL outputs, using spread spectrum techniques. This can be used to control the EMI characteristics of the circuits that are clocked via the FLLs. Each of the FLLs can be individually conf igured for Triangle modulation, Zero Mean Frequency Modulation (ZMFM) or Dither. The amplitude and frequency parameters of the spread spectrum functions is also programmable, using the registers described in Table 109. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R393 (0189h) FLL1 Spread Spectrum 5:4 FLL1_SS_AMPL [1:0]

00 FLL1 Spread Spectrum Amplitude

Controls the extent of the spread- spectrum modulation. 00 = 0.7% (triangle), 0.7% (ZMFM, dither) 01 = 1.1% (triangle), 1.3% (ZMFM, dither) 10 = 2.3% (triangle), 2.6% (ZMFM, dither) 11 = 4.6% (triangle), 5.2% (ZMFM, dither) 3:2 FLL1_SS_FREQ [1:0]

00 FLL1 Spread Spectrum Frequency

Controls the spread spectrum modulation frequency in Triangle mode. 00 = 439kHz 01 = 878kHz 10 = 1.17MHz 11 = 1.76MHz 1:0 FLL1_SS_SEL [1:0]

00 FLL1 Spread Spectrum Select

00 = Disabled 01 = Zero Mean Frequency (ZMFM) 10 = Triangle 11 = Dither R425 (01A9h) FLL2 Spread Spectrum 5:4 FLL2_SS_AMPL [1:0]

00 FLL2 Spread Spectrum Amplitude

Controls the extent of the spread- spectrum modulation. 00 = 0.7% (triangle), 0.7% (ZMFM, dither) 01 = 1.1% (triangle), 1.3% (ZMFM, dither) 10 = 2.3% (triangle), 2.6% (ZMFM, dither) 11 = 4.6% (triangle), 5.2% (ZMFM, dither) 3:2 FLL2_SS_FREQ [1:0]

00 FLL2 Spread Spectrum Frequency

Controls the spread spectrum modulation frequency in Triangle mode. 00 = 439kHz 01 = 878kHz 10 = 1.17MHz 11 = 1.76MHz 1:0 FLL2_SS_SEL [1:0]

00 FLL2 Spread Spectrum Select

00 = Disabled 01 = Zero Mean Frequency (ZMFM) 10 = Triangle 11 = Dither Table 109 FLL Spread Spectrum Control

288 Rev 4.0 FLL INTERRUPTS AND GPIO OUTPUT For each FLL, the WM8281 supports an ‘FLL Clock OK’ signal which, when asserted, indicates that the FLL has started up and is providing a n output clock. Each FLL also supports an ‘FLL Lock’ signal which indicates whether FLL Lock has been achieved (ie. the FLL is locked to the input reference signal). The FLL Clock OK status and FLL Lock status are inputs to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. Note that these Interrupt signals are de -bounced, and require clocking to be present in order to assert the respective Interrupt; either the 32kHz clock, or the SYSCLK signal, must be enabled to trigger an Interrupt from the FLL signals. The FLL Clock OK and FLL Lock signals can be output directly on a GPIO pin as an external indication of the FLL status. See “ General Purpose Input / Output ” to configure a GPIO pin for these functions. (These GPIO outputs are not de-bounced, and do not require clocking to be present.) Clock output signals derived from the FLL can be output on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for this function. The FLL clocking configuration is illustrated in Figure 71. EXAMPLE FLL CALCULATION The following example illustrates how to derive the FLL 1 registers to generate 147.456 MHz output (FOUT) from a 12.000 MHz reference clock (FREF):  Set FLL1_REFCLK_DIV in order to generate FREF <=13.5MHz: FLL1_REFCLK_DIV = 00 (divide by 1)  Set FLL1_OUTDIV for the required output frequency as shown in Table 102:- FOUT = 147.456 MHz, therefore FLL1_OUTDIV = 2h (divide by 2)  Set FLL1_FRATIO for the given reference frequency as shown in Table 103: FREF = 12MHz, therefore FLL1_FRATIO = 0h (divide by 1)  Calculate FVCO as given by FVCO = FOUT x FLL1_OUTDIV:- FVCO = 147.456 x 2 = 294.912 MHz  Calculate N.K as given by N.K = FVCO / (FLL1_FRATIO x 3 x FREF): N.K = 294.912 / (1 x 3 x 12) = 8.192  Confirm that a non-integer value has been calculated for N.K.  Confirm that the input frequency, FREF, is less than the applicable limit shown in Table 104.  Determine FLL1_N from the integer portion of N.K:- FLL1_N = 8 (008h)  Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FRATIO x FREF, FVCO / 3): GCD(FLL) = GCD(1 x 12000000, 294912000 / 3) = 96000  Determine FLL1_THETA, as given by FLL1_THETA = ((FVCO / 3) - (FLL1_N x FLL1_FRATIO x FREF)) / GCD(FLL): FLL1_THETA = ((294912000 / 3) - (8 x 1 x 12000000)) / 96000 FLL1_THETA = 24 (0018h)  Determine FLL_LAMBDA, as given by FLL1_LAMBDA = (FLL1_FRATIO x FREF) / GCD(FLL): FLL1_LAMBDA = (1 x 12000000) / 96000 FLL1_LAMBDA = 125 (007Dh)

Rev 4.0 289 EXAMPLE FLL SETTINGS Table 110 provides example FLL settings for generating 147.456MHz SYSCLK from a variety of low and high frequency reference inputs. FSOURCE FOUT (MHz) FREF Divider N.K FRATIO FVCO (MHz) OUTDIV FLLn_N FLLn_ THETA FLLn_ LAMBDA 32.000 kHz 147.456 1 204.8 15 294.912 2 0CCh 0004h 0005h 32.768 kHz 147.456 1 187.5 16 294.912 2 0BBh 0001h 0002h 48 kHz 147.456 1 136.5333 15 294.912 2 088h 0008h 000Fh 128 kHz 147.456 1 109.4173 7 294.912 2 06Dh 0005h 0007h 512 kHz 147.456 1 38.4 5 294.912 2 026h 0002h 0005h 1.536 MHz 147.456 1 21.3333 3 294.912 2 015h 0001h 0003h 3.072 MHz 147.456 1 10.6667 3 294.912 2 00Ah 0002h 0003h 11.2896 MHz 147.456 1 8.7075 1 294.912 2 008h 0068h 0093h 12.000 MHz 147.456 1 8.192 1 294.912 2 008h 0018h 007Dh 12.288 MHz 147.456 2 5.3333 3 294.912 2 005h 0001h 0003h 13.000 MHz 147.456 1 7.5618 1 294.912 2 007h 0391h 0659h 19.200 MHz 147.456 2 10.24 1 294.912 2 00Ah 0006h 0019h 24 MHz 147.456 2 8.192 1 294.912 2 008h 0018h 007Dh 26 MHz 147.456 2 7.5618 1 294.912 2 007h 0391h 0659h 27 MHz 147.456 2 7.2818 1 294.912 2 007h 013Dh 0465h FOUT = (FSOURCE / FREF Divider) * 3 * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above. See Table 106 and Table 107 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 110 Example FLL Settings Note that the odd -numbered FRATIO division is not possible on the FLL Synchroniser circuit. Table 111 provides alternative settings for the FLL Synchroniser for the affected examples. In all cases, note that the register coding of FLLn_FRATIO is different to FLLn_SYNC_FRATIO. FSOURCE FOUT (MHz) FREF Divider N.K FRATIO FVCO (MHz) OUTDIV FLLn_N FLLn_ THETA FLLn_ LAMBDA 32.000 kHz 147.456 1 192 16 294.912 2 0C0h 48 kHz 147.456 1 128 16 294.912 2 080h 128 kHz 147.456 1 96 8 294.912 2 060h 512 kHz 147.456 1 96 2 294.912 2 060h 1.536 MHz 147.456 1 64 1 294.912 2 040h 3.072 MHz 147.456 1 32 1 294.912 2 020h 12.288 MHz 147.456 1 8 1 294.912 2 008h FOUT = (FSOURCE / FREF Divider) * 3 * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above. See Table 106 and Table 107 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 111 Example FLL Synchroniser Settings

290 Rev 4.0 CONTROL INTERFACE The WM8281 is controlled by writing to its control registers. Readback is available for all registers. Two independent Control Interfaces are provided, giving flexible capability as described below. Note that t he SLIMbus interface also supports read/write access to the WM8281 control registers - see “SLIMbus Interface Control”. Note that the Control Interface function can be supported with or without system clocking. Where applicable, the register map access is synchronised with SYSCLK in order to ensure predictable operation of cross -domain functions. See “ Clocking and Sample Rates ” for furt her details of Control Interface clocking. When SYSCLK is present and enabled, register access is possible on all of the Control Interfaces (including SLIMbus) simultaneously. When SYSCLK is disabled, then register access will only be supported on whicheve r interface (I2C, SPI, or SLIMbus) is the first to attempt any register access after SYSCLK has stopped. Full access via all interfaces will be restored when SYSCLK is enabled. The WM8281 executes a Boot Sequence following Power -On Reset (POR), Hardware Re set, Software Reset or Wake -Up (from Sleep mode) . Note that Control Register writes should not be attempted until the Boot Sequence has completed. See “Power-On Reset (POR)” for further details. The WM8281 performs automatic checks to confirm that the control interface does not attempt a Read or Write operation to an invalid register address. The Control Interface Address Error condition can be monitored using the GPIO and/or Interrupt functions. See “ General Purpose Input / Output ” and “Interrupts” for further details. Control Interface 1 can be configured as a 2 -wire (I2C) interface or 4 -wire (SPI) interface. This is determined by the logic level on the CIF1MODE pin, as shown in Table 112. All of the CIF1 interface pins are referenced to the DBVDD1 power domain. CIF1MODE CONTROL INTERFACE MODE DESCRIPTION Logic 0 2-wire (I2C) mode CIF1SCLK is the interface clock input CIF1SDA is the bi-directional data pin Logic 1 4-wire (SPI) mode CIF1SCLK is the interface clock input CIF1MOSI is the data input pin CIF1MISO is the data output pin CIF1SS¯¯¯¯¯¯¯ is the ‘slave select’ input Table 112 Control Interface 1 Mode Selection The CIF1ADDR and CIF1SS¯¯¯¯¯¯¯ functions are implemented on a shared pin. In 2 -wire (I2C) mode, the CIF1ADDR input selects the Device ID, as described in Table 114. In 4-wire (SPI) mode, the CIF1SS¯¯¯¯¯¯¯ input provides the ‘Slave Select’ function. The CIF1MISO function shares the same pin as GPIO4 (see “General Purpose Input / Output ”). The CIF1MISO function is selected by default; this is determined by the SPI_GPIO register bit as described in Table 113. Control Interface 2 operates as a 2-wire (I2C) interface only. The CIF2 interface pins are referenced to the DBVDD2 power domain. A detailed description of the 2 -wire (I2C) interface and 4 -wire (SPI) interface modes is provided in the following sections. The Control Interface configuration registers are described in Table 113.

Rev 4.0 291 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R8 (08h) Ctrl IF SPI CFG 1

4 SPI_CFG 1 CIF1MISO pin configuration

(applies to SPI mode only) 0 = CMOS 1 = Wired ‘OR’.

3 SPI_GPIO 1 CIF1MISO / GPIO4 pin function select

0 = GPIO4 1 = CIF1MISO 1:0 SPI_AUTO_INC [1:0]

01 CIF1 SPI Address auto-increment select

00 = Disabled 01 = Increment by 1 on each access 10 = Increment by 2 on each access 11 = Increment by 3 on each access R9 (09h) Ctrl IF I2C1 CFG 1:0 I2C1_AUTO_IN C [1:0]

01 CIF1 I2C Address auto-increment select

00 = Disabled 01 = Increment by 1 on each access 10 = Increment by 2 on each access 11 = Increment by 3 on each access R10 (0Ah) Ctrl IF I2C2 CFG 1:0 I2C2_AUTO_IN C [1:0]

01 CIF2 I2C Address auto-increment select

00 = Disabled 01 = Increment by 1 on each access 10 = Increment by 2 on each access 11 = Increment by 3 on each access R11 (0Bh) Ctrl IF I2C1 CFG 6:0 I2C1_DEV_ID [6:0] 1Ah CIF1 Device ID (Read Only) Note that this 7-bit field identifies bits [7:1] of the CIF1 I2C device ID. The read/write bit is appended to these 7 bits. R12 (0Ch) Ctrl IF I2C2 CFG 6:0 I2C2_DEV_ID [6:0] 1Ah CIF2 Device ID Note that this 7-bit field identifies bits [7:1] of the CIF2 I2C device ID. The read/write bit is appended to these 7 bits. R3105 (0C21h) Misc Pad Ctrl 2

0 ADDR_PD 1 CIF1ADDR Pull-down enable

0 = Disabled 1 = Enabled Table 113 Control Interface Configuration 2-WIRE (I2C) CONTROL MODE The 2-wire (I2C) Control Interface mode is supported on CIF1 and CIF2, and uses the corresponding SCLK, SDA pins. The ADDR pin is also used to select the CIF1 Device ID. In 2-wire (I2C) mode, the WM8281 is a slave device on the control interface; SCLK is a clock input, while SDA is a bi -directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8281 transmits logic 1 by tri -stating the SDA pin, rather than pulling it high. An external pull -up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master. In order to allow many devices to share a single 2 -wire control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the address of each register in the WM8281). For Control Interface 1, the device ID is selectable using the CIF1ADDR pin, as described in Table 114. The LSB of the Device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”. The CIF1ADDR logic level is referenced to the DBVDD1 power domain. An internal pull -down resistor is enabled by default o n the CIF1ADDR pin; this can be configured using the ADDR_PD register bit described in Table 113.

292 Rev 4.0 CIF1ADDR DEVICE ID (CIF1) Logic 0 0011 010x = 34h (write) / 35h (read) Logic 1 0011 011x = 36h (write) / 37h (read) Table 114 Control Interface Device ID Selection For Control Interface 2, the device ID is selectable using the I2C2_DEV_ID control register, as described in Table 113. Note that this register identifies bits [7:1] of the CIF2 I2C device ID; the LSB of the Device ID is the Read/Write bit, as described above. Under default register conditions, the CIF2 device ID is 34h (write) / 35h (read). The WM8281 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDA while SCLK remains high. This indicates that a device ID, and subsequent address/data byte(s) will follow. The WM8281 responds to the start condition and shifts in the next eight bits on SDA (8-bit device ID , including Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8281, then the WM8281 responds by pulling SDA low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly , the WM8281 returns to the idle condition and waits for a new start condition and valid address. If the device I D matches the device ID of the WM8281, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDA while SCLK remains high. After receiving a complete address and data sequence the WM8281 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to the idle condition. The WM8281 supports the following read and write operations:  Single write  Single read  Multiple write (with optional auto-increment)  Multiple read (with optional auto-increment) The sequence of signals associated with a single register write operation is illustrated in Figure 72. A25D7 D1 A31SDA SCLK device ID register address A15 – A8 A24 A15 A8 Note: The SDA pin is used as input for the control register address and data; SDA is pulled low by the receiving device to provide the acknowledge (ACK) response R/W A9 A7 register address A31 – A24 register address A7 – A0 START (Write) ACK ACK ACK A17A23 A16 register address A23 – A16 ACK data bits B15 – B8 B15 B8 B1 B0B9 B7 data bits B7 – B0ACK ACK A1 A0 ACK STOP Figure 72 Control Interface 2-wire (I2C) Register Write

296 Rev 4.0 CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM8281 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the h ost processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. Default sequences for pop-suppressed start -up and shut -down of each headphone/earpiece output driver are provided (these are scheduled automatically when the respective output paths are enabled or disabled). Other control sequences can be programmed, and may be associated with Jack Detect , MICDET Clamp, DRC, Wake-Up or Sample Rate Detection functions - these sequences are automatically scheduled whenever a corresponding event is detected. When a sequence is initiated, the sequencer performs a series of pre -defined register writes. The ‘start index’ of a control sequence within the sequencer’s memory may be commanded directly by the host processor. The applicable ‘start index’ for each of the sequences associated with Jack Detect, MICDET Clamp, DRC, Wake -Up or Sample Rate Detection is held in a user -programmed control register. The Control Write Sequencer may be triggered in a number of ways, as described above. Multiple sequences will be queued if necessary, and each is scheduled in turn. When all of the queued sequences have completed, the sequencer stops, and an Interrupt status flag is asserted. A valid clock (SYSCLK) must be enabled whenever a Control Write Sequence is scheduled. See “Clocking and Sample Rates” for further details. INITIATING A SEQUENCE The Register fields associated with running the Control Write Sequencer are described in Table 116. The Write Sequencer is enabled using the WSEQ_ENA bit. The index location of the first command in the selected sequence is held in the WSEQ_START_INDEX register. Writing a ‘1’ to the WSEQ_START bit commands the sequencer to execute a control sequence, starting at the given index. Note that, if the sequencer is already running, then the WSEQ_START command will be queued, and will be executed later when the sequencer becomes available. Note that the mechanism for queuing multiple sequence requests has some limitations, when using the WSEQ_START bit to trigger the write sequencer. If a sequence is initiated using the WSEQ_START bit, no other control sequences should be triggered until the sequenc e completes. The WSEQ_BUSY bit (described in Table 121) provides an indication of the sequencer status, and can be used to confirm that sequence has completed. Contro l sequences triggered by another other method are queued if necessary, and scheduled in turn. The Write Sequencer can be interrupted by writing a ‘1’ to the WSEQ_ABORT bit. Note that this command will only abort a sequence that is currently running; if oth er sequence commands are pending and not yet started, these sequences will not be aborted by writing to the WSEQ_ABORT bit. The Write Sequencer stores up to 510 register write commands. These are defined in Registers R12288 (3000h) to R13307 (33FBh) . Each of the 51 0 possible commands is defined in 2 control registers - see Table 122 for a description of these registers. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R22 (0016h) Write Sequencer Ctrl 0

11 WSEQ_ABORT 0 Writing a 1 to this bit aborts the current

sequence.

10 WSEQ_START 0 Writing a 1 to this bit starts the write

sequencer at the index location selected by WSEQ_START_INDEX. At the end of the sequence, this bit will be reset by the Write Sequencer.

9 WSEQ_ENA 0 Write Sequencer Enable

0 = Disabled 1 = Enabled Only applies to sequences triggered using the WSEQ_START bit.

Rev 4.0 297 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8:0 WSEQ_START_I NDEX [8:0] 000h Sequence Start Index This field contains the index location in the sequencer memory of the first command in the selected sequence. Only applies to sequences triggered using the WSEQ_START bit. Valid from 0 to 509 (1FDh). Table 116 Write Sequencer Control - Initiating a Sequence AUTOMATIC SAMPLE RATE DETECTION SEQUENCES The WM8281 supports automatic sample rate detection on the digital audio interfaces (AIF1, AIF2 and AIF3), when operating in AIF Slave mode. Automatic sample rate detection is enabled using the RATE_EST_ENA register bit (see Table 101). Up to four audio sample rates can be configured for automatic detection; these sample rates are selected using the SAMPLE_RATE_DETECT_n registers. If one of the selected audio sample rates is detected, then the Control Write Sequencer will be triggered. The applicable start index location within the sequencer memory is separately configurable for each detected sample rate. The WSEQ_SAMPLE_RATE_DETECT_A_ INDEX register defines the sequencer start in dex corresponding to the SAMPLE_RATE_DETECT_A sample rate. Equivalent start index values are defined for the other sample rates, as described in Table 117. Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted. The automatic sample rate detection control sequences are undefined following Power -On Reset (POR), but can be user -programmed after power -up. Note that all control sequences are maintained in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode. See “Clocking and Sample Rates” for further details of the automatic sample rate detection function. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R97 (0061h) Sample Rate Sequence Select 1 8:0 WSEQ_SAMPLE _RATE_DETECT _A_INDEX [8:0] 1FFh Sample Rate A Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with Sample Rate A detection. Valid from 0 to 509 (1FDh) R98 (0062h) Sample Rate Sequence Select 2 8:0 WSEQ_SAMPLE _RATE_DETECT _B_INDEX [8:0] 1FFh Sample Rate B Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with Sample Rate B detection. Valid from 0 to 509 (1FDh) R99 (0063h) Sample Rate Sequence Select 3 8:0 WSEQ_SAMPLE _RATE_DETECT _C_INDEX [8:0] 1FFh Sample Rate C Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with Sample Rate C detection. Valid from 0 to 509 (1FDh) R100 (0064h) Sample Rate Sequence Select 4 8:0 WSEQ_SAMPLE _RATE_DETECT _D_INDEX [8:0] 1FFh Sample Rate D Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with Sample Rate D detection. Valid from 0 to 509 (1FDh) Table 117 Write Sequencer Control - Automatic Sample Rate Detection

298 Rev 4.0 JACK DETECT, GPIO, MICDET CLAMP, AND WAKE-UP SEQUENCES The WM8281 supports external accessory detection and GPIO functions. The JD1 signal (associated with external accessory detection) and the GP5 signal (associated with the GPIO5 pin) can be used to trigger the Control Write Sequencer. The JD1 signal is configured using the register bits described in Table 75. The GP5 signal is derived from the GPIO5 pin, which is configured using the register bits described in Table 86. The MICDET Clamp is controlled by the JD1 and/or GP5 signals, as described in Table 76. The MICDET Clamp status can also be used to trigger the Control Write Sequencer. A Control Write Sequence can be associated with a rising edge and/or a falling edge of the JD1, GP5 or MICDET Clamp. This is configured using the register bits described in Table 85. If one of the selected logic conditions is detected , the Control Write Sequencer will be triggered. The applicable start index location within the sequencer memory is separately configurable for each logic condition. The WSEQ_GP5_RISE_ INDEX register defines the sequencer start index corresponding to a GP5 Rising Edge event. Equivalent start index values are defined for the other logic conditions, as described in Table 118. Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted. The JD1, GP5 and MICDET Clamp control sequences are undefine d following Power -On Reset (POR), but can be user -programmed after power -up. Note that all control sequences are maintained in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode. See “Low Power Sleep Configuration ” for further details of the JD1, GP5 and MICDET Clamp status signals. See also “General Purpose Input / Output” for details of the GPIO5 pin. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R102 (0066h) Always On Triggers Sequence Select 1 8:0 WSEQ_MICD_CL AMP_RISE_INDE X [8:0] 1FFh MICDET Clamp (Rising) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with MICDET Clamp (Rising) detection. Valid from 0 to 509 (1FDh) R103 (0067h) Always On Triggers Sequence Select 2 8:0 WSEQ_MICD_CL AMP_FALL_INDE X [8:0] 1FFh MICDET Clamp (Falling) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with MICDET Clamp (Falling) detection. Valid from 0 to 509 (1FDh) R104 (0068h) Always On Triggers Sequence Select 3 8:0 WSEQ_GP5_RIS E_INDEX [8:0] 1FFh GP5 (Rising) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with GP5 (Rising) detection. Valid from 0 to 509 (1FDh) R105 (0069h) Always On Triggers Sequence Select 4 8:0 WSEQ_GP5_FAL L_INDEX [8:0] 1FFh GP5 (Falling) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with GP5 (Falling) detection. Valid from 0 to 509 (1FDh) R106 (006Ah) Always On Triggers Sequence Select 5 8:0 WSEQ_JD1_RIS E_INDEX [8:0] 1FFh JD1 (Rising) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with JD1 (Rising) detection. Valid from 0 to 509 (1FDh)

Rev 4.0 299 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R107 (006Bh) Always On Triggers Sequence Select 6 8:0 WSEQ_JD1_FAL L_INDEX [8:0] 1FFh JD1 (Falling) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with JD1 (Falling) detection. Valid from 0 to 509 (1FDh) Table 118 Write Sequencer Control - JD1, GP5 and MICDET Clamp A valid clock (SYSCLK) must be enabled whenever a Control Write Sequence is scheduled. If the JD1, GP5 or MICDET Clamp trigger status bits are associated with the Control Write Sequencer (using the register bits in Table 85) and also configured as Wake -Up events (using the register bits in Table 84), then the Boot Sequence must be programmed to configure and enable SYSCLK. (Note that the default SYSCLK frequency must be used in this case.) The Boot Sequence (see below) is scheduled as part of the Wake -Up transition, and provide s the capability to configure SYSCLK (and other register settings) prior to the Control Write Sequencer being triggered. Note that, if the Control Write Sequencer is triggered during normal operation, then SYSCLK will typically be already available, and no additional requirements will apply. DRC SIGNAL DETECT SEQUENCES The Dynamic Range Control (DRC) function within the WM8281 Digital Core provides a configurable signal detect function. This allows the signal level at the DRC input to be monitored and used to trigger other events. The DRC Signal Detect function s are enabled and configured using the register fields described in Table 15 and Table 16 for DRC1 and DRC2 respectively. A Control Write Sequence can be associated with a rising edge and/or a falling edge of the DRC 1 Signal Detect output. This is enabled using the DRC1_WSEQ_SIG_DET_ENA register bit. Note that signal detection is supported on DRC1 and DRC2, but the triggering of the Control Write Sequencer is available on DRC1 only. When the DRC Signal Detect sequence is enabled, the Control Write Sequencer will be triggered whenever the DRC1 Signal Detect output transitions (high or low). The applicable start index location within the sequencer memory is separately configurable for each logic condition. The WSEQ_ DRC1_SIG_DET_RISE_SEQ_INDEX register defines the sequencer start index corresponding to a DRC 1 Signal Detect Rising Edge event, as described in Table 119. The WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX register defines the sequencer start index corresponding to a DRC1 Signal Detect Falling Edge event. Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted. The DR C Signal Detect sequences cannot be independently enabled for rising and falling edges. Instead, a start index of 1FFh can be used to disable the sequence for either edge, if required. The DRC Signal Detect control sequences are undefined following Power -On Reset (POR), but can be user-programmed after power-up. Note that all control sequences are maintained in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode. See “Digital Core” for further details of the Dynamic Range Control (DRC) function.

300 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R110 (006Eh) Trigger Sequence Select 32 8:0 WSEQ_DRC1_SI G_DET_RISE_IN DEX [8:0] 1FFh DRC1 Signal Detect (Rising) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with DRC1 Signal Detect (Rising) detection. Valid from 0 to 509 (1FDh). R111 (006Fh) Trigger Sequence Select 33 8:0 WSEQ_DRC1_SI G_DET_FALL_IN DEX [8:0] 1FFh DRC1 Signal Detect (Falling) Write Sequence start index This field contains the index location in the sequencer memory of the first command in the sequence associated with DRC1 Signal Detect (Falling) detection. Valid from 0 to 509 (1FDh). Table 119 Write Sequencer Control - DRC Signal Detect BOOT SEQUENCE The WM8281 executes a Boot Sequence following Power -On Reset (POR) , Hardware Reset , Software Reset or Wake-Up (from Sleep mode). See “Power-On Reset (POR) ” and “ Hardware Reset, S oftware Reset, Wake-Up, and Device ID ” for further details. The Boot Sequence configures the WM8281 with factory-set trim (calibration) data. Space is allocated within the Boot Sequence memory to allow user -configurable register operations to be added (eg. to automatically enable SYSCLK as part of the Boot Sequence). Further details of the sequencer memory are provided later in this section. Note that all control sequences are maintained in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode. If the Boot Sequence is programmed to enable SYSCLK, note that the default SYSCLK frequency must be used. If a different SYSCLK frequency is required, this must be configured after the Boot Sequence has completed. The start index location of the the Boot Sequence is 384 (180h). Index locations 384 (180h) to 399 (18Fh) are available for any user-configured Boot Sequence requirements. The Boot Sequence can be commanded at any time by writing ‘1’ to the WSEQ_BOOT_START bit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (0018h) Write Sequencer Ctrl 2

1 WSEQ_BOOT_S

0 Writing a 1 to this bit starts the write

sequencer at the index location configured for the Boot Sequence. The Boot Sequence start index is 384 (180h). Table 120 Write Sequencer Control - Boot Sequence SEQUENCER OUTPUTS AND READBACK The status of the Write Sequencer can be read using the WSEQ_BUSY and WSEQ_CURRENT_INDEX registers, as described in Table 121. When the WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. The index address of the most recent Write Sequencer command can be read from the WSEQ_CURRENT_INDEX fiel d. This can be used to provide a precise indication of the Write Sequencer progress.

Rev 4.0 301 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R23 (0017h) Write Sequencer Ctrl 1

9 WSEQ_BUSY

(read only) 0 Sequencer Busy flag (Read Only). 0 = Sequencer idle 1 = Sequencer busy 8:0 WSEQ_CURREN T_INDEX [8:0] (read only) 000h Sequence Current Index. This indicates the memory location of the most recently accessed command in the write sequencer memory. Coding is the same as WSEQ_START_INDEX. Table 121 Write Sequencer Control - Status Readback The Write Sequencer status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The Write Sequencer status can be output directly on a GPIO pin as an external indication of the Write Sequencer. See “General Purpose Input / Output” to configure a GPIO pin for this function. PROGRAMMING A SEQUENCE A Control Write Sequence comprises a series of write operations to data bits (or groups of bits) within the control register map. Each write operation is defined by a block of 2 registers, each containing 5 fields, as described below. The block of 2 registers is replicated 510 times, defining each of the sequencer ’s 510 possible index addresses. Many sequences can be stored in the sequencer memory at the same time , with each assigned a unique range of index addresses. The WSEQ_DELAYn register is used to identify the ‘end of sequence’ position, as described below. Note that, in the following descriptions, the term ‘n’ denotes the sequencer index address (valid from 0 to 509). WSEQ_DATA_WIDTHn is a 3-bit field which identifies the width o f the data block to be written. Note that the maximum value of this field selects a width of 8-bits; writing to register fields greater than 8 bits wide must be performed using two separate operations of the Write Sequencer. WSEQ_ADDRn is a 13-bit field containing the register address in which the data should be written. WSEQ_DELAYn is a 4-bit field which controls the waiting time between the current step and the next step in the sequence (ie. the delay occurs after the write in which it was called ). The total delay time per step (including execution) is defined below, giving a useful range of execution/delay times from 3.3s up to 1s per step. Setting this field to 0xF identifies the step as the last in the sequence. If WSEQ_DELAYn = 0h or Fh, the step execution time is 3.3µs For all other values, the step execution time is 61.44µs x ((2 WSEQ_DELAY ) - 1) WSEQ_DATA_STARTn is a 4 -bit field which identifies the LSB position within the selected control register to which the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 will select bit 4 as the LSB position of the data to be written. WSEQ_DATAn is an 8 -bit field which con tains the data to be written to the selected c ontrol register. The WSEQ_DATA_WIDTH n field determines how many of these bits are written to the selected control register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTH n) are ignored. The register definitions for Step 0 are described in Table 122. The equivalent definitions also apply to Step 1 through to Step 509, in the subsequent register address locations.

302 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R12288 (3000h) WSEQ Sequence 1 15:13 WSEQ_DATA_ WIDTH0 [2:0]

000 Width of the data block written in this

sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 12:0 WSEQ_ADDR0 [12:0] 0000h Control Register Address to be written to in this sequence step. R12289 (3001h) WSEQ Sequence 2 15:12 WSEQ_DELAY0 [3:0] 0000 Time delay after executing this step. 00h = 3.3us 01h to 0Eh = 61.44us x ((2^WSEQ_DELAY)-1) 0Fh = End of sequence marker 11:8 WSEQ_DATA_S TART0 [3:0]

0000 Bit position of the LSB of the data

block written in this sequence step. 0000 = Bit 0 1111 = Bit 15 7:0 WSEQ_DATA0 [7:0] 00h Data to be written in this sequence step. When the data width is less than 8 bits, then one or more of the MSBs of WSEQ_DATAn are ignored. It is recommended that unused bits be set to 0. Table 122 Write Sequencer Control - Programming a Sequence SEQUENCER MEMORY DEFINITION The Write Sequencer memory defines up to 510 write operations; these are indexed as 0 to 509 in the sequencer memory map. Following Power -On Reset (POR), the sequence memory will contain the Boot Sequence, and the OUT1, OUT2, OUT3, OUT4 signal path enable/d isable sequences. The remainder of the sequence memory will be undefined on power -up. See the “ Applications Information” section for a summary of the WM8281 memory reset conditions. User-defined sequences can be programmed after power -up. Note that all control sequences are maintained in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode. The default control sequences can be overwritten in the sequencer memory, if required. Note that the headphone and earpiece output path enable registers (HPnx_ENA , SPKOUTx_ENA) will always trigger the Write Sequencer (at the pre-determined start index addresses). Writing ‘1’ to the WSEQ_LOAD_MEM bit will clear the sequencer memory to the POR state. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (0018h) Write Sequencer Ctrl 2

0 WSEQ_LOAD_

0 Writing a 1 to this bit resets the

sequencer memory to the POR state. Table 123 Write Sequencer Control - Load Memory Control User-defined sequences must be assigned space within the Write Sequencer memory. The start index for the user -defined sequences is configured using the registers described in Table 117 and Table 118.

Rev 4.0 303 The start index location of the the Boot Sequence is 384 (180h), as shown in Table 120. Index locations 385 (181h) to 391 (187h) are available for any user -configured Boot Sequence requirements. The remainder of the Boot Sequence memory (including index location 384) should not be written to. The sequencer memory is illustrated in Figure 81. The pre -programmed sequencer index locations are highlighted. User -defined sequences should be programmed in other areas of the sequencer memory. 000h 020h 040h 060h 0A0h 0C0h 0E0h 100h 140h 160h 180h 1A0h 1E0h 080h 120h 1C0h HPOUT1L enable HPOUT1R enable HPOUT2L enable HPOUT2R enable HPOUT2R disable HPOUT1L disable HPOUT1R disable HPOUT2L disable Index Description HPOUT3L enable HPOUT3R enable HPOUT3R disable HPOUT3L disable Boot Sequence (User space): 181h to 187h SPKOUTL/R enable/disable (4 sequences) Reserved memory space: 180h, and 188h to 1BEh Figure 81 Write Sequencer Memory

304 Rev 4.0 Further details of the pre-programmed sequencer index locations are provided in Table 124. SEQUENCE NAME START INDEX DEFAULT SEQUENCE INDEX RANGES HPOUT1L Enable 0 (000h) 0 to 30 HPOUT1L Disable 31 (01Fh) 31 to 38 HPOUT1R Enable 40 (028h) 40 to 70 HPOUT1R Disable 447 (1BFh) 447 to 454 HPOUT2L Enable 80 (050h) 80 to 110 HPOUT2L Disable 455 (1C7h) 455 to 462 HPOUT2R Enable 120 (078h) 120 to 150 HPOUT2R Disable 463 (1CFh) 463 to 470 HPOUT3L Enable 160 (0A0h) 160 to 190 HPOUT3L Disable 471 (1D7h) 471 to 478 HPOUT3R Enable 200 (0C8h) 200 to 230 HPOUT3R Disable 479 (1DFh) 479 to 486 SPKOUTL Enable 490 (1EAh) 490 to 497 SPKOUTL Disable 487 (1E7h) 487 to 489 SPKOUTR Enable 498 (1F2h) 498 to 505 SPKOUTR Disable 507 (1FBh) 507 to 509 Boot Sequence 384 (180h) 384 (Reserved) 385 to 391 (User space) 392 to 446 (Reserved) Table 124 Default Sequencer Memory Allocation

Rev 4.0 305 CHARGE PUMPS, REGULATORS AND VOLTAGE REFERENCE The WM8281 incorporates two Charge Pump circuits and two LDO Regulator circuits to generate supply rails for internal functions and to support external microphone require ments. The WM8281 also provides three MICBIAS generators which provide low noise reference voltages suitable for biasing electret condenser (ECM) type microphones or powering digital microphones. Refer to the “Applications Information” section for recommended external components. CHARGE PUMPS AND LDO2 REGULATOR Charge Pump 1 (CP1) is used to generate the positive and negative supply rails for the analogue output drivers. CP1 is enabled automatically by the WM8281 when required by the output drivers. Charge Pump 2 (CP2) powers LDO2, which provides the supply rail for analogue input circuits and for the MICBIAS generators. CP2 and LDO2 are enabled using the CP2_ENA register bit. The 32kHz clock must be configured and enabled when using CP2. See “Clocking and Sample Rates” for details of the system clocks. When CP2 and LDO2 are enabled, the MICVDD voltage can be selected using the LDO2_VSEL control field. Note that, when one or more of the MICBIAS generators is operating in normal (regulator) mode, then the MICVDD voltage must be at least 200mV greater than the highest selected MICBIASn output voltage(s). When CP2 and LDO2 are enabled, an internal bypass path may be selected, connecting the MICVDD pin directly to the CPVDD supply. This path i s controlled using the CP2_BYPASS register. Note that the bypass path is only supported when CP2 is enabled. When CP2 is disabled, the CP2VOUT pin can be configured to be floating or to be actively discharged. This is selected using the CP2_DISCH register bit. When LDO2 is disabled, the MICVDD pin can be configured to be floating or to be actively discharged. This is selected using the LDO2_DISCH register bit. The MICVDD pin is connected to the output of LDO2. Note that the MICVDD does not support direct connection to an external supply; MICVDD is always powered internally to the WM8281. The Charge Pumps and LDO2 Regulator circuits are illustrated in Figure 82. The associated register control bits are descrbed in Table 125. Note that decoupling capacitors and flyback capacitors are required for these circuits. Refer to the “Applications Information” section for recommended external components.

306 Rev 4.0 MICROPHONE BIAS (MICBIAS) CONTROL There are three MICBIAS generators which provide low noise reference voltages suitable for biasing electret condenser (ECM) type microphones or powering digital microphones . Refer to the “Applications Information” section for recommended external components. The MICBIAS generators are powered from MICVDD, which is generated by an internal Charge Pump and LDO, as illustrated in Figure 82. The MICBIAS outputs can be independently enabled using the MICBn_ENA register bits (where n = 1, 2 or 3 for MICBIAS1, 2 or 3 respectively). When a MICBIAS output is disabled, the output pin ca n be configured to be floating or to be actively discharged. This is selected using the MICBn_DISCH register bits. The MICBIAS generators can each operate as a voltage regulator or in bypass mode. The applicable mode is selected using the MICBn_BYPASS registers. In Regulator mode, the output voltage is selected using the MICB n_LVL register bits . In this mode, MICVDD must be at least 200mV greater than the required MICBIAS output voltages. The MICBIAS outputs are powered from the MICVDD pin, and use the internal bandgap circuit as a reference. In Regulator mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. The regulators can be configured to support a capacitive load if required, using the MICBn_EXT_CAP register b its. (This may be appropriate for a digital microphone supply.) It is important that the external capacitance is compatible with the applicable MICBn_EXT_CAP setting. The compatible load conditions are detailed in the “Electrical Characteristics” section. In Bypass mode, the output pin (MICBIAS1, MICBIAS2 or MICBIAS3) is connected directly to MICVDD. This enables a low power operating state. Note that the MICBn_EXT_CAP register settings are not applicable in Bypass mode ; there are no restrictions on the external MICBIAS capacitance in Bypass mode. The MICBIAS generators incorporate a pop -free control circuit to ensure smooth transitions when the MICBIAS outputs are enabl ed or disabled in Bypass mode; this feature is enabled using the MICBn_RATE registers. The MICBIAS generators are illustrated in Figure 82. The MICBIAS control regist er bits are descrbed in Table 125. The maximum output current for each MICBIAS n pin is noted in the “ Electrical Characteristics”. This limit must be observed on each MICBIAS output, especially if more than one microphone is connected to a single MICBIAS pin. Note that the maximum output current differs between Regulator mode and Bypass mode. VOLTAGE REFERENCE CIRCUIT The WM8281 incorporates a voltage reference circuit, powered by AVDD. This circuit ensures the accuracy of the LDO Regulator and MICBIAS voltage settings.

Rev 4.0 307 LDO1 REGULATOR AND DCVDD SUPPLY The LDO1 voltage regulator is intended for generating the DCVDD domain, which powers the digital core functions on the WM8281. In this configuration, the LDO output (LDOVOUT) should be connected to the DCVDD pin. Note that the use of the LDO1 regulator to power external circuits cannot be supported by the WM8281. LDO1 is powered by LDOVDD and can be controlled using hardware or software controls. Note that, depending on the application requirements, it may be necessary to use both the hardware and software enables for LDO1, as described below. Under hardware control, LDO1 is enabled when a logic ‘1’ is applied to the LDO ENA pin. The logic level is determined with respect to the DBVDD1 voltage domain . LDO1 is also enabled when the LDO1_ENA software control re gister is set to 1. Note that, to disable LDO1, the hardware and software controls must both be de-asserted. When LDO1 is enabled, the LDOVOUT voltage can be selected using the LDO 1_VSEL control field. Note that the default output voltage should always be used for normal operation. For correct Sleep mode behaviour, the LDOVOUT voltage should be reduced to 1.175V immediately before entering Sleep mode. See Table 125 for further details. See also “Low Power Sleep Configuration”. When LDO1 is disabled, the LDOVOUT pin can be configured to be floating or to be actively discharged. This is selected using the LDO1_DISCH register bit. It is possible to supply DCVDD from an external supply . In this configuration, the LDOVOUT pin should be left floating; it must not be connected to the DCVDD pin . The LDO1 regulator is not used in this case, and must be disabled at all times. For recommended use of the Sleep / Wake -Up functions (see “ Low Power Sleep Configuration ”), it is assumed that DCVDD is powered from the output of LDO1. In this case, Sleep mode is selected when LDO1 is disabled, causing the DCVDD supply to be removed . Note that the AVDD, DBVDD1, and LDOVDD supplies must be present throughout the Sleep mode duration. If DCVDD is powered externally (not from LDO1), then the ISOLATE_DCVDD1 register bit must be controlled as described in Table 125 when selecting WM8281 Sleep mode. In this case, Sleep mode is selected by setting the ISOLATE_DCVDD1 register bit, and then removing the DCVDD supply. For applications where DCVDD is powered externally, only the AVDD and DBVDD1 supplies are required in Sleep mode. An internal pull-down resistor is enabled by default on the LDOENA pin. This is configurable using the LDO1ENA_PD register bit. A pull-up resistor is also available, as described in Table 125. When the pull-up and pull-down resistors are both enabled, the WM8281 provides a ‘bus keeper’ function on the LDOENA pin. The bus keeper function holds the input logic level unchanged whenever the external circuit removes the drive (eg. if the signal is tri-stated). If DCVDD is powered from LDO1, then a logic ‘1’ must be applied to the LDOENA pin during power - up, to enable LDO1. The LDO must also be enabled using the LDOENA pin following a Hardware Reset or Software Reset, to allow the device to re -start. (It is recommended t hat the LDOENA pin is asserted before any reset, and is held at logic ‘1’ until after the reset is complete; this ensures the DSP firmware memory contents can be retained, and also allows faster reset time.) For normal operation following Power -On Reset (P OR), Hardware Reset, or Software Reset, LDO1 must be enabled using the hardware or software controls described above. Note that when the LDO1_ENA bit is set to 1, the LDOENA pin has no effect and may be de -asserted - the LDO is then under software control, allowing Sleep mode to be selected under register control, including via the Control Write Sequencer. See “Power-On Reset (POR) ” and “ Hardware Reset, S oftware Reset, Wake-Up, and Device ID ” for details of WM8281 Resets. See also “Low Power Sleep Configuration” for details of the Sleep / Wake- up functions. The LDO1 Regulator circuit is illustrated in Figure 82. The associated register control bits are described in Table 125. Note that the LDO output requires an external decoupling capacitor ; this requirement is typically achieved via decoupling on the DCVDD pins . Refer to the “Applications Information” section for recommended external components.

308 Rev 4.0 BLOCK DIAGRAM AND CONTROL REGISTERS The Charge Pump and Regulator circuits are illustrated in Figure 82. Note that decoupling capacitors and flyback capa citors are required for these circuits. Refer to the “ Applications Information” section for recommended external components. Analogue output supplyCPVDD CPGND AGND LDO 1 LDOVDD LDOENA Digital Core supply LDOVOUT DGND VREFC Analogue reference LDO1_ENA LDO1_VSEL[5:0] LDO1_DISCH LDO1ENA_PD LDO1ENA_PU MICBIAS2 MICBIAS1 MICB1_ENA MICB1_BYPASS MICB1_LVL[3:0] MICB1_RATE MICB1_DISCH MICB1_EXT_CAP MICB2_ENA MICB2_BYPASS MICB2_LVL[3:0] MICB2_RATE MICB2_DISCH MICB2_EXT_CAP MICBIAS3 MICB3_ENA MICB3_BYPASS MICB3_LVL[3:0] MICB3_RATE MICB3_DISCH MICB3_EXT_CAP DCVDD LDO2_VSEL[5:0] LDO2_DISCH CP2CA CP2VOUT CP2CB Charge Pump 1 CP2_ENA CP2_BYPASS CP2_DISCH LDO1 may be used to generate the DCVDD supply. In this case, the LDOVOUT pin must be connected to the DCVDD pin. Analogue input supply Voltage Reference AVDD Analogue supply MICVDD CP1C1A CP1C2A CP1VOUT2P CP1VOUT2N CP1VOUT1P CP1VOUT1N CP1C1B CP1C2B Charge Pump 2 LDO2 Figure 82 Charge Pumps and Regulators REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R512 (0200h) Mic Charge Pump 1

2 CP2_DISCH 1 Charge Pump 2 Discharge

0 = CP2VOUT floating when disabled 1 = CP2VOUT discharged when disabled

1 CP2_BYPASS 1 Charge Pump 2 and LDO2 Bypass Mode

0 = Normal 1 = Bypass mode In Bypass mode, CPVDD is connected directly to MICVDD. Note that CP2_ENA must also be set.

Rev 4.0 309 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 CP2_ENA 1 Charge Pump 2 and LDO2 Control

(Provides analogue input and MICVDD supplies) 0 = Disabled 1 = Enabled R528 (0210h) LDO1 Control 1 10:5 LDO1_VSEL [5:0] 0Ch LDO1 Output Voltage Select 0Bh = 1.175V 0Ch = 1.200V For normal operation, select 1.2V. For sleep mode, select 1.175V as the last register write before entering Sleep mode. Under recommended operating conditions, the LDO will return to 1.2V automatically following Wake-Up from Sleep mode. All other codes are Reserved

2 LDO1_DISCH 1 LDO1 Discharge

0 = LDOVOUT floating when disabled 1 = LDOVOUT discharged when disabled

0 LDO1_ENA 0 LDO1 Control

0 = Disabled 1 = Enabled R531 (0213h) LDO2 Control 1 10:5 LDO2_VSEL [5:0] 1Fh LDO2 Output Voltage Select 00h = 0.900V 01h = 0.925V 02h = 0.950V … (25mV steps) 13h = 1.375V 14h = 1.400V 15h = 1.500V 16h = 1.600V … (100mV steps) 26h = 3.200V 27h to 3Fh = 3.300V (See Table 126 for voltage range)

2 LDO2_DISCH 1 LDO2 Discharge

0 = MICVDD floating when disabled 1 = MICVDD discharged when disabled R536 (218h) Mic Bias Ctrl 1

15 MICB1_EXT_CA

P

0 Microphone Bias 1 External Capacitor

(when MICB1_BYPASS = 0). Configures the MICBIAS1 regulator according to the specified capacitance connected to the MICBIAS1 output. 0 = No external capacitor 1 = External capacitor connected 8:5 MICB1_LVL [3:0] 7h Microphone Bias 1 Voltage Control (when MICB1_BYPASS = 0) 0h = 1.5V 1h = 1.6V … (0.1V steps) Ch = 2.7V Dh to Fh = 2.8V

3 MICB1_RATE 0 Microphone Bias 1 Rate (Bypass mode)

0 = Fast start-up / shut-down 1 = Pop-free start-up / shut-down

2 MICB1_DISCH 1 Microphone Bias 1 Discharge

0 = MICBIAS1 floating when disabled 1 = MICBIAS1 discharged when disabled

310 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

1 MICB1_BYPASS 1 Microphone Bias 1 Mode

0 = Regulator mode 1 = Bypass mode

0 MICB1_ENA 0 Microphone Bias 1 Enable

0 = Disabled 1 = Enabled R537 (219h) Mic Bias Ctrl 2

15 MICB2_EXT_CA

P

0 Microphone Bias 2 External Capacitor

(when MICB2_BYPASS = 0). Configures the MICBIAS2 regulator according to the specified capacitance connected to the MICBIAS2 output. 0 = No external capacitor 1 = External capacitor connected 8:5 MICB2_LVL [3:0] 7h Microphone Bias 2 Voltage Control (when MICB2_BYPASS = 0) 0h = 1.5V 1h = 1.6V … (0.1V steps) Ch = 2.7V Dh to Fh = 2.8V

3 MICB2_RATE 0 Microphone Bias 2 Rate (Bypass mode)

0 = Fast start-up / shut-down 1 = Pop-free start-up / shut-down

2 MICB2_DISCH 1 Microphone Bias 2 Discharge

0 = MICBIAS2 floating when disabled 1 = MICBIAS2 discharged when disabled

1 MICB2_BYPASS 1 Microphone Bias 2 Mode

0 = Regulator mode 1 = Bypass mode

0 MICB2_ENA 0 Microphone Bias 2 Enable

0 = Disabled 1 = Enabled R538 (21Ah) Mic Bias Ctrl 3

15 MICB3_EXT_CA

P

0 Microphone Bias 3 External Capacitor

(when MICB3_BYPASS = 0). Configures the MICBIAS3 regulator according to the specified capacitance connected to the MICBIAS3 output. 0 = No external capacitor 1 = External capacitor connected 8:5 MICB3_LVL [3:0] 7h Microphone Bias 3 Voltage Control (when MICB3_BYPASS = 0) 0h = 1.5V 1h = 1.6V … (0.1V steps) Ch = 2.7V Dh to Fh = 2.8V

3 MICB3_RATE 0 Microphone Bias 3 Rate (Bypass mode)

0 = Fast start-up / shut-down 1 = Pop-free start-up / shut-down

2 MICB3_DISCH 1 Microphone Bias 3 Discharge

0 = MICBIAS3 floating when disabled 1 = MICBIAS3 discharged when disabled

1 MICB3_BYPASS 1 Microphone Bias 3 Mode

0 = Regulator mode 1 = Bypass mode

Rev 4.0 311 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 MICB3_ENA 0 Microphone Bias 3 Enable

0 = Disabled 1 = Enabled R715 (02CBh) Isolation control

0 ISOLATE_DCVD

0 Always-On power domain isolate control

Set this bit to 1 to isolate the ‘Always-On’ domain from the DCVDD pin. If DCVDD is powered externally (not from LDO1), this bit must be set before selecting Sleep mode (ie. before removing the external DCVDD supply). If DCVDD is powered from LDO1, then there is no requirement to set this bit. This bit is automatically reset to 0 following a Wake-up transition (from Sleep mode). R3104 (0C20h) Misc Pad Ctrl 1

15 LDO1ENA_PD 1 LDOENA Pull-Down Control

0 = Disabled 1 = Enabled Note - when LDO1ENA_PD and LDO1ENA_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the LDOENA pin.

14 LDO1ENA_PU 0 LDOENA Pull-Up Control

0 = Disabled 1 = Enabled Note - when LDO1ENA_PD and LDO1ENA_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the LDOENA pin. Table 125 Charge Pump and LDO Control Registers LDO2_VSEL [5:0] LDO OUTPUT LDO2_VSEL [5:0] LDO OUTPUT LDO2_VSEL [5:0] LDO OUTPUT 00h 0.900V 10h 1.300V 20h 2.600V 01h 0.925V 11h 1.325V 21h 2.700V 02h 0.950V 12h 1.350V 22h 2.800V 03h 0.975V 13h 1.375V 23h 2.900V 04h 1.000V 14h 1.400V 24h 3.000V 05h 1.025V 15h 1.500V 25h 3.100V 06h 1.050V 16h 1.600V 26h 3.200V 07h 1.075V 17h 1.700V 27h 3.300V 08h 1.100V 18h 1.800V 28h to 3Fh 3.300V 09h 1.125V 19h 1.900V 0Ah 1.150V 1Ah 2.000V 0Bh 1.175V 1Bh 2.100V 0Ch 1.200V 1Ch 2.200V 0Dh 1.225V 1Dh 2.300V 0Eh 1.250V 1Eh 2.400V 0Fh 1.275V 1Fh 2.500V Table 126 LDO2 Voltage Control

312 Rev 4.0 JTAG INTERFACE The JTAG interface provides test and debug access to the WM8281 DSP core. The interface comprises 5 pins, as detailed below.  TCK: Clock input  TDI: Data input  TDO: Data output  TMS: Mode select input  TRST: Test Access Port reset input (active low) For normal operation (test and debug access disabled), the JTAG interface should be held in reset (ie. TRST should be at logic 0). An internal pull -down resistor holds the TRST pin low when not actively driven. The other JTAG input pins (TCK, TDI, TMS) should also be held at logic 0 for normal operation. An internal pull-down resistor holds these pins low when not actively driven. If the JTAG interface is enabled (TRST de -asserted, and TCK active) at the time of Power -On Reset, or any other Reset, then a Software Reset must be scheduled, with the TCK input stopped or TRST asserted (logic ‘0’), before using the JTAG interface. As a general rule, it is recommended to always schedule a Software Reset before starting the JTAG clock, or de -asserting the JTAG reset. In this event, the JTAG interface should be held in its reset state until the Software Reset has completed, and the BOOT_DONE_STS bit has been set. See “Hardware Reset, S oftware Reset, Wake-Up, and Device ID ” for further details of the WM8281 Software Reset.

Rev 4.0 313 THERMAL SHUTDOWN AND SHORT CIRCUIT PROTECTION The WM8281 incorporates thermal protection functions, and also provides short -circuit detection on the Class D speaker and headphone output paths, as described below. The temperature sensor detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The temperature sensor is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. A two -stage indication is provided, via the SPK_OVERHEAT_WARN_EINTn and SPK_OVERHEAT_EINTn interrupts. If the upper temperature threshold (SPK_OV ERHEAT_EINTn) is exceeded, then the Class D speaker outputs will automatically be disabled in order to protect the device. When the speaker driver shutdown is complete, a further interrupt, SPK_SHUTDOWN_EINTn, will be asserted. The short circuit detection function for the Class D speaker outputs is triggered when the respective output drivers are enabled ( using the register bits described in Table 61). If a short circuit is detected at this time, then the enable will be unsuccessful, and the respective output driver will not be enabled. The Class D speaker short circuit detection provides inputs to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. If the Class D speaker short circuit condition is detected, then the respective driver(s) will automatically be disabled in order to protect the device. When the speaker driver shutdown is complete, a further interrupt, SPK_SHUTDOWN_EINTn, will be asserted. To enable the Class D speaker outputs following a short c ircuit detection, the host processor must disable and re-enable the output driver(s) twice over (ie. disable, enable, disable, enable) . Note that the short circuit status bits will always be cleared when the drivers are disabled. The short circuit detecti on function for the headphone output paths operates continuously whilst the respective output driver is enabled. If a short circuit is detected on any headphone output, then current limiting is applied, in order to protect the output driver. Note that the respective output driver will continue to operate, but the output is current-limited. The short circuit detection function for the headphone outputs is designed to operate under a range of typical load conditions. However, it is not compatible with highly reactive loads (either inductive or capacitive), as found on some multi -driver headphones, due to phase shifting that arises under these conditions. The headphone short circuit detection function must be disabled if these load conditions may be applicable. The short circuit detection function for the headphone output paths is enabled by default, but can be disabled using the register bits described in Table 127. The output path performance (THD, THD+N) is improved when the short circuit function is disabled. Note that, when writing to the HPn_SC_ENA bits, care is required not to change the value of other bits in the same register, which may have changed from the default setting. Accordingly, a ‘read - modify-write’ sequence is required to implement this. The headphone output short circuit detection provides inputs to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. Note that two short circuit indications are implemented for each headphone output channel (relating to detection in the positive and negative output voltage regions respective ly); if either of these indications is asserted, then a short circuit condition exists in the respective output path.

314 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1184 (04A0h) HP1 Short Circuit Ctrl

12 HP1_SC_ENA 1 HPOUT1 Short Circuit Detect Enable

0 = Disabled 1 = Enabled R1185 (04A1h) HP2 Short Circuit Ctrl

12 HP2_SC_ENA 1 HPOUT2 Short Circuit Detect Enable

0 = Disabled 1 = Enabled R1186 (04A2h) HP3 Short Circuit Ctrl

12 HP3_SC_ENA 1 HPOUT3 Short Circuit Detect Enable

0 = Disabled 1 = Enabled Table 127 Headphone Short Circuit Detection Control The Thermal Shutdown and Short Circuit protection status flags can be output directly on a GPIO pin as an external indication of the associated events. See “General Purpose Input / Output ” to configure a GPIO pin for this function. POWER-ON RESET (POR) The WM8281 will remain in the reset state until AVDD, DBVDD1 and DCVDD are all above their respective reset thresholds. Note that specified device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to “Recommended Operating Conditions” for the WM8281 power-up sequencing requirements. If DCVDD is powered from LDO1, then the DCVDD supply must be enabled using the LDOENA pin for the initial power-up. Note that subsequent interruption to DCVDD should only be permitted as part of a control sequence for entering Sleep mode. After the initial power -up, the Power -On Reset will be re -scheduled following an interruption to the DBVDD1 or AVDD supplies . Note that the AVDD supply must always be maintained whenever the DCVDD supply is present. If the WM8281 SLIMbus component is in its operational state, then it must be reset prior to scheduling a Power-On Reset . See “ SLIMbus Interfac e Co ntrol” for details of the SLIMbus reset control messages. Following Power-On Reset (POR), a Boot Sequence is executed. The BOOT_DONE_STS register is asserted on completion of the Boot Sequence, as described in Table 128. Control register writes should not be attempted until the BOOT_DONE_STS register has been asserted. The BOOT_DONE_STS signal is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. Under default register conditions, a falling edge on the IRQ¯¯¯ pin will indicate completion of the Boot Sequence. The BOOT_DONE_STS signal can also generate a GPIO output, pro viding an external indication of the Boot Sequence. See “General Purpose Input / Output” to configure a GPIO pin for this function. For details of the Boot Sequence, see “Control Write Sequencer”. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3363 (0D23h) Interrupt Raw Status 5 0 = Busy (boot sequence in progress) 1 = Idle (boot sequence completed) Control register writes should not be attempted until Boot Sequence has completed. Table 128 Device Boot-Up Status

Rev 4.0 315 The WM8281 is in Sleep mode when AVDD and DBVDD1 are present, and DCVDD is below its reset threshold. (Note that specific control requirements are also applicable for entering Sleep mode, as described in “Low Power Sleep Configuration”.) In Sleep mode, most of the Digital Core (and control registers) are held in reset; selected functions and control registers are maintained via an ‘Always -On’ internal supply domain. See “ Low Power Sleep Configuration” for details of the ‘Always-On’ functions. See “Hardware Reset, Software Reset, Wake-Up, and Device ID” for details of the Wake-Up transition (exit from Sleep mode). Table 129 describes the default status of the WM8281 digital I/O pins on completion of Power-On Reset, prior to any register writes. The same default conditions are also applicable on completion of a Hardware Reset or Software Reset ( see “Hardware Reset, S oftware Reset , Wake -Up, and Device ID”). The same default conditions are applicable following a Wake -Up transition, except for the GPIO5, IRQ, LDOENA, MCLK2 and RESET¯¯¯¯¯¯ pins. These are ‘Always -On’ pins whose configuration is unchanged in Sleep mode and during a Wake-Up transition. Note that the default conditions described in Table 129 will not be valid if modi fied by the Boot Sequence or by a ‘Wake-Up’ control sequence . See “Control Write Sequencer ” for details of these functions. PIN NO NAME TYPE RESET STATUS MICVDD power domain F3 DMICCLK4 Digital Output Digital output E3 DMICDAT4 Digital Input Digital input A4 IN1LN / DMICCLK1 Analogue Input / Digital Output Analogue input D4 IN1RN / DMICDAT1 Analogue input / Digital Input Analogue input A3 IN2LN / DMICCLK2 Analogue Input / Digital Output Analogue input D3 IN2RN / DMICDAT2 Analogue input / Digital Input Analogue input A2 IN3LN / DMICCLK3 Analogue Input / Digital Output Analogue input D2 IN3RN / DMICDAT3 Analogue input / Digital Input Analogue input DBVDD1 power domain J13 AIF1BCLK Digital Input / Output Digital input H13 AIF1RXDAT Digital Input Digital input H12 AIF1LRCLK Digital Input / Output Digital input J11 AIF1TXDAT Digital Output Digital output L13 SLIMCLK Digital Input / Output Digital input K12 SLIMDAT Digital Input / Output Digital input F12 CIF1ADDR / CIF1SS¯¯¯¯¯¯ Digital Input Digital input (Pull-down to DGND if CIF1MODE=logic 0) J12 CIF1MISO / GPIO4 Digital Output Digital output F11 CIF1MODE Digital Input Digital input G13 CIF1SCLK Digital Input Digital input G12 CIF1SDA / CIF1MOSI Digital Input / Output Digital input H11 GPIO1 Digital Input / Output Digital input, Pull-down to DGND F13 GPIO5 Digital Input / Output Digital input, Pull-down to DGND E11 IRQ¯¯¯ Digital Output Digital output E13 LDOENA Digital Input Digital input, Pull-down to DGND K13 MCLK1 Digital Input Digital input G14 MCLK2 Digital Input Digital input E12 RESET¯¯¯¯¯¯ Digital Input Digital input, Pull-up to DBVDD1

316 Rev 4.0 PIN NO NAME TYPE RESET STATUS DBVDD2 power domain K9 AIF2BCLK Digital Input / Output Digital input J8 AIF2RXDAT Digital Input Digital input J9 AIF2LRCLK Digital Input / Output Digital input K8 AIF2TXDAT Digital Output Digital output L12 CIF2SCLK Digital Input Digital input K10 CIF2SDA Digital Input / Output Digital input J10 GPIO2 Digital Input / Output Digital input, Pull-down to DGND H9 SPKCLK1 Digital Output Digital output H8 SPKCLK2 Digital Output Digital output H10 SPKDAT1 Digital Output Digital output H7 SPKDAT2 Digital Output Digital output F9 TCK Digital Input Digital input, Pull-down to DGND F8 TDI Digital Input Digital input, Pull-down to DGND K11 TDO Digital Output Digital output F7 TMS Digital Input Digital input, Pull-down to DGND F6 TRST Digital Input Digital input, Pull-down to DGND DBVDD3 power domain K7 AIF3BCLK Digital Input / Output Digital input H4 AIF3RXDAT Digital Input Digital input J7 AIF3LRCLK Digital Input / Output Digital input H5 AIF3TXDAT Digital Output Digital output H6 GPIO3 Digital Input / Output Digital input, Pull-down to DGND Table 129 WM8281 Digital I/O Status in Reset Note that the dual function INnLP/DMICCLKn and INnRP/DMICDATn pins default to their respective analogue input functions after Power -On Reset is completed. The analogue input functions are referenced to the MICVDD power domain.

Rev 4.0 317 HARDWARE RESET, SOFTWARE RESET, WAKE-UP, AND DEVICE ID The WM8281 provides a Hardware Reset function , which is executed whenever the RESET¯¯¯¯¯¯ input is asserted (logic 0). The RESET¯¯¯¯¯¯ input is active low and is referenced to the DBVDD1 power domain. A Hardware Reset causes most of the WM8281 control registers to be reset to their default states. Note that the Control Write Sequencer memory and DSP firmware memory contents are retained during Hardware Reset (assuming the conditions noted below). An internal pull -up resistor is enabled by default on the RESET¯¯¯¯¯¯ pin; this can be configured using the RESET_PU register bit . A pull -down resistor is also available, as described in Table 130. When the pull-up and pull-down resistors are both enabled, the WM8281 provides a ‘bus keeper’ function on the RESET¯¯¯¯¯¯ pin. The bus keeper function holds the input logic level unchanged whenever the external circuit removes the drive (eg. if the signal is tri-stated). If the WM8281 SLIMbus component is in its operational state, then it must be reset prior to scheduling a Hardware Reset. See “ SLIMbus Interfac e Co ntrol” for details of the SLIMbus reset control messages. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3104 (0C20h) Misc Pad Ctrl 1

1 RESET_PU 1 RESET Pull-up enable

0 = Disabled 1 = Enabled Note - when RESET_PD and RESET_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the RESET pin.

0 RESET_PD 0 RESET Pull-down enable

0 = Disabled 1 = Enabled Note - when RESET_PD and RESET_PU are both set to ‘1’, then a ‘bus keeper’ function is enabled on the RESET pin. Table 130 Reset Pull-Up Configuration A Software Reset is executed by writing any value to register R0. A Software Reset causes most of the WM8281 control registers to be reset to their default states. Note that the Control Write Sequencer memory and DSP firmware memory contents are retained during Software Reset (assuming the conditions noted below). A Wake-Up transition (from Sleep mode) is similar to a Software Reset, but selected f unctions and control registers are maintained via an ‘Always -On’ internal supply domain. The ‘Always -On’ registers are not reset during Wake -Up. See “ Low Power Sleep Configuration ” for details of the ‘Always -On’ functions. The Control Write Sequencer memory contents are retained during Hardware Reset, Software Reset or Sleep mode; these registers are only reset following a Power-On Reset (POR). The DSP firmware memory contents are also retained during Hardware Reset and Software Reset, provided DCVDD is held above its reset threshold, and the DSPn_MEM_ENA bits are set to ‘1’ (default). See the “ Applications Information” section for a summary of the WM8281 memory reset conditions. The DSPn_MEM_ENA register bits are described in Table 27. If DCVDD is powered from LDO1, it is recommended that the LDOENA pin is asserted (logic 1) before Hardware Reset or Software Reset; this ensures the DSP memory contents can be retained, and also allows faster reset time. Following Hardware Reset , Software Reset or Wake -Up (from Sleep mode) , a Boot Sequence is executed. The BOOT_DONE_STS register (see Table 128) is de -asserted during Hardware Reset , Software Reset and in Sleep mode . The BOOT_DONE_STS register is asserted on completion of the boot-up sequence. Control register writes should not be attempted until the BOOT_DONE_STS register has been asserted.

318 Rev 4.0 The BOOT_DONE_STS signal is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The BOOT_DONE_STS signal can also generate a GPIO output, providing an external indication of the Boot Sequence. See “General Purpose Input / Output” to configure a GPIO pin for this function. For details of the Boot Sequence, see “Control Write Sequencer”. The status of the WM8281 digital I/O pins following Hardware Reset, Software Reset or Wake -Up is described in the “Power-On Reset (POR)” section. The Device ID can be read back from Register R0. The Hardware Revision can be read back from Register R1. The Software Revision can be read back from Register R2 . The Software Revision code is incremented if software driver compatibility or software feature support is changed. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 (0000h) Software Reset 15:0 SW_RST_DEV_ ID [15:0] 5110h Writing to this register resets all registers to their default state. Reading from this register will indicate Device ID 5110h. R1 (0001h) Hardware Revision 7:0 HW_REVISION [7:0] Hardware Device revision. (incremented for every new revision of the device) R2 (0002h) Software Revision 6:0 SW_REVISION [6:0] Software Device revision. (incremented if software driver compatibility or software feature support is changed) Table 131 Device Reset and ID

Rev 4.0 319 REGISTER MAP The WM8281 control registers are listed below. Note that only the register addresses described here should be accessed; writing to other addresses may result in undefined behaviour. Register bits that are not documented should not be changed from the defau lt values. REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R0 (0h) Software Reset SW_RST_DEV_ID [15:0] 5110h R1 (1h) Hardware Revision 0 0 0 0 0 0 0 0 HW_REVISION [7:0] R2 (2h) Software Revision 0 0 0 0 0 0 0 0 0 SW_REVISION [6:0] R8 (8h) Ctrl IF SPI CFG 1 0 0 0 0 0 0 0 0 0 0 0 SPI_C FG SPI_G PIO

0 SPI_AUTO_IN

C [1:0] 0019h R9 (9h) Ctrl IF I2C1 CFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C1_AUTO_IN C [1:0] 0001h R10 (Ah) Ctrl IF I2C2 CFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C2_AUTO_IN C [1:0] 0001h R11 (Bh) Ctrl IF I2C1 CFG 0 0 0 0 0 0 0 0 0 I2C1_DEV_ID [6:0] 001Ah R12 (Ch) Ctrl IF I2C2 CFG 0 0 0 0 0 0 0 0 0 I2C2_DEV_ID [6:0] 001Ah R22 (16h) Write Sequencer Ctrl 0 0 0 0 0 WSEQ _ABO RT WSEQ _STAR T WSEQ _ENA WSEQ_START_INDEX [8:0] 0000h R23 (17h) Write Sequencer Ctrl 1 0 0 0 0 0 0 WSEQ _BUSY WSEQ_CURRENT_INDEX [8:0] 0000h R24 (18h) Write Sequencer Ctrl 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WSEQ _BOO T_STA RT WSEQ _LOAD _MEM 0000h R32 (20h) Tone Generator 1 0 TONE_RATE [3:0] 0 TONE_OFFSE T [1:0] 0 0 TONE 2_OVD TONE 1_OVD 0 0 TONE 2_ENA TONE 1_ENA 0000h R33 (21h) Tone Generator 2 TONE1_LVL [23:8] 1000h R34 (22h) Tone Generator 3 0 0 0 0 0 0 0 0 TONE1_LVL [7:0] 0000h R35 (23h) Tone Generator 4 TONE2_LVL [23:80] 1000h R36 (24h) Tone Generator 5 0 0 0 0 0 0 0 0 TONE2_LVL [7:0] 0000h R48 (30h) PWM Drive 1 0 PWM_RATE [3:0] PWM_CLK_SEL [2:0] 0 0 PWM2 _OVD PWM1 _OVD 0 0 PWM2 _ENA PWM1 _ENA 0000h R49 (31h) PWM Drive 2 0 0 0 0 0 0 PWM1_LVL [9:0] 0100h R50 (32h) PWM Drive 3 0 0 0 0 0 0 PWM2_LVL [9:0] 0100h R64 (40h) Wake control 0 0 0 0 0 0 0 0 WKUP _MICD _CLA MP_F ALL WKUP _MICD _CLA MP_RI SE WKUP _GP5_ FALL WKUP _GP5_ RISE WKUP _JD1_ FALL WKUP _JD1_ RISE 0 0 0000h R65 (41h) Sequence control 0 0 0 0 0 0 0 0 WSEQ _ENA_ MICD_ CLAM P_FAL L WSEQ _ENA_ MICD_ CLAM P_RIS E WSEQ _ENA_ GP5_F ALL WSEQ _ENA_ GP5_R ISE WSEQ _ENA_ JD1_F ALL WSEQ _ENA_ JD1_R ISE 0 0 0000h R97 (61h) Sample Rate Sequence Select 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_A_INDEX [8:0] 01FFh R98 (62h) Sample Rate Sequence Select 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_B_INDEX [8:0] 01FFh

320 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R99 (63h) Sample Rate Sequence Select 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_C_INDEX [8:0] 01FFh R100 (64h) Sample Rate Sequence Select 0 0 0 0 0 0 0 WSEQ_SAMPLE_RATE_DETECT_D_INDX [8:0] 01FFh R102 (66h) Always On Triggers Sequence Select 0 0 0 0 0 0 0 WSEQ_MICD_CLAMP_RISE_INDEX [8:0] 01FFh R103 (67h) Always On Triggers Sequence Select 0 0 0 0 0 0 0 WSEQ_MICD_CLAMP_FALL_INDEX [8:0] 01FFh R104 (68h) Always On Triggers Sequence Select 0 0 0 0 0 0 0 WSEQ_GP5_RISE_INDEX [8:0] 01FFh R105 (69h) Always On Triggers Sequence Select 0 0 0 0 0 0 0 WSEQ_GP5_FALL_INDEX [8:0] 01FFh R106 (6Ah) Always On Triggers Sequence Select 0 0 0 0 0 0 0 WSEQ_JD1_RISE_INDEX [8:0] 01FFh R107 (6Bh) Always On Triggers Sequence Select 0 0 0 0 0 0 0 WSEQ_JD1_FALL_INDEX [8:0] 01FFh R110 (6Eh) Trigger Sequence Select 32 0 0 0 0 0 0 0 WSEQ_SIG_DET_RISE_INDEX [8:0] 01FFh R111 (6Fh) Trigger Sequence Select 33 0 0 0 0 0 0 0 WSEQ_SIG_DET_FALL_INDEX [8:0] 01FFh R112 (70h) Comfort Noise Generator

0 NOISE_GEN_RATE [3:0] 0 0 0 0 0 NOISE

_GEN_ ENA NOISE_GEN_GAIN [4:0] 0000h R135 (87h) HP Detect Calibration 1 HP_OFFSET_ DIFF_11 [1:0] HP_OFFSET_DIFF_10 [1:0] HP_OFFSET_01 [1:0] HP_OFFSET_DIFF_00 [1:0] 0000h R135 (88h) HP Detect Calibration 2 HP_OFFSET_ DIFF_11 [3:2] HP_GRADIENT_1X [6:0] HP_GRADIENT_0X [6:0] 0000h R144 (90h) Haptics Control 1 0 HAP_RATE [3:0] 0 0 0 0 0 0 ONES HOT_T RIG HAP_CTRL [1:0] HAP_A CT 0 0000h R145 (91h) Haptics Control 2 0 LRA_FREQ [14:0] 7FFFh R146 (92h) Haptics phase 1 intensity 0 0 0 0 0 0 0 0 PHASE1_INTENSITY [7:0] 0000h R147 (93h) Haptics phase 1 duration 0 0 0 0 0 0 0 PHASE1_DURATION [8:0] 0000h R148 (94h) Haptics phase 2 intensity 0 0 0 0 0 0 0 0 PHASE2_INTENSITY [7:0] 0000h R149 (95h) Haptics phase 2 duration 0 0 0 0 0 PHASE2_DURATION [10:0] 0000h R150 (96h) Haptics phase 3 intensity 0 0 0 0 0 0 0 0 PHASE3_INTENSITY [7:0] 0000h R151 (97h) Haptics phase 3 duration 0 0 0 0 0 0 0 PHASE3_DURATION [8:0] 0000h

Rev 4.0 321 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R152 (98h) Haptics Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ONES HOT_ STS 0000h R256 (100h) Clock 32k 1 0 0 0 0 0 0 0 0 0 CLK_3 2K_EN A 0 0 0 0 CLK_32K_SRC [1:0] 0002h R257 (101h) System Clock 1 SYSCL K_FRA C 0 0 0 0 SYSCLK_FREQ [2:0] 0 SYSCL K_ENA 0 0 SYSCLK_SRC [3:0] 0504h R258 (102h) Sample rate 1 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_1 [4:0] 0011h R259 (103h) Sample rate 2 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_2 [4:0] 0011h R260 (104h) Sample rate 3 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_3 [4:0] 0011h R266 (10Ah) Sample rate 1 status 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_1_STS [4:0] 0000h R267 (10Bh) Sample rate 2 status 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_2_STS [4:0] 0000h R268 (10Ch) Sample rate 3 status 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_3_STS [4:0] 0000h R274 (112h) Async clock 1 0 0 0 0 0 ASYNC_CLK_FREQ [2:0]

0 ASYN

C_CLK _ENA 0 0 ASYNC_CLK_SRC [3:0] 0305h R275 (113h) Async sample rate 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_1 [4:0] 0011h R276 (114h) Async sample rate 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_2 [4:0] 0011h R283 (11Bh) Async sample rate 1 status 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_1_STS [4:0] 0000h R284 (11Ch) Async sample rate 2 status 0 0 0 0 0 0 0 0 0 0 0 ASYNC_SAMPLE_RATE_2_STS [4:0] 0000h R329 (149h) Output system clock OPCL K_ENA 0 0 0 0 0 0 0 OPCLK_DIV [4:0] OPCLK_SEL [2:0] 0000h R330 (14Ah) Output async clock OPCL K_ASY NC_E NA 0 0 0 0 0 0 0 OPCLK_ASYNC_DIV [4:0] OPCLK_ASYNC_SEL [2:0] 0000h R338 (152h) Rate Estimator 1 0 0 0 0 0 0 0 0 0 0 0 TRIG_ ON_S TART UP LRCLK_SRC [2:0] RATE_ EST_E NA 0000h R339 (153h) Rate Estimator 2 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_DETECT_A [4:0] 0000h R340 (154h) Rate Estimator 3 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_DETECT_B [4:0] 0000h R341 (155h) Rate Estimator 4 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_DETECT_C [4:0] 0000h R342 (156h) Rate Estimator 5 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_RATE_DETECT_D [4:0] 0000h R369 (171h) FLL1 Control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL1_ FREE RUN FLL1_ ENA 0002h R370 (172h) FLL1 Control 2 FLL1_ CTRL_ UPD 0 0 0 0 0 FLL1_N [9:0] 0008h R371 (173h) FLL1 Control 3 FLL1_THETA [15:0] 0018h R372 (174h) FLL1 Control 4 FLL1_LAMBDA [15:0] 007Dh R373 (175h) FLL1 Control 5 0 0 0 0 FLL1_FRATIO [3:0] 0 0 0 0 FLL1_OUTDIV [2:0] 0 0006h R374 (176h) FLL1 Control 6 0 0 0 0 0 0 0 0 FLL1_REFCLK _DIV [1:0] 0 0 FLL1_REFCLK_SRC [3:0] 0000h

322 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R375 (177h) FLL1 Loop Filter Test 1 FLL1_ FRC_I NTEG _UPD 0 0 0 FLL1_FRC_INTEG_VAL [11:0] 0281h R376 (178h) FLL1 NCO Test 0 FLL1_I NTEG _VALI D 0 0 0 FLL1_INTEG [11:0] 0000h R377 (179h) FLL1 Control 7 0 0 0 0 0 0 0 0 0 0 FLL1_GAIN [3:0] 0 0 0000h R385 (181h) FLL1 Synchroniser 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL1_ SYNC _ENA 0000h R386 (182h) FLL1 Synchroniser 2 0 0 0 0 0 0 FLL1_SYNC_N [9:0] 0000h R387 (183h) FLL1 Synchroniser 3 FLL1_SYNC_THETA [15:0] 0000h R388 (184h) FLL1 Synchroniser 4 FLL1_SYNC_LAMBDA [15:0] 0000h R389 (185h) FLL1 Synchroniser 5 0 0 0 0 0 FLL1_SYNC_FRATIO [2:0] 0 0 0 0 0 0 0 0 0000h R390 (186h) FLL1 Synchroniser 6 0 0 0 0 0 0 0 0 FLL1_SYNCCL K_DIV [1:0] 0 0 FLL1_SYNCCLK_SRC [3:0] 0000h R391 (187h) FLL1 Synchroniser 7 0 0 0 0 0 0 0 0 0 0 FLL1_SYNC_GAIN [3:0] 0 FLL1_ SYNC _DFSA T 0001h R393 (189h) FLL1 Spread Spectrum 0 0 0 0 0 0 0 0 0 0 FLL1_SS_AMP L [1:0] FLL1_SS_FRE Q [1:0] FLL1_SS_SEL [1:0] 0000h R394 (18Ah) FLL1 GPIO Clock 0 0 0 0 0 0 0 0 FLL1_GPCLK_DIV [6:0] FLL1_ GPCL K_ENA 000Ch R401 (191h) FLL2 Control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL2_ FREE RUN FLL2_ ENA 0002h R402 (192h) FLL2 Control 2 FLL2_ CTRL_ UPD 0 0 0 0 0 FLL2_N [9:0] 0008h R403 (193h) FLL2 Control 3 FLL2_THETA [15:0] 0018h R404 (194h) FLL2 Control 4 FLL2_LAMBDA [15:0] 007Dh R405 (195h) FLL2 Control 5 0 0 0 0 FLL2_FRATIO [3:0] 0 0 0 0 FLL2_OUTDIV [2:0] 0 000Ch R406 (196h) FLL2 Control 6 0 0 0 0 0 0 0 0 FLL2_REFCLK _DIV [1:0] 0 0 FLL2_REFCLK_SRC [3:0] 0000h R407 (197h) FLL2 Loop Filter Test 1 FLL2_ FRC_I NTEG _UPD 0 0 0 FLL2_FRC_INTEG_VAL [11:0] 0000h R408 (198h) FLL2 NCO Test 0 FLL2_I NTEG _VALI D 0 0 0 FLL2_INTEG [11:0] 0000h R409 (199h) FLL2 Control 7 0 0 0 0 0 0 0 0 0 0 FLL2_GAIN [3:0] 0 0 0000h R417 (1A1h) FLL2 Synchroniser 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL2_ SYNC _ENA 0000h R418 (1A2h) FLL2 Synchroniser 2 0 0 0 0 0 0 FLL2_SYNC_N [9:0] 0000h R419 (1A3h) FLL2 Synchroniser 3 FLL2_SYNC_THETA [15:0] 0000h

Rev 4.0 323 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R420 (1A4h) FLL2 Synchroniser 4 FLL2_SYNC_LAMBDA [15:0] 0000h R421 (1A5h) FLL2 Synchroniser 5 0 0 0 0 0 FLL2_SYNC_FRATIO [2:0] 0 0 0 0 0 0 0 0 0000h R422 (1A6h) FLL2 Synchroniser 6 0 0 0 0 0 0 0 0 FLL2_SYNCCL K_DIV [1:0] 0 0 FLL2_SYNCCLK_SRC [3:0] 0000h R423 (1A7h) FLL2 Synchroniser 7 0 0 0 0 0 0 0 0 0 0 FLL2_SYNC_GAIN [3:0] 0 FLL2_ SYNC _DFSA T 0001h R425 (1A9h) FLL2 Spread Spectrum 0 0 0 0 0 0 0 0 0 0 FLL2_SS_AMP L [1:0] FLL2_SS_FRE Q [1:0] FLL2_SS_SEL [1:0] 0000h R426 (1AAh) FLL2 GPIO Clock 0 0 0 0 0 0 0 0 FLL2_GPCLK_DIV [6:0] FLL2_ GPCL K_ENA 000Ch R512 (200h) Mic Charge Pump 0 0 0 0 0 0 0 0 0 0 0 0 0 CP2_D ISCH CP2_B YPAS S CP2_E NA 0007h R528 (210h) LDO1 Control 1 0 0 0 0 0 LDO1_VSEL [5:0] 0 0 LDO1_ DISCH

0 LDO1_

R531 (213h) LDO2 Control 1 0 0 0 0 0 LDO2_VSEL [5:0] 0 0 LDO2_ DISCH 0 0 03E4h R536 (218h) Mic Bias Ctrl 1 MICB1 _EXT_ CAP 0 0 0 0 0 0 MICB1_LVL [3:0] 0 MICB1 _RATE MICB1 _DISC H MICB1 _BYPA SS MICB1 _ENA 00E6h R537 (219h) Mic Bias Ctrl 2 MICB2 _EXT_ CAP 0 0 0 0 0 0 MICB2_LVL [3:0] 0 MICB2 _RATE MICB2 _DISC H MICB2 _BYPA SS MICB2 _ENA 00E6h R538 (21Ah) Mic Bias Ctrl 3 MICB3 _EXT_ CAP 0 0 0 0 0 0 MICB3_LVL [3:0] 0 MICB3 _RATE MICB3 _DISC H MICB3 _BYPA SS MICB3 _ENA 00E6h R549 (225h) HP Ctrl 1L 0 0 0 0 0 1 0 0 0 0 0 0 0 HP1L_ FLWR HP1L_ SHRTI HP1L_ SHRT O 0406h R550 (226h) HP Ctrl 1R 0 0 0 0 0 1 0 0 0 0 0 0 0 HP1R_ FLWR HP1R_ SHRTI HP1R_ SHRT O 0406h R659 (293h) Accessory Detect Mode 1 0 0 ACCD ET_SR C 0 0 0 0 0 0 0 0 0 0 0 ACCDET_MOD E [1:0] 0000h R667 (29Bh) Headphone Detect 1 0 0 0 0 0 HP_IMPEDAN CE_RANGE [1:0]

0 HP_HOLDTIME [2:0] HP_CLK_DIV

[1:0]

0 HP_R

HP_P OLL 0028h R668 (29Ch) Headphone Detect 2 HP_D ONE HP_LVL [14:0] 0000h R669 (29Dh) Headphone Detect Test 0 0 0 0 0 0 HP_DACVAL [9:0] 0000h R674 (2A2h) Micd Clamp control 0 0 0 0 0 0 0 0 0 0 0 0 MICD_CLAMP_MODE [3:0] 0000h R675 (2A3h) Mic Detect 1 MICD_BIAS_STARTTIME [3:0] MICD_RATE [3:0] 0 0 MICD_BIAS_S RC [1:0] 0 0 MICD_ DBTIM E MICD_ ENA 1102h R676 (2A4h) Mic Detect 2 0 0 0 0 0 0 0 0 MICD_LVL_SEL [7:0] 009Fh R677 (2A5h) Mic Detect 3 0 0 0 0 0 MICD_LVL [8:0] MICD_ VALID MICD_ STS 0000h R683 (2ABh) Mic Detect 4 MICDET_ADCVAL_DIFF [7:0] 0 MICDET_ADCVAL [6:0] 0000h

324 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R707 (2C3h) Mic noise mix control 1

0 MICMUTE_RATE [3:0] 0 0 0 MICM

UTE_N OISE_ ENA MICM UTE_ MIX_E NA 0 0 0 0 0 0 0000h R715 (2CBh) Isolation control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISOLA TE_DC VDD1 0000h R723 (2D3h) Jack detect analogue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JD1_E NA 0000h R768 (300h) Input Enables 0 0 0 0 0 0 0 0 IN4L_ ENA IN4R_ ENA IN3L_ ENA IN3R_ ENA IN2L_ ENA IN2R_ ENA IN1L_ ENA IN1R_ ENA 0000h R769 (301h) Input Enables Status 0 0 0 0 0 0 0 0 IN4L_ ENA_S TS IN4R_ ENA_S TS IN3L_ ENA_S TS IN3R_ ENA_S TS IN2L_ ENA_S TS IN2R_ ENA_S TS IN1L_ ENA_S TS IN1R_ ENA_S TS 0000h R776 (308h) Input Rate 0 IN_RATE [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R777 (309h) Input Volume Ramp 0 0 0 0 0 0 0 0 0 IN_VD_RAMP [2:0] 0 IN_VI_RAMP [2:0] 0022h R780 (30Ch) HPF Control 0 0 0 0 0 0 0 0 0 0 0 0 0 IN_HPF_CUT [2:0] 0002h R784 (310h) IN1L Control IN1L_ HPF IN1_OSR [1:0] IN1_DMIC_SU P [1:0] IN1_MODE [1:0]

0 IN1L_PGA_VOL [6:0] 0 2080h

R785 (311h) ADC Digital Volume 1L 0 0 0 0 0 0 IN_VU IN1L_ MUTE IN1L_VOL [7:0] 0180h R786 (312h) DMIC1L Control 0 0 0 0 0 0 0 0 0 0 IN1L_DMIC_DLY [5:0] 0000h R788 (314h) IN1R Control IN1R_ HPF 0 0 0 0 0 0 0 IN1R_PGA_VOL [6:0] 0 0080h R789 (315h) ADC Digital Volume 1R 0 0 0 0 0 0 IN_VU IN1R_ MUTE IN1R_VOL [7:0] 0180h R790 (316h) DMIC1R Control 0 0 0 0 0 0 0 0 0 0 IN1R_DMIC_DLY [5:0] 0000h R792 (318h) IN2L Control IN2L_ HPF IN2_OSR [1:0] IN2_DMIC_SU P [1:0] IN2_MODE [1:0]

0 IN2L_PGA_VOL [6:0] 0 2080h

R793 (319h) ADC Digital Volume 2L 0 0 0 0 0 0 IN_VU IN2L_ MUTE IN2L_VOL [7:0] 0180h R794 (31Ah) DMIC2L Control 0 0 0 0 0 0 0 0 0 0 IN2L_DMIC_DLY [5:0] 0000h R796 (31Ch) IN2R Control IN2R_ HPF 0 0 0 0 0 0 0 IN2R_PGA_VOL [6:0] 0 0080h R797 (31Dh) ADC Digital Volume 2R 0 0 0 0 0 0 IN_VU IN2R_ MUTE IN2R_VOL [7:0] 0180h R798 (31Eh) DMIC2R Control 0 0 0 0 0 0 0 0 0 0 IN2R_DMIC_DLY [5:0] 0000h R800 (320h) IN3L Control IN3L_ HPF IN3_OSR [1:0] IN3_DMIC_SU P [1:0] IN3_MODE [1:0]

0 IN3L_PGA_VOL [6:0] 0 2080h

R801 (321h) ADC Digital Volume 3L 0 0 0 0 0 0 IN_VU IN3L_ MUTE IN3L_VOL [7:0] 0180h R802 (322h) DMIC3L Control 0 0 0 0 0 0 0 0 0 0 IN3L_DMIC_DLY [5:0] 0000h R804 (324h) IN3R Control IN3R_ HPF 0 0 0 0 0 0 0 IN3R_PGA_VOL [6:0] 0 0080h R805 (325h) ADC Digital Volume 3R 0 0 0 0 0 0 IN_VU IN3R_ MUTE IN3R_VOL [7:0] 0180h R806 (326h) DMIC3R Control 0 0 0 0 0 0 0 0 0 0 IN3R_DMIC_DLY [5:0] 0000h R808 (328h) IN4L Control IN4L_ HPF IN4_OSR [1:0] IN4_DMIC_SU P [1:0] 0 0 0 0 0 0 0 0 0 0 0 2000h R809 (329h) ADC Digital Volume 4L 0 0 0 0 0 0 IN_VU IN4L_ MUTE IN4L_VOL [7:0] 0180h R810 (32Ah) DMIC4L Control 0 0 0 0 0 0 0 0 0 0 IN4L_DMIC_DLY [5:0] 0000h R812 (32Ch) IN4R Control IN4R_ HPF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h

Rev 4.0 325 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R813 (32Dh) ADC Digital Volume 4R 0 0 0 0 0 0 IN_VU IN4R_ MUTE IN4R_VOL [7:0] 0180h R814 (32Eh) DMIC4R Control 0 0 0 0 0 0 0 0 0 0 IN4R_DMIC_DLY [5:0] 0000h R1024 (400h) Output Enables 1 0 0 0 0 OUT6L _ENA OUT6 R_EN A OUT5L _ENA OUT5 R_EN A SPKO UTL_E NA SPKO UTR_E NA HP3L_ ENA HP3R_ ENA HP2L_ ENA HP2R_ ENA HP1L_ ENA HP1R_ ENA 0000h R1025 (401h) Output Status 1 0 0 0 0 OUT6L _ENA_ STS OUT6 R_EN A_STS OUT5L _ENA_ STS OUT5 R_EN A_STS OUT4L _ENA_ STS OUT4 R_EN A_STS 0 0 0 0 0 0 0000h R1030 (406h) Raw Output Status 1 0 0 0 0 0 0 0 0 0 0 OUT3L _ENA_ STS OUT3 R_EN A_STS OUT2L _ENA_ STS OUT2 R_EN A_STS OUT1L _ENA_ STS OUT1 R_EN A_STS 0000h R1032 (408h) Output Rate 1 0 OUT_RATE [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R1033 (409h) Output Volume Ramp 0 0 0 0 0 0 0 0 0 OUT_VD_RAMP [2:0] 0 OUT_VI_RAMP [2:0] 0022h R1040 (410h) Output Path Config 1L 0 0 OUT1_ MONO OUT1L_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1041 (411h) DAC Digital Volume 1L 0 0 0 0 0 OUT_ VU OUT1L _MUT E OUT1L_VOL [7:0] 0180h R1042 (412h) DAC Volume Limit 0 0 0 0 0 0 0 OUT1L_VOL_LIM [7:0] 0081h R1043 (413h) Noise Gate Select 0 0 0 OUT1L_NGATE_SRC [11:0] 0001h R1044 (414h) Output Path Config 1R 0 0 0 OUT1R_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1045 (415h) DAC Digital Volume 1R 0 0 0 0 0 OUT_ VU OUT1 R_MU TE OUT1R_VOL [7:0] 0180h R1046 (416h) DAC Volume Limit 0 0 0 0 0 0 0 OUT1R_VOL_LIM [7:0] 0081h R1047 (417h) Noise Gate Select 0 0 0 OUT1R_NGATE_SRC [11:0] 0002h R1048 (418h) Output Path Config 2L 0 0 OUT2_ MONO OUT2L_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 000h R1049 (419h) DAC Digital Volume 2L 0 0 0 0 0 OUT_ VU OUT2L _MUT E OUT2L_VOL [7:0] 0180h R1050 (41Ah) DAC Volume Limit 0 0 0 0 0 0 0 OUT2L_VOL_LIM [7:0] 0081h R1051 (41Bh) Noise Gate Select 0 0 0 OUT2L_NGATE_SRC [11:0] 0004h R1052 (41Ch) Output Path Config 2R 0 0 0 OUT2R_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1053 (41Dh) DAC Digital Volume 2R 0 0 0 0 0 OUT_ VU OUT2 R_MU TE OUT2R_VOL [7:0] 0180h R1054 (41Eh) DAC Volume Limit 0 0 0 0 0 0 0 OUT2R_VOL_LIM [7:0] 0081h R1055 (41Fh) Noise Gate Select 0 0 0 OUT2R_NGATE_SRC [11:0] 0008h R1056 (420h) Output Path Config 3L 0 0 OUT3_ MONO OUT3L_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1057 (421h) DAC Digital Volume 3L 0 0 0 0 0 0 OUT_ VU OUT3L _MUT E OUT3L_VOL [7:0] 0180h

326 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1058 (422h) DAC Volume Limit 0 0 0 0 0 0 0 0 OUT3L_VOL_LIM [7:0] 0081h R1059 (423h) Noise Gate Select 0 0 0 0 OUT3L_NGATE_SRC [11:0] 0010h R1061 (425h) DAC Digital Volume 3R 0 0 0 0 0 0 OUT_ VU OUT3 R_MU TE OUT3R_VOL [7:0] 0180h R1062 (426h) DAC Volume Limit 0 0 0 0 OUT3R_ANC_ SRC [1:0] 0 0 OUT3R_VOL_LIM [7:0] 0081h R1063 (427h) Noise Gate Select 0 0 0 OUT3R_NGATE_SRC [11:0] 0020h R1064 (428h) Output Path Config 4L 0 0 0 OUT4L_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1065 (429h) DAC Digital Volume 4L 0 0 0 0 0 0 OUT_ VU OUT4L _MUT E OUT4L_VOL [7:0] 0180h R1066 (42Ah) Out Volume 4L 0 0 0 0 0 0 0 0 OUT4L_VOL_LIM [7:0] 0081h R1067 (42Bh) Noise Gate Select 0 0 0 0 OUT4L_NGATE_SRC [11:0] 0040h R1068 (42Ch) Output Path Config 4R 0 0 0 0 OUT4R_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1069 (42Dh) DAC Digital Volume 4R 0 0 0 0 0 0 OUT_ VU OUT4 R_MU TE OUT4R_VOL [7:0] 0180h R1070 (42Eh) Out Volume 4R 0 0 0 0 0 0 0 0 OUT4R_VOL_LIM [7:0] 0081h R1071 (42Fh) Noise Gate Select 0 0 0 0 OUT4R_NGATE_SRC [11:0] 0080h R1072 (430h) Output Path Config 5L 0 0 OUT5_ OSR

0 OUT5L_ANC_

SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1073 (431h) DAC Digital Volume 5L 0 0 0 0 0 0 OUT_ VU OUT5L _MUT E OUT5L_VOL [7:0] 0180h R1074 (432h) DAC Volume Limit 0 0 0 0 0 0 0 0 OUT5L_VOL_LIM [7:0] 0081h R1075 (433h) Noise Gate Select 0 0 0 0 OUT5L_NGATE_SRC [11:0] 0100h R1076 (434h) Output Path Config 5R 0 0 0 0 OUT5R_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1077 (435h) DAC Digital Volume 5R 0 0 0 0 0 0 OUT_ VU OUT5 R_MU TE OUT5R_VOL [7:0] 0180h R1078 (436h) DAC Volume Limit 0 0 0 0 0 0 0 0 OUT5R_VOL_LIM [7:0] 0081h R1079 (437h) Noise Gate Select 0 0 0 0 OUT5R_NGATE_SRC [11:0] 0200h R1080 (438h) Output Path Config 6L 0 0 OUT6_ OSR

0 OUT6L_ANC_

SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h R1081 (439h) DAC Digital Volume 6L 0 0 0 0 0 0 OUT_ VU OUT6L _MUT E OUT6L_VOL [7:0] 0180h R1082 (43Ah) DAC Volume Limit 0 0 0 0 0 0 0 0 OUT6L_VOL_LIM [7:0] 0081h R1083 (43Bh) Noise Gate Select 0 0 0 0 OUT6L_NGATE_SRC [11:0] 0400h R1084 (43Ch) Output Path Config 6R 0 0 0 0 OUT6R_ANC_ SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0000h

Rev 4.0 327 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1085 (43Dh) DAC Digital Volume 6R 0 0 0 0 0 0 OUT_ VU OUT6 R_MU TE OUT6R_VOL [7:0] 0180h R1086 (43Eh) DAC Volume Limit 0 0 0 0 0 0 0 0 OUT6R_VOL_LIM [7:0] 0081h R1087 (43Fh) Noise Gate Select 0 0 0 0 OUT6R_NGATE_SRC [11:0] 0800h R1104 (450h) DAC AEC Control 0 0 0 0 0 0 0 0 0 0 AEC_LOOPBACK_SRC [3:0] AEC_E NA_ST S AEC_L OOPB ACK_E NA 0000h R1112 (458h) Noise Gate Control 0 0 0 0 0 0 0 0 0 0 NGATE_HOLD [1:0] NGATE_THR [2:0] NGAT E_ENA 0000h R1168 (490h) PDM SPK1 CTRL 0 0 SPK1R _MUT E SPK1L _MUT E 0 0 0 SPK1_ MUTE _ENDI AN SPK1_MUTE_SEQ [7:0] 0069h R1169 (491h) PDM SPK1 CTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPK1_ FMT 0000h R1170 (492h) PDM SPK2 CTRL 0 0 SPK2R _MUT E SPK2L _MUT E 0 0 0 SPK2_ MUTE _ENDI AN SPK2_MUTE_SEQ [7:0] 0069h R1171 (493h) PDM SPK2 CTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPK2_ FMT 0000h R1184 (4A0h) HP1 Short Circuit Ctrl 0 0 1 HP1_S C_EN A 0 1 0 0 1 0 0 0 0 0 0 0 3480h R1185 (4A1h) HP2 Short Circuit Ctrl 0 0 1 HP2_S C_EN A 0 1 0 0 1 0 0 0 0 0 0 0 3480h R1186 (4A2h) HP3 Short Circuit Ctrl 0 0 1 HP3_S C_EN A 0 1 0 0 1 0 0 0 0 0 0 0 3480h R1188 (4A4h) HP Test Ctrl 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HP1_TST_CAP _SEL [1:0] 0003h R1280 (500h) AIF1 BCLK Ctrl 0 0 0 0 0 0 0 0 AIF1_ BCLK_ INV AIF1_ BCLK_ FRC AIF1_ BCLK_ MSTR AIF1_BCLK_FREQ [4:0] 000Ch R1281 (501h) AIF1 Tx Pin Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1T X_DAT _TRI

0 AIF1T

X_LRC LK_SR C AIF1T X_LRC LK_IN V AIF1T X_LRC LK_FR C AIF1T X_LRC LK_MS TR 0008h R1282 (502h) AIF1 Rx Pin Ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1R X_LRC LK_IN V AIF1R X_LRC LK_FR C AIF1R X_LRC LK_MS TR 0000h R1283 (503h) AIF1 Rate Ctrl 0 AIF1_RATE [3:0] 0 0 0 0 AIF1_T RI 0 0 0 0 0 0 0000h R1284 (504h) AIF1 Format 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF1_FMT [2:0] 0000h R1285 (505h) AIF1 Tx BCLK Rate 0 0 0 AIF1TX_BCPF [12:0] 0040h R1286 (506h) AIF1 Rx BCLK Rate 0 0 0 AIF1RX_BCPF [12:0] 0040h R1287 (507h) AIF1 Frame Ctrl 1 0 0 AIF1TX_WL [5:0] AIF1TX_SLOT_LEN [7:0] 1818h R1288 (508h) AIF1 Frame Ctrl 2 0 0 AIF1RX_WL [5:0] AIF1RX_SLOT_LEN [7:0] 1818h R1289 (509h) AIF1 Frame Ctrl 3 0 0 0 0 0 0 0 0 0 0 AIF1TX1_SLOT [5:0] 0000h R1290 (50Ah) AIF1 Frame Ctrl 4 0 0 0 0 0 0 0 0 0 0 AIF1TX2_SLOT [5:0] 0001h

328 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1291 (50Bh) AIF1 Frame Ctrl 5 0 0 0 0 0 0 0 0 0 0 AIF1TX3_SLOT [5:0] 0002h R1292 (50Ch) AIF1 Frame Ctrl 6 0 0 0 0 0 0 0 0 0 0 AIF1TX4_SLOT [5:0] 0003h R1293 (50Dh) AIF1 Frame Ctrl 7 0 0 0 0 0 0 0 0 0 0 AIF1TX5_SLOT [5:0] 0004h R1294 (50Eh) AIF1 Frame Ctrl 8 0 0 0 0 0 0 0 0 0 0 AIF1TX6_SLOT [5:0] 0005h R1295 (50Fh) AIF1 Frame Ctrl 9 0 0 0 0 0 0 0 0 0 0 AIF1TX7_SLOT [5:0] 0006h R1296 (510h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1TX8_SLOT [5:0] 0007h R1297 (511h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX1_SLOT [5:0] 0000h R1298 (512h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX2_SLOT [5:0] 0001h R1299 (513h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX3_SLOT [5:0] 0002h R1300 (514h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX4_SLOT [5:0] 0003h R1301 (515h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX5_SLOT [5:0] 0004h R1302 (516h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX6_SLOT [5:0] 0005h R1303 (517h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX7_SLOT [5:0] 0006h R1304 (518h) AIF1 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF1RX8_SLOT [5:0] 0007h R1305 (519h) AIF1 Tx Enables 0 0 0 0 0 0 0 0 AIF1T X8_EN A AIF1T X7_EN A AIF1T X6_EN A AIF1T X5_EN A AIF1T X4_EN A AIF1T X3_EN A AIF1T X2_EN A AIF1T X1_EN A 0000h R1306 (51Ah) AIF1 Rx Enables 0 0 0 0 0 0 0 0 AIF1R X8_EN A AIF1R X7_EN A AIF1R X6_EN A AIF1R X5_EN A AIF1R X4_EN A AIF1R X3_EN A AIF1R X2_EN A AIF1R X1_EN A 0000h R1344 (540h) AIF2 BCLK Ctrl 0 0 0 0 0 0 0 0 AIF2_ BCLK_ INV AIF2_ BCLK_ FRC AIF2_ BCLK_ MSTR AIF2_BCLK_FREQ [4:0] 000Ch R1345 (541h) AIF2 Tx Pin Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2T X_DAT _TRI

0 AIF2T

X_LRC LK_SR C AIF2T X_LRC LK_IN V AIF2T X_LRC LK_FR C AIF2T X_LRC LK_MS TR 0008h R1346 (542h) AIF2 Rx Pin Ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2R X_LRC LK_IN V AIF2R X_LRC LK_FR C AIF2R X_LRC LK_MS TR 0000h R1347 (543h) AIF2 Rate Ctrl 0 AIF2_RATE [3:0] 0 0 0 0 AIF2_T RI 0 0 0 0 0 0 0000h R1348 (544h) AIF2 Format 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF2_FMT [2:0] 0000h R1349 (545h) AIF2 Tx BCLK Rate 0 0 0 AIF2TX_BCPF [12:0] 0040h R1350 (546h) AIF2 Rx BCLK Rate 0 0 0 AIF2RX_BCPF [12:0] 0040h R1351 (547h) AIF2 Frame Ctrl 1 0 0 AIF2TX_WL [5:0] AIF2TX_SLOT_LEN [7:0] 1818h R1352 (548h) AIF2 Frame Ctrl 2 0 0 AIF2RX_WL [5:0] AIF2RX_SLOT_LEN [7:0] 1818h R1353 (549h) AIF2 Frame Ctrl 3 0 0 0 0 0 0 0 0 0 0 AIF2TX1_SLOT [5:0] 0000h R1354 (54Ah) AIF2 Frame Ctrl 4 0 0 0 0 0 0 0 0 0 0 AIF2TX2_SLOT [5:0] 0001h R1355 (54Bh) AIF2 Frame Ctrl 5 0 0 0 0 0 0 0 0 0 0 AIF2TX3_SLOT [5:0] 0002h R1356 (54Ch) AIF2 Frame Ctrl 6 0 0 0 0 0 0 0 0 0 0 AIF2TX4_SLOT [5:0] 0003h R1357 (54Dh) AIF2 Frame Ctrl 7 0 0 0 0 0 0 0 0 0 0 AIF2TX5_SLOT [5:0] 0004h R1358 (54Eh) AIF2 Frame Ctrl 8 0 0 0 0 0 0 0 0 0 0 AIF2TX6_SLOT [5:0] 0005h

Rev 4.0 329 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1361 (551h) AIF2 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2RX1_SLOT [5:0] 0000h R1362 (552h) AIF2 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2RX2_SLOT [5:0] 0001h R1363 (553h) AIF2 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2RX3_SLOT [5:0] 0002h R1364 (554h) AIF2 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2RX4_SLOT [5:0] 0003h R1365 (555h) AIF2 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2RX5_SLOT [5:0] 0004h R1366 (556h) AIF2 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF2RX6_SLOT [5:0] 0005h R1369 (559h) AIF2 Tx Enables 0 0 0 0 0 0 0 0 0 0 AIF2T X6_EN A AIF2T X5_EN A AIF2T X4_EN A AIF2T X3_EN A AIF2T X2_EN A AIF2T X1_EN A 0000h R1370 (55Ah) AIF2 Rx Enables 0 0 0 0 0 0 0 0 0 0 AIF2R X6_EN A AIF2R X5_EN A AIF2R X4_EN A AIF2R X3_EN A AIF2R X2_EN A AIF2R X1_EN A 0000h R1408 (580h) AIF3 BCLK Ctrl 0 0 0 0 0 0 0 0 AIF3_ BCLK_ INV AIF3_ BCLK_ FRC AIF3_ BCLK_ MSTR AIF3_BCLK_FREQ [4:0] 000Ch R1409 (581h) AIF3 Tx Pin Ctrl 0 0 0 0 0 0 0 0 0 0 AIF3T X_DAT _TRI

0 AIF3T

X_LRC LK_SR C AIF3T X_LRC LK_IN V AIF3T X_LRC LK_FR C AIF3T X_LRC LK_MS TR 0008h R1410 (582h) AIF3 Rx Pin Ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3R X_LRC LK_IN V AIF3R X_LRC LK_FR C AIF3R X_LRC LK_MS TR 0000h R1411 (583h) AIF3 Rate Ctrl 0 AIF3_RATE [3:0] 0 0 0 0 AIF3_T RI 0 0 0 0 0 0 0000h R1412 (584h) AIF3 Format 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3_FMT [2:0] 0000h R1413 (585h) AIF3 Tx BCLK Rate 0 0 0 AIF3TX_BCPF [12:0] 0040h R1414 (586h) AIF3 Rx BCLK Rate 0 0 0 AIF3RX_BCPF [12:0] 0040h R1415 (587h) AIF3 Frame Ctrl 1 0 0 AIF3TX_WL [5:0] AIF3TX_SLOT_LEN [7:0] 1818h R1416 (588h) AIF3 Frame Ctrl 2 0 0 AIF3RX_WL [5:0] AIF3RX_SLOT_LEN [7:0] 1818h R1417 (589h) AIF3 Frame Ctrl 3 0 0 0 0 0 0 0 0 0 0 AIF3TX1_SLOT [5:0] 0000h R1418 (58Ah) AIF3 Frame Ctrl 4 0 0 0 0 0 0 0 0 0 0 AIF3TX2_SLOT [5:0] 0001h R1425 (591h) AIF3 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF3RX1_SLOT [5:0] 0000h R1426 (592h) AIF3 Frame Ctrl 0 0 0 0 0 0 0 0 0 0 AIF3RX2_SLOT [5:0] 0001h R1433 (599h) AIF3 Tx Enables 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3T X2_EN A AIF3T X1_EN A 0000h R1434 (59Ah) AIF3 Rx Enables 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIF3R X2_EN A AIF3R X1_EN A 0000h R1490 (05D2h) SLIMbus RX Ports0 0 0 SLIMRX2_PORT_ADDR [5:0] 0 0 SLIMRX1_PORT_ADDR [5:0] 0100h R1491 (05D3h) SLIMbus RX Ports1 0 0 SLIMRX4_PORT_ADDR [5:0] 0 0 SLIMRX3_PORT_ADDR [5:0] 0302h R1492 (05D4h) SLIMbus RX Ports2 0 0 SLIMRX6_PORT_ADDR [5:0] 0 0 SLIMRX5_PORT_ADDR [5:0] 0504h

330 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1493 (05D5h) SLIMbus RX Ports3 0 0 SLIMRX8_PORT_ADDR [5:0] 0 0 SLIMRX7_PORT_ADDR [5:0] 0706h R1494 (05D6h) SLIMbus TX Ports0 0 0 SLIMTX2_PORT_ADDR [5:0] 0 0 SLIMTX1_PORT_ADDR [5:0] 0908h R1495 (05D7h) SLIMbus TX Ports1 0 0 SLIMTX4_PORT_ADDR [5:0] 0 0 SLIMTX3_PORT_ADDR [5:0] 0B0Ah R1496 (05D8h) SLIMbus TX Ports2 0 0 SLIMTX6_PORT_ADDR [5:0] 0 0 SLIMTX5_PORT_ADDR [5:0] 0D0Ch R1497 (05D9h) SLIMbus TX Ports3 0 0 SLIMTX8_PORT_ADDR [5:0] 0 0 SLIMTX7_PORT_ADDR [5:0] 0F0Eh R1507 (5E3h) SLIMbus Framer Ref Gear 0 0 0 0 0 0 0 0 0 0 0 SLIMC LK_SR C SLIMCLK_REF_GEAR [3:0] 0004h R1509 (5E5h) SLIMbus Rates 1 0 SLIMRX2_RATE [3:0] 0 0 0 0 SLIMRX1_RATE [3:0] 0 0 0 0000h R1510 (5E6h) SLIMbus Rates 2 0 SLIMRX4_RATE [3:0] 0 0 0 0 SLIMRX3_RATE [3:0] 0 0 0 0000h R1511 (5E7h) SLIMbus Rates 3 0 SLIMRX6_RATE [3:0] 0 0 0 0 SLIMRX5_RATE [3:0] 0 0 0 0000h R1512 (5E8h) SLIMbus Rates 4 0 SLIMRX8_RATE [3:0] 0 0 0 0 SLIMRX7_RATE [3:0] 0 0 0 0000h R1513 (5E9h) SLIMbus Rates 5 0 SLIMTX2_RATE [3:0] 0 0 0 0 SLIMTX1_RATE [3:0] 0 0 0 0000h R1514 (5EAh) SLIMbus Rates 6 0 SLIMTX4_RATE [3:0] 0 0 0 0 SLIMTX3_RATE [3:0] 0 0 0 0000h R1515 (5EBh) SLIMbus Rates 7 0 SLIMTX6_RATE [3:0] 0 0 0 0 SLIMTX5_RATE [3:0] 0 0 0 0000h R1516 (5ECh) SLIMbus Rates 8 0 SLIMTX8_RATE [3:0] 0 0 0 0 SLIMTX7_RATE [3:0] 0 0 0 0000h R1525 (5F5h) SLIMbus RX Channel Enable 0 0 0 0 0 0 0 0 SLIMR X8_EN A SLIMR X7_EN A SLIMR X6_EN A SLIMR X5_EN A SLIMR X4_EN A SLIMR X3_EN A SLIMR X2_EN A SLIMR X1_EN A 0000h R1526 (5F6h) SLIMbus TX Channel Enable 0 0 0 0 0 0 0 0 SLIMT X8_EN A SLIMT X7_EN A SLIMT X6_EN A SLIMT X5_EN A SLIMT X4_EN A SLIMT X3_EN A SLIMT X2_EN A SLIMT X1_EN A 0000h R1527 (5F7h) SLIMbus RX Port Status 0 0 0 0 0 0 0 0 SLIMR X8_PO RT_ST S SLIMR X7_PO RT_ST S SLIMR X6_PO RT_ST S SLIMR X5_PO RT_ST S SLIMR X4_PO RT_ST S SLIMR X3_PO RT_ST S SLIMR X2_PO RT_ST S SLIMR X1_PO RT_ST S 0000h R1528 (5F8h) SLIMbus TX Port Status 0 0 0 0 0 0 0 0 SLIMT X8_PO RT_ST S SLIMT X7_PO RT_ST S SLIMT X6_PO RT_ST S SLIMT X5_PO RT_ST S SLIMT X4_PO RT_ST S SLIMT X3_PO RT_ST S SLIMT X2_PO RT_ST S SLIMT X1_PO RT_ST S 0000h R1600 (640h) PWM1MIX Input 1 Source PWM1 MIX_S TS1 0 0 0 0 0 0 0 PWM1MIX_SRC1 [7:0] 0000h R1601 (641h) PWM1MIX Input 1 Volume 0 0 0 0 0 0 0 0 PWM1MIX_VOL1 [6:0] 0 0080h R1602 (642h) PWM1MIX Input 2 Source PWM1 MIX_S TS2 0 0 0 0 0 0 0 PWM1MIX_SRC2 [7:0] 0000h R1603 (643h) PWM1MIX Input 2 Volume 0 0 0 0 0 0 0 0 PWM1MIX_VOL2 [6:0] 0 0080h R1604 (644h) PWM1MIX Input 3 Source PWM1 MIX_S TS3 0 0 0 0 0 0 0 PWM1MIX_SRC3 [7:0] 0000h R1605 (645h) PWM1MIX Input 3 Volume 0 0 0 0 0 0 0 0 PWM1MIX_VOL3 [6:0] 0 0080h R1606 (646h) PWM1MIX Input 4 Source PWM1 MIX_S TS4 0 0 0 0 0 0 0 PWM1MIX_SRC4 [7:0] 0000h

Rev 4.0 331 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1607 (647h) PWM1MIX Input 4 Volume 0 0 0 0 0 0 0 0 PWM1MIX_VOL4 [6:0] 0 0080h R1608 (648h) PWM2MIX Input 1 Source PWM2 MIX_S TS1 0 0 0 0 0 0 0 PWM2MIX_SRC1 [7:0] 0000h R1609 (649h) PWM2MIX Input 1 Volume 0 0 0 0 0 0 0 0 PWM2MIX_VOL1 [6:0] 0 0080h R1610 (64Ah) PWM2MIX Input 2 Source PWM2 MIX_S TS2 0 0 0 0 0 0 0 PWM2MIX_SRC2 [7:0] 0000h R1611 (64Bh) PWM2MIX Input 2 Volume 0 0 0 0 0 0 0 0 PWM2MIX_VOL2 [6:0] 0 0080h R1612 (64Ch) PWM2MIX Input 3 Source PWM2 MIX_S TS3 0 0 0 0 0 0 0 PWM2MIX_SRC3 [7:0] 0000h R1613 (64Dh) PWM2MIX Input 3 Volume 0 0 0 0 0 0 0 0 PWM2MIX_VOL3 [6:0] 0 0080h R1614 (64Eh) PWM2MIX Input 4 Source PWM2 MIX_S TS4 0 0 0 0 0 0 0 PWM2MIX_SRC4 [7:0] 0000h R1615 (64Fh) PWM2MIX Input 4 Volume 0 0 0 0 0 0 0 0 PWM2MIX_VOL4 [6:0] 0 0080h R1632 (660h) MICMIX Input 1 Source MICMI X_STS 0 0 0 0 0 0 0 MICMIX_SRC1 [7:0] 0000h R1633 (661h) MICMIX Input 1 Volume 0 0 0 0 0 0 0 0 MICMIX_VOL1 [6:0] 0 0080h R1634 (662h) MICMIX Input 2 Source MICMI X_STS 0 0 0 0 0 0 0 MICMIX_SRC2 [7:0] 0000h R1635 (663h) MICMIX Input 2 Volume 0 0 0 0 0 0 0 0 MICMIX_VOL2 [6:0] 0 0080h R1636 (664h) MICMIX Input 3 Source MICMI X_STS 0 0 0 0 0 0 0 MICMIX_SRC3 [7:0] 0000h R1637 (665h) MICMIX Input 3 Volume 0 0 0 0 0 0 0 0 MICMIX_VOL3 [6:0] 0 0080h R1638 (666h) MICMIX Input 4 Source MICMI X_STS 0 0 0 0 0 0 0 MICMIX_SRC4 [7:0] 0000h R1639 (667h) MICMIX Input 4 Volume 0 0 0 0 0 0 0 0 MICMIX_VOL4 [6:0] 0 0080h R1640 (668h) NOISEMIX Input 1 Source NOISE MIX_S TS1 0 0 0 0 0 0 0 NOISEMIX_SRC1 [7:0] 0000h R1641 (669h) NOISEMIX Input 1 Volume 0 0 0 0 0 0 0 0 NOISEMIX_VOL1 [6:0] 0 0080h R1642 (66Ah) NOISEMIX Input 2 Source NOISE MIX_S TS2 0 0 0 0 0 0 0 NOISEMIX_SRC2 [7:0] 0000h R1643 (66Bh) NOISEMIX Input 2 Volume 0 0 0 0 0 0 0 0 NOISEMIX_VOL2 [6:0] 0 0080h R1644 (66Ch) NOISEMIX Input 3 Source NOISE MIX_S TS3 0 0 0 0 0 0 0 NOISEMIX_SRC3 [7:0] 0000h R1645 (66Dh) NOISEMIX Input 3 Volume 0 0 0 0 0 0 0 0 NOISEMIX_VOL3 [6:0] 0 0080h

332 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1646 (66Eh) NOISEMIX Input 4 Source NOISE MIX_S TS4 0 0 0 0 0 0 0 NOISEMIX_SRC4 [7:0] 0000h R1647 (66Fh) NOISEMIX Input 4 Volume 0 0 0 0 0 0 0 0 NOISEMIX_VOL4 [6:0] 0 0080h R1664 (680h) OUT1LMIX Input

1 Source

MIX_S TS1 0 0 0 0 0 0 0 OUT1LMIX_SRC1 [7:0] 0000h R1665 (681h) OUT1LMIX Input

1 Volume

0 0 0 0 0 0 0 0 OUT1LMIX_VOL1 [6:0] 0 0080h R1666 (682h) OUT1LMIX Input

2 Source

MIX_S TS2 0 0 0 0 0 0 0 OUT1LMIX_SRC2 [7:0] 0000h R1667 (683h) OUT1LMIX Input

2 Volume

0 0 0 0 0 0 0 0 OUT1LMIX_VOL2 [6:0] 0 0080h R1668 (684h) OUT1LMIX Input

3 Source

MIX_S TS3 0 0 0 0 0 0 0 OUT1LMIX_SRC3 [7:0] 0000h R1669 (685h) OUT1LMIX Input

3 Volume

0 0 0 0 0 0 0 0 OUT1LMIX_VOL3 [6:0] 0 0080h R1670 (686h) OUT1LMIX Input

4 Source

MIX_S TS4 0 0 0 0 0 0 0 OUT1LMIX_SRC4 [7:0] 0000h R1671 (687h) OUT1LMIX Input

4 Volume

0 0 0 0 0 0 0 0 OUT1LMIX_VOL4 [6:0] 0 0080h R1672 (688h) OUT1RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 OUT1RMIX_SRC1 [7:0] 0000h R1673 (689h) OUT1RMIX Input 0 0 0 0 0 0 0 0 OUT1RMIX_VOL1 [6:0] 0 0080h R1674 (68Ah) OUT1RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 OUT1RMIX_SRC2 [7:0] 0000h R1675 (68Bh) OUT1RMIX Input 0 0 0 0 0 0 0 0 OUT1RMIX_VOL2 [6:0] 0 0080h R1676 (68Ch) OUT1RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 OUT1RMIX_SRC3 [7:0] 0000h R1677 (68Dh) OUT1RMIX Input 0 0 0 0 0 0 0 0 OUT1RMIX_VOL3 [6:0] 0 0080h R1678 (68Eh) OUT1RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 OUT1RMIX_SRC4 [7:0] 0000h R1679 (68Fh) OUT1RMIX Input 0 0 0 0 0 0 0 0 OUT1RMIX_VOL4 [6:0] 0 0080h R1680 (690h) OUT2LMIX Input MIX_S TS1 0 0 0 0 0 0 0 OUT2LMIX_SRC1 [7:0] 0000h R1681 (691h) OUT2LMIX Input 0 0 0 0 0 0 0 0 OUT2LMIX_VOL1 [6:0] 0 0080h R1682 (692h) OUT2LMIX Input MIX_S TS2 0 0 0 0 0 0 0 OUT2LMIX_SRC2 [7:0] 0000h R1683 (693h) OUT2LMIX Input 0 0 0 0 0 0 0 0 OUT2LMIX_VOL2 [6:0] 0 0080h R1684 (694h) OUT2LMIX Input MIX_S TS3 0 0 0 0 0 0 0 OUT2LMIX_SRC3 [7:0] 0000h

Rev 4.0 333 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1685 (695h) OUT2LMIX Input 0 0 0 0 0 0 0 0 OUT2LMIX_VOL3 [6:0] 0 0080h R1686 (696h) OUT2LMIX Input MIX_S TS4 0 0 0 0 0 0 0 OUT2LMIX_SRC4 [7:0] 0000h R1687 (697h) OUT2LMIX Input 0 0 0 0 0 0 0 0 OUT2LMIX_VOL4 [6:0] 0 0080h R1688 (698h) OUT2RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 OUT2RMIX_SRC1 [7:0] 0000h R1689 (699h) OUT2RMIX Input 0 0 0 0 0 0 0 0 OUT2RMIX_VOL1 [6:0] 0 0080h R1690 (69Ah) OUT2RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 OUT2RMIX_SRC2 [7:0] 0000h R1691 (69Bh) OUT2RMIX Input 0 0 0 0 0 0 0 0 OUT2RMIX_VOL2 [6:0] 0 0080h R1692 (69Ch) OUT2RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 OUT2RMIX_SRC3 [7:0] 0000h R1693 (69Dh) OUT2RMIX Input 0 0 0 0 0 0 0 0 OUT2RMIX_VOL3 [6:0] 0 0080h R1694 (69Eh) OUT2RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 OUT2RMIX_SRC4 [7:0] 0000h R1695 (69Fh) OUT2RMIX Input 0 0 0 0 0 0 0 0 OUT2RMIX_VOL4 [6:0] 0 0080h R1696 (6A0h) OUT3LMIX Input MIX_S TS1 0 0 0 0 0 0 0 OUT3LMIX_SRC1 [7:0] 0000h R1697 (6A1h) OUT3LMIX Input 0 0 0 0 0 0 0 0 OUT3LMIX_VOL1 [6:0] 0 0080h R1698 (6A2h) OUT3LMIX Input MIX_S TS2 0 0 0 0 0 0 0 OUT3LMIX_SRC2 [7:0] 0000h R1699 (6A3h) OUT3LMIX Input 0 0 0 0 0 0 0 0 OUT3LMIX_VOL2 [6:0] 0 0080h R1700 (6A4h) OUT3LMIX Input MIX_S TS3 0 0 0 0 0 0 0 OUT3LMIX_SRC3 [7:0] 0000h R1701 (6A5h) OUT3LMIX Input 0 0 0 0 0 0 0 0 OUT3LMIX_VOL3 [6:0] 0 0080h R1702 (6A6h) OUT3LMIX Input MIX_S TS4 0 0 0 0 0 0 0 OUT3LMIX_SRC4 [7:0] 0000h R1703 (6A7h) OUT3LMIX Input 0 0 0 0 0 0 0 0 OUT3LMIX_VOL4 [6:0] 0 0080h R1704 (6A8h) OUT3RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 OUT3RMIX_SRC1 [7:0] 0000h R1705 (6A9h) OUT3RMIX Input 0 0 0 0 0 0 0 0 OUT3RMIX_VOL1 [6:0] 0 0080h R1706 (6AAh) OUT3RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 OUT3RMIX_SRC2 [7:0] 0000h R1707 (6ABh) OUT3RMIX Input 0 0 0 0 0 0 0 0 OUT3RMIX_VOL2 [6:0] 0 0080h

334 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1708 (6ACh) OUT3RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 OUT3RMIX_SRC3 [7:0] 0000h R1709 (6ADh) OUT3RMIX Input 0 0 0 0 0 0 0 0 OUT3RMIX_VOL3 [6:0] 0 0080h R1710 (6AEh) OUT3RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 OUT3RMIX_SRC4 [7:0] 0000h R1711 (6AFh) OUT3RMIX Input 0 0 0 0 0 0 0 0 OUT3RMIX_VOL4 [6:0] 0 0080h R1712 (6B0h) OUT4LMIX Input MIX_S TS1 0 0 0 0 0 0 0 OUT4LMIX_SRC1 [7:0] 0000h R1713 (6B1h) OUT4LMIX Input 0 0 0 0 0 0 0 0 OUT4LMIX_VOL1 [6:0] 0 0080h R1714 (6B2h) OUT4LMIX Input MIX_S TS2 0 0 0 0 0 0 0 OUT4LMIX_SRC2 [7:0] 0000h R1715 (6B3h) OUT4LMIX Input 0 0 0 0 0 0 0 0 OUT4LMIX_VOL2 [6:0] 0 0080h R1716 (6B4h) OUT4LMIX Input MIX_S TS3 0 0 0 0 0 0 0 OUT4LMIX_SRC3 [7:0] 0000h R1717 (6B5h) OUT4LMIX Input 0 0 0 0 0 0 0 0 OUT4LMIX_VOL3 [6:0] 0 0080h R1718 (6B6h) OUT4LMIX Input MIX_S TS4 0 0 0 0 0 0 0 OUT4LMIX_SRC4 [7:0] 0000h R1719 (6B7h) OUT4LMIX Input 0 0 0 0 0 0 0 0 OUT4LMIX_VOL4 [6:0] 0 0080h R1720 (6B8h) OUT4RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 OUT4RMIX_SRC1 [7:0] 0000h R1721 (6B9h) OUT4RMIX Input 0 0 0 0 0 0 0 0 OUT4RMIX_VOL1 [6:0] 0 0080h R1722 (6BAh) OUT4RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 OUT4RMIX_SRC2 [7:0] 0000h R1723 (6BBh) OUT4RMIX Input 0 0 0 0 0 0 0 0 OUT4RMIX_VOL2 [6:0] 0 0080h R1724 (6BCh) OUT4RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 OUT4RMIX_SRC3 [7:0] 0000h R1725 (6BDh) OUT4RMIX Input 0 0 0 0 0 0 0 0 OUT4RMIX_VOL3 [6:0] 0 0080h R1726 (6BEh) OUT4RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 OUT4RMIX_SRC4 [7:0] 0000h R1727 (6BFh) OUT4RMIX Input 0 0 0 0 0 0 0 0 OUT4RMIX_VOL4 [6:0] 0 0080h R1728 (6C0h) OUT5LMIX Input MIX_S TS1 0 0 0 0 0 0 0 OUT5LMIX_SRC1 [7:0] 0000h R1729 (6C1h) OUT5LMIX Input 0 0 0 0 0 0 0 0 OUT5LMIX_VOL1 [6:0] 0 0080h R1730 (6C2h) OUT5LMIX Input MIX_S TS2 0 0 0 0 0 0 0 OUT5LMIX_SRC2 [7:0] 0000h

Rev 4.0 335 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1731 (6C3h) OUT5LMIX Input 0 0 0 0 0 0 0 0 OUT5LMIX_VOL2 [6:0] 0 0080h R1732 (6C4h) OUT5LMIX Input MIX_S TS3 0 0 0 0 0 0 0 OUT5LMIX_SRC3 [7:0] 0000h R1733 (6C5h) OUT5LMIX Input 0 0 0 0 0 0 0 0 OUT5LMIX_VOL3 [6:0] 0 0080h R1734 (6C6h) OUT5LMIX Input MIX_S TS4 0 0 0 0 0 0 0 OUT5LMIX_SRC4 [7:0] 0000h R1735 (6C7h) OUT5LMIX Input 0 0 0 0 0 0 0 0 OUT5LMIX_VOL4 [6:0] 0 0080h R1736 (6C8h) OUT5RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 OUT5RMIX_SRC1 [7:0] 0000h R1737 (6C9h) OUT5RMIX Input 0 0 0 0 0 0 0 0 OUT5RMIX_VOL1 [6:0] 0 0080h R1738 (6CAh) OUT5RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 OUT5RMIX_SRC2 [7:0] 0000h R1739 (6CBh) OUT5RMIX Input 0 0 0 0 0 0 0 0 OUT5RMIX_VOL2 [6:0] 0 0080h R1740 (6CCh) OUT5RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 OUT5RMIX_SRC3 [7:0] 0000h R1741 (6CDh) OUT5RMIX Input 0 0 0 0 0 0 0 0 OUT5RMIX_VOL3 [6:0] 0 0080h R1742 (6CEh) OUT5RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 OUT5RMIX_SRC4 [7:0] 0000h R1743 (6CFh) OUT5RMIX Input 0 0 0 0 0 0 0 0 OUT5RMIX_VOL4 [6:0] 0 0080h R1744 (6D0h) OUT6LMIX Input MIX_S TS1 0 0 0 0 0 0 0 OUT6LMIX_SRC1 [7:0] 0000h R1745 (6D1h) OUT6LMIX Input 0 0 0 0 0 0 0 0 OUT6LMIX_VOL1 [6:0] 0 0080h R1746 (6D2h) OUT6LMIX Input MIX_S TS2 0 0 0 0 0 0 0 OUT6LMIX_SRC2 [7:0] 0000h R1747 (6D3h) OUT6LMIX Input 0 0 0 0 0 0 0 0 OUT6LMIX_VOL2 [6:0] 0 0080h R1748 (6D4h) OUT6LMIX Input MIX_S TS3 0 0 0 0 0 0 0 OUT6LMIX_SRC3 [7:0] 0000h R1749 (6D5h) OUT6LMIX Input 0 0 0 0 0 0 0 0 OUT6LMIX_VOL3 [6:0] 0 0080h R1750 (6D6h) OUT6LMIX Input MIX_S TS4 0 0 0 0 0 0 0 OUT6LMIX_SRC4 [7:0] 0000h R1751 (6D7h) OUT6LMIX Input 0 0 0 0 0 0 0 0 OUT6LMIX_VOL4 [6:0] 0 0080h R1752 (6D8h) OUT6RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 OUT6RMIX_SRC1 [7:0] 0000h R1753 (6D9h) OUT6RMIX Input 0 0 0 0 0 0 0 0 OUT6RMIX_VOL1 [6:0] 0 0080h

336 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1754 (6DAh) OUT6RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 OUT6RMIX_SRC2 [7:0] 0000h R1755 (6DBh) OUT6RMIX Input 0 0 0 0 0 0 0 0 OUT6RMIX_VOL2 [6:0] 0 0080h R1756 (6DCh) OUT6RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 OUT6RMIX_SRC3 [7:0] 0000h R1757 (6DDh) OUT6RMIX Input 0 0 0 0 0 0 0 0 OUT6RMIX_VOL3 [6:0] 0 0080h R1758 (6DEh) OUT6RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 OUT6RMIX_SRC4 [7:0] 0000h R1759 (6DFh) OUT6RMIX Input 0 0 0 0 0 0 0 0 OUT6RMIX_VOL4 [6:0] 0 0080h R1792 (700h) AIF1TX1MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX1MIX_SRC1 [7:0] 0000h R1793 (701h) AIF1TX1MIX Input 0 0 0 0 0 0 0 0 AIF1TX1MIX_VOL1 [6:0] 0 0080h R1794 (702h) AIF1TX1MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX1MIX_SRC2 [7:0] 0000h R1795 (703h) AIF1TX1MIX Input 0 0 0 0 0 0 0 0 AIF1TX1MIX_VOL2 [6:0] 0 0080h R1796 (704h) AIF1TX1MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX1MIX_SRC3 [7:0] 0000h R1797 (705h) AIF1TX1MIX Input 0 0 0 0 0 0 0 0 AIF1TX1MIX_VOL3 [6:0] 0 0080h R1798 (706h) AIF1TX1MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX1MIX_SRC4 [7:0] 0000h R1799 (707h) AIF1TX1MIX Input 0 0 0 0 0 0 0 0 AIF1TX1MIX_VOL4 [6:0] 0 0080h R1800 (708h) AIF1TX2MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX2MIX_SRC1 [7:0] 0000h R1801 (709h) AIF1TX2MIX Input 0 0 0 0 0 0 0 0 AIF1TX2MIX_VOL1 [6:0] 0 0080h R1802 (70Ah) AIF1TX2MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX2MIX_SRC2 [7:0] 0000h R1803 (70Bh) AIF1TX2MIX Input 0 0 0 0 0 0 0 0 AIF1TX2MIX_VOL2 [6:0] 0 0080h R1804 (70Ch) AIF1TX2MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX2MIX_SRC3 [7:0] 0000h R1805 (70Dh) AIF1TX2MIX Input 0 0 0 0 0 0 0 0 AIF1TX2MIX_VOL3 [6:0] 0 0080h R1806 (70Eh) AIF1TX2MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX2MIX_SRC4 [7:0] 0000h R1807 (70Fh) AIF1TX2MIX Input 0 0 0 0 0 0 0 0 AIF1TX2MIX_VOL4 [6:0] 0 0080h R1808 (710h) AIF1TX3MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX3MIX_SRC1 [7:0] 0000h

Rev 4.0 337 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1809 (711h) AIF1TX3MIX Input 0 0 0 0 0 0 0 0 AIF1TX3MIX_VOL1 [6:0] 0 0080h R1810 (712h) AIF1TX3MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX3MIX_SRC2 [7:0] 0000h R1811 (713h) AIF1TX3MIX Input 0 0 0 0 0 0 0 0 AIF1TX3MIX_VOL2 [6:0] 0 0080h R1812 (714h) AIF1TX3MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX3MIX_SRC3 [7:0] 0000h R1813 (715h) AIF1TX3MIX Input 0 0 0 0 0 0 0 0 AIF1TX3MIX_VOL3 [6:0] 0 0080h R1814 (716h) AIF1TX3MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX3MIX_SRC4 [7:0] 0000h R1815 (717h) AIF1TX3MIX Input 0 0 0 0 0 0 0 0 AIF1TX3MIX_VOL4 [6:0] 0 0080h R1816 (718h) AIF1TX4MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX4MIX_SRC1 [7:0] 0000h R1817 (719h) AIF1TX4MIX Input 0 0 0 0 0 0 0 0 AIF1TX4MIX_VOL1 [6:0] 0 0080h R1818 (71Ah) AIF1TX4MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX4MIX_SRC2 [7:0] 0000h R1819 (71Bh) AIF1TX4MIX Input 0 0 0 0 0 0 0 0 AIF1TX4MIX_VOL2 [6:0] 0 0080h R1820 (71Ch) AIF1TX4MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX4MIX_SRC3 [7:0] 0000h R1821 (71Dh) AIF1TX4MIX Input 0 0 0 0 0 0 0 0 AIF1TX4MIX_VOL3 [6:0] 0 0080h R1822 (71Eh) AIF1TX4MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX4MIX_SRC4 [7:0] 0000h R1823 (71Fh) AIF1TX4MIX Input 0 0 0 0 0 0 0 0 AIF1TX4MIX_VOL4 [6:0] 0 0080h R1824 (720h) AIF1TX5MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX5MIX_SRC1 [7:0] 0000h R1825 (721h) AIF1TX5MIX Input 0 0 0 0 0 0 0 0 AIF1TX5MIX_VOL1 [6:0] 0 0080h R1826 (722h) AIF1TX5MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX5MIX_SRC2 [7:0] 0000h R1827 (723h) AIF1TX5MIX Input 0 0 0 0 0 0 0 0 AIF1TX5MIX_VOL2 [6:0] 0 0080h R1828 (724h) AIF1TX5MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX5MIX_SRC3 [7:0] 0000h R1829 (725h) AIF1TX5MIX Input 0 0 0 0 0 0 0 0 AIF1TX5MIX_VOL3 [6:0] 0 0080h R1830 (726h) AIF1TX5MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX5MIX_SRC4 [7:0] 0000h R1831 (727h) AIF1TX5MIX Input 0 0 0 0 0 0 0 0 AIF1TX5MIX_VOL4 [6:0] 0 0080h

338 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1832 (728h) AIF1TX6MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX6MIX_SRC1 [7:0] 0000h R1833 (729h) AIF1TX6MIX Input 0 0 0 0 0 0 0 0 AIF1TX6MIX_VOL1 [6:0] 0 0080h R1834 (72Ah) AIF1TX6MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX6MIX_SRC2 [7:0] 0000h R1835 (72Bh) AIF1TX6MIX Input 0 0 0 0 0 0 0 0 AIF1TX6MIX_VOL2 [6:0] 0 0080h R1836 (72Ch) AIF1TX6MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX6MIX_SRC3 [7:0] 0000h R1837 (72Dh) AIF1TX6MIX Input 0 0 0 0 0 0 0 0 AIF1TX6MIX_VOL3 [6:0] 0 0080h R1838 (72Eh) AIF1TX6MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX6MIX_SRC4 [7:0] 0000h R1839 (72Fh) AIF1TX6MIX Input 0 0 0 0 0 0 0 0 AIF1TX6MIX_VOL4 [6:0] 0 0080h R1840 (730h) AIF1TX7MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX7MIX_SRC1 [7:0] 0000h R1841 (731h) AIF1TX7MIX Input 0 0 0 0 0 0 0 0 AIF1TX7MIX_VOL1 [6:0] 0 0080h R1842 (732h) AIF1TX7MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX7MIX_SRC2 [7:0] 0000h R1843 (733h) AIF1TX7MIX Input 0 0 0 0 0 0 0 0 AIF1TX7MIX_VOL2 [6:0] 0 0080h R1844 (734h) AIF1TX7MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX7MIX_SRC3 [7:0] 0000h R1845 (735h) AIF1TX7MIX Input 0 0 0 0 0 0 0 0 AIF1TX7MIX_VOL3 [6:0] 0 0080h R1846 (736h) AIF1TX7MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX7MIX_SRC4 [7:0] 0000h R1847 (737h) AIF1TX7MIX Input 0 0 0 0 0 0 0 0 AIF1TX7MIX_VOL4 [6:0] 0 0080h R1848 (738h) AIF1TX8MIX Input _STS1 0 0 0 0 0 0 0 AIF1TX8MIX_SRC1 [7:0] 0000h R1849 (739h) AIF1TX8MIX Input 0 0 0 0 0 0 0 0 AIF1TX8MIX_VOL1 [6:0] 0 0080h R1850 (73Ah) AIF1TX8MIX Input _STS2 0 0 0 0 0 0 0 AIF1TX8MIX_SRC2 [7:0] 0000h R1851 (73Bh) AIF1TX8MIX Input 0 0 0 0 0 0 0 0 AIF1TX8MIX_VOL2 [6:0] 0 0080h R1852 (73Ch) AIF1TX8MIX Input _STS3 0 0 0 0 0 0 0 AIF1TX8MIX_SRC3 [7:0] 0000h R1853 (73Dh) AIF1TX8MIX Input 0 0 0 0 0 0 0 0 AIF1TX8MIX_VOL3 [6:0] 0 0080h R1854 (73Eh) AIF1TX8MIX Input _STS4 0 0 0 0 0 0 0 AIF1TX8MIX_SRC4 [7:0] 0000h

Rev 4.0 339 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1855 (73Fh) AIF1TX8MIX Input 0 0 0 0 0 0 0 0 AIF1TX8MIX_VOL4 [6:0] 0 0080h R1856 (740h) AIF2TX1MIX Input _STS1 0 0 0 0 0 0 0 AIF2TX1MIX_SRC1 [7:0] 0000h R1857 (741h) AIF2TX1MIX Input 0 0 0 0 0 0 0 0 AIF2TX1MIX_VOL1 [6:0] 0 0080h R1858 (742h) AIF2TX1MIX Input _STS2 0 0 0 0 0 0 0 AIF2TX1MIX_SRC2 [7:0] 0000h R1859 (743h) AIF2TX1MIX Input 0 0 0 0 0 0 0 0 AIF2TX1MIX_VOL2 [6:0] 0 0080h R1860 (744h) AIF2TX1MIX Input _STS3 0 0 0 0 0 0 0 AIF2TX1MIX_SRC3 [7:0] 0000h R1861 (745h) AIF2TX1MIX Input 0 0 0 0 0 0 0 0 AIF2TX1MIX_VOL3 [6:0] 0 0080h R1862 (746h) AIF2TX1MIX Input _STS4 0 0 0 0 0 0 0 AIF2TX1MIX_SRC4 [7:0] 0000h R1863 (747h) AIF2TX1MIX Input 0 0 0 0 0 0 0 0 AIF2TX1MIX_VOL4 [6:0] 0 0080h R1864 (748h) AIF2TX2MIX Input _STS1 0 0 0 0 0 0 0 AIF2TX2MIX_SRC1 [7:0] 0000h R1865 (749h) AIF2TX2MIX Input 0 0 0 0 0 0 0 0 AIF2TX2MIX_VOL1 [6:0] 0 0080h R1866 (74Ah) AIF2TX2MIX Input _STS2 0 0 0 0 0 0 0 AIF2TX2MIX_SRC2 [7:0] 0000h R1867 (74Bh) AIF2TX2MIX Input 0 0 0 0 0 0 0 0 AIF2TX2MIX_VOL2 [6:0] 0 0080h R1868 (74Ch) AIF2TX2MIX Input _STS3 0 0 0 0 0 0 0 AIF2TX2MIX_SRC3 [7:0] 0000h R1869 (74Dh) AIF2TX2MIX Input 0 0 0 0 0 0 0 0 AIF2TX2MIX_VOL3 [6:0] 0 0080h R1870 (74Eh) AIF2TX2MIX Input _STS4 0 0 0 0 0 0 0 AIF2TX2MIX_SRC4 [7:0] 0000h R1871 (74Fh) AIF2TX2MIX Input 0 0 0 0 0 0 0 0 AIF2TX2MIX_VOL4 [6:0] 0 0080h R1872 (750h) AIF2TX3MIX Input _STS1 0 0 0 0 0 0 0 AIF2TX3MIX_SRC1 [7:0] 0000h R1873 (751h) AIF2TX3MIX Input 0 0 0 0 0 0 0 0 AIF2TX3MIX_VOL1 [6:0] 0 0080h R1874 (752h) AIF2TX3MIX Input _STS2 0 0 0 0 0 0 0 AIF2TX3MIX_SRC2 [7:0] 0000h R1875 (753h) AIF2TX3MIX Input 0 0 0 0 0 0 0 0 AIF2TX3MIX_VOL2 [6:0] 0 0080h R1876 (754h) AIF2TX3MIX Input _STS3 0 0 0 0 0 0 0 AIF2TX3MIX_SRC3 [7:0] 0000h R1877 (755h) AIF2TX3MIX Input 0 0 0 0 0 0 0 0 AIF2TX3MIX_VOL3 [6:0] 0 0080h

340 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1878 (756h) AIF2TX3MIX Input _STS4 0 0 0 0 0 0 0 AIF2TX3MIX_SRC4 [7:0] 0000h R1879 (757h) AIF2TX3MIX Input 0 0 0 0 0 0 0 0 AIF2TX3MIX_VOL4 [6:0] 0 0080h R1880 (758h) AIF2TX4MIX Input _STS1 0 0 0 0 0 0 0 AIF2TX4MIX_SRC1 [7:0] 0000h R1881 (759h) AIF2TX4MIX Input 0 0 0 0 0 0 0 0 AIF2TX4MIX_VOL1 [6:0] 0 0080h R1882 (75Ah) AIF2TX4MIX Input _STS2 0 0 0 0 0 0 0 AIF2TX4MIX_SRC2 [7:0] 0000h R1883 (75Bh) AIF2TX4MIX Input 0 0 0 0 0 0 0 0 AIF2TX4MIX_VOL2 [6:0] 0 0080h R1884 (75Ch) AIF2TX4MIX Input _STS3 0 0 0 0 0 0 0 AIF2TX4MIX_SRC3 [7:0] 0000h R1885 (75Dh) AIF2TX4MIX Input 0 0 0 0 0 0 0 0 AIF2TX4MIX_VOL3 [6:0] 0 0080h R1886 (75Eh) AIF2TX4MIX Input _STS4 0 0 0 0 0 0 0 AIF2TX4MIX_SRC4 [7:0] 0000h R1887 (75Fh) AIF2TX4MIX Input 0 0 0 0 0 0 0 0 AIF2TX4MIX_VOL4 [6:0] 0 0080h R1888 (760h) AIF2TX5MIX Input _STS1 0 0 0 0 0 0 0 AIF2TX5MIX_SRC1 [7:0] 0000h R1889 (761h) AIF2TX5MIX Input 0 0 0 0 0 0 0 0 AIF2TX5MIX_VOL1 [6:0] 0 0080h R1890 (762h) AIF2TX5MIX Input _STS2 0 0 0 0 0 0 0 AIF2TX5MIX_SRC2 [7:0] 0000h R1891 (763h) AIF2TX5MIX Input 0 0 0 0 0 0 0 0 AIF2TX5MIX_VOL2 [6:0] 0 0080h R1892 (764h) AIF2TX5MIX Input _STS3 0 0 0 0 0 0 0 AIF2TX5MIX_SRC3 [7:0] 0000h R1893 (765h) AIF2TX5MIX Input 0 0 0 0 0 0 0 0 AIF2TX5MIX_VOL3 [6:0] 0 0080h R1894 (766h) AIF2TX5MIX Input _STS4 0 0 0 0 0 0 0 AIF2TX5MIX_SRC4 [7:0] 0000h R1895 (767h) AIF2TX5MIX Input 0 0 0 0 0 0 0 0 AIF2TX5MIX_VOL4 [6:0] 0 0080h R1896 (768h) AIF2TX6MIX Input _STS1 0 0 0 0 0 0 0 AIF2TX6MIX_SRC1 [7:0] 0000h R1897 (769h) AIF2TX6MIX Input 0 0 0 0 0 0 0 0 AIF2TX6MIX_VOL1 [6:0] 0 0080h R1898 (76Ah) AIF2TX6MIX Input _STS2 0 0 0 0 0 0 0 AIF2TX6MIX_SRC2 [7:0] 0000h R1899 (76Bh) AIF2TX6MIX Input 0 0 0 0 0 0 0 0 AIF2TX6MIX_VOL2 [6:0] 0 0080h R1900 (76Ch) AIF2TX6MIX Input _STS3 0 0 0 0 0 0 0 AIF2TX6MIX_SRC3 [7:0] 0000h

Rev 4.0 341 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1901 (76Dh) AIF2TX6MIX Input 0 0 0 0 0 0 0 0 AIF2TX6MIX_VOL3 [6:0] 0 0080h R1902 (76Eh) AIF2TX6MIX Input _STS4 0 0 0 0 0 0 0 AIF2TX6MIX_SRC4 [7:0] 0000h R1903 (76Fh) AIF2TX6MIX Input 0 0 0 0 0 0 0 0 AIF2TX6MIX_VOL4 [6:0] 0 0080h R1920 (780h) AIF3TX1MIX Input _STS1 0 0 0 0 0 0 0 AIF3TX1MIX_SRC1 [7:0] 0000h R1921 (781h) AIF3TX1MIX Input 0 0 0 0 0 0 0 0 AIF3TX1MIX_VOL1 [6:0] 0 0080h R1922 (782h) AIF3TX1MIX Input _STS2 0 0 0 0 0 0 0 AIF3TX1MIX_SRC2 [7:0] 0000h R1923 (783h) AIF3TX1MIX Input 0 0 0 0 0 0 0 0 AIF3TX1MIX_VOL2 [6:0] 0 0080h R1924 (784h) AIF3TX1MIX Input _STS3 0 0 0 0 0 0 0 AIF3TX1MIX_SRC3 [7:0] 0000h R1925 (785h) AIF3TX1MIX Input 0 0 0 0 0 0 0 0 AIF3TX1MIX_VOL3 [6:0] 0 0080h R1926 (786h) AIF3TX1MIX Input _STS4 0 0 0 0 0 0 0 AIF3TX1MIX_SRC4 [7:0] 0000h R1927 (787h) AIF3TX1MIX Input 0 0 0 0 0 0 0 0 AIF3TX1MIX_VOL4 [6:0] 0 0080h R1928 (788h) AIF3TX2MIX Input _STS1 0 0 0 0 0 0 0 AIF3TX2MIX_SRC1 [7:0] 0000h R1929 (789h) AIF3TX2MIX Input 0 0 0 0 0 0 0 0 AIF3TX2MIX_VOL1 [6:0] 0 0080h R1930 (78Ah) AIF3TX2MIX Input _STS2 0 0 0 0 0 0 0 AIF3TX2MIX_SRC2 [7:0] 0000h R1931 (78Bh) AIF3TX2MIX Input 0 0 0 0 0 0 0 0 AIF3TX2MIX_VOL2 [6:0] 0 0080h R1932 (78Ch) AIF3TX2MIX Input _STS3 0 0 0 0 0 0 0 AIF3TX2MIX_SRC3 [7:0] 0000h R1933 (78Dh) AIF3TX2MIX Input 0 0 0 0 0 0 0 0 AIF3TX2MIX_VOL3 [6:0] 0 0080h R1934 (78Eh) AIF3TX2MIX Input _STS4 0 0 0 0 0 0 0 AIF3TX2MIX_SRC4 [7:0] 0000h R1935 (78Fh) AIF3TX2MIX Input 0 0 0 0 0 0 0 0 AIF3TX2MIX_VOL4 [6:0] 0 0080h R1984 (7C0h) SLIMTX1MIX Input 1 Source SLIMT X1MIX _STS1 0 0 0 0 0 0 0 SLIMTX1MIX_SRC1 [7:0] 0000h R1985 (7C1h) SLIMTX1MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX1MIX_VOL1 [6:0] 0 0080h R1986 (7C2h) SLIMTX1MIX Input 2 Source SLIMT X1MIX _STS2 0 0 0 0 0 0 0 SLIMTX1MIX_SRC2 [7:0] 0000h R1987 (7C3h) SLIMTX1MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX1MIX_VOL2 [6:0] 0 0080h

342 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1988 (7C4h) SLIMTX1MIX Input 3 Source SLIMT X1MIX _STS3 0 0 0 0 0 0 0 SLIMTX1MIX_SRC3 [7:0] 0000h R1989 (7C5h) SLIMTX1MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX1MIX_VOL3 [6:0] 0 0080h R1990 (7C6h) SLIMTX1MIX Input 4 Source SLIMT X1MIX _STS4 0 0 0 0 0 0 0 SLIMTX1MIX_SRC4 [7:0] 0000h R1991 (7C7h) SLIMTX1MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX1MIX_VOL4 [6:0] 0 0080h R1992 (7C8h) SLIMTX2MIX Input 1 Source SLIMT X2MIX _STS1 0 0 0 0 0 0 0 SLIMTX2MIX_SRC1 [7:0] 0000h R1993 (7C9h) SLIMTX2MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX2MIX_VOL1 [6:0] 0 0080h R1994 (7CAh) SLIMTX2MIX Input 2 Source SLIMT X2MIX _STS2 0 0 0 0 0 0 0 SLIMTX2MIX_SRC2 [7:0] 0000h R1995 (7CBh) SLIMTX2MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX2MIX_VOL2 [6:0] 0 0080h R1996 (7CCh) SLIMTX2MIX Input 3 Source SLIMT X2MIX _STS3 0 0 0 0 0 0 0 SLIMTX2MIX_SRC3 [7:0] 0000h R1997 (7CDh) SLIMTX2MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX2MIX_VOL3 [6:0] 0 0080h R1998 (7CEh) SLIMTX2MIX Input 4 Source SLIMT X2MIX _STS4 0 0 0 0 0 0 0 SLIMTX2MIX_SRC4 [7:0] 0000h R1999 (7CFh) SLIMTX2MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX2MIX_VOL4 [6:0] 0 0080h R2000 (7D0h) SLIMTX3MIX Input 1 Source SLIMT X3MIX _STS1 0 0 0 0 0 0 0 SLIMTX3MIX_SRC1 [7:0] 0000h R2001 (7D1h) SLIMTX3MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX3MIX_VOL1 [6:0] 0 0080h R2002 (7D2h) SLIMTX3MIX Input 2 Source SLIMT X3MIX _STS2 0 0 0 0 0 0 0 SLIMTX3MIX_SRC2 [7:0] 0000h R2003 (7D3h) SLIMTX3MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX3MIX_VOL2 [6:0] 0 0080h R2004 (7D4h) SLIMTX3MIX Input 3 Source SLIMT X3MIX _STS3 0 0 0 0 0 0 0 SLIMTX3MIX_SRC3 [7:0] 0000h R2005 (7D5h) SLIMTX3MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX3MIX_VOL3 [6:0] 0 0080h R2006 (7D6h) SLIMTX3MIX Input 4 Source SLIMT X3MIX _STS4 0 0 0 0 0 0 0 SLIMTX3MIX_SRC4 [7:0] 0000h R2007 (7D7h) SLIMTX3MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX3MIX_VOL4 [6:0] 0 0080h R2008 (7D8h) SLIMTX4MIX Input 1 Source SLIMT X4MIX _STS1 0 0 0 0 0 0 0 SLIMTX4MIX_SRC1 [7:0] 0000h R2009 (7D9h) SLIMTX4MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX4MIX_VOL1 [6:0] 0 0080h R2010 (7DAh) SLIMTX4MIX Input 2 Source SLIMT X4MIX _STS2 0 0 0 0 0 0 0 SLIMTX4MIX_SRC2 [7:0] 0000h

Rev 4.0 343 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2011 (7DBh) SLIMTX4MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX4MIX_VOL2 [6:0] 0 0080h R2012 (7DCh) SLIMTX4MIX Input 3 Source SLIMT X4MIX _STS3 0 0 0 0 0 0 0 SLIMTX4MIX_SRC3 [7:0] 0000h R2013 (7DDh) SLIMTX4MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX4MIX_VOL3 [6:0] 0 0080h R2014 (7DEh) SLIMTX4MIX Input 4 Source SLIMT X4MIX _STS4 0 0 0 0 0 0 0 SLIMTX4MIX_SRC4 [7:0] 0000h R2015 (7DFh) SLIMTX4MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX4MIX_VOL4 [6:0] 0 0080h R2016 (7E0h) SLIMTX5MIX Input 1 Source SLIMT X5MIX _STS1 0 0 0 0 0 0 0 SLIMTX5MIX_SRC1 [7:0] 0000h R2017 (7E1h) SLIMTX5MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX5MIX_VOL1 [6:0] 0 0080h R2018 (7E2h) SLIMTX5MIX Input 2 Source SLIMT X5MIX _STS2 0 0 0 0 0 0 0 SLIMTX5MIX_SRC2 [7:0] 0000h R2019 (7E3h) SLIMTX5MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX5MIX_VOL2 [6:0] 0 0080h R2020 (7E4h) SLIMTX5MIX Input 3 Source SLIMT X5MIX _STS3 0 0 0 0 0 0 0 SLIMTX5MIX_SRC3 [7:0] 0000h R2021 (7E5h) SLIMTX5MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX5MIX_VOL3 [6:0] 0 0080h R2022 (7E6h) SLIMTX5MIX Input 4 Source SLIMT X5MIX _STS4 0 0 0 0 0 0 0 SLIMTX5MIX_SRC4 [7:0] 0000h R2023 (7E7h) SLIMTX5MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX5MIX_VOL4 [6:0] 0 0080h R2024 (7E8h) SLIMTX6MIX Input 1 Source SLIMT X6MIX _STS1 0 0 0 0 0 0 0 SLIMTX6MIX_SRC1 [7:0] 0000h R2025 (7E9h) SLIMTX6MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX6MIX_VOL1 [6:0] 0 0080h R2026 (7EAh) SLIMTX6MIX Input 2 Source SLIMT X6MIX _STS2 0 0 0 0 0 0 0 SLIMTX6MIX_SRC2 [7:0] 0000h R2027 (7EBh) SLIMTX6MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX6MIX_VOL2 [6:0] 0 0080h R2028 (7ECh) SLIMTX6MIX Input 3 Source SLIMT X6MIX _STS3 0 0 0 0 0 0 0 SLIMTX6MIX_SRC3 [7:0] 0000h R2029 (7EDh) SLIMTX6MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX6MIX_VOL3 [6:0] 0 0080h R2030 (7EEh) SLIMTX6MIX Input 4 Source SLIMT X6MIX _STS4 0 0 0 0 0 0 0 SLIMTX6MIX_SRC4 [7:0] 0000h R2031 (7EFh) SLIMTX6MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX6MIX_VOL4 [6:0] 0 0080h R2032 (7F0h) SLIMTX7MIX Input 1 Source SLIMT X7MIX _STS1 0 0 0 0 0 0 0 SLIMTX7MIX_SRC1 [7:0] 0000h R2033 (7F1h) SLIMTX7MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX7MIX_VOL1 [6:0] 0 0080h

344 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2034 (7F2h) SLIMTX7MIX Input 2 Source SLIMT X7MIX _STS2 0 0 0 0 0 0 0 SLIMTX7MIX_SRC2 [7:0] 0000h R2035 (7F3h) SLIMTX7MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX7MIX_VOL2 [6:0] 0 0080h R2036 (7F4h) SLIMTX7MIX Input 3 Source SLIMT X7MIX _STS3 0 0 0 0 0 0 0 SLIMTX7MIX_SRC3 [7:0] 0000h R2037 (7F5h) SLIMTX7MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX7MIX_VOL3 [6:0] 0 0080h R2038 (7F6h) SLIMTX7MIX Input 4 Source SLIMT X7MIX _STS4 0 0 0 0 0 0 0 SLIMTX7MIX_SRC4 [7:0] 0000h R2039 (7F7h) SLIMTX7MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX7MIX_VOL4 [6:0] 0 0080h R2040 (7F8h) SLIMTX8MIX Input 1 Source SLIMT X8MIX _STS1 0 0 0 0 0 0 0 SLIMTX8MIX_SRC1 [7:0] 0000h R2041 (7F9h) SLIMTX8MIX Input 1 Volume 0 0 0 0 0 0 0 0 SLIMTX8MIX_VOL1 [6:0] 0 0080h R2042 (7FAh) SLIMTX8MIX Input 2 Source SLIMT X8MIX _STS2 0 0 0 0 0 0 0 SLIMTX8MIX_SRC2 [7:0] 0000h R2043 (7FBh) SLIMTX8MIX Input 2 Volume 0 0 0 0 0 0 0 0 SLIMTX8MIX_VOL2 [6:0] 0 0080h R2044 (7FCh) SLIMTX8MIX Input 3 Source SLIMT X8MIX _STS3 0 0 0 0 0 0 0 SLIMTX8MIX_SRC3 [7:0] 0000h R2045 (7FDh) SLIMTX8MIX Input 3 Volume 0 0 0 0 0 0 0 0 SLIMTX8MIX_VOL3 [6:0] 0 0080h R2046 (7FEh) SLIMTX8MIX Input 4 Source SLIMT X8MIX _STS4 0 0 0 0 0 0 0 SLIMTX8MIX_SRC4 [7:0] 0000h R2047 (7FFh) SLIMTX8MIX Input 4 Volume 0 0 0 0 0 0 0 0 SLIMTX8MIX_VOL4 [6:0] 0 0080h R2176 (880h) EQ1MIX Input 1 Source EQ1MI X_STS 0 0 0 0 0 0 0 EQ1MIX_SRC1 [7:0] 0000h R2177 (881h) EQ1MIX Input 1 Volume 0 0 0 0 0 0 0 0 EQ1MIX_VOL1 [6:0] 0 0080h R2178 (882h) EQ1MIX Input 2 Source EQ1MI X_STS 0 0 0 0 0 0 0 EQ1MIX_SRC2 [7:0] 0000h R2179 (883h) EQ1MIX Input 2 Volume 0 0 0 0 0 0 0 0 EQ1MIX_VOL2 [6:0] 0 0080h R2180 (884h) EQ1MIX Input 3 Source EQ1MI X_STS 0 0 0 0 0 0 0 EQ1MIX_SRC3 [7:0] 0000h R2181 (885h) EQ1MIX Input 3 Volume 0 0 0 0 0 0 0 0 EQ1MIX_VOL3 [6:0] 0 0080h R2182 (886h) EQ1MIX Input 4 Source EQ1MI X_STS 0 0 0 0 0 0 0 EQ1MIX_SRC4 [7:0] 0000h R2183 (887h) EQ1MIX Input 4 Volume 0 0 0 0 0 0 0 0 EQ1MIX_VOL4 [6:0] 0 0080h R2184 (888h) EQ2MIX Input 1 Source EQ2MI X_STS 0 0 0 0 0 0 0 EQ2MIX_SRC1 [7:0] 0000h

Rev 4.0 345 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2185 (889h) EQ2MIX Input 1 Volume 0 0 0 0 0 0 0 0 EQ2MIX_VOL1 [6:0] 0 0080h R2186 (88Ah) EQ2MIX Input 2 Source EQ2MI X_STS 0 0 0 0 0 0 0 EQ2MIX_SRC2 [7:0] 0000h R2187 (88Bh) EQ2MIX Input 2 Volume 0 0 0 0 0 0 0 0 EQ2MIX_VOL2 [6:0] 0 0080h R2188 (88Ch) EQ2MIX Input 3 Source EQ2MI X_STS 0 0 0 0 0 0 0 EQ2MIX_SRC3 [7:0] 0000h R2189 (88Dh) EQ2MIX Input 3 Volume 0 0 0 0 0 0 0 0 EQ2MIX_VOL3 [6:0] 0 0080h R2190 (88Eh) EQ2MIX Input 4 Source EQ2MI X_STS 0 0 0 0 0 0 0 EQ2MIX_SRC4 [7:0] 0000h R2191 (88Fh) EQ2MIX Input 4 Volume 0 0 0 0 0 0 0 0 EQ2MIX_VOL4 [6:0] 0 0080h R2192 (890h) EQ3MIX Input 1 Source EQ3MI X_STS 0 0 0 0 0 0 0 EQ3MIX_SRC1 [7:0] 0000h R2193 (891h) EQ3MIX Input 1 Volume 0 0 0 0 0 0 0 0 EQ3MIX_VOL1 [6:0] 0 0080h R2194 (892h) EQ3MIX Input 2 Source EQ3MI X_STS 0 0 0 0 0 0 0 EQ3MIX_SRC2 [7:0] 0000h R2195 (893h) EQ3MIX Input 2 Volume 0 0 0 0 0 0 0 0 EQ3MIX_VOL2 [6:0] 0 0080h R2196 (894h) EQ3MIX Input 3 Source EQ3MI X_STS 0 0 0 0 0 0 0 EQ3MIX_SRC3 [7:0] 0000h R2197 (895h) EQ3MIX Input 3 Volume 0 0 0 0 0 0 0 0 EQ3MIX_VOL3 [6:0] 0 0080h R2198 (896h) EQ3MIX Input 4 Source EQ3MI X_STS 0 0 0 0 0 0 0 EQ3MIX_SRC4 [7:0] 0000h R2199 (897h) EQ3MIX Input 4 Volume 0 0 0 0 0 0 0 0 EQ3MIX_VOL4 [6:0] 0 0080h R2200 (898h) EQ4MIX Input 1 Source EQ4MI X_STS 0 0 0 0 0 0 0 EQ4MIX_SRC1 [7:0] 0000h R2201 (899h) EQ4MIX Input 1 Volume 0 0 0 0 0 0 0 0 EQ4MIX_VOL1 [6:0] 0 0080h R2202 (89Ah) EQ4MIX Input 2 Source EQ4MI X_STS 0 0 0 0 0 0 0 EQ4MIX_SRC2 [7:0] 0000h R2203 (89Bh) EQ4MIX Input 2 Volume 0 0 0 0 0 0 0 0 EQ4MIX_VOL2 [6:0] 0 0080h R2204 (89Ch) EQ4MIX Input 3 Source EQ4MI X_STS 0 0 0 0 0 0 0 EQ4MIX_SRC3 [7:0] 0000h R2205 (89Dh) EQ4MIX Input 3 Volume 0 0 0 0 0 0 0 0 EQ4MIX_VOL3 [6:0] 0 0080h R2206 (89Eh) EQ4MIX Input 4 Source EQ4MI X_STS 0 0 0 0 0 0 0 EQ4MIX_SRC4 [7:0] 0000h R2207 (89Fh) EQ4MIX Input 4 Volume 0 0 0 0 0 0 0 0 EQ4MIX_VOL4 [6:0] 0 0080h

346 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2240 (8C0h) DRC1LMIX Input MIX_S TS1 0 0 0 0 0 0 0 DRC1LMIX_SRC1 [7:0] 0000h R2241 (8C1h) DRC1LMIX Input 0 0 0 0 0 0 0 0 DRC1LMIX_VOL1 [6:0] 0 0080h R2242 (8C2h) DRC1LMIX Input MIX_S TS2 0 0 0 0 0 0 0 DRC1LMIX_SRC2 [7:0] 0000h R2243 (8C3h) DRC1LMIX Input 0 0 0 0 0 0 0 0 DRC1LMIX_VOL2 [6:0] 0 0080h R2244 (8C4h) DRC1LMIX Input MIX_S TS3 0 0 0 0 0 0 0 DRC1LMIX_SRC3 [7:0] 0000h R2245 (8C5h) DRC1LMIX Input 0 0 0 0 0 0 0 0 DRC1LMIX_VOL3 [6:0] 0 0080h R2246 (8C6h) DRC1LMIX Input MIX_S TS4 0 0 0 0 0 0 0 DRC1LMIX_SRC4 [7:0] 0000h R2247 (8C7h) DRC1LMIX Input 0 0 0 0 0 0 0 0 DRC1LMIX_VOL4 [6:0] 0 0080h R2248 (8C8h) DRC1RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 DRC1RMIX_SRC1 [7:0] 0000h R2249 (8C9h) DRC1RMIX Input 0 0 0 0 0 0 0 0 DRC1RMIX_VOL1 [6:0] 0 0080h R2250 (8CAh) DRC1RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 DRC1RMIX_SRC2 [7:0] 0000h R2251 (8CBh) DRC1RMIX Input 0 0 0 0 0 0 0 0 DRC1RMIX_VOL2 [6:0] 0 0080h R2252 (8CCh) DRC1RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 DRC1RMIX_SRC3 [7:0] 0000h R2253 (8CDh) DRC1RMIX Input 0 0 0 0 0 0 0 0 DRC1RMIX_VOL3 [6:0] 0 0080h R2254 (8CEh) DRC1RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 DRC1RMIX_SRC4 [7:0] 0000h R2255 (8CFh) DRC1RMIX Input 0 0 0 0 0 0 0 0 DRC1RMIX_VOL4 [6:0] 0 0080h R2256 (8D0h) DRC2LMIX Input MIX_S TS1 0 0 0 0 0 0 0 DRC2LMIX_SRC1 [7:0] 0000h R2257 (8D1h) DRC2LMIX Input 0 0 0 0 0 0 0 0 DRC2LMIX_VOL1 [6:0] 0 0080h R2258 (8D2h) DRC2LMIX Input MIX_S TS2 0 0 0 0 0 0 0 DRC2LMIX_SRC2 [7:0] 0000h R2259 (8D3h) DRC2LMIX Input 0 0 0 0 0 0 0 0 DRC2LMIX_VOL2 [6:0] 0 0080h R2260 (8D4h) DRC2LMIX Input MIX_S TS3 0 0 0 0 0 0 0 DRC2LMIX_SRC3 [7:0] 0000h R2261 (8D5h) DRC2LMIX Input 0 0 0 0 0 0 0 0 DRC2LMIX_VOL3 [6:0] 0 0080h R2262 (8D6h) DRC2LMIX Input MIX_S TS4 0 0 0 0 0 0 0 DRC2LMIX_SRC4 [7:0] 0000h

Rev 4.0 347 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2263 (8D7h) DRC2LMIX Input 0 0 0 0 0 0 0 0 DRC2LMIX_VOL4 [6:0] 0 0080h R2264 (8D8h) DRC2RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 DRC2RMIX_SRC1 [7:0] 0000h R2265 (8D9h) DRC2RMIX Input 0 0 0 0 0 0 0 0 DRC2RMIX_VOL1 [6:0] 0 0080h R2266 (8DAh) DRC2RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 DRC2RMIX_SRC2 [7:0] 0000h R2267 (8DBh) DRC2RMIX Input 0 0 0 0 0 0 0 0 DRC2RMIX_VOL2 [6:0] 0 0080h R2268 (8DCh) DRC2RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 DRC2RMIX_SRC3 [7:0] 0000h R2269 (8DDh) DRC2RMIX Input 0 0 0 0 0 0 0 0 DRC2RMIX_VOL3 [6:0] 0 0080h R2270 (8DEh) DRC2RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 DRC2RMIX_SRC4 [7:0] 0000h R2271 (8DFh) DRC2RMIX Input 0 0 0 0 0 0 0 0 DRC2RMIX_VOL4 [6:0] 0 0080h R2304 (900h) HPLP1MIX Input 1 Source LHPF1 MIX_S TS1 0 0 0 0 0 0 0 LHPF1MIX_SRC1 [7:0] 0000h R2305 (901h) HPLP1MIX Input 1 Volume 0 0 0 0 0 0 0 0 LHPF1MIX_VOL1 [6:0] 0 0080h R2306 (902h) HPLP1MIX Input 2 Source LHPF1 MIX_S TS2 0 0 0 0 0 0 0 LHPF1MIX_SRC2 [7:0] 0000h R2307 (903h) HPLP1MIX Input 2 Volume 0 0 0 0 0 0 0 0 LHPF1MIX_VOL2 [6:0] 0 0080h R2308 (904h) HPLP1MIX Input 3 Source LHPF1 MIX_S TS3 0 0 0 0 0 0 0 LHPF1MIX_SRC3 [7:0] 0000h R2309 (905h) HPLP1MIX Input 3 Volume 0 0 0 0 0 0 0 0 LHPF1MIX_VOL3 [6:0] 0 0080h R2310 (906h) HPLP1MIX Input 4 Source LHPF1 MIX_S TS4 0 0 0 0 0 0 0 LHPF1MIX_SRC4 [7:0] 0000h R2311 (907h) HPLP1MIX Input 4 Volume 0 0 0 0 0 0 0 0 LHPF1MIX_VOL4 [6:0] 0 0080h R2312 (908h) HPLP2MIX Input 1 Source LHPF2 MIX_S TS1 0 0 0 0 0 0 0 LHPF2MIX_SRC1 [7:0] 0000h R2313 (909h) HPLP2MIX Input 1 Volume 0 0 0 0 0 0 0 0 LHPF2MIX_VOL1 [6:0] 0 0080h R2314 (90Ah) HPLP2MIX Input 2 Source LHPF2 MIX_S TS2 0 0 0 0 0 0 0 LHPF2MIX_SRC2 [7:0] 0000h R2315 (90Bh) HPLP2MIX Input 2 Volume 0 0 0 0 0 0 0 0 LHPF2MIX_VOL2 [6:0] 0 0080h R2316 (90Ch) HPLP2MIX Input 3 Source LHPF2 MIX_S TS3 0 0 0 0 0 0 0 LHPF2MIX_SRC3 [7:0] 0000h R2317 (90Dh) HPLP2MIX Input 3 Volume 0 0 0 0 0 0 0 0 LHPF2MIX_VOL3 [6:0] 0 0080h

348 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2318 (90Eh) HPLP2MIX Input 4 Source LHPF2 MIX_S TS4 0 0 0 0 0 0 0 LHPF2MIX_SRC4 [7:0] 0000h R2319 (90Fh) HPLP2MIX Input 4 Volume 0 0 0 0 0 0 0 0 LHPF2MIX_VOL4 [6:0] 0 0080h R2320 (910h) HPLP3MIX Input 1 Source LHPF3 MIX_S TS1 0 0 0 0 0 0 0 LHPF3MIX_SRC1 [7:0] 0000h R2321 (911h) HPLP3MIX Input 1 Volume 0 0 0 0 0 0 0 0 LHPF3MIX_VOL1 [6:0] 0 0080h R2322 (912h) HPLP3MIX Input 2 Source LHPF3 MIX_S TS2 0 0 0 0 0 0 0 LHPF3MIX_SRC2 [7:0] 0000h R2323 (913h) HPLP3MIX Input 2 Volume 0 0 0 0 0 0 0 0 LHPF3MIX_VOL2 [6:0] 0 0080h R2324 (914h) HPLP3MIX Input 3 Source LHPF3 MIX_S TS3 0 0 0 0 0 0 0 LHPF3MIX_SRC3 [7:0] 0000h R2325 (915h) HPLP3MIX Input 3 Volume 0 0 0 0 0 0 0 0 LHPF3MIX_VOL3 [6:0] 0 0080h R2326 (916h) HPLP3MIX Input 4 Source LHPF3 MIX_S TS4 0 0 0 0 0 0 0 LHPF3MIX_SRC4 [7:0] 0000h R2327 (917h) HPLP3MIX Input 4 Volume 0 0 0 0 0 0 0 0 LHPF3MIX_VOL4 [6:0] 0 0080h R2328 (918h) HPLP4MIX Input 1 Source LHPF4 MIX_S TS1 0 0 0 0 0 0 0 LHPF4MIX_SRC1 [7:0] 0000h R2329 (919h) HPLP4MIX Input 1 Volume 0 0 0 0 0 0 0 0 LHPF4MIX_VOL1 [6:0] 0 0080h R2330 (91Ah) HPLP4MIX Input 2 Source LHPF4 MIX_S TS2 0 0 0 0 0 0 0 LHPF4MIX_SRC2 [7:0] 0000h R2331 (91Bh) HPLP4MIX Input 2 Volume 0 0 0 0 0 0 0 0 LHPF4MIX_VOL2 [6:0] 0 0080h R2332 (91Ch) HPLP4MIX Input 3 Source LHPF4 MIX_S TS3 0 0 0 0 0 0 0 LHPF4MIX_SRC3 [7:0] 0000h R2333 (91Dh) HPLP4MIX Input 3 Volume 0 0 0 0 0 0 0 0 LHPF4MIX_VOL3 [6:0] 0 0080h R2334 (91Eh) HPLP4MIX Input 4 Source LHPF4 MIX_S TS4 0 0 0 0 0 0 0 LHPF4MIX_SRC4 [7:0] 0000h R2335 (91Fh) HPLP4MIX Input 4 Volume 0 0 0 0 0 0 0 0 LHPF4MIX_VOL4 [6:0] 0 0080h R2368 (940h) DSP1LMIX Input 1 Source DSP1L MIX_S TS1 0 0 0 0 0 0 0 DSP1LMIX_SRC1 [7:0] 0000h R2369 (941h) DSP1LMIX Input 1 Volume 0 0 0 0 0 0 0 0 DSP1LMIX_VOL1 [6:0] 0 0080h R2370 (942h) DSP1LMIX Input 2 Source DSP1L MIX_S TS2 0 0 0 0 0 0 0 DSP1LMIX_SRC2 [7:0] 0000h R2371 (943h) DSP1LMIX Input 2 Volume 0 0 0 0 0 0 0 0 DSP1LMIX_VOL2 [6:0] 0 0080h R2372 (944h) DSP1LMIX Input 3 Source DSP1L MIX_S TS3 0 0 0 0 0 0 0 DSP1LMIX_SRC3 [7:0] 0000h

Rev 4.0 349 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2373 (945h) DSP1LMIX Input 3 Volume 0 0 0 0 0 0 0 0 DSP1LMIX_VOL3 [6:0] 0 0080h R2374 (946h) DSP1LMIX Input 4 Source DSP1L MIX_S TS4 0 0 0 0 0 0 0 DSP1LMIX_SRC4 [7:0] 0000h R2375 (947h) DSP1LMIX Input 4 Volume 0 0 0 0 0 0 0 0 DSP1LMIX_VOL4 [6:0] 0 0080h R2376 (948h) DSP1RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 DSP1RMIX_SRC1 [7:0] 0000h R2377 (949h) DSP1RMIX Input 0 0 0 0 0 0 0 0 DSP1RMIX_VOL1 [6:0] 0 0080h R2378 (94Ah) DSP1RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 DSP1RMIX_SRC2 [7:0] 0000h R2379 (94Bh) DSP1RMIX Input 0 0 0 0 0 0 0 0 DSP1RMIX_VOL2 [6:0] 0 0080h R2380 (94Ch) DSP1RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 DSP1RMIX_SRC3 [7:0] 0000h R2381 (94Dh) DSP1RMIX Input 0 0 0 0 0 0 0 0 DSP1RMIX_VOL3 [6:0] 0 0080h R2382 (94Eh) DSP1RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 DSP1RMIX_SRC4 [7:0] 0000h R2383 (94Fh) DSP1RMIX Input 0 0 0 0 0 0 0 0 DSP1RMIX_VOL4 [6:0] 0 0080h R2384 (950h) DSP1AUX1MIX Input 1 Source DSP1A UX1MI X_STS 0 0 0 0 0 0 0 DSP1AUX1_SRC [7:0] 0000h R2392 (958h) DSP1AUX2MIX Input 1 Source DSP1A UX2MI X_STS 0 0 0 0 0 0 0 DSP1AUX2_SRC [7:0] 0000h R2400 (960h) DSP1AUX3MIX Input 1 Source DSP1A UX3MI X_STS 0 0 0 0 0 0 0 DSP1AUX3_SRC [7:0] 0000h R2408 (968h) DSP1AUX4MIX Input 1 Source DSP1A UX4MI X_STS 0 0 0 0 0 0 0 DSP1AUX4_SRC [7:0] 0000h R2416 (970h) DSP1AUX5MIX Input 1 Source DSP1A UX5MI X_STS 0 0 0 0 0 0 0 DSP1AUX5_SRC [7:0] 0000h R2424 (978h) DSP1AUX6MIX Input 1 Source DSP1A UX6MI X_STS 0 0 0 0 0 0 0 DSP1AUX6_SRC [7:0] 0000h R2432 (980h) DSP2LMIX Input 1 Source DSP2L MIX_S TS1 0 0 0 0 0 0 0 DSP2LMIX_SRC1 [7:0] 0000h R2433 (981h) DSP2LMIX Input 1 Volume 0 0 0 0 0 0 0 0 DSP2LMIX_VOL1 [6:0] 0 0080h R2434 (982h) DSP2LMIX Input 2 Source DSP2L MIX_S TS2 0 0 0 0 0 0 0 DSP2LMIX_SRC2 [7:0] 0000h R2435 (983h) DSP2LMIX Input 2 Volume 0 0 0 0 0 0 0 0 DSP2LMIX_VOL2 [6:0] 0 0080h R2436 (984h) DSP2LMIX Input 3 Source DSP2L MIX_S TS3 0 0 0 0 0 0 0 DSP2LMIX_SRC3 [7:0] 0000h

350 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2437 (985h) DSP2LMIX Input 3 Volume 0 0 0 0 0 0 0 0 DSP2LMIX_VOL3 [6:0] 0 0080h R2438 (986h) DSP2LMIX Input 4 Source DSP2L MIX_S TS4 0 0 0 0 0 0 0 DSP2LMIX_SRC4 [7:0] 0000h R2439 (987h) DSP2LMIX Input 4 Volume 0 0 0 0 0 0 0 0 DSP2LMIX_VOL4 [6:0] 0 0080h R2440 (988h) DSP2RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 DSP2RMIX_SRC1 [7:0] 0000h R2441 (989h) DSP2RMIX Input 0 0 0 0 0 0 0 0 DSP2RMIX_VOL1 [6:0] 0 0080h R2442 (98Ah) DSP2RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 DSP2RMIX_SRC2 [7:0] 0000h R2443 (98Bh) DSP2RMIX Input 0 0 0 0 0 0 0 0 DSP2RMIX_VOL2 [6:0] 0 0080h R2444 (98Ch) DSP2RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 DSP2RMIX_SRC3 [7:0] 0000h R2445 (98Dh) DSP2RMIX Input 0 0 0 0 0 0 0 0 DSP2RMIX_VOL3 [6:0] 0 0080h R2446 (98Eh) DSP2RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 DSP2RMIX_SRC4 [7:0] 0000h R2447 (98Fh) DSP2RMIX Input 0 0 0 0 0 0 0 0 DSP2RMIX_VOL4 [6:0] 0 0080h R2448 (990h) DSP2AUX1MIX Input 1 Source DSP2A UX1MI X_STS 0 0 0 0 0 0 0 DSP2AUX1_SRC [7:0] 0000h R2456 (998h) DSP2AUX2MIX Input 1 Source DSP2A UX2MI X_STS 0 0 0 0 0 0 0 DSP2AUX2_SRC [7:0] 0000h R2464 (9A0h) DSP2AUX3MIX Input 1 Source DSP2A UX3MI X_STS 0 0 0 0 0 0 0 DSP2AUX3_SRC [7:0] 0000h R2472 (9A8h) DSP2AUX4MIX Input 1 Source DSP2A UX4MI X_STS 0 0 0 0 0 0 0 DSP2AUX4_SRC [7:0] 0000h R2480 (9B0h) DSP2AUX5MIX Input 1 Source DSP2A UX5MI X_STS 0 0 0 0 0 0 0 DSP2AUX5_SRC [7:0] 0000h R2488 (9B8h) DSP2AUX6MIX Input 1 Source DSP2A UX6MI X_STS 0 0 0 0 0 0 0 DSP2AUX6_SRC [7:0] 0000h R2496 (9C0h) DSP3LMIX Input 1 Source DSP3L MIX_S TS1 0 0 0 0 0 0 0 DSP3LMIX_SRC1 [7:0] 0000h R2497 (9C1h) DSP3LMIX Input 1 Volume 0 0 0 0 0 0 0 0 DSP3LMIX_VOL1 [6:0] 0 0080h R2498 (9C2h) DSP3LMIX Input 2 Source DSP3L MIX_S TS2 0 0 0 0 0 0 0 DSP3LMIX_SRC2 [7:0] 0000h R2499 (9C3h) DSP3LMIX Input 2 Volume 0 0 0 0 0 0 0 0 DSP3LMIX_VOL2 [6:0] 0 0080h R2500 (9C4h) DSP3LMIX Input 3 Source DSP3L MIX_S TS3 0 0 0 0 0 0 0 DSP3LMIX_SRC3 [7:0] 0000h

Rev 4.0 351 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2501 (9C5h) DSP3LMIX Input 3 Volume 0 0 0 0 0 0 0 0 DSP3LMIX_VOL3 [6:0] 0 0080h R2502 (9C6h) DSP3LMIX Input 4 Source DSP3L MIX_S TS4 0 0 0 0 0 0 0 DSP3LMIX_SRC4 [7:0] 0000h R2503 (9C7h) DSP3LMIX Input 4 Volume 0 0 0 0 0 0 0 0 DSP3LMIX_VOL4 [6:0] 0 0080h R2504 (9C8h) DSP3RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 DSP3RMIX_SRC1 [7:0] 0000h R2505 (9C9h) DSP3RMIX Input 0 0 0 0 0 0 0 0 DSP3RMIX_VOL1 [6:0] 0 0080h R2506 (9CAh) DSP3RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 DSP3RMIX_SRC2 [7:0] 0000h R2507 (9CBh) DSP3RMIX Input 0 0 0 0 0 0 0 0 DSP3RMIX_VOL2 [6:0] 0 0080h R2508 (9CCh) DSP3RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 DSP3RMIX_SRC3 [7:0] 0000h R2509 (9CDh) DSP3RMIX Input 0 0 0 0 0 0 0 0 DSP3RMIX_VOL3 [6:0] 0 0080h R2510 (9CEh) DSP3RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 DSP3RMIX_SRC4 [7:0] 0000h R2511 (9CFh) DSP3RMIX Input 0 0 0 0 0 0 0 0 DSP3RMIX_VOL4 [6:0] 0 0080h R2512 (9D0h) DSP3AUX1MIX Input 1 Source DSP3A UX1MI X_STS 0 0 0 0 0 0 0 DSP3AUX1_SRC [7:0] 0000h R2520 (9D8h) DSP3AUX2MIX Input 1 Source DSP3A UX2MI X_STS 0 0 0 0 0 0 0 DSP3AUX2_SRC [7:0] 0000h R2528 (9E0h) DSP3AUX3MIX Input 1 Source DSP3A UX3MI X_STS 0 0 0 0 0 0 0 DSP3AUX3_SRC [7:0] 0000h R2536 (9E8h) DSP3AUX4MIX Input 1 Source DSP3A UX4MI X_STS 0 0 0 0 0 0 0 DSP3AUX4_SRC [7:0] 0000h R2544 (9F0h) DSP3AUX5MIX Input 1 Source DSP3A UX5MI X_STS 0 0 0 0 0 0 0 DSP3AUX5_SRC [7:0] 0000h R2552 (9F8h) DSP3AUX6MIX Input 1 Source DSP3A UX6MI X_STS 0 0 0 0 0 0 0 DSP3AUX6_SRC [7:0] 0000h R2560 (A00h) DSP4LMIX Input 1 Source DSP4L MIX_S TS1 0 0 0 0 0 0 0 DSP4LMIX_SRC1 [7:0] 0000h R2561 (A01h) DSP4LMIX Input 1 Volume 0 0 0 0 0 0 0 0 DSP4LMIX_VOL1 [6:0] 0 0080h R2562 (A02h) DSP4LMIX Input 2 Source DSP4L MIX_S TS2 0 0 0 0 0 0 0 DSP4LMIX_SRC2 [7:0] 0000h R2563 (A03h) DSP4LMIX Input 2 Volume 0 0 0 0 0 0 0 0 DSP4LMIX_VOL2 [6:0] 0 0080h R2564 (A04h) DSP4LMIX Input 3 Source DSP4L MIX_S TS3 0 0 0 0 0 0 0 DSP4LMIX_SRC3 [7:0] 0000h

352 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2565 (A05h) DSP4LMIX Input 3 Volume 0 0 0 0 0 0 0 0 DSP4LMIX_VOL3 [6:0] 0 0080h R2566 (A06h) DSP4LMIX Input 4 Source DSP4L MIX_S TS4 0 0 0 0 0 0 0 DSP4LMIX_SRC4 [7:0] 0000h R2567 (A07h) DSP4LMIX Input 4 Volume 0 0 0 0 0 0 0 0 DSP4LMIX_VOL4 [6:0] 0 0080h R2568 (A08h) DSP4RMIX Input RMIX_ STS1 0 0 0 0 0 0 0 DSP4RMIX_SRC1 [7:0] 0000h R2569 (A09h) DSP4RMIX Input 0 0 0 0 0 0 0 0 DSP4RMIX_VOL1 [6:0] 0 0080h R2570 (A0Ah) DSP4RMIX Input RMIX_ STS2 0 0 0 0 0 0 0 DSP4RMIX_SRC2 [7:0] 0000h R2571 (A0Bh) DSP4RMIX Input 0 0 0 0 0 0 0 0 DSP4RMIX_VOL2 [6:0] 0 0080h R2572 (A0Ch) DSP4RMIX Input RMIX_ STS3 0 0 0 0 0 0 0 DSP4RMIX_SRC3 [7:0] 0000h R2573 (A0Dh) DSP4RMIX Input 0 0 0 0 0 0 0 0 DSP4RMIX_VOL3 [6:0] 0 0080h R2574 (A0Eh) DSP4RMIX Input RMIX_ STS4 0 0 0 0 0 0 0 DSP4RMIX_SRC4 [7:0] 0000h R2575 (A0Fh) DSP4RMIX Input 0 0 0 0 0 0 0 0 DSP4RMIX_VOL4 [6:0] 0 0080h R2576 (A10h) DSP4AUX1MIX Input 1 Source DSP4A UX1MI X_STS 0 0 0 0 0 0 0 DSP4AUX1_SRC [7:0] 0000h R2584 (A18h) DSP4AUX2MIX Input 1 Source DSP4A UX2MI X_STS 0 0 0 0 0 0 0 DSP4AUX2_SRC [7:0] 0000h R2592 (A20h) DSP4AUX3MIX Input 1 Source DSP4A UX3MI X_STS 0 0 0 0 0 0 0 DSP4AUX3_SRC [7:0] 0000h R2600 (A28h) DSP4AUX4MIX Input 1 Source DSP4A UX4MI X_STS 0 0 0 0 0 0 0 DSP4AUX4_SRC [7:0] 0000h R2608 (A30h) DSP4AUX5MIX Input 1 Source DSP4A UX5MI X_STS 0 0 0 0 0 0 0 DSP4AUX5_SRC [7:0] 0000h R2616 (A38h) DSP4AUX6MIX Input 1 Source DSP4A UX6MI X_STS 0 0 0 0 0 0 0 DSP4AUX6_SRC [7:0] 0000h R2688 (A80h) ASRC1LMIX Input _STS 0 0 0 0 0 0 0 ASRC1L_SRC [7:0] 0000h R2696 (A88h) ASRC1RMIX Input 1 Source ASRC 1RMIX _STS 0 0 0 0 0 0 0 ASRC1R_SRC [7:0] 0000h R2704 (A90h) ASRC2LMIX Input _STS 0 0 0 0 0 0 0 ASRC2L_SRC [7:0] 0000h R2712 (A98h) ASRC2RMIX Input 1 Source ASRC 2RMIX _STS 0 0 0 0 0 0 0 ASRC2R_SRC [7:0] 0000h

Rev 4.0 353 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2816 (B00h) ISRC1DEC1MIX Input 1 Source ISRC1 DEC1 MIX_S TS 0 0 0 0 0 0 0 ISRC1DEC1_SRC [7:0] 0000h R2824 (B08h) ISRC1DEC2MIX Input 1 Source ISRC1 DEC2 MIX_S TS 0 0 0 0 0 0 0 ISRC1DEC2_SRC [7:0] 0000h R2832 (B10h) ISRC1DEC3MIX Input 1 Source ISRC1 DEC3 MIX_S TS 0 0 0 0 0 0 0 ISRC1DEC3_SRC [7:0] 0000h R2840 (B18h) ISRC1DEC4MIX Input 1 Source ISRC1 DEC4 MIX_S TS 0 0 0 0 0 0 0 ISRC1DEC4_SRC [7:0] 0000h R2848 (B20h) ISRC1INT1MIX Input 1 Source ISRC1I NT1MI X_STS 0 0 0 0 0 0 0 ISRC1INT1_SRC [7:0] 0000h R2856 (B28h) ISRC1INT2MIX Input 1 Source ISRC1I NT2MI X_STS 0 0 0 0 0 0 0 ISRC1INT2_SRC [7:0] 0000h R2864 (B30h) ISRC1INT3MIX Input 1 Source ISRC1I NT3MI X_STS 0 0 0 0 0 0 0 ISRC1INT3_SRC [7:0] 0000h R2872 (B38h) ISRC1INT4MIX Input 1 Source ISRC1I NT4MI X_STS 0 0 0 0 0 0 0 ISRC1INT4_SRC [7:0] 0000h R2880 (B40h) ISRC2DEC1MIX Input 1 Source ISRC2 DEC1 MIX_S TS 0 0 0 0 0 0 0 ISRC2DEC1_SRC [7:0] 0000h R2888 (B48h) ISRC2DEC2MIX Input 1 Source ISRC2 DEC2 MIX_S TS 0 0 0 0 0 0 0 ISRC2DEC2_SRC [7:0] 0000h R2896 (B50h) ISRC2DEC3MIX Input 1 Source ISRC2 DEC3 MIX_S TS 0 0 0 0 0 0 0 ISRC2DEC3_SRC [7:0] 0000h R2904 (B58h) ISRC2DEC4MIX Input 1 Source ISRC2 DEC4 MIX_S TS 0 0 0 0 0 0 0 ISRC2DEC4_SRC [7:0] 0000h R2912 (B60h) ISRC2INT1MIX Input 1 Source ISRC2I NT1MI X_STS 0 0 0 0 0 0 0 ISRC2INT1_SRC [7:0] 0000h R2920 (B68h) ISRC2INT2MIX Input 1 Source ISRC2I NT2MI X_STS 0 0 0 0 0 0 0 ISRC2INT2_SRC [7:0] 0000h R2928 (B70h) ISRC2INT3MIX Input 1 Source ISRC2I NT3MI X_STS 0 0 0 0 0 0 0 ISRC2INT3_SRC [7:0] 0000h R2936 (B78h) ISRC2INT4MIX Input 1 Source ISRC2I NT4MI X_STS 0 0 0 0 0 0 0 ISRC2INT4_SRC [7:0] 0000h R2944 (B80h) ISRC3DEC1MIX Input 1 Source ISRC3 DEC1 MIX_S TS 0 0 0 0 0 0 0 ISRC3DEC1_SRC [7:0] 0000h

354 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2952 (B88h) ISRC3DEC2MIX Input 1 Source ISRC3 DEC2 MIX_S TS 0 0 0 0 0 0 0 ISRC3DEC2_SRC [7:0] 0000h R2960 (B90h) ISRC3DEC3MIX Input 1 Source ISRC3 DEC3 MIX_S TS 0 0 0 0 0 0 0 ISRC3DEC3_SRC [7:0] 0000h R2968 (B98h) ISRC3DEC4MIX Input 1 Source ISRC3 DEC4 MIX_S TS 0 0 0 0 0 0 0 ISRC3DEC4_SRC [7:0] 0000h R2976 (BA0h) ISRC3INT1MIX Input 1 Source ISRC3I NT1MI X_STS 0 0 0 0 0 0 0 ISRC3INT1_SRC [7:0] 0000h R2984 (BA8h) ISRC3INT2MIX Input 1 Source ISRC3I NT2MI X_STS 0 0 0 0 0 0 0 ISRC3INT2_SRC [7:0] 0000h R2992 (BB0h) ISRC3INT3MIX Input 1 Source ISRC3I NT3MI X_STS 0 0 0 0 0 0 0 ISRC3INT3_SRC [7:0] 0000h R3000 (BB8h) ISRC3INT4MIX Input 1 Source ISRC3I NT4MI X_STS 0 0 0 0 0 0 0 ISRC3INT4_SRC [7:0] 0000h R3072 (C00h) GPIO1 CTRL GP1_D IR GP1_P U GP1_P D

0 GP1_L

GP1_P OL GP1_ OP_C FG GP1_D B

0 GP1_FN [6:0] A101h

R3073 (C01h) GPIO2 CTRL GP2_D IR GP2_P U GP2_P D

0 GP2_L

GP2_P OL GP2_ OP_C FG GP2_D B

0 GP2_FN [6:0] A101h

R3074 (C02h) GPIO3 CTRL GP3_D IR GP3_P U GP3_P D

0 GP3_L

GP3_P OL GP3_ OP_C FG GP3_D B

0 GP3_FN [6:0] A101h

R3075 (C03h) GPIO4 CTRL GP4_D IR GP4_P U GP4_P D

0 GP4_L

GP4_P OL GP4_ OP_C FG GP4_D B

0 GP4_FN [6:0] A101h

R3076 (C04h) GPIO5 CTRL GP5_D IR GP5_P U GP5_P D

0 GP5_L

GP5_P OL GP5_ OP_C FG GP5_D B

0 GP5_FN [6:0] A101h

(C0Fh) IRQ CTRL 1 0 0 0 0 0 IRQ_P OL IRQ_O P_CF G 0 0 0 0 0 0 0 0 0 0400h R3088 (C10h) GPIO Debounce Config GP_DBTIME [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 1000h R3096 (C18h) GP Switch 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW1_MODE [1:0] 0000h R3104 (C20h) Misc Pad Ctrl 1 LDO1E NA_P D LDO1E NA_P U MCLK 2_PD 0 0 0 0 0 0 0 0 0 0 0 RESE T_PU RESE T_PD 8002h R3105 (C21h) Misc Pad Ctrl 2 0 0 0 MCLK 1_PD 0 0 0 0 0 0 0 0 0 0 0 ADDR _PD 0001h R3106 (C22h) Misc Pad Ctrl 3 0 0 0 0 0 0 0 0 0 0 0 0 DMICD AT4_P D DMICD AT3_P D DMICD AT2_P D DMICD AT1_P D 0000h R3107 (C23h) Misc Pad Ctrl 4 0 0 0 0 0 0 0 0 0 0 AIF1L RCLK_ PU AIF1L RCLK_ PD AIF1B CLK_P U AIF1B CLK_P D AIF1R XDAT_ PU AIF1R XDAT_ PD 0000h

Rev 4.0 355 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3108 (C24h) Misc Pad Ctrl 5 0 0 0 0 0 0 0 0 0 0 AIF2L RCLK_ PU AIF2L RCLK_ PD AIF2B CLK_P U AIF2B CLK_P D AIF2R XDAT_ PU AIF2R XDAT_ PD 0000h R3109 (C25h) Misc Pad Ctrl 6 0 0 0 0 0 0 0 0 0 0 AIF3L RCLK_ PU AIF3L RCLK_ PD AIF3B CLK_P U AIF3B CLK_P D AIF3R XDAT_ PU AIF3R XDAT_ PD 0000h R3120 (C30h) Misc Pad Ctrl 7 0 0 0 0 0 CIF1MI SO_G PIO4_ DRV_ STR 0 0 0 0 0 0 0 CIF1S DA_CI F1MIS O_DR V_STR 0 0 0404h R3121 (C31h) Misc Pad Ctrl 8 0 0 0 0 0 0 0 0 0 0 0 0 0 CIF2S DA_D RV_ST R 0 0 0004h R3122 (C32h) Misc Pad Ctrl 9 0 0 0 0 0 AIF1L RCLK_ DRV_ STR 0 0 0 0 0 0 0 GPIO1 _DRV_ STR 0 0 0404h R3123 (C33h) Misc Pad Ctrl 10 0 0 0 0 0 AIF1B CLK_D RV_ST R 0 0 0 0 0 0 0 AIF1T XDAT_ DRV_ STR 0 0 0404h R3124 (C34h) Misc Pad Ctrl 11 0 0 0 0 0 AIF2L RCLK_ DRV_ STR 0 0 0 0 0 0 0 GPIO2 _DRV_ STR 0 0 0404h R3125 (C35h) Misc Pad Ctrl 12 0 0 0 0 0 AIF2B CLK_D RV_ST R 0 0 0 0 0 0 0 AIF2T XDAT_ DRV_ STR 0 0 0404h R3126 (C36h) Misc Pad Ctrl 13 0 0 0 0 0 AIF3L RCLK_ DRV_ STR 0 0 0 0 0 0 0 GPIO3 _DRV_ STR 0 0 0404h R3127 (C37h) Misc Pad Ctrl 14 0 0 0 0 0 AIF3B CLK_D RV_ST R 0 0 0 0 0 0 0 AIF3T XDAT_ DRV_ STR 0 0 0404h R3128 (C38h) Misc Pad Ctrl 15 0 0 0 0 0 SLIMD AT_DR V_STR 0 0 0 0 0 0 0 SLIMC LK_DR V_STR 0 00 0004h R3129 (C39h) Misc Pad Ctrl 16 0 0 0 0 0 IRQ_D RV_ST R 0 0 0 0 0 0 0 GPIO5 _DRV_ STR 0 0 0404h R3130 (C3Ah) Misc Pad Ctrl 17 0 0 0 0 0 SPKD AT1_D RV_ST R 0 0 0 0 0 0 0 SPKCL K1_DR V_STR 0 00 0404h R3131 (C3Bh) Misc Pad Ctrl 18 0 0 0 0 0 SPKD AT2_D RV_ST R 0 0 0 0 0 0 0 SPKCL K2_DR V_STR 0 0 0404h R3328 (D00h) Interrupt Status 1 0 0 0 0 0 0 0 0 0 0 0 0 GP4_E INT1 GP3_E INT1 GP2_E INT1 GP1_E INT1 0000h R3329 (D01h) Interrupt Status 2 0 0 0 0 DSP4_ RAM_ RDY_ EINT1 DSP3_ RAM_ RDY_ EINT1 DSP2_ RAM_ RDY_ EINT1 DSP1_ RAM_ RDY_ EINT1 DSP_I RQ8_E INT1 DSP_I RQ7_E INT1 DSP_I RQ6_E INT1 DSP_I RQ5_E INT1 DSP_I RQ4_E INT1 DSP_I RQ3_E INT1 DSP_I RQ2_E INT1 DSP_I RQ1_E INT1 0000h

356 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3330 (D02h) Interrupt Status 3 SPK_ OVER HEAT_ WARN _EINT SPK_ OVER HEAT_ EINT1 HPDE T_EIN MICDE T_EIN WSEQ _DON E_EIN DRC2_ SIG_D ET_EI NT1 DRC1_ SIG_D ET_EI NT1 ASRC 2_LOC K_EIN ASRC 1_LOC K_EIN UNDE RCLO CKED _EINT OVER CLOC KED_E INT1

0 FLL2_

LOCK_ EINT1 FLL1_ LOCK_ EINT1 CLKG EN_E RR_EI NT1 CLKG EN_E RR_A SYNC _EINT 0000h R3331 (D03h) Interrupt Status 4 0 0 0 CTRLI F_ERR _EINT MIXER _DRO PPED_ SAMP LE_EI NT1 ASYN C_CLK _ENA_ LOW_ EINT1 SYSCL K_ENA _LOW _EINT ISRC1 _CFG_ ERR_ EINT1 ISRC2 _CFG_ ERR_ EINT1 ISRC3 _CFG_ ERR_ EINT1 HP3R_ DONE _EINT HP3L_ DONE _EINT HP2R_ DONE _EINT HP2L_ DONE _EINT HP1R_ DONE _EINT HP1L_ DONE _EINT 0000h R3332 (D04h) Interrupt Status 5 0 0 0 0 0 0 0 BOOT _DON E_EIN 0 0 ADC_ OVER FLOW _EINT ADC_F IFO_O U_EIN ASRC _CFG_ ERR_ EINT1 K_OK_ EINT1 FLL1_ CLOC K_OK_ EINT1 0000h R3333 (D05h) Interrupt Status 6 DSP_S HARE D_WR _COLL _EINT SPK_S HUTD OWN_ EINT1 SPKO UTR_S HORT _EINT SPKO UTL_S HORT _EINT HP3R_ SC_N EG_EI NT1 HP3R_ SC_P OS_EI NT1 HP3L_ SC_N EG_EI NT1 HP3L_ SC_P OS_EI NT1 HP2R_ SC_N EG_EI NT1 HP2R_ SC_P OS_EI NT1 HP2L_ SC_N EG_EI NT1 HP2L_ SC_P OS_EI NT1 HP1R_ SC_N EG_EI NT1 HP1R_ SC_P OS_EI NT1 HP1L_ SC_N EG_EI NT1 HP1L_ SC_P OS_EI NT1 0000h R3336 (D08h) Interrupt Status 1 Mask 0 0 0 0 0 0 0 0 0 0 0 0 IM_GP 4_EIN IM_GP 3_EIN IM_GP 2_EIN IM_GP 1_EIN 000Fh R3337 (D09h) Interrupt Status 2 Mask 0 0 0 0 IM_DS P4_RA M_RD Y_EIN IM_DS P3_RA M_RD Y_EIN IM_DS P2_RA M_RD Y_EIN IM_DS P1_RA M_RD Y_EIN IM_DS P_IRQ 8_EIN IM_DS P_IRQ 7_EIN IM_DS P_IRQ 6_EIN IM_DS P_IRQ 5_EIN IM_DS P_IRQ 4_EIN IM_DS P_IRQ 3_EIN IM_DS P_IRQ 2_EIN IM_DS P_IRQ 1_EIN 0FFFh R3338 (D0Ah) Interrupt Status 3 Mask IM_SP K_OV ERHE AT_W ARN_ EINT1 IM_SP K_OV ERHE AT_EI NT1 IM_HP DET_E INT1 IM_MI CDET_ EINT1 IM_WS EQ_D ONE_ EINT1 IM_DR C2_SI G_DE T_EIN IM_DR C1_SI G_DE T_EIN IM_AS RC2_L OCK_ EINT1 IM_AS RC1_L OCK_ EINT1 IM_UN DERC LOCK ED_EI NT1 IM_OV ERCL OCKE D_EIN

0 IM_FL

L2_LO CK_EI NT1 IM_FL L1_LO CK_EI NT1 IM_CL KGEN _ERR_ EINT1 IM_CL KGEN _ERR_ ASYN C_EIN FFEFh R3339 (D0Bh) Interrupt Status 4 Mask 1 1 1 IM_CT RLIF_ ERR_ EINT1 IM_MI XER_ DROP PED_S AMPL E_EIN IM_AS YNC_ CLK_E NA_LO W_EIN IM_SY SCLK_ ENA_L OW_EI NT1 IM_IS RC1_C FG_E RR_EI NT1 IM_IS RC2_C FG_E RR_EI NT1 IM_IS RC3_C FG_E RR_EI NT1 IM_HP 3R_D ONE_ EINT1 IM_HP 3L_DO NE_EI NT1 IM_HP 2R_D ONE_ EINT1 IM_HP 2L_DO NE_EI NT1 IM_HP 1R_D ONE_ EINT1 IM_HP 1L_DO NE_EI NT1 FFFFh R3340 (D0Ch) Interrupt Status 5 Mask 1 1 1 1 1 1 1 IM_BO OT_D ONE_ EINT1 0 0 IM_AD C_OV ERFL OW_EI NT1 IM_AD C_FIF O_OU _EINT IM_AS RC_C FG_E RR_EI NT1 L2_CL OCK_ OK_EI NT1 IM_FL L1_CL OCK_ OK_EI NT1 FE3Bh R3341 (D0Dh) Interrupt Status 6 Mask IM_DS P_SHA RED_ WR_C OLL_E INT1 IM_SP K_SH UTDO WN_EI NT1 IM_SP KOUT R_SH ORT_ EINT1 IM_SP KOUT L_SHO RT_EI NT1 IM_HP 3R_SC _NEG_ EINT1 IM_HP 3R_SC _POS_ EINT1 IM_HP 3L_SC _NEG_ EINT1 IM_HP 3L_SC _POS_ EINT1 IM_HP 2R_SC _NEG_ EINT1 IM_HP 2R_SC _POS_ EINT1 IM_HP 2L_SC _NEG_ EINT1 IM_HP 2L_SC _POS_ EINT1 IM_HP 1R_SC _NEG_ EINT1 IM_HP 1R_SC _POS_ EINT1 IM_HP 1L_SC _NEG_ EINT1 IM_HP 1L_SC _POS_ EINT1 FFFFh R3343 (D0Fh) Interrupt Control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM_IR 0000h R3344 (D10h) IRQ2 Status 1 0 0 0 0 0 0 0 0 0 0 0 0 GP4_E INT2 GP3_E INT2 GP2_E INT2 GP1_E INT2 0000h

Rev 4.0 357 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3345 (D11h) IRQ2 Status 2 0 0 0 0 DSP4_ RAM_ RDY_ EINT2 DSP3_ RAM_ RDY_ EINT2 DSP2_ RAM_ RDY_ EINT2 DSP1_ RAM_ RDY_ EINT2 DSP_I RQ8_E INT2 DSP_I RQ7_E INT2 DSP_I RQ6_E INT2 DSP_I RQ5_E INT2 DSP_I RQ4_E INT2 DSP_I RQ3_E INT2 DSP_I RQ2_E INT2 DSP_I RQ1_E INT2 0000h R3346 (D12h) IRQ2 Status 3 SPK_ OVER HEAT_ WARN _EINT SPK_ OVER HEAT_ EINT2 HPDE T_EIN MICDE T_EIN WSEQ _DON E_EIN DRC2_ SIG_D ET_EI NT2 DRC1_ SIG_D ET_EI NT2 ASRC 2_LOC K_EIN ASRC 1_LOC K_EIN UNDE RCLO CKED _EINT OVER CLOC KED_E INT2 LOCK_ EINT2 FLL1_ LOCK_ EINT2 CLKG EN_E RR_EI NT2 CLKG EN_E RR_A SYNC _EINT 0000h R3347 (D13h) IRQ2 Status 4 0 0 0 CTRLI F_ERR _EINT MIXER _DRO PPED_ SAMP LE_EI NT2 ASYN C_CLK _ENA_ LOW_ EINT2 SYSCL K_ENA _LOW _EINT ISRC1 _CFG_ ERR_ EINT2 ISRC2 _CFG_ ERR_ EINT2 ISRC3 _CFG_ ERR_ EINT2 HP3R_ DONE _EINT HP3L_ DONE _EINT HP2R_ DONE _EINT HP2L_ DONE _EINT HP1R_ DONE _EINT HP1L_ DONE _EINT 0000h R3348 (D14h) IRQ2 Status 5 0 0 0 0 0 0 0 BOOT _DON E_EIN 0 0 ADC_ OVER FLOW _EINT ADC_F IFO_O U_EIN ASRC _CFG_ ERR_ EINT2 K_OK_ EINT2 FLL1_ CLOC K_OK_ EINT2 0000h R3349 (D15h) IRQ2 Status 6 DSP_S HARE D_WR _COLL _EINT SPK_S HUTD OWN_ EINT2 SPKO UTR_S HORT _EINT SPKO UTL_S HORT _EINT HP3R_ SC_N EG_EI NT2 HP3R_ SC_P OS_EI NT2 HP3L_ SC_N EG_EI NT2 HP3L_ SC_P OS_EI NT2 HP2R_ SC_N EG_EI NT2 HP2R_ SC_P OS_EI NT2 HP2L_ SC_N EG_EI NT2 HP2L_ SC_P OS_EI NT2 HP1R_ SC_N EG_EI NT2 HP1R_ SC_P OS_EI NT2 HP1L_ SC_N EG_EI NT2 HP1L_ SC_P OS_EI NT2 0000h R3352 (D18h) IRQ2 Status 1 Mask 0 0 0 0 0 0 0 0 0 0 0 0 IM_GP 4_EIN IM_GP 3_EIN IM_GP 2_EIN IM_GP 1_EIN 000Fh R3353 (D19h) IRQ2 Status 2 Mask 0 0 0 0 IM_DS P4_RA M_RD Y_EIN IM_DS P3_RA M_RD Y_EIN IM_DS P2_RA M_RD Y_EIN IM_DS P1_RA M_RD Y_EIN IM_DS P_IRQ 8_EIN IM_DS P_IRQ 7_EIN IM_DS P_IRQ 6_EIN IM_DS P_IRQ 5_EIN IM_DS P_IRQ 4_EIN IM_DS P_IRQ 3_EIN IM_DS P_IRQ 2_EIN IM_DS P_IRQ 1_EIN 0FFFh R3354 (D1Ah) IRQ2 Status 3 Mask IM_SP K_OV ERHE AT_W ARN_ EINT2 IM_SP K_OV ERHE AT_EI NT2 IM_HP DET_E INT2 IM_MI CDET_ EINT2 IM_WS EQ_D ONE_ EINT2 IM_DR C2_SI G_DE T_EIN IM_DR C1_SI G_DE T_EIN IM_AS RC2_L OCK_ EINT2 IM_AS RC1_L OCK_ EINT2 IM_UN DERC LOCK ED_EI NT2 IM_OV ERCL OCKE D_EIN L2_LO CK_EI NT2 IM_FL L1_LO CK_EI NT2 IM_CL KGEN _ERR_ EINT2 IM_CL KGEN _ERR_ ASYN C_EIN FFEFh R3355 (D1Bh) IRQ2 Status 4 Mask 1 1 1 IM_CT RLIF_ ERR_ EINT2 IM_MI XER_ DROP PED_S AMPL E_EIN IM_AS YNC_ CLK_E NA_LO W_EIN IM_SY SCLK_ ENA_L OW_EI NT2 IM_IS RC1_C FG_E RR_EI NT2 IM_IS RC2_C FG_E RR_EI NT2 IM_IS RC3_C FG_E RR_EI NT2 IM_HP 3R_D ONE_ EINT IM_HP 3L_DO NE_EI NT2 IM_HP 2R_D ONE_ EINT2 IM_HP 2L_DO NE_EI NT2 IM_HP 1R_D ONE_ EINT2 IM_HP 1L_DO NE_EI NT2 FFFFh R3356 (D1Ch) IRQ2 Status 5 Mask 1 1 1 1 1 1 1 IM_BO OT_D ONE_ EINT2 0 0 IM_AD C_OV ERFL OW_EI NT2 IM_AD C_FIF O_OU _EINT IM_AS RC_C FG_E RR_EI NT2 L2_CL OCK_ OK_EI NT2 IM_FL L1_CL OCK_ OK_EI NT2 FE3Bh R3357 (D1Dh) IRQ2 Status 6 Mask IM_DS P_SHA RED_ WR_C OLL_E INT2 IM_SP K_SH UTDO WN_EI NT2 IM_SP KOUT R_SH ORT_ EINT2 IM_SP KOUT L_SHO RT_EI NT2 IM_HP 3R_SC _NEG_ EINT2 IM_HP 3R_SC _POS_ EINT2 IM_HP 3L_SC _NEG_ EINT2 IM_HP 3L_SC _POS_ EINT2 IM_HP 2R_SC _NEG_ EINT2 IM_HP 2R_SC _POS_ EINT2 IM_HP 2L_SC _NEG_ EINT2 IM_HP 2L_SC _POS_ EINT2 IM_HP 1R_SC _NEG_ EINT2 IM_HP 1R_SC _POS_ EINT2 IM_HP 1L_SC _NEG_ EINT2 IM_HP 1L_SC _POS_ EINT2 FFFFh R3359 (D1Fh) IRQ2 Control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM_IR 0000h

358 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3360 (D20h) Interrupt Raw Status 1 0 0 0 0 DSP4_ RAM_ RDY_ STS DSP3_ RAM_ RDY_ STS DSP2_ RAM_ RDY_ STS DSP1_ RAM_ RDY_ STS DSP_I RQ8_S TS DSP_I RQ7_S TS DSP_I RQ6_S TS DSP_I RQ5_S TS DSP_I RQ4_S TS DSP_I RQ3_S TS DSP_I RQ2_S TS DSP_I RQ1_S TS 0000h R3361 (D21h) Interrupt Raw Status 2 SPK_ OVER HEAT_ WARN _STS SPK_ OVER HEAT_ STS 0 0 WSEQ _DON E_STS DRC2_ SIG_D ET_ST S DRC1_ SIG_D ET_ST S ASRC 2_LOC K_STS ASRC 1_LOC K_STS UNDE RCLO CKED _STS OVER CLOC KED_S TS LOCK_ STS FLL1_ LOCK_ STS CLKG EN_E RR_ST S CLKG EN_E RR_A SYNC _STS 0000h R3362 (D22h) Interrupt Raw Status 3 ASRC _CFG_ ERR_ STS AIF3_ ERR_ STS AIF2_ ERR_ STS AIF1_ ERR_ STS CTRLI F_ERR _STS MIXER _DRO PPED_ SAMP LE_ST S ASYN C_CLK _ENA_ LOW_ STS SYSCL K_ENA _LOW _STS ISRC1 _CFG_ ERR_ STS ISRC2 _CFG_ ERR_ STS HP3R_ DONE _STS HP3L_ DONE _STS HP2R_ DONE _STS HP2L_ DONE _STS HP1R_ DONE _STS HP1L_ DONE _STS 0000h R3363 (D23h) Interrupt Raw Status 4 0 0 0 0 0 0 0 BOOT _DON E_STS 0 0 ADC_ OVER FLOW _STS ADC_F IFO_O U_STS ADC_ CIC_O VERFL OW_S TS K_OK_ STS FLL1_ CLOC K_OK_ STS 0000h R3364 (D24h) Interrupt Raw Status 5 0 0 PWM_ OVER CLOC KED_S TS FX_C ORE_ OVER CLOC KED_S TS

0 DAC_

SYS_ OVER CLOC KED_S TS DAC_ WARP _OVE RCLO CKED _STS ADC_ OVER CLOC KED_S TS MIXER _OVE RCLO CKED _STS AIF3_ ASYN C_OV ERCL OCKE D_STS AIF2_ ASYN C_OV ERCL OCKE D_STS AIF1_ ASYN C_OV ERCL OCKE D_STS AIF3_ SYNC _OVE RCLO CKED _STS AIF2_ SYNC _OVE RCLO CKED _STS AIF1_ SYNC _OVE RCLO CKED _STS PAD_ CTRL_ OVER CLOC KED_S TS 0000h R3365 (D25h) Interrupt Raw Status 6 SLIMB US_S UBSY S_OV ERCL OCKE D_STS SLIMB US_AS YNC_ OVER CLOC KED_S TS SLIMB US_SY NC_O VERC LOCK ED_ST S ASRC _ASYN C_SYS _OVE RCLO CKED _STS ASRC _ASYN C_WA RP_O VERC LOCK ED_ST S ASRC _SYN C_SYS _OVE RCLO CKED _STS ASRC _SYN C_WA RP_O VERC LOCK ED_ST S DSP4_ OVER CLOC KED_S TS DSP3_ OVER CLOC KED_S TS

0 DSP2_

KED_S TS

0 DSP1_

KED_S TS ISRC3 _OVE RCLO CKED _STS ISRC2 _OVE RCLO CKED _STS ISRC1 _OVE RCLO CKED _STS 0000h R3366 (D26h) Interrupt Raw Status 7 0 0 0 0 0 AIF3_ UNDE RCLO CKED _STS AIF2_ UNDE RCLO CKED _STS AIF1_ UNDE RCLO CKED _STS ISRC3 _UND ERCL OCKE D_STS ISRC2 _UND ERCL OCKE D_STS ISRC1 _UND ERCL OCKE D_STS FX_UN DERC LOCK ED_ST S ASRC _UND ERCL OCKE D_STS DAC_ UNDE RCLO CKED _STS ADC_ UNDE RCLO CKED _STS MIXER _UND ERCL OCKE D_STS 0000h R3368 (D28h) Interrupt Raw Status 8

0 SPK_S

OWN_ STS SPKO UTR_S HORT _STS SPKO UTL_S HORT _STS HP3R_ SC_N EG_ST S HP3R_ SC_P OS_ST S HP3L_ SC_N EG_ST S HP3L_ SC_P OS_ST S HP2R_ SC_N EG_ST S HP2R_ SC_P OS_ST S HP2L_ SC_N EG_ST S HP2L_ SC_P OS_ST S HP1R_ SC_N EG_ST S HP1R_ SC_P OS_ST S HP1L_ SC_N EG_ST S HP1L_ SC_P OS_ST S 0000h R3392 (D40h) IRQ Pin Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ2_ STS IRQ1_ STS 0000h R3393 (D41h) ADSP2 IRQ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_I RQ2 DSP_I RQ1 0000h R3394 (D42h) ADSP2 IRQ1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_I RQ4 DSP_I RQ3 0000h R3395 (D43h) ADSP2 IRQ2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_I RQ6 DSP_I RQ5 0000h R3396 (D44h) ADSP2 IRQ3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_I RQ8 DSP_I RQ7 0000h R3408 (D50h) AOD wkup and trig 0 0 0 0 0 0 0 0 MICD_ CLAM P_FAL L_TRI G_STS MICD_ CLAM P_RIS E_TRI G_STS GP5_F ALL_T RIG_S TS GP5_R ISE_T RIG_S TS JD1_F ALL_T RIG_S TS JD1_R ISE_T RIG_S TS 0 0 0000h

Rev 4.0 359 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3409 (D51h) AOD IRQ1 0 0 0 0 0 0 0 0 MICD_ CLAM P_FAL L_EIN MICD_ CLAM P_RIS E_EIN GP5_F ALL_EI NT1 GP5_R ISE_EI NT1 JD1_F ALL_EI NT1 JD1_R ISE_EI NT1 0 0 0000h R3410 (D52h) AOD IRQ2 0 0 0 0 0 0 0 0 MICD_ CLAM P_FAL L_EIN MICD_ CLAM P_RIS E_EIN GP5_F ALL_EI NT2 GP5_R ISE_EI NT2 JD1_F ALL_EI NT2 JD1_R ISE_EI NT2 0 0 0000h R3411 (D53h) AOD IRQ Mask IRQ1 0 0 0 0 0 0 0 0 IM_MI CD_CL AMP_ FALL_ EINT1 IM_MI CD_CL AMP_ RISE_ EINT1 IM_GP 5_FAL L_EIN IM_GP 5_RIS E_EIN IM_JD 1_FAL L_EIN IM_JD 1_RIS E_EIN 0 0 00FCh R3412 (D54h) AOD IRQ Mask IRQ2 0 0 0 0 0 0 0 0 IM_MI CD_CL AMP_ FALL_ EINT2 IM_MI CD_CL AMP_ RISE_ EINT2 IM_GP 5_FAL L_EIN IM_GP 5_RIS E_EIN IM_JD 1_FAL L_EIN IM_JD 1_RIS E_EIN 0 0 00FCh R3413 (D55h) AOD IRQ Raw Status 0 0 0 0 0 0 0 0 0 0 0 0 MICD_ CLAM P_STS GP5_S TS

0 JD1_S

R3414 (D56h) Jack detect debounce 0 0 0 0 0 0 0 0 0 0 0 0 MICD_ CLAM P_DB 0 0 JD1_D B 0000h R3584 (E00h) FX_Ctrl1 0 FX_RATE [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3585 (E01h) FX_Ctrl2 FX_STS [11:0] 0 0 0 0 0000h R3600 (E10h) EQ1_1 EQ1_B1_GAIN [4:0] EQ1_B2_GAIN [4:0] EQ1_B3_GAIN [4:0] EQ1_E NA 6318h R3601 (E11h) EQ1_2 EQ1_B4_GAIN [4:0] EQ1_B5_GAIN [4:0] 0 0 0 0 0 EQ1_ MODE 6300h R3602 (E12h) EQ1_3 EQ1_B1_A [15:0] 0FC8h R3603 (E13h) EQ1_4 EQ1_B1_B [15:0] 03FEh R3604 (E14h) EQ1_5 EQ1_B1_PG [15:0] 00E0h R3605 (E15h) EQ1_6 EQ1_B2_A [15:0] 1EC4h R3606 (E16h) EQ1_7 EQ1_B2_B [15:0] F136h R3607 (E17h) EQ1_8 EQ1_B2_C [15:0] 0409h R3608 (E18h) EQ1_9 EQ1_B2_PG [15:0] 04CCh R3609 (E19h) EQ1_10 EQ1_B3_A [15:0] 1C9Bh R3610 (E1Ah) EQ1_11 EQ1_B3_B [15:0] F337h R3611 (E1Bh) EQ1_12 EQ1_B3_C [15:0] 040Bh R3612 (E1Ch) EQ1_13 EQ1_B3_PG [15:0] 0CBBh R3613 (E1Dh) EQ1_14 EQ1_B4_A [15:0] 16F8h R3614 (E1Eh) EQ1_15 EQ1_B4_B [15:0] F7D9h R3615 (E1Fh) EQ1_16 EQ1_B4_C [15:0] 040Ah R3616 (E20h) EQ1_17 EQ1_B4_PG [15:0] 1F14h R3617 (E21h) EQ1_18 EQ1_B5_A [15:0] 058Ch R3618 (E22h) EQ1_19 EQ1_B5_B [15:0] 0563h R3619 (E23h) EQ1_20 EQ1_B5_PG [15:0] 4000h R3620 (E24h) EQ1_21 EQ1_B1_C [15:0] 0B75h

360 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3622 (E26h) EQ2_1 EQ2_B1_GAIN [4:0] EQ2_B2_GAIN [4:0] EQ2_B3_GAIN [4:0] EQ2_E NA 6318h R3623 (E27h) EQ2_2 EQ2_B4_GAIN [4:0] EQ2_B5_GAIN [4:0] 0 0 0 0 0 EQ2_ MODE 6300h R3624 (E28h) EQ2_3 EQ2_B1_A [15:0] 0FC8h R3625 (E29h) EQ2_4 EQ2_B1_B [15:0] 03FEh R3626 (E2Ah) EQ2_5 EQ2_B1_PG [15:0] 00E0h R3627 (E2Bh) EQ2_6 EQ2_B2_A [15:0] 1EC4h R3628 (E2Ch) EQ2_7 EQ2_B2_B [15:0] F136h R3629 (E2Dh) EQ2_8 EQ2_B2_C [15:0] 0409h R3630 (E2Eh) EQ2_9 EQ2_B2_PG [15:0] 04CCh R3631 (E2Fh) EQ2_10 EQ2_B3_A [15:0] 1C9Bh R3632 (E30h) EQ2_11 EQ2_B3_B [15:0] F337h R3633 (E31h) EQ2_12 EQ2_B3_C [15:0] 040Bh R3634 (E32h) EQ2_13 EQ2_B3_PG [15:0] 0CBBh R3635 (E33h) EQ2_14 EQ2_B4_A [15:0] 16F8h R3636 (E34h) EQ2_15 EQ2_B4_B [15:0] F7D9h R3637 (E35h) EQ2_16 EQ2_B4_C [15:0] 040Ah R3638 (E36h) EQ2_17 EQ2_B4_PG [15:0] 1F14h R3639 (E37h) EQ2_18 EQ2_B5_A [15:0] 058Ch R3640 (E38h) EQ2_19 EQ2_B5_B [15:0] 0563h R3641 (E39h) EQ2_20 EQ2_B5_PG [15:0] 4000h R3642 (E3Ah) EQ2_21 EQ2_B1_C [15:0] 0B75h R3644 (E3Ch) EQ3_1 EQ3_B1_GAIN [4:0] EQ3_B2_GAIN [4:0] EQ3_B3_GAIN [4:0] EQ3_E NA 6318h R3645 (E3Dh) EQ3_2 EQ3_B4_GAIN [4:0] EQ3_B5_GAIN [4:0] 0 0 0 0 0 EQ3_ MODE 6300h R3646 (E3Eh) EQ3_3 EQ3_B1_A [15:0] 0FC8h R3647 (E3Fh) EQ3_4 EQ3_B1_B [15:0] 03FEh R3648 (E40h) EQ3_5 EQ3_B1_PG [15:0] 00E0h R3649 (E41h) EQ3_6 EQ3_B2_A [15:0] 1EC4h R3650 (E42h) EQ3_7 EQ3_B2_B [15:0] F136h R3651 (E43h) EQ3_8 EQ3_B2_C [15:0] 0409h R3652 (E44h) EQ3_9 EQ3_B2_PG [15:0] 04CCh R3653 (E45h) EQ3_10 EQ3_B3_A [15:0] 1C9Bh R3654 (E46h) EQ3_11 EQ3_B3_B [15:0] F337h R3655 (E47h) EQ3_12 EQ3_B3_C [15:0] 040Bh R3656 (E48h) EQ3_13 EQ3_B3_PG [15:0] 0CBBh R3657 (E49h) EQ3_14 EQ3_B4_A [15:0] 16F8h R3658 (E4Ah) EQ3_15 EQ3_B4_B [15:0] F7D9h R3659 (E4Bh) EQ3_16 EQ3_B4_C [15:0] 040Ah R3660 (E4Ch) EQ3_17 EQ3_B4_PG [15:0] 1F14h

Rev 4.0 361 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3661 (E4Dh) EQ3_18 EQ3_B5_A [15:0] 058Ch R3662 (E4Eh) EQ3_19 EQ3_B5_B [15:0] 0563h R3663 (E4Fh) EQ3_20 EQ3_B5_PG [15:0] 4000h R3664 (E50h) EQ3_21 EQ3_B1_C [15:0] 0B75h R3666 (E52h) EQ4_1 EQ4_B1_GAIN [4:0] EQ4_B2_GAIN [4:0] EQ4_B3_GAIN [4:0] EQ4_E NA 6318h R3667 (E53h) EQ4_2 EQ4_B4_GAIN [4:0] EQ4_B5_GAIN [4:0] 0 0 0 0 0 EQ4_ MODE 6300h R3668 (E54h) EQ4_3 EQ4_B1_A [15:0] 0FC8h R3669 (E55h) EQ4_4 EQ4_B1_B [15:0] 03FEh R3670 (E56h) EQ4_5 EQ4_B1_PG [15:0] 00E0h R3671 (E57h) EQ4_6 EQ4_B2_A [15:0] 1EC4h R3672 (E58h) EQ4_7 EQ4_B2_B [15:0] F136h R3673 (E59h) EQ4_8 EQ4_B2_C [15:0] 0409h R3674 (E5Ah) EQ4_9 EQ4_B2_PG [15:0] 04CCh R3675 (E5Bh) EQ4_10 EQ4_B3_A [15:0] 1C9Bh R3676 (E5Ch) EQ4_11 EQ4_B3_B [15:0] F337h R3677 (E5Dh) EQ4_12 EQ4_B3_C [15:0] 040Bh R3678 (E5Eh) EQ4_13 EQ4_B3_PG [15:0] 0CBBh R3679 (E5Fh) EQ4_14 EQ4_B4_A [15:0] 16F8h R3680 (E60h) EQ4_15 EQ4_B4_B [15:0] F7D9h R3681 (E61h) EQ4_16 EQ4_B4_C [15:0] 040Ah R3682 (E62h) EQ4_17 EQ4_B4_PG [15:0] 1F14h R3683 (E63h) EQ4_18 EQ4_B5_A [15:0] 058Ch R3684 (E64h) EQ4_19 EQ4_B5_B [15:0] 0563h R3685 (E65h) EQ4_20 EQ4_B5_PG [15:0] 4000h R3686 (E66h) EQ4_21 EQ4_B1_C [15:0] 0B75h R3712 (E80h) DRC1 ctrl1 DRC1_SIG_DET_RMS [4:0] DRC1_SIG_DE T_PK [1:0] DRC1_ NG_E NA DRC1_ SIG_D ET_M ODE DRC1_ SIG_D ET DRC1_ KNEE2 _OP_E NA DRC1_ QR DRC1_ ANTIC LIP DRC1_ WSEQ _SIG_ DET_E NA DRC1L _ENA DRC1 R_EN A 0018h R3713 (E81h) DRC1 ctrl2 0 0 0 DRC1_ATK [3:0] DRC1_DCY [3:0] DRC1_MINGAIN [2:0] DRC1_MAXGA IN [1:0] 0933h R3714 (E82h) DRC1 ctrl3 DRC1_NG_MINGAIN [3:0] DRC1_NG_EX P [1:0] DRC1_QR_TH R [1:0] DRC1_QR_DC Y [1:0] DRC1_HI_COMP [2:0] DRC1_LO_COMP [2:0] 0018h R3715 (E83h) DRC1 ctrl4 0 0 0 0 0 DRC1_KNEE_IP [5:0] DRC1_KNEE_OP [4:0] 0000h R3716 (E84h) DRC1 ctrl5 0 0 0 0 0 0 DRC1_KNEE2_IP [4:0] DRC1_KNEE2_OP [4:0] 0000h R3721 (E89h) DRC2 ctrl1 DRC2_SIG_DET_RMS [4:0] DRC2_SIG_DE T_PK [1:0] DRC2_ NG_E NA DRC2_ SIG_D ET_M ODE DRC2_ SIG_D ET DRC2_ KNEE2 _OP_E NA DRC2_ QR DRC2_ ANTIC LIP

0 DRC2L

_ENA DRC2 R_EN A 0018h R3722 (E8Ah) DRC2 ctrl2 0 0 0 DRC2_ATK [3:0] DRC2_DCY [3:0] DRC2_MINGAIN [2:0] DRC2_MAXGA IN [1:0] 0933h R3723 (E8Bh) DRC2 ctrl3 DRC2_NG_MINGAIN [3:0] DRC2_NG_EX P [1:0] DRC2_QR_TH R [1:0] DRC2_QR_DC Y [1:0] DRC2_HI_COMP [2:0] DRC2_LO_COMP [2:0] 0018h R3724 (E8Ch) DRC2 ctrl4 0 0 0 0 0 DRC2_KNEE_IP [5:0] DRC2_KNEE_OP [4:0] 0000h

362 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3725 (E8Dh) DRC2 ctrl5 0 0 0 0 0 0 DRC2_KNEE2_IP [4:0] DRC2_KNEE2_OP [4:0] 0000h R3776 (EC0h) HPLPF1_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF1 _MOD E LHPF1 _ENA 0000h R3777 (EC1h) HPLPF1_2 LHPF1_COEFF [15:0] 0000h R3780 (EC4h) HPLPF2_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF2 _MOD E LHPF2 _ENA 0000h R3781 (EC5h) HPLPF2_2 LHPF2_COEFF [15:0] 0000h R3784 (EC8h) HPLPF3_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF3 _MOD E LHPF3 _ENA 0000h R3785 (EC9h) HPLPF3_2 LHPF3_COEFF [15:0] 0000h R3788 (ECCh) HPLPF4_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHPF4 _MOD E LHPF4 _ENA 0000h R3789 (ECDh) HPLPF4_2 LHPF4_COEFF [15:0] 0000h R3808 (EE0h) ASRC_ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 ASRC 2L_EN A ASRC 2R_EN A ASRC 1L_EN A ASRC 1R_EN A 0000h R3809 (EE1h) ASRC_STATUS 0 0 0 0 0 0 0 0 0 0 0 0 ASRC 2L_EN A_STS ASRC 2R_EN A_STS ASRC 1L_EN A_STS ASRC 1R_EN A_STS 0000h R3810 (EE2h) ASRC_RATE1 0 ASRC_RATE1 [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3811 (EE3h) ASRC_RATE2 0 ASRC_RATE2 [3:0] 0 0 0 0 0 0 0 0 0 0 0 4000h R3824 (EF0h) ISRC 1 CTRL 1 0 ISRC1_FSH [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3825 (EF1h) ISRC 1 CTRL 2 0 ISRC1_FSL [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3826 (EF2h) ISRC 1 CTRL 3 ISRC1 _INT1_ ENA ISRC1 _INT2_ ENA ISRC1 _INT3_ ENA ISRC1 _INT4_ ENA 0 0 ISRC1 _DEC1 _ENA ISRC1 _DEC2 _ENA ISRC1 _DEC3 _ENA ISRC1 _DEC4 _ENA 0 0 0 0 0 ISRC1 _NOT CH_E NA 0000h R3827 (EF3h) ISRC 2 CTRL 1 0 ISRC2_FSH [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3828 (EF4h) ISRC 2 CTRL 2 0 ISRC2_FSL [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3829 (EF5h) ISRC 2 CTRL 3 ISRC2 _INT1_ ENA ISRC2 _INT2_ ENA ISRC2 _INT3_ ENA ISRC2 _INT4_ ENA 0 0 ISRC2 _DEC1 _ENA ISRC2 _DEC2 _ENA ISRC2 _DEC3 _ENA ISRC2 _DEC4 _ENA 0 0 0 0 0 ISRC2 _NOT CH_E NA 0000h R3830 (EF6h) ISRC 3 CTRL 1 0 ISRC3_FSH [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3831 (EF7h) ISRC 3 CTRL 2 0 ISRC3_FSL [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3832 (EF8h) ISRC 3 CTRL 3 ISRC3 _INT1_ ENA ISRC3 _INT2_ ENA ISRC3 _INT3_ ENA ISRC3 _INT4_ ENA 0 0 ISRC3 _DEC1 _ENA ISRC3 _DEC2 _ENA ISRC3 _DEC3 _ENA ISRC3 _DEC4 _ENA 0 0 0 0 0 ISRC3 _NOT CH_E NA 0000h R3841 (F01h) ANC_SRC 0 0 0 0 0 0 0 0 0 IN_RXANCR_SEL [2:0] 0 IN_RXANCL_SEL [2:0] 0000h R4352 (1100h) DSP1 Control 1 0 DSP1_RATE [3:0] 0 0 0 0 0 0 DSP1_ MEM_ ENA DSP1_ DBG_ CLK_E NA DSP1_ SYS_E NA DSP1_ CORE _ENA DSP1_ START 0010h R4353 (1101h) DSP1 Clocking 1 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_CLK_SEL [2:0] 0000h

Rev 4.0 363 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R4356 (1104h) DSP1 Status 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_ RAM_ RDY 0000h R4357 (1105h) DSP1 Status 2 DSP1_ PING_ FULL DSP1_ PONG _FULL 0 0 0 0 0 0 DSP1_WDMA_ACTIVE_CHANNELS [7:0] 0000h R4358 (1106h) DSP1 Status 3 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_CLK_SEL_STS [2:0] DSP1_ CLK_A VAIL 0000h R4368 (1110h) DSP1 WDMA Buffer 1 DSP1_START_ADDRESS_WDMA_BUFFER_0 [15:0] 0000h R4369 (1111h) DSP1 WDMA Buffer 2 DSP1_START_ADDRESS_WDMA_BUFFER_1 [15:0] 0000h R4370 (1112h) DSP1 WDMA Buffer 3 DSP1_START_ADDRESS_WDMA_BUFFER_2 [15:0] 0000h R4371 (1113h) DSP1 WDMA Buffer 4 DSP1_START_ADDRESS_WDMA_BUFFER_3 [15:0] 0000h R4372 (1114h) DSP1 WDMA Buffer 5 DSP1_START_ADDRESS_WDMA_BUFFER_4 [15:0] 0000h R4373 (1115h) DSP1 WDMA Buffer 6 DSP1_START_ADDRESS_WDMA_BUFFER_5 [15:0] 0000h R4374 (1116h) DSP1 WDMA Buffer 7 DSP1_START_ADDRESS_WDMA_BUFFER_6 [15:0] 0000h R4375 (1117h) DSP1 WDMA Buffer 8 DSP1_START_ADDRESS_WDMA_BUFFER_7 [15:0] 0000h R4384 (1120h) DSP1 RDMA Buffer 1 DSP1_START_ADDRESS_RDMA_BUFFER_0 [15:0] 0000h R4385 (1121h) DSP1 RDMA Buffer 2 DSP1_START_ADDRESS_RDMA_BUFFER_1 [15:0] 0000h R4386 (1122h) DSP1 RDMA Buffer 3 DSP1_START_ADDRESS_RDMA_BUFFER_2 [15:0] 0000h R4387 (1123h) DSP1 RDMA Buffer 4 DSP1_START_ADDRESS_RDMA_BUFFER_3 [15:0] 0000h R4388 (1124h) DSP1 RDMA Buffer 5 DSP1_START_ADDRESS_RDMA_BUFFER_4 [15:0] 0000h R4389 (1125h) DSP1 RDMA Buffer 6 DSP1_START_ADDRESS_RDMA_BUFFER_5 [15:0] 0000h R4400 (1130h) DSP1 WDMA Config 1 0 0 DSP1_WDMA_BUFFER_LENGTH [13:0] 0000h R4401 (1131h) DSP1 WDMA Config 2 0 0 0 0 0 0 0 0 DSP1_WDMA_CHANNEL_ENABLE [7:0] 0000h R4402 (1132h) DSP1 WDMA Offset 1 0 0 0 0 0 0 0 0 DSP1_WDMA_CHANNEL_OFFSET [7:0] 0000h R4404 (1134h) DSP1 RDMA Config 1 0 0 0 0 0 0 0 0 0 0 DSP1_RDMA_CHANNEL_ENABLE [5:0] 0000h R4405 (1135h) DSP1 RDMA Offset 1 0 0 0 0 0 0 0 0 0 0 DSP1_RDMA_CHANNEL_OFFSET [5:0] 0000h R4408 (1138h) DSP1 External Start Select 1 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_START_IN_SEL [3:0] 0000h R4416 (1140h) DSP1 Scratch 0 DSP1_SCRATCH_0 [15:0] 0000h R4417 (1141h) DSP1 Scratch 1 DSP1_SCRATCH_1 [15:0] 0000h R4418 (1142h) DSP1 Scratch 2 DSP1_SCRATCH_2 [15:0] 0000h R4419 (1143h) DSP1 Scratch 3 DSP1_SCRATCH_3 [15:0] 0000h

364 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R4608 (1200h) DSP2 Control 1 0 DSP2_RATE [3:0] 0 0 0 0 0 0 DSP2_ MEM_ ENA DSP2_ DBG_ CLK_E NA DSP2_ SYS_E NA DSP2_ CORE _ENA DSP2_ START 0010h R4609 (1201h) DSP2 Clocking 1 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP2_CLK_SEL [2:0] 0000h R4612 (1204h) DSP2 Status 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP2_ RAM_ RDY 0000h R4613 (1205h) DSP2 Status 2 DSP2_ PING_ FULL DSP2_ PONG _FULL 0 0 0 0 0 0 DSP2_WDMA_ACTIVE_CHANNELS [7:0] 0000h R4614 (1206h) DSP2 Status 3 0 0 0 0 0 0 0 0 0 0 0 0 DSP2_CLK_SEL_STS [2:0] DSP2_ CLK_A VAIL 0000h R4624 (1210h) DSP2 WDMA Buffer 1 DSP2_START_ADDRESS_WDMA_BUFFER_0 [15:0] 0000h R4625 (1211h) DSP2 WDMA Buffer 2 DSP2_START_ADDRESS_WDMA_BUFFER_1 [15:0] 0000h R4626 (1212h) DSP2 WDMA Buffer 3 DSP2_START_ADDRESS_WDMA_BUFFER_2 [15:0] 0000h R4627 (1213h) DSP2 WDMA Buffer 4 DSP2_START_ADDRESS_WDMA_BUFFER_3 [15:0] 0000h R4628 (1214h) DSP2 WDMA Buffer 5 DSP2_START_ADDRESS_WDMA_BUFFER_4 [15:0] 0000h R4629 (1215h) DSP2 WDMA Buffer 6 DSP2_START_ADDRESS_WDMA_BUFFER_5 [15:0] 0000h R4630 (1216h) DSP2 WDMA Buffer 7 DSP2_START_ADDRESS_WDMA_BUFFER_6 [15:0] 0000h R4631 (1217h) DSP2 WDMA Buffer 8 DSP2_START_ADDRESS_WDMA_BUFFER_7 [15:0] 0000h R4640 (1220h) DSP2 RDMA Buffer 1 DSP2_START_ADDRESS_RDMA_BUFFER_0 [15:0] 0000h R4641 (1221h) DSP2 RDMA Buffer 2 DSP2_START_ADDRESS_RDMA_BUFFER_1 [15:0] 0000h R4642 (1222h) DSP2 RDMA Buffer 3 DSP2_START_ADDRESS_RDMA_BUFFER_2 [15:0] 0000h R4643 (1223h) DSP2 RDMA Buffer 4 DSP2_START_ADDRESS_RDMA_BUFFER_3 [15:0] 0000h R4644 (1224h) DSP2 RDMA Buffer 5 DSP2_START_ADDRESS_RDMA_BUFFER_4 [15:0] 0000h R4645 (1225h) DSP2 RDMA Buffer 6 DSP2_START_ADDRESS_RDMA_BUFFER_5 [15:0] 0000h R4656 (1230h) DSP2 WDMA Config 1 0 0 DSP2_WDMA_BUFFER_LENGTH [13:0] 0000h R4657 (1231h) DSP2 WDMA Config 2 0 0 0 0 0 0 0 0 DSP2_WDMA_CHANNEL_ENABLE [7:0] 0000h R4658 (1232h) DSP2 WDMA Offset 1 0 0 0 0 0 0 0 0 DSP2_WDMA_CHANNEL_OFFSET [7:0] 0000h R4660 (1234h) DSP2 RDMA Config 1 0 0 0 0 0 0 0 0 0 0 DSP2_RDMA_CHANNEL_ENABLE [5:0] 0000h R4661 (1235h) DSP2 RDMA Offset 1 0 0 0 0 0 0 0 0 0 0 DSP2_RDMA_CHANNEL_OFFSET [5:0] 0000h R4664 (1238h) DSP2 External Start Select 1 0 0 0 0 0 0 0 0 0 0 0 0 DSP2_START_IN_SEL [3:0] 0000h R4672 (1240h) DSP2 Scratch 0 DSP2_SCRATCH_0 [15:0] 0000h

Rev 4.0 365 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R4673 (1241h) DSP2 Scratch 1 DSP2_SCRATCH_1 [15:0] 0000h R4674 (1242h) DSP2 Scratch 2 DSP2_SCRATCH_2 [15:0] 0000h R4675 (1243h) DSP2 Scratch 3 DSP2_SCRATCH_3 [15:0] 0000h R4864 (1300h) DSP3 Control 1 0 DSP3_RATE [3:0] 0 0 0 0 0 0 DSP3_ MEM_ ENA DSP3_ DBG_ CLK_E NA DSP3_ SYS_E NA DSP3_ CORE _ENA DSP3_ START 0010h R4865 (1301h) DSP3 Clocking 1 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP3_CLK_SEL [2:0] 0000h R4868 (1304h) DSP3 Status 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP3_ RAM_ RDY 0000h R4869 (1305h) DSP3 Status 2 DSP3_ PING_ FULL DSP3_ PONG _FULL 0 0 0 0 0 0 DSP3_WDMA_ACTIVE_CHANNELS [7:0] 0000h R4870 (1306h) DSP3 Status 3 0 0 0 0 0 0 0 0 0 0 0 0 DSP3_CLK_SEL_STS [2:0] DSP3_ CLK_A VAIL 0000h R4871 (1307h) DSP3 Status 4 DSP3_DUALMEM_COLLISION_ADDR [15:0] 0000h R4880 (1310h) DSP3 WDMA Buffer 1 DSP3_START_ADDRESS_WDMA_BUFFER_0 [15:0] 0000h R4881 (1311h) DSP3 WDMA Buffer 2 DSP3_START_ADDRESS_WDMA_BUFFER_1 [15:0] 0000h R4882 (1312h) DSP3 WDMA Buffer 3 DSP3_START_ADDRESS_WDMA_BUFFER_2 [15:0] 0000h R4883 (1313h) DSP3 WDMA Buffer 4 DSP3_START_ADDRESS_WDMA_BUFFER_3 [15:0] 0000h R4884 (1314h) DSP3 WDMA Buffer 5 DSP3_START_ADDRESS_WDMA_BUFFER_4 [15:0] 0000h R4885 (1315h) DSP3 WDMA Buffer 6 DSP3_START_ADDRESS_WDMA_BUFFER_5 [15:0] 0000h R4886 (1316h) DSP3 WDMA Buffer 7 DSP3_START_ADDRESS_WDMA_BUFFER_6 [15:0] 0000h R4887 (1317h) DSP3 WDMA Buffer 8 DSP3_START_ADDRESS_WDMA_BUFFER_7 [15:0] 0000h R4896 (1320h) DSP3 RDMA Buffer 1 DSP3_START_ADDRESS_RDMA_BUFFER_0 [15:0] 0000h R4897 (1321h) DSP3 RDMA Buffer 2 DSP3_START_ADDRESS_RDMA_BUFFER_1 [15:0] 0000h R4898 (1322h) DSP3 RDMA Buffer 3 DSP3_START_ADDRESS_RDMA_BUFFER_2 [15:0] 0000h R4899 (1323h) DSP3 RDMA Buffer 4 DSP3_START_ADDRESS_RDMA_BUFFER_3 [15:0] 0000h R4900 (1324h) DSP3 RDMA Buffer 5 DSP3_START_ADDRESS_RDMA_BUFFER_4 [15:0] 0000h R4901 (1325h) DSP3 RDMA Buffer 6 DSP3_START_ADDRESS_RDMA_BUFFER_5 [15:0] 0000h R4912 (1330h) DSP3 WDMA Config 1 0 0 DSP3_WDMA_BUFFER_LENGTH [13:0] 0000h R4913 (1331h) DSP3 WDMA Config 2 0 0 0 0 0 0 0 0 DSP3_WDMA_CHANNEL_ENABLE [7:0] 0000h R4914 (1332h) DSP3 WDMA Offset 1 0 0 0 0 0 0 0 0 DSP3_WDMA_CHANNEL_OFFSET [7:0] 0000h

366 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R4916 (1334h) DSP3 RDMA Config 1 0 0 0 0 0 0 0 0 0 0 DSP3_RDMA_CHANNEL_ENABLE [5:0] 0000h R4917 (1335h) DSP3 RDMA Offset 1 0 0 0 0 0 0 0 0 0 0 DSP3_RDMA_CHANNEL_OFFSET [5:0] 0000h R4920 (1338h) DSP3 External Start Select 1 0 0 0 0 0 0 0 0 0 0 0 0 DSP3_START_IN_SEL [3:0] 0000h R4928 (1340h) DSP3 Scratch 0 DSP3_SCRATCH_0 [15:0] 0000h R4929 (1341h) DSP3 Scratch 1 DSP3_SCRATCH_1 [15:0] 0000h R4930 (1342h) DSP3 Scratch 2 DSP3_SCRATCH_2 [15:0] 0000h R4931 (1343h) DSP3 Scratch 3 DSP3_SCRATCH_3 [15:0] 0000h R5120 (1400h) DSP4 Control 1 0 DSP4_RATE [3:0] 0 0 0 0 0 0 DSP4_ MEM_ ENA DSP4_ DBG_ CLK_E NA DSP4_ SYS_E NA DSP4_ CORE _ENA DSP4_ START 0010h R5121 (1401h) DSP4 Clocking 1 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP4_CLK_SEL [2:0] 0000h R5124 (1404h) DSP4 Status 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP4_ RAM_ RDY 0000h R5125 (1405h) DSP4 Status 2 DSP4_ PING_ FULL DSP4_ PONG _FULL 0 0 0 0 0 0 DSP4_WDMA_ACTIVE_CHANNELS [7:0] 0000h R5126 (1406h) DSP4 Status 3 0 0 0 0 0 0 0 0 0 0 0 0 DSP4_CLK_SEL_STS [2:0] DSP4_ CLK_A VAIL 0000h R5136 (1410h) DSP4 WDMA Buffer 1 DSP4_START_ADDRESS_WDMA_BUFFER_0 [15:0] 0000h R5137 (1411h) DSP4 WDMA Buffer 2 DSP4_START_ADDRESS_WDMA_BUFFER_1 [15:0] 0000h R5138 (1412h) DSP4 WDMA Buffer 3 DSP4_START_ADDRESS_WDMA_BUFFER_2 [15:0] 0000h R5139 (1413h) DSP4 WDMA Buffer 4 DSP4_START_ADDRESS_WDMA_BUFFER_3 [15:0] 0000h R5140 (1414h) DSP4 WDMA Buffer 5 DSP4_START_ADDRESS_WDMA_BUFFER_4 [15:0] 0000h R5141 (1415h) DSP4 WDMA Buffer 6 DSP4_START_ADDRESS_WDMA_BUFFER_5 [15:0] 0000h R5142 (1416h) DSP4 WDMA Buffer 7 DSP4_START_ADDRESS_WDMA_BUFFER_6 [15:0] 0000h R5143 (1417h) DSP4 WDMA Buffer 8 DSP4_START_ADDRESS_WDMA_BUFFER_7 [15:0] 0000h R5152 (1420h) DSP4 RDMA Buffer 1 DSP4_START_ADDRESS_RDMA_BUFFER_0 [15:0] 0000h R5153 (1421h) DSP4 RDMA Buffer 2 DSP4_START_ADDRESS_RDMA_BUFFER_1 [15:0] 0000h R5154 (1422h) DSP4 RDMA Buffer 3 DSP4_START_ADDRESS_RDMA_BUFFER_2 [15:0] 0000h R5155 (1423h) DSP4 RDMA Buffer 4 DSP4_START_ADDRESS_RDMA_BUFFER_3 [15:0] 0000h R5156 (1424h) DSP4 RDMA Buffer 5 DSP4_START_ADDRESS_RDMA_BUFFER_4 [15:0] 0000h R5157 (1425h) DSP4 RDMA Buffer 6 DSP4_START_ADDRESS_RDMA_BUFFER_5 [15:0] 0000h

Rev 4.0 367 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R5168 (1430h) DSP4 WDMA Config 1 0 0 DSP4_WDMA_BUFFER_LENGTH [13:0] 0000h R5169 (1431h) DSP4 WDMA Config 2 0 0 0 0 0 0 0 0 DSP4_WDMA_CHANNEL_ENABLE [7:0] 0000h R5170 (1432h) DSP4 WDMA Offset 1 0 0 0 0 0 0 0 0 DSP4_WDMA_CHANNEL_OFFSET [7:0] 0000h R5172 (1434h) DSP4 RDMA Config 1 0 0 0 0 0 0 0 0 0 0 DSP4_RDMA_CHANNEL_ENABLE [5:0] 0000h R5173 (1435h) DSP4 RDMA Offset 1 0 0 0 0 0 0 0 0 0 0 DSP4_RDMA_CHANNEL_OFFSET [5:0] 0000h R5176 (1438h) DSP4 External Start Select 1 0 0 0 0 0 0 0 0 0 0 0 0 DSP4_START_IN_SEL [3:0] 0000h R5184 (1440h) DSP4 Scratch 0 DSP4_SCRATCH_0 [15:0] 0000h R5185 (1441h) DSP4 Scratch 1 DSP4_SCRATCH_1 [15:0] 0000h R5186 (1442h) DSP4 Scratch 2 DSP4_SCRATCH_2 [15:0] 0000h R5187 (1443h) DSP4 Scratch 3 DSP4_SCRATCH_3 [15:0] 0000h Control Write Sequencer Memory R12288 (3000h) WSEQ Sequence WSEQ_DATA_WIDTH0 [2:0] WSEQ_ADDR0 [12:0] 0225h R12289 (3001h) WSEQ Sequence WSEQ_DELAY0 [3:0] WSEQ_DATA_START0 [3:0] WSEQ_DATA0 [7:0] 0001h R12290 (3002h) WSEQ Sequence WSEQ_DATA_WIDTH1 [2:0] WSEQ_ADDR1 [12:0] 0000h R12291 (3003h) WSEQ Sequence WSEQ_DELAY1 [3:0] WSEQ_DATA_START1 [3:0] WSEQ_DATA1 [7:0] 0003h (Similar for WSEQ Index 2…508) R13306 (33FAh) WSEQ Sequence 1019 WSEQ_DATA_WIDTH5 09 [2:0] WSEQ_ADDR509 [12:0] 0000h R13307 (33FBh) WSEQ Sequence 1020 WSEQ_DELAY509 [3:0] WSEQ_DATA_START509 [3:0] WSEQ_DATA509 [7:0] F000h DSP1 Firmware Memory R1048576 (10_0000h) DSP1 PM 0 0 0 0 0 0 0 0 0 DSP1_PM_0 [39:32] 0000h R1048577 (10_0001h) DSP1 PM 1 DSP1_PM_0 [31:16] 0000h R1048578 (10_0002h) DSP1 PM 2 DSP1_PM_0 [15:0] 0000h R1048579 (10_0003h) DSP1 PM 3 0 0 0 0 0 0 0 0 DSP1_PM_1 [39:32] 0000h R1048580 (10_0004h) DSP1 PM 4 DSP1_PM_1 [31:16] 0000h R1048581 (10_0005h) DSP1 PM 5 DSP1_PM_1 [15:0] 0000h (Similar for DSP1 Program Memory 2 … 8190) R1073149 (10_5FFDh) DSP1 PM 24573 0 0 0 0 0 0 0 0 DSP1_PM_8191 [39:32] 0000h R1073150 (10_5FFEh) DSP1 PM 24574 DSP1_PM_8191 [31:16] 0000h

368 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R1073151 (10_5FFFh) DSP1 PM 24575 DSP1_PM_8191 [15:0] 0000h R1572864 (18_0000h) DSP1 ZM 0 0 0 0 0 0 0 0 0 DSP1_ZM_0 [23:16] 0000h R1572865 (18_0001h) DSP1 ZM 1 DSP1_ZM_0 [15:0] 0000h R1572866 (18_0002h) DSP1 ZM 2 0 0 0 0 0 0 0 0 DSP1_ZM_1 [23:16] 0000h R1572867 (18_0003h) DSP1 ZM 3 DSP1_ZM_1 [15:0] 0000h (Similar for DSP1 Coefficient Memory 2 … 4094) R1581054 (18_1FFEh) DSP1 ZM 8190 0 0 0 0 0 0 0 0 DSP1_ZM_4095 [23:16] 0000h R1581055 (18_1FFFh) DSP1 ZM 8191 DSP1_ZM_4095 [15:0] 0000h R1638400 (19_0000h) DSP1 XM 0 0 0 0 0 0 0 0 0 DSP1_XM_0 [23:16] 0000h R1638401 (19_0001h) DSP1 XM 1 DSP1_XM_0 [15:0] 0000h R1638402 (19_0002h) DSP1 XM 2 0 0 0 0 0 0 0 0 DSP1_XM_1 [23:16] 0000h R1638403 (19_0003h) DSP1 XM 3 DSP1_XM_1 [15:0] 0000h (Similar for DSP1 X Data Memory 2 … 16382) R1671166 (19_7FFEh) DSP1 XM 32766 0 0 0 0 0 0 0 0 DSP1_XM_16383 [23:16] 0000h R1671167 (19_7FFFh) DSP1 XM 32767 DSP1_XM_16383 [15:0] 0000h R1736704 (1A_8000h) DSP1 YM 0 0 0 0 0 0 0 0 0 DSP1_YM_0 [23:16] 0000h R1736705 (1A_8001h) DSP1 YM 1 DSP1_YM_0 [15:0] 0000h R1736706 (1A_8002h) DSP1 YM 2 0 0 0 0 0 0 0 0 DSP1_YM_1 [23:16] 0000h R1736707 (1A_8003h) DSP1 YM 3 DSP1_YM_1 [15:0] 0000h (Similar for DSP1 Y Data Memory 2 … 4094) R1744894 (1A_9FFEh) DSP1 YM 8190 0 0 0 0 0 0 0 0 DSP1_YM_4095 [23:16] 0000h R1744895 (1A_9FFFh) DSP1 YM 8191 DSP1_YM_4095 [15:0] 0000h DSP2 Firmware Memory R2097152 (20_0000h) DSP2 PM 0 0 0 0 0 0 0 0 0 DSP2_PM_0 [39:32] 0000h R2097153 (20_0001h) DSP2 PM 1 DSP2_PM_0 [31:16] 0000h R2097154 (20_0002h) DSP2 PM 2 DSP2_PM_0 [15:0] 0000h R2097155 (20_0003h) DSP2 PM 3 0 0 0 0 0 0 0 0 DSP2_PM_1 [39:32] 0000h R2097156 (20_0004h) DSP2 PM 4 DSP2_PM_1 [31:16] 0000h

Rev 4.0 369 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2097157 (20_0005h) DSP2 PM 5 DSP2_PM_1 [15:0] 0000h (Similar for DSP2 Program Memory 2 … 20478) R2158589 (20_EFFDh) DSP2 PM 61437 0 0 0 0 0 0 0 0 DSP2_PM_20479 [39:32] 0000h R2158590 (20_EFFEh) DSP2 PM 61438 DSP2_PM_20479 [31:16] 0000h R2158591 (20_EFFFh) DSP2 PM 61439 DSP2_PM_20479 [15:0] 0000h R2621440 (28_0000h) DSP2 ZM 0 0 0 0 0 0 0 0 0 DSP2_ZM_0 [23:16] 0000h R2621441 (28_0001h) DSP2 ZM 1 DSP2_ZM_0 [15:0] 0000h R2621442 (28_0002h) DSP2 ZM 2 0 0 0 0 0 0 0 0 DSP2_ZM_1 [23:16] 0000h R2621443 (28_0003h) DSP2 ZM 3 DSP2_ZM_1 [15:0] 0000h (Similar for DSP2 Coefficient Memory 2 … 4094) R2629630 (28_1FFEh) DSP2 ZM 8190 0 0 0 0 0 0 0 0 DSP2_ZM_4095 [23:16] 0000h R2629631 (28_1FFFh) DSP2 ZM 8191 DSP2_ZM_4095 [15:0] 0000h R2686976 (29_0000h) DSP2 XM 0 0 0 0 0 0 0 0 0 DSP2_XM_0 [23:16] 0000h R2686977 (29_0001h) DSP2 XM 1 DSP2_XM_0 [15:0] 0000h R2686978 (29_0002h) DSP2 XM 2 0 0 0 0 0 0 0 0 DSP2_XM_1 [23:16] 0000h R2686979 (29_0003h) DSP2 XM 3 DSP2_XM_1 [15:0] 0000h (Similar for DSP2 X Data Memory 2 … 24574) R2736126 (29_BFFEh) DSP2 XM 49150 0 0 0 0 0 0 0 0 DSP2_XM_24575 [23:16] 0000h R2736127 (29_BFFFh) DSP2 XM 49151 DSP2_XM_24575 [15:0] 0000h R2777088 (2A_6000h) DSP2 XM EXT 0 0 0 0 0 0 0 0 0 DSP2_XM_EXT_0 [23:16] 0000h R2777089 (2A_6001h) DSP2 XM EXT 1 DSP2_XM_EXT_0 [15:0] 0000h R2777090 (2A_6002h) DSP2 XM EXT 2 0 0 0 0 0 0 0 0 DSP2_XM_EXT_1 [23:16] 0000h R2777091 (2A_6003h) DSP2 XM EXT 3 DSP2_XM_EXT_1 [15:0] 0000h (Similar for DSP2 X Data Memory 2 … 4094) R2785278 (2A_7FFEh) DSP2 XM EXT 8190 0 0 0 0 0 0 0 0 DSP2_XM_EXT_4095 [23:16] 0000h R2785279 (2A_7FFFh) DSP2 XM EXT 8191 DSP2_XM_EXT_4095 [15:0] 0000h R2785280 (2A_8000h) DSP2 YM 0 0 0 0 0 0 0 0 0 DSP2_YM_0 [23:16] 0000h

370 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R2785281 (2A_8001h) DSP2 YM 1 DSP2_YM_0 [15:0] 0000h R2785282 (2A_8002h) DSP2 YM 2 0 0 0 0 0 0 0 0 DSP2_YM_1 [23:16] 0000h R2785283 (2A_8003h) DSP2 YM 3 DSP2_YM_1 [15:0] 0000h (Similar for DSP2 Y Data Memory 2 … 24574) R2834430 (2B_3FFEh) DSP2 YM 49150 0 0 0 0 0 0 0 0 DSP2_YM_24575 [23:16] 0000h R2834431 (2B_3FFFh) DSP2 YM 49151 DSP2_YM_24575 [15:0] 0000h DSP3 Firmware Memory R3145728 (30_0000h) DSP3 PM 0 0 0 0 0 0 0 0 0 DSP3_PM_0 [39:32] 0000h R3145729 (30_0001h) DSP3 PM 1 DSP3_PM_0 [31:16] 0000h R3145730 (30_0002h) DSP3 PM 2 DSP3_PM_0 [15:0] 0000h R3145731 (30_0003h) DSP3 PM 3 0 0 0 0 0 0 0 0 DSP3_PM_1 [39:32] 0000h R3145732 (30_0004h) DSP3 PM 4 DSP3_PM_1 [31:16] 0000h R3145733 (30_0005h) DSP3 PM 5 DSP3_PM_1 [15:0] 0000h (Similar for DSP3 Program Memory 2 … 20478) R3207165 (30_EFFDh) DSP3 PM 61437 0 0 0 0 0 0 0 0 DSP3_PM_20479 [39:32] 0000h R3207166 (30_EFFEh) DSP3 PM 61438 DSP3_PM_20479 [31:16] 0000h R3207167 (30_EFFFh) DSP3 PM 61439 DSP3_PM_20479 [15:0] 0000h R3670016 (38_0000h) DSP3 ZM 0 0 0 0 0 0 0 0 0 DSP3_ZM_0 [23:16] 0000h R3670017 (38_0001h) DSP3 ZM 1 DSP3_ZM_0 [15:0] 0000h R3670018 (38_0002h) DSP3 ZM 2 0 0 0 0 0 0 0 0 DSP3_ZM_1 [23:16] 0000h R3670019 (38_0003h) DSP3 ZM 3 DSP3_ZM_1 [15:0] 0000h (Similar for DSP3 Coefficient Memory 2 … 4094) R3678206 (38_1FFEh) DSP3 ZM 8190 0 0 0 0 0 0 0 0 DSP3_ZM_4095 [23:16] 0000h R3678207 (38_1FFFh) DSP3 ZM 8191 DSP3_ZM_4095 [15:0] 0000h R3735552 (39_0000h) DSP3 XM 0 0 0 0 0 0 0 0 0 DSP3_XM_0 [23:16] 0000h R3735553 (39_0001h) DSP3 XM 1 DSP3_XM_0 [15:0] 0000h R3735554 (39_0002h) DSP3 XM 2 0 0 0 0 0 0 0 0 DSP3_XM_1 [23:16] 0000h

Rev 4.0 371 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3735555 (39_0003h) DSP3 XM 3 DSP3_XM_1 [15:0] 0000h (Similar for DSP3 X Data Memory 2 … 36864) R3809278 (3A_1FFEh) DSP3 XM 73726 0 0 0 0 0 0 0 0 DSP3_XM_36865 [23:16] 0000h R3809279 (3A_1FFFh) DSP3 XM 73727 DSP3_XM_36865 [15:0] 0000h R3825664 (3A_6000h) DSP3 XM EXT 0 0 0 0 0 0 0 0 0 DSP3_XM_EXT_0 [23:16] 0000h R3825665 (3A_6001h) DSP3 XM EXT 1 DSP3_XM_EXT_0 [15:0] 0000h R3825666 (3A_6002h) DSP3 XM EXT 2 0 0 0 0 0 0 0 0 DSP3_XM_EXT_1 [23:16] 0000h R3825667 (3A_6003h) DSP3 XM EXT 3 DSP3_XM_EXT_1 [15:0] 0000h (Similar for DSP3 X Data Memory 2 … 4094) R3833854 (3A_7FFEh) DSP3 XM EXT 8190 0 0 0 0 0 0 0 0 DSP3_XM_EXT_4095 [23:16] 0000h R3833855 (3A_7FFFh) DSP3 XM EXT 8191 DSP3_XM_EXT_4095 [15:0] 0000h R3833856 (3A_8000h) DSP3 YM 0 0 0 0 0 0 0 0 0 DSP3_YM_0 [23:16] 0000h R3833857 (3A_8001h) DSP3 YM 1 DSP3_YM_0 [15:0] 0000h R3833858 (3A_8002h) DSP3 YM 2 0 0 0 0 0 0 0 0 DSP3_YM_1 [23:16] 0000h R3833859 (3A_8003h) DSP3 YM 3 DSP3_YM_1 [15:0] 0000h (Similar for DSP3 Y Data Memory 2 … 24574) R3883006 (3B_3FFEh) DSP3 YM 49150 0 0 0 0 0 0 0 0 DSP3_YM_24575 [23:16] 0000h R3883007 (3B_3FFFh) DSP3 YM 49151 DSP3_YM_24575 [15:0] 0000h DSP4 Firmware Memory R4194304 (40_0000h) DSP4 PM 0 0 0 0 0 0 0 0 0 DSP4_PM_0 [39:32] 0000h R4194305 (40_0001h) DSP4 PM 1 DSP4_PM_0 [31:16] 0000h R4194306 (40_0002h) DSP4 PM 2 DSP4_PM_0 [15:0] 0000h R4194307 (40_0003h) DSP4 PM 3 0 0 0 0 0 0 0 0 DSP4_PM_1 [39:32] 0000h R4194308 (40_0004h) DSP4 PM 4 DSP4_PM_1 [31:16] 0000h R4194309 (40_0005h) DSP4 PM 5 DSP4_PM_1 [15:0] 0000h (Similar for DSP4 Program Memory 2 … 8190) R4218877 (40_5FFDh) DSP4 PM 24573 0 0 0 0 0 0 0 0 DSP4_PM_8191 [39:32] 0000h

372 Rev 4.0 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R4218878 (40_5FFEh) DSP4 PM 24574 DSP4_PM_8191 [31:16] 0000h R4218879 (40_5FFFh) DSP4 PM 24575 DSP4_PM_8191 [15:0] 0000h R4718592 (48_0000h) DSP4 ZM 0 0 0 0 0 0 0 0 0 DSP4_ZM_0 [23:16] 0000h R4718593 (48_0001h) DSP4 ZM 1 DSP4_ZM_0 [15:0] 0000h R4718594 (48_0002h) DSP4 ZM 2 0 0 0 0 0 0 0 0 DSP4_ZM_1 [23:16] 0000h R4718595 (48_0003h) DSP4 ZM 3 DSP4_ZM_1 [15:0] 0000h (Similar for DSP4 Coefficient Memory 2 … 4094) R4726782 (48_1FFEh) DSP4 ZM 8190 0 0 0 0 0 0 0 0 DSP4_ZM_4095 [23:16] 0000h R4726783 (48_1FFFh) DSP4 ZM 8191 DSP4_ZM_4095 [15:0] 0000h R4784128 (49_0000h) DSP4 XM 0 0 0 0 0 0 0 0 0 DSP4_XM_0 [23:16] 0000h R4784129 (49_0001h) DSP4 XM 1 DSP4_XM_0 [15:0] 0000h R4784130 (49_0002h) DSP4 XM 2 0 0 0 0 0 0 0 0 DSP4_XM_1 [23:16] 0000h R4784131 (49_0003h) DSP4 XM 3 DSP4_XM_1 [15:0] 0000h (Similar for DSP4 X Data Memory 2 … 16382) R4816894 (49_7FFEh) DSP4 XM 32766 0 0 0 0 0 0 0 0 DSP4_XM_16383 [23:16] 0000h R4816895 (49_7FFFh) DSP4 XM 32767 DSP4_XM_16383 [15:0] 0000h R4882432 (4A_8000h) DSP4 YM 0 0 0 0 0 0 0 0 0 DSP4_YM_0 [23:16] 0000h R4882433 (4A_8001h) DSP4 YM 1 DSP4_YM_0 [15:0] 0000h R4882434 (4A_8002h) DSP4 YM 2 0 0 0 0 0 0 0 0 DSP4_YM_1 [23:16] 0000h R4882435 (4A_8003h) DSP4 YM 3 DSP4_YM_1 [15:0] 0000h (Similar for DSP4 Y Data Memory 2 … 4094) R4890622 (4A_9FFEh) DSP4 YM 8190 0 0 0 0 0 0 0 0 DSP4_YM_4095 [23:16] 0000h R4890623 (4A_9FFFh) DSP4 YM 8191 DSP4_YM_4095 [15:0] 0000h

Rev 4.0 373 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS ANALOGUE INPUT PATHS The WM8281 provides up to 6 analogue audio input paths. Each of these inputs is referenced to the internal DC reference, VMID. A DC blocking capacitor is required for each analogue input pin used in the target application. The choice of capacitor is determined by the filter that is formed between that capacitor and the impedance of the input pin. The circuit is illustrated in Figure 83. PGA Input C R Fc = high pass 3dB cut-off frequency Fc = 1

2 RCpVMID

Figure 83 Audio Input Path DC Blocking Capacitor In accordance with the WM8281 input pin resistance (see “ Electrical Characteristics ”), it is recommended that a 1F capacitance for all input connections will give good results in most cases , with a 3dB cut-off frequency around 13Hz. Ceramic capacitors are suitable , but care must be taken to ensure the desired capacitance is maintained at the AVDD operating voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required. A single capacitor is required for a single -ended line or microphone input connection. For a differential input connection, a DC blocking capacitor is required on both input pins. The external connections for single -ended and differential microphones, incorporating the WM8281 microphone bias circuit, are shown later in the “Microphone Bias Circuit” section - see Figure 84. DIGITAL MICROPHONE INPUT PATHS The WM8281 provides up to 8 digital microphone input paths; two channels of audio data can be multiplexed on each of the DMICDATn pins. Each of these stereo pairs is clocked using the respective DMICCLKn pin. The external connections for digital microphones, incorporating the WM8281 microphone bias circuit, are shown later in the “Microphone Bias Circuit” section - see Figure 86. Ceramic decoupling capacitors for the digital microphones may be required - refer to the specific recommendations for the application microphone(s). When two microphones are connected to a single DMICDAT pin, the microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic transmits a data bit when DMICCLK is low. The WM8281 samples the digital microphone data at the end of each DMICCLK phase. Each microphone must tri -state its data output when the other microphone is transmitting. Integrated pull-down resistors can be enabled on the DMICDAT pins if required. The voltage reference for e ach digital microphone interface is selectable. It is important that the selected reference for the WM8281 interface is compatible with the applicable configuration of the external microphone.

Rev 4.0 375 Digital microphone connection to the WM8281 is illustrated in Figure 86. Ceramic decoupling capacitor s for the digital microphones may be required - refer to the specific recommendations for the application microphone(s). Digital Mic MICVDD or MICBIASn AGND Digital Mic VDD CLK DATA VDD CLK DATA CHANCHAN VDD DMICDATn DMICCLKn Digital Microphone Interface Figure 86 Digital Microphone Connection The MICBIAS generators can each operate as a voltage regulator or in bypass mode. See “Charge Pumps, Regulators and Voltage Reference” for details of the MICBIAS generators. In Regulator mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. The regulators can be configured to support a capacitive load if required (eg. for digital microphone supply decoupling). The compatible load conditions are detailed in the “ Electrical Characteristics” section. If the capacitive load on MICBIAS1, MICBIAS2 or MICBIAS3 exceeds the specified conditions for Regulator mode (eg. due to a decoupling capacitor or long PCB trace), then the respective generator must be configured in Bypass mode. The maximum output current for each MICBIAS n pin is noted in the “ Electrical Characteristics”. This limit must be observed on each MICBIAS output, especially if more than one microphone is connected to a single MICBIAS pin. Note that the maximum output current differs between Regulator mode and Bypass mode. The MICBIAS output voltage can be adjusted using register control in Regulator mode. HEADPHONE DRIVER OUTPUT PATH The WM8281 provides 3 stereo headphone output drivers. These outputs are all ground -referenced, allowing direct connection to the external load(s). There is no requirement for DC blocking capacitors. In single -ended (default) configuration, the headphone outputs comprise 6 independently controlled output channels, for up to 3 stereo headphone or line outputs. In mono (BTL) mode, the headphone drivers support up to 3 differential outputs, suitable for a mono earpiece or hearing coil load. The headphone outputs incorporate a common mode, or ground loop, feedback path which provides rejection of system-related ground noise. The feedback pins must be connected to ground for normal operation of the headphone outputs. A separate feedback path is provided for each of the stereo headphone outputs. The HPOUT1 feedback is supported on two pins - the applicable pin is selected using the ACCDET_SRC register bit. The feedback pins should be connected to GND close to the respective headphone jack, as illustrated in Figure 87. In mono (differential) mode, the fee dback pin(s) should be connected to the ground plane that is physically closest to the earpiece output PCB tracks. It is recommended to ensure that the electrical characteristics of the PCB traces for each output pair are closely matched. This is particula rly important to matching the two traces of a differential (BTL) output.

378 Rev 4.0 Fc = R 2 p L WM8281 R L SPKOUTxP SPKOUTxN Fc = low pass 3dB cut-off frequency Figure 91 Speaker Equivalent Circuit for Filterless Operation For filterless Class D operation, it is important to ensure that a speaker with suitable inductance is chosen. For example, if we know the speaker impedance is 8Ω and the desired cut-off frequency is 20kHz, then the optimum speaker inductance may be calculated as: L = = = 64HR 2 p Fc 2 p * 20kHz 8 loudspeakers typically have an inducta nce in the range 20 H to 100 H, however, it should be noted that a loudspeaker inductance will not be constant across the relevant frequencies for Class D operation (up to and beyond the Class D switching frequency). Care should be taken to ensure that the cut-off frequency of the loudspeaker’s filtering is low enough to suppress the high frequency energy of the Class D switching and, in so doing, to prevent speaker damage. The Class D outputs of the WM8281 operate at much higher frequencies than is recomme nded for most speakers and it must be ensured that the cut-off frequency is low enough to protect the speaker.

380 Rev 4.0 CHARGE PUMP COMPONENTS The WM8281 incorporates two Charge Pump circuits, identified as CP1 and CP2. CP1 generates the CP1VOUTP and CP1VOUTN supply rails for the ground -referenced headphone drivers; CP2 generates the CP2VOUT supply rail for the microphone bias (MICBIAS) regulators. Decoupling capacitors are required on each of the Charge Pump outputs. Two fly-back capacitors are required for CP1; a single fly-back capacitor is required for CP2. The recommended Charge Pump capacitors for WM8281 are detailed below in Table 133. DESCRIPTION CAPACITOR CP1VOUT1P decoupling Required capacitance is 2.0F at 2V. Suitable component typically 4.7F. CP1VOUT1N decoupling Required capacitance is 2.0F at 2V. Suitable component typically 4.7F. CP1 fly-back 1 (connect between CP1C1A and CP1C1B) Required capacitance is 1.0F at 2V. Suitable component typically 2.2F. CP1VOUT2P decoupling Required capacitance is 2.0F at 2V. Suitable component typically 4.7F. CP1VOUT2N decoupling Required capacitance is 2.0F at 2V. Suitable component typically 4.7F. CP1 fly-back 2 (connect between CP1C2A and CP1C2B) Required capacitance is 1.0F at 2V. Suitable component typically 2.2F. CP2VOUT decoupling Required capacitance is 1.0F at 3.6V. Suitable component typically 4.7F. CP2 fly-back (connect between CP2CA and CP2CB) Required capacitance is 220nF at 2V. Suitable component typically 470nF. Table 133 Charge Pump External Capacitors Ceramic capacitors are recommended for these Charge Pump requirements. Note that, d ue to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. Ceramic capacitors with X5R dielectric are recommended. The positioning of the Charge Pump capacitors is important, particularly the fly -back capacitors. These capacitors should be placed as close as possible to the WM8281. The component choice and positioning of the CP1 compone nts are more critical than those of CP2, due to the higher ou tput power requirements of CP1. EXTERNAL ACCESSORY DETECTION COMPONENTS The external accessory detection circuit measures jack insertion using the JACKDET pin. The insertion switch status is detected using an internal pull-up resistor circuit on the JACKDET pin. Microphone detection and key -button press detection is supported using the MICDETn pins. The applicable pin should be connected to one of the MICBIAS n outputs, via a 2.2k bias resistor, as described in the “ Microphone Bias Circuit ” section. Note that, when using the External Accessory Detection function, the MICBIASn resistor must be 2.2k +/-2%. A recommended circuit configuration, including headphone output on HPOUT1 and microphone connections, is shown in Figure 93. See “ Analogue Input Paths ” for details of the DC -blocking microphone input capacitor selection. The recommended external components and connections for microphone / push -button detection are illustrated in Figure 94. Note that, when using the Microphone Detect circuit, it is recommended to use one of the Right channel analogue microphone input paths, to ensure best immunity to electrical transients arising from the external accessory.

382 Rev 4.0 RECOMMENDED EXTERNAL COMPONENTS DIAGRAM WM8281 VREFC GPIO GPIO3 CIF1MISO/GPIO4 GPIO5 CIF2SDA CIF2SCLK Control Interface 2 MCLK1 MCLK2 Master Clocks AGND SUBGND DGND CPGND SPKGNDRN GPIO1 GPIO2 CIF1ADDR/CIF1SS CIF1SCLK CIF1SDA/CIF1MOSI CIF1MODE Control Interface 1 HPOUT1R HPOUT1FB1/MICDET2 HPOUT1L Headphone (Note: HPOUT1FB ground connection close to headset jack)HPDETL HPDETR JACKDET Jack Detect input HPOUT3R HPOUT3FB HPOUT3L HPOUT2R HPOUT2FB HPOUT2L Line Output (Note: HPOUT2FB ground connection close to headset jack) Earpiece Speaker Outputs HPOUT1, HPOUT2 and HPOUT3 can be configured as Stereo pairs or Differential Mono. Digital Speaker (PDM) interface SPKCLK1 SPKDAT1 SPKCLK2 SPKDAT2 SPKOUTLN SPKOUTRP SPKOUTRN SPKOUTLP Loudspeaker Loudspeaker CP2CA CP2VOUT CP2CB 470nF 4.7F CP1C1A CP1VOUT1N CP1VOUT1P CP1C1B 2.2F 4.7F 4.7F CP1C2A CP1VOUT2N CP1VOUT2P CP1C2B 2.2F 4.7F 4.7F SPKGNDRP GPSWA GPSWB LDOVDD CPVDD 4.7F 4.7F 4.2V 1.8V SPKVDDL 4.7F DBVDD1 DBVDD2 DBVDD3 2 x 1.0F SPKVDDR AVDD1 AVDD2 4 x 0.1F SPKGNDLN SPKGNDLP 2.2F220 (1%) MICBIAS2 MICBIAS1 MICBIAS3 MICVDD Bias / Supplies for Microphones and External Accessory Detection 4.7F MICDET1/HPOUT1FB2 AIF1RXDAT AIF1LRCLK AIF1BCLK AIF1TXDAT Audio Interface 1 AIF2RXDAT AIF2LRCLK AIF2BCLK AIF2TXDAT Audio Interface 2 Audio Interface 3 AIF3RXDAT AIF3LRCLK AIF3BCLK AIF3TXDAT LDOENALDO Control RESETReset Control IRQInterrupt Output SLIMDAT SLIMCLK SLIMbus Interface MCLK2 MCLK1 Master Clocks IN1LP IN2LP IN1RN/DMICDAT1 IN1RP IN2LN/DMICCLK2 IN1LN/DMICCLK1 IN2RP IN2RN/DMICDAT2 1F 1F 1F Analogue and Digital Inputs IN3LP DMICCLK4 IN3RN/DMICDAT3 IN3RP IN3LN/DMICCLK3 DMICDAT4 1F DMIC CLK DAT CLK DAT VDD CHAN 2.2k 2.2k MICBIAS1 MICBIAS2 DMIC GND VDD CHAN GND Differential Microphone connection Single-ended Line connection Stereo Digital Microphone connection LDOVOUT DCVDD 2 x 2.2F DCVDD (Note: 2 x DCVDD decoupling capacitors are recommended; one close to each DCVDD pin)

Rev 4.0 383 RESETS SUMMARY The contents of Table 134 provide a summary of the WM8281 registers and other programmable memory under different reset conditions. The associated events and conditions are listed below.  A Power-On Reset occurs when AVDD or DBVDD1 is below its respective reset threshold. (Note that DCVDD is also required for initial start -up; subsequent interruption to DCVDD should only be permitted as part of a control sequence for entering Sleep mode.)  A Hardware Reset occurs when the RESET¯¯¯¯¯¯ input is asserted (logic 0).  A Software Reset occurs when register R0 is written to.  Sleep Mode is selected when LDO1 is disabled. (LDO1 can be controlled using the LDO1_ENA register bit, or using the LDOENA pin; both of these con trols must be de - asserted to disable the LDO.) Note that the AVDD, DBVDD1 and LDOVDD supplies must be present, and the LDOENA pin held low. It is assumed that DCVDD is supplied by LDO1. ALWAYS-ON REGISTERS OTHER REGISTERS CONTROL SEQUENCER MEMORY DSP FIRMWARE MEMORY Power-On Reset Reset Reset Reset Reset Hardware Reset Reset Reset Retained Configurable (see note) Software Reset Reset Reset Retained Configurable (see note) Sleep Mode Retained Reset Retained Reset Table 134 Memory Reset Summary See “Low Power Sleep Configuration” for details of the ‘Always-On’ registers. See “DSP Firmware Control” for details of the configurable DSP memory behaviour. Note that, to retain the DSP firmware memory contents during Hardware Reset or Software Reset, it must be ensured that DCVDD is held above its reset t hreshold. If DCVDD is powered from internal LDO, then it is recommended to assert the LDOENA pin before the Reset, in order to maintain the DCVDD supply.

384 Rev 4.0 OUTPUT SIGNAL DRIVE STRENGTH CONTROL The WM8281 supports configurable drive strength control for the digital output pins. This can be used to assist system-level integration and design considerations. The drive strength control registers are described in Table 135. Note that, in the case of bi -directional pins (eg. GPIOn), the drive strength control registers are only applicable when the pin is configured as an output. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3120 (0C30h) Misc Pad Ctrl 7

10 CIF1MISO_GPIO

4_DRV_STR

1 CIF1MISO / GPIO4 output drive strength

0 = 4mA 1 = 8mA

2 CIF1SDA_CIF1M

OSI_DRV_STR

1 CIF1SDA / CIF1MOSI output drive

0 = 4mA 1 = 8mA R3121 (0C31h) Misc Pad Ctrl 8

2 CIF2SDA_DRV_

1 CIF2SDA output drive strength

0 = 4mA 1 = 8mA R3122 (0C32h) Misc Pad Ctrl 9

10 AIF1LRCLK_DRV

_STR

1 AIF1LRCLK output drive strength

0 = 4mA 1 = 8mA

2 GPIO1_DRV_ST

R

1 GPIO1 output drive strength

0 = 4mA 1 = 8mA R3123 (0C33h) Misc Pad Ctrl 10

10 AIF1BCLK_DRV_

1 AIF1BCLK output drive strength

0 = 4mA 1 = 8mA

2 AIF1TXDAT_DR

V_STR

1 AIF1TXDAT output drive strength

0 = 4mA 1 = 8mA R3124 (0C34h) Misc Pad Ctrl 11

10 AIF2LRCLK_DRV

_STR

1 AIF2LRCLK output drive strength

0 = 4mA 1 = 8mA

2 GPIO2_DRV_ST

R

1 GPIO2 output drive strength

0 = 4mA 1 = 8mA R3125 (0C35h) Misc Pad Ctrl 12

10 AIF2BCLK_DRV_

1 AIF2BCLK output drive strength

0 = 4mA 1 = 8mA

2 AIF2TXDAT_DR

V_STR

1 AIF2TXDAT output drive strength

0 = 4mA 1 = 8mA R3126 (0C36h) Misc Pad Ctrl 13

10 AIF3LRCLK_DRV

_STR

1 AIF3LRCLK output drive strength

0 = 4mA 1 = 8mA

2 GPIO3_DRV_ST

R

1 GPIO3 output drive strength

0 = 4mA 1 = 8mA R3127 (0C37h) Misc Pad Ctrl 14

10 AIF3BCLK_DRV_

1 AIF3BCLK output drive strength

0 = 4mA 1 = 8mA

2 AIF3TXDAT_DR

V_STR

1 AIF3TXDAT output drive strength

0 = 4mA 1 = 8mA

Rev 4.0 385 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3128 (0C38h) Misc Pad Ctrl 15

10 SLIMDAT_DRV_

0 SLIMDAT output drive strength

0 = 8mA 1 = 12mA

2 SLIMCLK_DRV_

1 SLIMCLK output drive strength

0 = 2mA 1 = 4mA R3129 (0C39h) Misc Pad Ctrl 16

10 IRQ_DRV_STR 1 IRQ output drive strength

0 = 4mA 1 = 8mA

2 GPIO5_DRV_ST

R

1 GPIO5 output drive strength

0 = 4mA 1 = 8mA R3130 (0C3Ah) Misc Pad Ctrl 17

10 SPKDAT1_DRV_

1 SPKDAT1 output drive strength

0 = 4mA 1 = 8mA

2 SPKCLK1_DRV_

1 SPKCLK1 output drive strength

0 = 4mA 1 = 8mA R3131 (0C3Bh) Misc Pad Ctrl 18

10 SPKDAT2_DRV_

1 SPKDAT2 output drive strength

0 = 4mA 1 = 8mA

2 SPKCLK2_DRV_

1 SPKCLK2 output drive strength

0 = 4mA 1 = 8mA Table 135 Output Drive Strength and Slew Rate Control

386 Rev 4.0 DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS The digital audio interface s (AIF1, AIF2, AIF3) can be configured in Master or Slave modes. In all applications, it is important that the system clocking configuration is correctly designed. Incorrect clock configurations will lead to audible clicks arising from dropped or repeated audio samples; this is caused by the inherent tolerances of multiple asynchronous system clocks. To ensure reliable clocking of the audio interface functions, it is a requirement that the externa l interface clocks (eg. BCLK, LRCLK) are derived from the same clock source as SYSCLK (or ASYNCCLK, where applicable). In AIF Master mode , the external BCLK and LRCLK signals are generated by the WM8281 and synchronisation of these signals with SYSCLK (or ASYNCCLK) is ensured. In this case, clocking of the AIF is typically derived from the MCLK1 or MCLK2 inputs, either directly or via one of the Frequency Locked Loop (FLL) circuits. It is also possible to use a different interface (AIFn or SLIMbus) to provide the reference clock to which the AIF Master can be synchronised. In AIF Slave mode, the external BCLK and LRCLK signals are generated by another device, as inputs to the WM8281. In this case, it must be ensured that the applicable system clock (SYSCLK o r ASYNCCLK) is generated from a source that is synchronised to the external BCLK and LRCLK inputs. In a typical Slave mode application , the BCLK input is selected as the clock reference, using the FLL to perform frequency shifting. It is also possible to u se the MCLK1 or MCLK2 inputs, but only if the selected clock is synchronised externally to the BCLK and LRCLK inputs. The SLIMbus interface can also provide the clock reference, via one of the FLLs , provided that the BCLK and LRCLK signals are externally synchronised with the SLIMCLK input. The valid AIF clocking configurations are listed in Table 136 for AIF Master and AIF Slave modes. The applicable system clock (SYSCLK or ASYNCCLK) depends on the AIFn_RATE setting for the relevant digital audio interface; if AIFn_RATE < 1000 , then SYSCL K is applicable; if AIFn_RATE ≥ 1000, then ASYNCCLK is applicable. AIF MODE CLOCKING CONFIGURATION AIF Master Mode SYSCLK_SRC (ASYNCCLK_SRC) selects MCLK1 or MCLK2 as SYSCLK (ASYNCCLK) source. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects MCLK1 or MCLK2 as FLLn source. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects a different interface (BCLK, LRCLK, SLIMCLK) as FLLn source. AIF Slave Mode SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects BCLK as FLLn source. SYSCLK_SRC (ASYNCCLK_SRC) selects MCLK1 or MCLK2 as SYSCLK (ASYNCCLK) source, provided MCLK is externally synchronised to the BCLK input. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects MCLK1 or MCLK2 as FLLn source, provided MCLK is externally synchronised to the BCLK input. SYSCLK_SRC (ASYNCCLK_SRC) selects FLLn as SYSCLK (ASYNCCLK) source; FLLn_REFCLK_SRC selects a different interface (eg. SLIMCLK) as FLLn source, provided the other interface is externally synchronised to the BCLK input. Table 136 Audio Interface (AIF) Clocking Confgurations

390 Rev 4.0 PACKAGE DIMENSIONS

Rev 4.0 391 IMPORTANT NOTICE Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale suppli ed at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specific ations or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant informati on from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative purposes only. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without a lteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consen t does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, SoundClear, WISCE, and Ez2 Hear are among the trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners . Copyright © 2014–2016 Cirrus Logic, Inc. All rights reserved. SLIMbus is a trademark or registered trademark of MIPI Alliance, Inc. SPI is a trademark of Motorola.

392 Rev 4.0

REVISION HISTORY

DATE REV DESCRIPTION OF CHANGES PAGE CHANGED BY 23/01/14 2.0 Initial version PH 13/06/14 3.0 Additional notes on SLIMbus Value Map & Information Map. JTAG Interface input pins all have internal pull-down resistors. Clarification of the TRIG_ON_STARTUP (automatic sample rate detection) behaviour. Typical performance data (power consumption and latency) added. 161-170 10, 305, 309 256 27, 28 PH 06/05/15 3.1 Clarification of LDOENA & LDOVDD pin requirements. Electrical Characteristics updated. Thermal characteristics data added. Power consumption data updated. Correction to PWMn_LVL description. Updates to DSP Clocking registers and controls. Added description of DSP DMA functions. Class-D phase inversion noted. Clarification to the AEC Loopback path description. Bus-keeper function on GPIO pins is removed. Clarification of Sleep Mode control using external DCVDD (not LDO1). Clocking required for FLL Interrupt. Updated recommendations for DCVDD decoupling. PH 11/01/16 4.0 Clarification of DCVDD, GPSWA, GPSWB voltage limits Electrical Characteristics updated. Power consumption data updated (earpiece and speaker playback) Sample Rate control requirements updated (*RATE, *FSL, *FSH) Clarification of SLIMbus requirements for different TP options. Recommended SLIMbus subframe mode (SM) selection noted. FLL set-up procedure updated Correction to FLLn_SS_SEL description. Noted constraints for using WSEQ_START to trigger WSEQ. 14, 22 19-21 102-120 168 173 276-278 287 296 PH