WM8255

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Single Channel 16-bit CIS/CCD AFE with RGB LED Current Drive WOLFSON MICROELECTRONICS plc Production Data, August 2013, Rev 4.7 Copyright 2013 Wolfson Microelectronics plc

DESCRIPTION

The WM8255 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12 MSPS. The device includes a comple te signal processing channel containing Reset Level Cl amping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 16-bit Analogue to Digital Converter. The digital output data is available in a 2 bit or 4-bit wide multiplexed format. An internal 4-bit DAC is suppli ed for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Lev el Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. The device includes an RGB LED current drive using current and PWM functionality to control the operation of sensor LEDs. The device typically uses an analogue supply voltage of 5.75V and a digital interface supply of 3.3V.

FEATURES

 16-bit ADC  12 MSPS conversion rate  Low power – 250 mW typical  5.75V and 3.3V supply operation  Single channel operation  Correlated double sampling  Programmable gain (8-bit resolution)  Programmable offset adjust (8-bit resolution)  Programmable clamp voltage  RGB LED current drive using current and PWM  2-bit or 4-bit wide multiplexed data output format  Internally generated voltage references  28-lead QFN package  3 wire serial control interface

APPLICATIONS

 Flatbed and sheetfeed scanners  USB compatible scanners  Multi-function peripherals BLOCK DIAGRAM

w PD, Rev 4.7, August 2013 TABLE OF CONTENTS

w PD, Rev 4.7, August 2013

w PD, Rev 4.7, August 2013 PIN CONFIGURATION EXTRES VRB VRT VRX NC AGND2 AVDD2 VSMP SEN SCK SDI NC LEDSTART TG

ORDERING INFORMATION

o C 4x4x0.85mm 28-lead QFN (Pb-free) MSL3 260 o C WM8255BGEFL/RV 0 to 85 o C 4x4x0.85mm 28-lead QFN (Pb-free, tape and reel) MSL3 260 o C Note: Reel quantity = 3,500

w PD, Rev 4.7, August 2013 PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION 1 MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 4, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital multiplexed output data bus. ADC output data (d15:d0) is available in a 4-bit multiplexed format as shown below. A 2-bit multiplexed output is also available as described in the OUTPUT FORMATS section of this datasheet on page 18. A B C D

2 OP[3]/SDO Digital output d15 d11 d7 d3

3 OP[2] Digital output d14 d10 d6 d2

4 OP[1] Digital output d13 d9 d5 d1

5 OP[0] Digital output d12 d8 d4 d0

Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 6 DVDD Supply Digital supply (3.3V) 7 DGND Supply Digital ground (0V). 8 EXTRES Analogue input External resistor connection for LED absolute current control. Must be connected to ground via a suitable resistor. 9 VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 10 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor.

11 VRX Analogue output Input return bias voltage

This pin must be connected to AGND via a decoupling capacitor. 12 NC No Connect Not Connected.

13 AGND2 Supply Analogue ground pin (0V)

14 AVDD2 Supply Analogue supply (3.3V) Not required to be driven if AVDD1 is being used. A decoupling capacitor must be connected to AGND. 15 VINP Analogue input Video input.

16 VRLC/VBIAS

Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z.

17 ILEDB Analogue input Blue LED pin

18 ILEDG Analogue input Green LED pin

19 ILEDR Analogue input Red LED pin

20 AVDD1 Supply Analogue Supply (5.75V) 21 AGND1 Supply Analogue ground (0V).

22 TG Digital input Line synchronisation pulse

23 LEDSTART Digital input LED start pulse

24 NC No Connect Not Connected. 25 SDI Digital input Serial data input.

26 SCK Digital input Serial clock

27 SEN Digital input Enables the serial interface when high. 28 VSMP Digital input Video sample synchronisation pulse.

w PD, Rev 4.7, August 2013 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specificati ons are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. The WM8255 has been classified as MSL1, wh ich has an unlimited floor life at <30 o C / 85% Relative Humidity and therefore will not be supplied in moisture barrier bags. CONDITION MIN MAX Analogue supply voltage: AVDD1 GND - 0.3V GND + 7V Analogue supply voltage: AVDD2 GND - 0.3V GND + 4.2V Digital core supply and I/O voltage: DVDD GND - 0.3V GND + 4.2V Digital ground: DGND GND - 0.3V GND + 0.3V Analogue grounds AGND GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital I/O pins GND - 0.3V DVDD + 0.3V Analogue input VINP GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V Operating temperature range: TA 0C +85 C Notes: 1. GND denotes the voltage of any ground pin. 2. AGND and DGND pins are intended to be operated at the sa me potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN TYP MAX UNITS Operating temperature range TA 0 85 C Analogue supply voltage AVDD1 4.75 5.75 6.0 V Analogue supply voltage AVDD2 2.97 3.3 3.63 V Digital Core and I/O supply voltage DVDD 2.97 3.3 3.63 V Notes 1. AVDD2 supply not required if using AVDD1. AVDD2 w ould require connection to ground via a capacitor in that situation. 2. If AVDD2 is being used, both AVDD2 and DVDD should be operated at the same potential. THERMAL PERFORMANCE PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Performance Thermal resistance – junction to case (5x5x0.9mm package) RθJC Tambient = 25°C 10.27 °C/W Thermal resistance – junction to ambient (5x5x0.9mm package) RθJA 29.45 °C/W Thermal resistance – junction to ambient (4x4x0.85mm package) RθJA 24.05 °C/W Notes: 1. Figures given are for package mounted on 4-layer FR4 according to JESD51-5 and JESD51-7.

w PD, Rev 4.7, August 2013

ELECTRICAL CHARACTERISTICS

AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz, mode 1 unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Full-scale input voltage range (see Note 1) Max Gain Min Gain 0.24 2.56 Vp-p Vp-p Input signal limits (see Note 2) VIN 0 AVDD1 V Full-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 10 +50 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 10 +50 mV Differential non-linearity DNL 1.5 LSB Integral non-linearity INL 25 LSB Input referred noise 9 LSB rms References Upper reference voltage VRT 2.05 V Lower reference voltage VRB 1.05 V Diff. reference voltage (VRT-VRB) VRTB 1.0 V Output resistance VRT, VRB, VRX 1  VRLC/Reset-Level Clamp (RLC) RLC switching impedance 10 50 100  VRLC short-circuit current 8 mA VRLC output resistance 2  VRLC Hi-Z leakage current VRLC = 0 to AVDD1 1 A RLCDAC resolution 4 bits RLCDAC step size VRLCSTEP 0.24 V/step RLCDAC output voltage at code 0(hex) VRLCBOT 0.3 V RLCDAC output voltage at code F(hex) VRLCTOP 3.9 V Offset DAC, Monotonicity Guaranteed Resolution 8 bits Differential non-linearity DNL 0.6 LSB Integral non-linearity INL 2 LSB Step size 1.96 mV/step Output voltage Code 00(hex) Code FF(hex) -220 +220 -250 +250 -280 +280 mV mV Notes: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input range. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie.

w PD, Rev 4.7, August 2013 Test Conditions AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Programmable Gain Amplifier Resolution 8 bits Gain equation 255 V/V Max gain GMAX 8 8.35 8.7 V/V Min gain GMIN 0.72 0.78 0.82 V/V Internal channel offset VOFF 10 mV Analogue to Digital Converter Resolution 16 bits Maximum Speed 12 MSPS Full-scale input range (2*(VRT-VRB)) VFS 2.0 V DIGITAL SPECIFICATIONS Digital Inputs High level input voltage VIH 0.7  DVDD V Low level input voltage VIL 0.2  DVDD V High level input current IIH 1 A Low level input current IIL 1 A Input capacitance CI 5 pF Digital Outputs High level output voltage VOH I OH = 1mA DVDD - 0.5 V Low level output voltage VOL I OL = 1mA 0.5 V Supply Currents (LED Current DAC switched off) Total supply current  active 42.5 mA  Total analogue AVDD, supply current  active IAVDD 39 mA  Total digital core, DVDD, supply current  active IDVDD1 3.5 mA  Supply current  full power down mode 500 A Notes: 1. Digital I/O supply current depends on t he capacitive load attached to the pin. The Digital I/O supply current is measured with approximately 50pF attached to the pin.

w PD, Rev 4.7, August 2013 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL LED CURRENT DRIVE Coarse Absolute LED Current Drive Range Adjust EXTRES = 13K7 ohm +/- 1% over process and temperature. Coarse LED Current Full Scale Range with External Reference including absolute and temperature tolerances ILEDCRE0 LEDIRNG = 00 25 32 mA ILEDCRE1 LEDIRNG = 01 30 42.25 mA ILEDCRE2 LEDIRNG = 10 40 56.5 mA ILEDCRE3 LEDIRNG = 11 50 68 mA Coarse LED Current Maximum Limit Range ILEDMAX LEDIMAX = 0 28 45 mA ILEDMAX LEDIMAX = 1 35 53 mA FINE LED ABSOLUTE CURRENT DRIVE Resolution ILEDFRes 8 bits Range ILEDFRan ILEDCRXX Zero Current 0 mA Differential non-linearity ILEDFDNL No missing codes -1 1.15 LSB Integral non-linearity ILEFINL 1 LSB Compliance Voltage ILEDR ILEDRVC ILED=50mA 0.75+ AGND AVDD1 - 0.5V V Compliance Voltage ILEDG and ILEDB ILEDGBVC ILED=50mA 0.25+ AGND AVDD1 - 0.5V V

w PD, Rev 4.7, August 2013 SERIAL INTERFACE SCK SDI SEN SDO tSPER tSCKL tSCKH tSSU tSH tSCE tSEW tSEC tSERD tSCRD MSB LSB tSCRDZ ADC DATA ADC DATA REGISTER DATA Figure 3 Serial Interface Timing Test Conditions AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 41.6 ns SCK high tSCKH 18.8 ns SCK low t SCKL 18.8 ns SDI set-up time tSSU 6 ns SDI hold time tSH 6 ns SCK to SEN set-up time tSCE 12 ns SEN to SCK set-up time tSEC 12 ns SEN pulse width tSEW 25 ns SEN low to SDO = Register data tSERD 30 ns SCK low to SDO = Register data tSCRD 30 ns SCK low to SDO = ADC data tSCRDZ 30 ns Note: 1. Parameters are measured at 50% of the rising/falling edge

w PD, Rev 4.7, August 2013 PWM TIMING Figure 4 PWM Timing Test Conditions AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, T A = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM LED Current Drive Control PWM Period tPWMPER (CLKDIV+1) * LEDPWMPER * tPER ns PWM Duty Cycle LEDPWMDC/ LEDPWMPER - PWM Period Resolution (CLKDIV +1) * tPER ns PWM Period Range (CLKDIV +1) * 4096 * t PER ns PWM Duty Cycle Resolution (CLKDIV +1) * t PER ns PWM Duty Cycle Range (CLKDIV +1) * 4096 * t PER ns PWM Enable Coarse Adjust tPWMMaxCount t PWMPER*1 t PWMPER *128 ns LEDSTART set-up time TLEDSU 6 ns LEDSTART hold time TLEDH 3 ns TG set-up time tTGSU 6 ns TG hold time tTGH 3 ns PWM Rise / Fall Time tPWMR /tPWMF 1 5 us Minimum blank period tBLANK 25 us Notes: 1. For LED Current Drive Description refer to Page 17. 2. The Blank period starts on the 2 nd falling edge of MCLK after TG goes high. 3. CLKDIV, LEDPWMPER and LEDPWMDC are register settings. For further details see Table 10.

w PD, Rev 4.7, August 2013 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8255 processes the sampled video signal on VINP with respect to the video-reset level or an internally/externally generated reference level through the analogue-processing channel. This processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 16-bit digita l word. The digital output from the ADC is presented on a 4-bit wide bus. On-chip control registers determi ne the configuration of the devic e, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. The device can control the brightness and timing of the Red, Green and Blue LEDs used in a CIS sensor. This is controlled via the serial control interface and external timing pins. INPUT SAMPLING The WM8255 has a single analogue proc essing channel and ADC, which can be used in a flexible manner to process both monochrome and line-by-line colour inputs. Monochrome: The selected input (VINP) is samp led, processed by the analogue channel, and converted by the ADC. The same offset DAC and PGA register values are always applied. Colour Line-by-Line: VINP is sampled and process ed by the analogue channel before being converted by the ADC. The gains and offset regist er values applied to the PGA and offset DAC can be switched between the independent Red, Green and Blue digital registers (e.g. Red  Green Blue  Red…) at the start of each line in order to facilitate line-by-line colour operation. The INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset DAC. By using the INTM[1:0] bits to select the des ired register values only one register write is required at the start of each new colour line. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8255 VINP pin lies within the valid input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, C IN. When active, the RLC circuit clamps the WM8255 side of this capacitor to a suitable voltage during the CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit. A typical input configuration is shown in Figure 5. The Timing Control Block generates a clamp pulse, CL, from MCLK and VSMP (when RLCINT is high) . When CL is active the voltage on the WM8255 side of C IN, at VINP, is forced to the VRLC/VBIAS voltage (V VRLC) by switch 1. When the CL pulse turns off, the voltage at VINP initially remains at V VRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to VINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section.

w PD, Rev 4.7, August 2013 Figure 7 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this ca se, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by R s at the same time as Vs samples the video level in this mode. OFFSET ADJUST AND PROGRAMMABLE GAIN The output from the CDS block is a differential si gnal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or B). In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 1. INTM[1:0] DESCRIPTION

00 Red offset and gain registers are applied to offset DAC and PGA

(DACR[7:0] and PGAR[7:0])

01 Green offset and gain registers applied to offset DAC and PGA

(DACG[7:0] and PGAG[7:0])

10 Blue offset and gain registers applied to offset DAC and PGA

(DACB[7:0] and PGAB[7:0]) 11 Reserved. Table 1 Offset DAC and PGA Register Control The gain characteristic of the WM8255 PGA is shown in Figure 8. Figure 9 shows the maximum input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.0V). 0 64 128 192 256 Gain register value (PGA[7:0]) PGA Gain (V/V) 0.5 1.5 2.5 0 64 128 192 256 Gain register value (PGA[7:0]) Peak input voltage to match ADC Full- scale I nput Range Figure 8 PGA Gain Characteristic Figure 9 Peak Input Voltage to Match ADC Full-scale Range MCLK VSMP VS RS/CL (CDSREF = 00) RS/CL (CDSREF = 01) RS/CL (CDSREF = 10) RS/CL (CDSREF = 11)

w PD, Rev 4.7, August 2013 VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then convert ed to a 16-bit unsigned number, with input range configured by PGAFS[1:0]. D1[15:0] = INT{ (V3 /VFS)  65535} + 32767 PGAFS[1:0] = 00 or 01 Eqn. 6 D1[15:0] = INT{ (V3 /VFS)  65535} PGAFS[1:0] = 11 Eqn. 7 D1[15:0] = INT{ (V3 /VFS)  65535} + 65535 PGAFS[1:0] = 10 Eqn. 8 where the ADC full-scale range, VFS = 2.0V if D1[15:0] > 65535 D1[15:0] = 65535 OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP. D2[15:0] = D1[15:0] (INVOP = 0) Eqn. 9

w PD, Rev 4.7, August 2013 MONOCHROME (COMPOSITE) MODE In Monochrome Mode, the progression between sequence states is triggered by the completion of the previous sequence state. This allows a complete LED sequence change for each line scan. With both TG and LEDSTART high, the sequence state machine is synchronously set to the STATE_0 by MCLK. When the STATE_0 has r eached the end of its enable period, the sequence state machine is progressed to the next state by MCLK. This is repeated until the maximum number of states determined by STATERST has been reached. At this point the LED drive current will be switched away from the selected LEDs. The sequence state machine will be held in this state until restarted by LEDSTART and TG. If at any time both TG and LEDSTART are high, the sequence is synchronously set back to STATE_0 by MCLK. LED CURRENT DRIVE INTENSITY CONTROL The LED current driver is programmable to allow the LED light intensity to be adjusted independent of the LED light wavelength. Two methods are available for this:  The absolute LED current drive may be set using a programmable 8-bit current DAC. The current DAC range for each of the LEDs may be adjusted to one of four ranges using the register LEDIRNG.  The LED current drive may be pulsed using a pulse width modulated. The pulse width modulated period is set using the register LEDPWMPER and on time using the registers LEDPWMDCR, LEDPWMDCB and LEDPWMDCG. Control of the absolute LED current drive and PWM modulation are independently programmable for each of the red, green and blue LEDs using the register map. The signals LEDSTART, TG and MCLK determine timing. LED CURRENT DRIVE STATE TRANSITION AND PWM SWITCHING The WM8255 is the combination of a LED current sw itching matrix and an AFE. With reference to Figure 15, during a typical line scan the video signal of the previous line scan is digitised by the AFE while the image of the current line scan is illuminated. To suppress any switching noise of the LED switching matrix coupling into the AFE, care is taken while switching the current. Two types of current switching are available in the WM8255, state transition switching and PWM switching. State transition switching occurs when either a new LED is to be selected or the LED current DAC has to be updated. PWM transition swit ching occurs when the illumination intensity is controlled by pulsing the LED drive current. In colour mode, state transition switching should occur at the start of a line scan. In mono mode, state trans ition switching can occur during the line scan. In either colour mode or mono mode, PWM transition switching can occur during the line scan.

w PD, Rev 4.7, August 2013 Figure 15 Relationship between Line Scan Illumination and Video Signal Readout Two current switching techniques are used for st ate and PWM transition switching, slew rate controlled current switching and current steering switching. With reference to Figure 16, the LED drive current has three blocks, the LED current DAC, the LED RGB matrix switch and a shunt current path switch. With reference to Figure 16, for current slew rate controlled switching, the LED current DAC value is reset from the current value to zero then set to an updated value. Slew rate limited current switch may be partitioned into four operations:

w PD, Rev 4.7, August 2013 Figure 16 Current Slew Rate Controlled Switching 1. The red RGB switch is initially closed and t he LED drive current will flow in the red diode 2. The Red RGB switch will open and the shunt cu rrent path switch is closed. The LED drive current will flow in the shunt current path. Du ring this period the LED current DAC is reset to zero then updated to the next value. No current will flow in any LEDs. 3. The green RGB switch will be closed. 4. The auxiliary current path switch will be opened and LED drive current will flow in the green LED. The finite time taken for a slew rate controlled current switch is the period necessary to change the value of the LED current DAC. The slew rate of the current change is limited by the dynamic performance of the LED current DAC. During this time the LED IDAC current will flow through the shunt current path switch and no illumination will occu r. This period of time is defined by blanking period MONO MODE REQUIREMENTS During a slew rate limited current switch of the LED IDAC, the change of current flowing in the IDAC will couple a minor disturbance into the AFE. In col our mode this disturbance is not an issue since the state change switching will occur at the beginning of a line scan when no imaging is occurring. In mono mode a red, blue and green state switching ma y occur during a line scan and couple correlated switching noise into the signal path. In mono mode to minimise switching noise into the signal path:: - The blanking period must be dis abled. In this mode during a state change, no slew rate limiting switching will occur, Only the RGB switches will be switched. Table 3 defines the method to disable blanking during a state transition. - In this mode of operation, between states the abs olute value of the LED IDAC current must not change.

w PD, Rev 4.7, August 2013 - In this mode of operation, setting the duty cycle to zero is an invalid state. The RGB switches should be used to switch off the LED current. This method will have no effect on colour mode performance. BLANKING DISABLE CODE SET Address Data Comment 0x01 0xA3 This will put the part into test configuration mode. Any address will now point to the extended page reconfiguration register 0x24 0x1C This will: -- force the LED IDAC control state machine to stay on at all time - force the value to be held in LEDIDACR to be loaded into the LED current DAC 0x01 0x23 This will take the part back into normal operating mode. Notes: 1. If this COMPLETE SEQUENCE of operation is not carried out TOGETHER the part may go into an unsupported mode To finish a mono mode scan with blanking period disabled and perform another operation, the part needs to get into a know state. Two options are available for a complete reset of the device or a reset of the LED sequence controller: Option 1: WM8255 global reset from blanking period disable Address Data Comment 0x04 0x00 This will reset the WM8255 into its default condition. The part should now be fully reconfigured into the user configuration. Option 2: WM8255 LED sequence controller reset from blanking period disable Address Data Comment 0x2F 0x00 This will reset LED sequence controlle r WM8255. All configuration data will be held. Table 3 Blanking Period Disable With reference to Figure 17 for current steering, 1. The appropriate RGB matrix swit ch is closed allowing the LED current DAC current to flow in the LED 2. The first step to switch off the LED current is to close the shunt current path switch 3. The LED is switched off by opening the RGB switch matrix. 4. To switch on the LED, first the shunt current path switch is closed and the cycle repeats. A make before break switch sequence is used when t he LED is switched on or off. As a result the LED current DAC always has a path to flow and never changes value.

w PD, Rev 4.7, August 2013 1 2 3 4 Figure 17 Current Steering Switching LED CURRENT DRIVE CURRENT PWM CONTROL During each sequence state, the LED control m odule can be pulsed by Pu lse Width Modulating (PWM) the LED current drive. For each sequence state, the PWM frequency, duty cycle, and number of PWM cycles can be configured. The PWM controller consists of two blocks; t he MCLK divider and the PWM counter. The MCLK divider divides the MCLK by an amount set by the register CLKDIV. The divided MCLK is then used to clock the PWM counter. The PWM counter will increment until it reaches its maximum count set by the register LEDPWMPER. At this point, the PWM counter will reset to zero, then continue to increment. This will set the period of the PWM control. As the PWM counter is incremented, its state is co mpared with the duty cycle setting, which is set by the value in register LEDPWMDC. PWMCtrl is set while the counter value is smaller than the duty cycle setting. When the counter is larger than or equal to the duty cycle, PWMCTRL is reset for the rest of the PWM period. This will set the duty cycle of the PWM control. The reset of the PWM counter will increment the LEDEnable counter. W hen the LEDEnable counter has reached LEDENSTART, PWMEn is set high, whic h allows PWMCtrl to control the LED current drive. The LEDEnable counter will continue to incr ement until it has reached LEDENSTOP. At this point PWMEn is set low, which stops PWMCtrl from controlling the LED current drive. This will set the number of cycles of the PWM control. The PWM frequency is defined by LEDPWMPER and the divider CLKDIV. LEDPWMPER and CLKDIV may be calculated as the nearest integr al of the MCLK frequency divided by the PWM frequency. If the maximum value of LEDPWMPER would reach its maximum before the desired PWM period is achieved, CLKDIV should be incremented to scale LEDPWMPER correctly. The PWM duty cycle is defined by LEDPWM DC and CLKDIV. For a chosen PWM frequency, an integral number of PWM cycles for the period of TG may be calculated. The range of the PWM period and the duty cycle can be up to (2^4 X 2^12) MCLK cycles.

w PD, Rev 4.7, August 2013 ILIMITEN [1:0] DESCRIPTION

00 At a state transition, one blanking period will be used before the LED can be

enabled. LED DAC current will be changed and next LED in sequence shall be selected. No Safe Operating Area test will be performed.

01 At a state transition, two blanking periods will be used before the LED can be

enabled. During the first blanking period, should the LED DAC current exceed LEDIMAX, ILIMITFLAG is set and the LED DAC current is reduced by the percentage set by ILIMITDEC. During the second blanking period, should the LED current exceed LEDIMAX, ILIMITFLAG is set and the LED DAC current will be shutdown.

10 At a state transition, one blanking period will be used before the LED can be

enabled. Should the LED current exceed LEDIMAX, ILIMITFLAG is set. The LED current will not be reduced automatically. In this situation, the user should take measures to protect the LED by reducing the LED current.

11 Not a valid setting

Table 4 Modes of Operation of ILIMITEN Register SETTING THE INITBLANK REGISTER With reference to Figure 19, the period t BLANK is the initial blank period with no illumination. The initial blank period time must be controlled by setting a val ue for a 9-bit register INITBLANK. Setting this register will enable a counter that is clocked by MCLK to allow for the necessary minimum 25 microseconds. The last three LSBs are fixed to zero and only the 6 MSBs are adjustable. The value needed for the register INITBLANK is calculated by :- BLANK *0.8)/ MCLK period = INITBLANKdec. This number should be rounded up to an integral decimal number. The binary equivalent of INITBLANK dec should be calculated and, making sure the last 3 LSBs are zero, should be set in the register. For example:- MCLK = 24 Mhz => 41.6ns (t PER) The nearest integral number where the binary equivalent has zero values in the last 3 LSBs is 480. 480 = 111100000 bin. Therefore the 6 MSBs to be set to the register INITBLANK are:- 111100 By default INITBLANK is set to zero which sets the initial blank period to equal the PWM period/0.8 set by LEDPWMPER. If ILIMITEN is set to ‘01’ then this blanking period will be doubled. Note that the INITBLANK register value does not require a new value in this situation.

w PD, Rev 4.7, August 2013 10 2 3 0 1 Figure 23 PWM LED Current Control Timing - Monochromatic Scan with PWM Duty Cycle and Blanking Period Disabled CURRENT ACCURACY AND ABSOLUTE MAXIMUM CURRENT LIMIT To protect the LED when operated near its maximum operating current range, an accurate absolute maximum current limit can be set. An external resistor connected to the EXTR ES pin must be provided to generate an accurate reference current for the LED circuit. As the cu rrent DAC is designed for low compliance voltage, a separate higher accuracy current detection circuit is provided. At the start of every state change the Current DAC setting for that LED is measured (Red, Green or Blue). If the state machine is at RED and the cu rrent, LEDIDACR, exceeds the absolute maximum current limit, a register, LEDRFLAG will be set. If ILIM ITEN is set to the appropriate mode, the current will be automatically reduced and the current retested. Should this new current be within the safe operating area the Red LED will be enabled. The LEDRFLAG register will remain set to indicate that the reduction has been implemented. The next time the state machine enters the RED st ate, the current value is measured again. If the current, LEDIDACR is now an acceptable value (wit hout a reduction) the LEDRFLAG will reset. This is the same when in the GREEN and BLUE stat es, where LEDIDACG and LEDIDACB are measured respectively. Note that for the initial current test of a new state, the machine always loads the Current DAC register setting, not a reduced value previously used. Throughout the DAC loading and current limit testing, the LED is disabled and the current is steered through the power supply AVDD1. This prevents stress in the LED, by ensuring that it is not enabled until the current is within the safe operating area. A register bit ILIMITFLAG will get set when any of the LED Flags are set. All of the Flags will be reset when applying a LED Software Reset. For example: The Red LED maximum current is 53mA in this example. LEDIRNGR = 11 which gives an absolute maximum current of 68 mA. LEDIMAX = 1 which gives a maximum limit of up to 53 mA. ILIMITDEC = 1 which sets reduction to 25% ILIMITEN = 01 which enables current reduction

w PD, Rev 4.7, August 2013 LEDRFLAG and subsequently ILIMITFLAG will be set and LED current will be reduced to: 68 mA * (1- 0.25) = 51 mA This is within the safe operating area of the LED to be driven. In the case of a safe operating area test fail, the LED current will be reduced by 25% to give a maximum limit of up to 39.75 mA Should this LED current drive be insufficient during operation it may be calibrated until a target is met. The algorithm used to control the calibration of the LE D DAC current is user specific but it has access to the LED Flags, ILIMITFLAG and the LED current DAC register values. A binary incremental or binary weighted search ma y be used to increase the LED DAC current to the absolute current maximum limit. An indication of how to perform a binary incremental search is mentioned below. A SUGGESTED BINARY INCREMENTAL SEARCH IMPLEMENTED BY THE USER When the LED maximum current is detected, the LE D current can be trimmed back by either 12.5% or 25%, depending on ILIMITDEC. At 25% this will guarantee the LED current is below the LED DAC absolute maximum current limit. The LED current can then be incremented by an LSB of the LED current register. The LED current will continue to be incremented until ILIMITFLAG is again set. Figure 24 shows this process graphically. The LSB of the current is 0.4% of the full LED cu rrent DAC full scale range. As a result the LED current DAC may trim the LED current drive to within +/-0.2% of target. If the coarse LED current limit is 35mA to 53mA when LEDIMAX=1, this means the trip point accuracy will be:- Min. Limit – ((Min. Full Scale Range/255)/2) >> Max. Limit + ((Max. Full Scale Range/255)/2) In this case LEDRNG = 11 so Min. FSR is 50 and Max FSR is 68. LEDIMAX=1 so Min. Limit is 35 and Max. Limit is 53. Therefore:- During the binary incremental search, the LE D current will continue to be incremented until ILIMITFLAG is again set. At this point it is desir able to disable the reduction of the LED current. Different options to disable the reduction of current can be achieved through the register bit ILIMITEN. Refer to Table 4 in the Blank Period Section.

w PD, Rev 4.7, August 2013 Figure 24 An Example of How LED Current Limiting Can Be Operated LED CONTROL WORKED EXAMPLE As an example of configuring the LED current driv e control, consider the scan of a US Letter page size with the AFE configured to sample at 12 MHz MCLK and 3:1 MCLK:VSMP ratio. The aim is to calculate LEDPWMPER for the given MCLK frequency to give a PWM frequency of typically 2.5kHz. Then the number of PWM cycles per line scan is calculated to check that there is sufficient imaging time and coarse trim range. Assumptions MCLK:VSMP ratio = 3:1 MCLK frequency = 12MHz VSMP frequency = 4MHz LED Enable counter range = 2^7 (maximum) PWM clock periods LED PWM counter range = 2^12 (maximum) PWM clock periods Colour Scan Mode Target blanking period = 25uSec Desired PWM frequency = 2.5kHz Colour sequence = red, green, blue Sensor scan width = 9 inches Scan resolution = 2400 dpi

w PD, Rev 4.7, August 2013 1. The number of MCLK cycles per PWM period is given by: LEDPWMPER = 12 MHz / 2.5kHz = 4800. This exceeds the maximum 4095 so CLKDIV must be set to ‘0001’. Therefore 12Mhz / 2 = 6MHz Therefore LEDPWMPER = 6MHz / 2.5kHz = 2400 2. The number of MCLK cycles necessa ry for blanking period is given by: BLANK *0.8)*MCLK = INITBLANKdec. (25uSec * 0.8)*12MHz = 240 The binary equivalent of INITBLANK dec should be calculated and, making sure the last 3 LSBs are zero, should be set in the register. 240 = 0 1111 0000bin. Therefore the 6 MSBs to be set to the register INITBLANK are :- 011110bin By default INITBLANK is set to zero which sets the initial blank period to equal the PWM period/0.8 3. The number of MCLK cycles per line scan is given by: MCLK cycles per line scan = 9inch * 2400dpi * 3 = 64800 4. The number of MCLK cycles av ailable for imaging is given by: MCLK cycles per line scan - MCLK cycles per line scan = 64800 – 240 = 64560 5. The Number of PWM cycles per line scan is given by: MCLK cycles per PWM period LEDPWMPER = 2400 Number of PWM cycles per line scan = 64560 / 2400 = 26.9 The nearest integral number of PWM cycles per line scan then 26. The illumination period should be check ed. Assuming 26 PWM cycles per line, with the first PWM cycle reserved for the current DAC setup and transition, and an 80% duty cycle Period of illumination = 26 * 0.8 / 2.5kHz = 8.32 msec Period of illumination coarse trim LSB = 1 / 2.5kHz = 400 usec Period of illumination fine trim LSB = 1 / 6MHz = 166.66 nsec If the period of illumination per line scan is too s hort, the imaging period is limiting the scan period. The period between TG pulses should be increased and step 2 should be repeated to calculate the number of MCLK cycles per line scan. Set values for LEDPWMDCR / G / B as appropriate. Using the number of PWM cycles per line scan fo r reference, set values for LEDENSTART and LEDENSTOPR / G / B as appropriate. Set values for LEDIDACR / G / B as appropriate. A red, green, blue, red, green, blue colour transit ion is required, so set STATE0 = 00 for red, STATE1 = 01 for green and STATE2 = 10 for blue. Set STATERST = 10

w PD, Rev 4.7, August 2013 REFERENCES The ADC reference voltages are derived from an in ternal band-gap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS when this is configured as an output. POWER SUPPLY The WM8255 operates from either a 5.75V (AVDD1) supply or a 3.3V (AVDD2). POWER MANAGEMENT The WM8255 has a power management system to detect the presence and correct level of the power supplies AVDD1, AVDD2 and DVDD. With reference to Figure 28, the WM8255 is parti tioned into three power domains, a digital domain powered by DVDD, LED current drive domain powered by AVDD1 and AFE domain powered by AVDD2. In the digital domain, until DVDD has reac hed the correct level, a Power On Reset (POR) shall disable the WM8255. The LDO voltage regul ator and AFE voltage references shall be enabled and allowed to power up as AVDD1 is applied when the POR released. With AVDD1, AVDD2 and AFE voltage references at the correct level a system enable is set and WM8255 shall power up in a controlled manner. Figure 28 Power Management System Power management for the device is performed via t he Control Interface. The device can be powered on or off completely by setting the EN bit low. All the internal registers maintain their prev iously programmed value in power down mode and the Control Interface inputs remain active.

w PD, Rev 4.7, August 2013 POWER ON SEQUENCE In order to guarantee correct operation, the digital supply (DVDD) and analogue supply (AVDD1) should be applied as specified in Figure 29 and Table 5. If it is not possible to apply the recommended power up sequence, the user must wait until both DVDD and AVDD1 have risen fully, then disable and enable the WM8255 by software write to EN (R0, b0). It is then possible to apply further register writes and operate the WM8255 correctly. When powering down the WM8255, no specific power down sequence is required. REDUCED POWER With DVDD applied, AVDD1 may be powered down with no loss to digital configuration data. This will reduce the power consumption of the device whilst still keeping register settings and configurations. Figure 29 Power On Sequence Test Conditions AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DVDD set up time to AVDD1 rising edge tPSU 100 μs Table 5 Power On Timing OPERATING MODES Table 6 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE TIMING REQUIREMENTS REGISTER CONTENTS WITH CDS REGISTER

CONTENTS

1 Monochrome/

Yes 6 MSPS MCLK max = 24MHz MCLK:VSMP ratio is 2n:1 n  2 SetReg1: 0F(hex) SetReg1: 0D(hex)

2 Fast Monochrome/

Yes 8 MSPS MCLK max = 24MHz MCLK:VSMP ratio is 3:1 Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to Mode 1

3 Maximum speed

No 12 MSPS MCLK max = 24MHz MCLK:VSMP ratio is 2:1 CDS not possible SetReg1: 4D(hex) Table 6 WM8255 Operating Modes *Note: Maximum sample rate depends on the MCLK to VSMP ratio. A higher ratio will mean a lower maximum sample rate for a specified MCLK speed.

w PD, Rev 4.7, August 2013 OPERATING MODE TIMING DIAGRAMS The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 6. The diagrams are identical for both CDS and non-CDS operation. MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)

16.5 MCLK PERIODS

A B C DA B C DA B C DA B C D A B C DA B CA B CA B C D A B C DA B CA B CA B C A B C DA B C DA B C DA B C DA B C D D D DA B C D D D D D Figure 30 Mode 1 Operation ABC ABC ABCD ABC ABC ABC ABC ABC D ABC ABCD ABCD ABC ABC C ABC ABC C ABC ABC C ABC ABC C MCLK VSMP (DEL = 00) VINP OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)

24.5 MCLK PERIODS

OP[3:0] RESET SAMPLE VIDEO SAMPLE RS VS RS VS RS VS RS VS RS VS RS VS D D D DDD ABC ABC ABCD D D D ABCD D ABCDD D D D D D D D D D D D Figure 31 Mode 2 Operation

w PD, Rev 4.7, August 2013 MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) A B C D A B C D A B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C D A B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C D A B C D A B C D A B C D A B C D A B C DA B C D A B C D Figure 32 Mode 3 Operation DEVICE REVISION CODES To read the device revision code the test registers must be accessed. Table 7 defines the method: DEVICE REVISION CODE Address Data Comment 0x01 0xA3 This will put the part into test configuration mode. Any address will now point to the extended page reconfiguration register 0x27 Read Read all eight bits of this r egister. Bit[7:1] contain the revision code information, Bit[0] should be ignored 0x01 0x23 This will take the part back into normal operating mode. Table 7 Revision Code Note: For Rev C devices it will read ‘01’

w PD, Rev 4.7, August 2013 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8255. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. Address <a5:a0> Description Def (hex) RW BIT b7 b6 b5 b4 b3 b2 b1 b0

000001 Setup Reg 1 03 RW TREG_OPEN MODE3 PGAFS[1] PGAFS[ 0] VSMPDET 0 CDS EN

000010 Setup Reg 2 00 RW DEL[1] DEL[0] 0 RLCINT VRLCEXT INVOP 2BITOP POSNEG

000011 Setup Reg 3 13 RW INTM[1] INTM[0] CDSREF [1 ] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0]

000100 Software

000101 Setup Reg 4 00 RW 0 LEDIMAX 0 0 0 VDEL[2] VDEL[1] VDEL[0]

000110 Setup Reg 5 20 RW LEDIDACR

[7] LEDIDACR [6] LEDIDACR [5] LEDIDACR [4] LEDIDACR [3] LEDIDACR [2] LEDIDACR [1] LEDIDACR [0]

000111 Setup Reg 6 20 RW LEDIDACG

[7] LEDIDACG [6] LEDIDACG [5] LEDIDACG [4] LEDIDACG [3] LEDIDAC [2] LEDIDACG [1] LEDIDACG [0]

001000 Setup Reg 7 20 RW LEDIDACB

[7] LEDIDACB [6] LEDIDACB [5] LEDIDACB [4] LEDIDACB [3] LEDIDACB [2] LEDIDACB [1] LEDIDACB [0]

001001 Setup Reg 8 C0 RW STATE_

RST[1] STATE_ RST[0]

0 LEDIRNGG

[1] LEDIRNGG [0]

0 LEDIRNGR

[1] LEDIRNGR [0]

001010 Setup Reg 9 00 RW ILIMIT EN [1] ILIMIT EN[0] MONOMODE MONOTG REQLEDST 0 LEDIRNGB

[1] LEDIRNGB [0] 001011 Setup Reg 10 E4 RW STATE3 [1] STAT E3 [0] STATE2 [1] STATE2 [0] STATE1 [1] STATE1 [0] STATE0 [1] STATE0 [0]

001100 Setup Reg 11 00 RW LEDPWM

PER[7] LEDPWM PER[6] LEDPWM PER[5] LEDPWM PER[4] LEDPWM PER[3] LEDPWM PER[2] LEDPWM PER[1] LEDPWM PER[0]

001101 Setup Reg 12 00 RW CLKDIV[3] CLKD IV[2] CLKDIV[1] CL KDIV[0] LEDPWM

PER[11] LEDPWM PER[10] LEDPWM PER[9] LEDPWM PER[8]

001110 Setup Reg 13 00 RW LEDPWM

DCR[7] LEDPWM DCR[6] LEDPWM DCR[5] LEDPWM DCR[4] LEDPWM DCR[3] LEDPWM DCR[2] LEDPWM DCR[1] LEDPWM DCR[0]

001111 Setup Reg 14 00 RW LEDPWM

DCG[7] LEDPWM DCG[6] LEDPWM DCG[5] LEDPWM DCG[4] LEDPWM DCG[3] LEDPWM DCG[2] LEDPWM DCG[1] LEDPWM DCG[0]

100000 DAC Value

(Red)

80 RW DACR[7] DACR[6] DACR[5] DACR[4] DACR[3] DACR[2] DACR[1] DACR[0]

100001 DAC Value

(Green)

80 RW DACG[7] DACG[6] DACG[5] DACG[4 ] DACG[3] DACG[2] DACG[1] DACG[0]

100010 DAC Value

(Blue)

80 RW DACB[7] DACB[6] DACB[5] DACB[4 ] DACB[3] DACB[2] DACB[1] DACB[0]

100011 DAC Value

(RGB)

80 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

100100 Setup Reg 15 00 RW LEDPWM

DCB[7] LEDPWM DCB[6] LEDPWM DCB[5] LEDPWM DCB[4] LEDPWM DCB[3] LEDPWM DCB[2] LEDPWM DCB[1] LEDPWM DCB[0]

100101 Setup Reg 16 11 RW LEDPWM

DCG[11] LEDPWM DCG[10] LEDPWM DCG[9] LEDPWM DCG[8] LEDPWM DCR[11] LEDPWM DCR[10] LEDPWM DCR[9] LEDPWM DCR[8]

100110 Setup Reg 17 01 RW LEDSTART

[3] LEDSTART [2] LEDSTART [1] LEDSTART [0] LEDPWM DCB[11] LEDPWM DCB[10] LEDPWM DCB[9] LEDPWM DCB[8]

100111 Setup Reg 18 10 RW LEDSTART

[4] LEDSTOPR [6] LEDSTOPR [5] LEDSTOPR [4] LEDSTOPR [3] LEDSTOPR [2] LEDSTOPR [1] LEDSTOPR [0]

101000 PGA Gain

(Red)

00 RW PGAR[7] PGAR[6] PG AR[5] PGAR[4] PGAR[3] PGAR[2] PGAR[1] PGAR[0]

101001 PGA Gain

(Green)

00 RW PGAG[7] PGAG[6] PGAG[5] PGAG[4 ] PGAG[3] PGAG[2] PGAG[1] PGAG[0]

101010 PGA Gain

(Blue)

00 RW PGAB[7] PGAB[6] PG AB[5] PGAB[4] PGAB[3] PG AB[2] PGAB[1] PGAB[0]

w PD, Rev 4.7, August 2013 Address <a5:a0> Description Def (hex) RW BIT b7 b6 b5 b4 b3 b2 b1 b0

101011 PGA Gain

(RGB)

00 W PGA[7] PGA[6] PGA[ 5] PGA[4] PGA[3] PG A[2] PGA[1] PGA[0]

101100 Setup Reg 19 10 RW LEDSTART

[5] LEDSTOPG [6] LEDSTOPG [5] LEDSTOPG [4] LEDSTOPG [3] LEDSTOPG [2] LEDSTOPG [1] LEDSTOPG [0]

101101 Setup Reg 20 10 RW LEDSTART

[6] LEDSTOPB [6] LEDSTOPB [5] LEDSTOPB [4] LEDSTOPB [3] LEDSTOPB [2] LEDSTOPB [1] LEDSTOPB [0]

101110 Setup Reg 21 00 RW ILIMITFLAG ILIMITDEC INITBLANK

[8] INITBLANK [7] INITBLANK [6] INITBLANK [5] INITBLANK [4] INITBLANK [3]

101111 LED Software

00 R LEDRFLAG LEDGFLAG LEDBFLAG

<a5:a0> Description Def (hex) RW BIT b7 b6 b5 b4 b3 b2 b1 b0

100100 LED Control 0 0 LED_TEST

CTRL[3] LED_TEST CTRL[2] LED_TEST CTRL[1] LED_TEST CTRL[0] 0 0 Number REV_NUM [6] REV_NUM [5] REV_NUM [4] REV_NUM [3] REV_NUM [2] REV_NUM [1] REV_NUM [0] X Table 9 Extended Page Registers Note: To access the Extended Page Registers the TREG_OPEN bit must be set to ‘1’ in Setup Reg 1. This bit must then be set to ‘0’ once access is complete. Please refer to Pages 23 and 38 for details on when to access these registers. REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 8. REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Setup Register 1 0 EN 1 0 = complete power down, 1 = fully active.

1 CDS 1 Select correlated double sampling mode: 0 = single ended mode,

1 = CDS mode.

2 Reserved 0 Must be set to zero

3 VSMPDET 0 0 = Normal operation, signal on VSMP input pin is applied directly to

Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronization pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 5:4 PGAFS[1:0] 00 Offsets PGA output to optimize the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) 6 MODE3 0 Required when operating in MODE3: 0 = other modes, 1 = MODE3.

7 TREG_OPEN 0 Enables the extended page register access

w PD, Rev 4.7, August 2013 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Setup Register 2 0 POSNEG 0 When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 27 for further details. 1 2BITOP 0 Changes the digital output from 4 bit muxed to 2 bit muxed output. 2 INVOP 0 Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data.

3 VRLCEXT 0 When set powers down the RLCDAC, changing its output to Hi-Z,

allowing VRLC/VBIAS to be externally driven. 4 RLCINT 0 This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. 5 Reserved 0 Must be set to zero. 7:6 DEL[1:0] 00 Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC

clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods Setup Register 3 3:0 RLCV[3:0] 0011 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. 5:4 CDSREF[1:0] 01 CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods 7:6 INTM[1:0] 00 Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 1 for details. Software Reset Any write to Software Reset causes all cells (including LED) to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. Setup Register 4 2:0 VDEL[2:0] 000 When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 27, Internal VSMP Pulses Generated for details. 5:3 Reserved 000 Must be set to zero

6 LEDIMAX 0 Sets the maximum current limit to one of two ranges (see electrical

characteristics section).

7 Reserved 0 Must be set to zero

7:0 LEDIDACR [7:0] 00100000 Fine LED current during imaging for Red LED Setup Register 6 7:0 LEDIDACG [7:0] 00100000 Fine LED current during imaging for Green LED Setup Register 7 7:0 LEDIDACB [7:0] 00100000 Fine LED current during imaging for Blue LED Setup Register 8 1:0 LEDIRNGR [1:0] 00 Coarse LED current range during imaging for Red LED

w PD, Rev 4.7, August 2013 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION 4:3 LEDIRNGG [1:0] 00 Coarse LED current range during imaging for Green LED

5 Reserved 0 Must be set to zero

7:6 STATERST [1:0] 11 State reset. Sets the number of states to be used. 00 = State_0 only 01 = State_0 to State_1 10 = State_0 to State_2 11 = State_0 to State_3 Setup Register 9 1:0 LEDIRNGB [1:0] 00 Coarse LED current range during imaging for Blue LED

3 REQLEDST 0 If LEDSTART is to be used this register must be set high

4 MONOTG 0 When MONOMODE=0 this register has no effect. When set high allows the TG pin to restart the colour sequence when in mono mode.

5 MONOMODE 0 When set, puts the LED control in to monochrome (composite mode)

7:6 ILIMITEN[1:0] 00 Specifies the mode of operation of current limiting of the LED DAC. See Table 4 for details. Setup Register 10 1:0 STATE0[1:0] 00 Sets the State 0 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 3:2 STATE1[1:0] 01 Sets the State 1 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 5:4 STATE2[1:0] 10 Sets the State 2 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 7:6 STATE3[1:0] 11 Sets the State 3 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 Setup Register 11 7:0 LEDPWMPER [7:0] (LSBs) 00000000 Sets the LSBs of the maximum value for the LED PWM period. [7:0] Setup Register 12 3:0 LEDPWMPER [11:8] (MSBs) 0000 Sets the MSBs of the maximum value for the LED PWM period. [11:8] 7:4 CLKDIV [3:0] 0000 Sets the division of MCLK applied to the PWM counter. Setup Register 13 7:0 LEDPWMDCR [7:0] (LSBs) 00000000 Sets the LSBs of the LED PWM Duty Cycle for the RED LED. [7:0] Setup Register 14 7:0 LEDPWMDCG [7:0] (LSBs) 00000000 Sets the LSBs of the LED PWM Duty Cycle for the GREEN LED. [7:0] Offset DAC (Red) 7:0 DACR[7:0] 10000000 Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Green) 7:0 DACG[7:0] 10000000 Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Blue) 7:0 DACB[7:0] 10000000 Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (RGB) 7:0 DAC[7:0] A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value. Setup Register 15 7:0 LEDPWMDCB [7:0] (LSBs) 00000000 Sets the LSBs of the LED PWM Duty Cycle for the BLUE LED. [7:0] Setup Register 16 3:0 LEDPWMDCR [11:8] (MSBs) 0001 Sets the MSBs of the LED PWM Duty Cycle for the RED LED. [11:8] The LEDPWMDCR must not be set to zero (MSB and LSB both zero) 7:4 LEDPWMDCG [11:8] (MSBs) 0001 Sets the MSBs of the LED PWM Duty Cycle for the GREEN LED. [11:8] The LEDPWMDCG must not be set to zero (MSB and LSB both zero) Set up Register 17 3:0 LEDPWMDCB [11:8] (MSBs) 0001 Sets the MSBs of the LED PWM Duty Cycle for the BLUE LED. [11:8] The LEDPWMDCB must not be set to zero (MSB and LSB both zero) 7:4 LEDSTART [3:0] 0000 Sets the LSBs of the 7 bit LEDSTART time. [3:0]

w PD, Rev 4.7, August 2013 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Setup Register 18 6:0 LEDSTOPR [6:0] 0010000 Sets the LED stop time for the RED LED. 7 LEDSTART [4] 0 Sets the next significant bit of the 7 bit LEDSTART time. [4] PGA gain (Red) 7:0 PGAR[7:0] 0 Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Green) 7:0 PGAG[7:0] 0 Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Blue) 7:0 PGAB[7:0] 0 Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (RGB) 7:0 PGA[7:0] A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value Setup Register 19 6:0 LEDSTOPG [6:0] 0010000 Sets the LED stop time for the GREEN LED. 7 LEDSTART [5] 0 Sets the next significant bit of the 7 bit LEDSTART time. [5] Setup Register 20 6:0 LEDSTOPB [6:0] 0010000 Sets the LED stop time for the BLUE LED. 7 LEDSTART [6] 0 Sets the MSB of the 7 bit LEDSTART time. [6] Setup Register 21 5:0 INITBLANK [8:3] 000000 Sets the 6 MSBs of the 9 bit register to adjust the initial blank period following a sequence transition. The 3 LSBs are fixed to zero. Must be set so the initial blank period is 25s. See Initial Blank Period on page 25 for details. 6 ILIMITDEC 0 When ILIMITEN = 0 this register has no effect. When the maximum LED current limit is exceeded and the ILIMITFLAG is set, the current is reduced to a safe level to protect the LED. 0 = 12.5% reduction in current 1 = 25% reduction in current 7 ILIMITFLAG 0 When ILIMITEN=00 this read register will not be active. Read only register. Set high by the device when the current limit has been exceeded. LED Reset Resets all LED timing control to its reset state at register write LED RGB FLAGS

0 LEDBFLAG 0 Set high by the device when the current limit has been exceeded for the

Blue LED. May be read.

1 LEDGFLAG 0 Set high by the device when the current limit has been exceeded for the

Green LED. May be read.

2 LEDRFLAG 0 Set high by the device when the current limit has been exceeded for the

Red LED. May be read. Table 10 Register Control Bits

w PD, Rev 4.7, August 2013 EXTENDED PAGE REGISTER MAP DESCRIPTION REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION LED Control 1:0 Reserved 0 Must be set to zero 5:2 LED_TESTCTRL [3:0]

0000 General LED test modes:

LED_TESTCTRL[1:0] = Mode override. The IDAC can be forced into one of three modes: 01 = IDAC_LOAD: IDAC is loaded with new current value (based on the current state), and CHANGE_SETUP & IDAC_DISABLE are high. 10 = IDAC_CHECK: RGB switch is enabled (based on current state) and IDAC_CALIBRATE is set high. Current setting will not change unless test load is enabled. 11 = IDAC_ON: IDAC is fully out of reset. PWM_LEDON will still be driven by the counters unless the test override is used. Current setting will not change unless test load is enabled. LED_TESTCTRL[2] = Test update. The current setting is continuously reloaded (from Red register when machine in reset). LED_TESTCTRL[3] = PWM test enable. PWM_LEDON is now driven using the LEDSTART pin. 7:6 Reserved 00 Must be set to zero Revision Number

0 Reserved X This bit should be ignored

7:1 REV_NUM [6:0] Revision Number of device Table 11 Extended Page Register Bits

w PD, Rev 4.7, August 2013 RECOMMENDED EXTERNAL COMPONENTS Figure 33 External Components Diagram COMPONENT REFERENCE SUGGESTED VALUE R1 13k7ohm Resistor used for LED current maximum limit accuracy C1 100nF De-coupling for AVDD1 C2 100nF De-coupling for AVDD2 C3 100nF De-coupling for DVDD C4 10nF High frequency de-coupling between VRT and VRB C5 1uF Low frequency de-coupling between VRT and VRB C6 100nF De-coupling for VRB C7 100nF De-coupling for VRX C8 100nF De-coupling for VRT C9 100nF De-coupling for VRLC C10 10uF Reservoir capacitor for DVDD C11 10uF Reservoir capacitor for AVDD1 C12 10uF Reservoir capacitor for AVDD2 Table 12 External Components Descriptions

w PD, Rev 4.7, August 2013 PACKAGE DIMENSIONS DM090.AFL: 28 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.85 mm BODY, 0.40 mm LEAD PITCH INDEX AREA (D/2 X E/2) TOP VIEW Caaa2 X b L Caaa2 X D E e PIN 1 C A A1C (A3) SEATING PLANE NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION. bbb Cccc 14 8 BOTTOM VIEW VIEW M - M Cddd M A B Ceee A B Ceee A B B A M M Symbols Dimensions (mm) MIN NOM MAX NOTE A b D E e L 0.85 0.250.200.15

4.00 BSC

2.802.702.60

0.4 BSC

2.70 2.802.60 0.30 0.35 0.40 0 0.035 0.05

0.203 REF

JEDEC, MO-220 VGGE Tolerances of Form and Position aaa bbb ccc 0.10 0.08 0.10 REF 0.8 0.9 A2 - 0.65 0.67 ddd eee 0.10 0.10

w PD, Rev 4.7, August 2013 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at t he date of shipment. Wolfson reserves the right to make changes to its products and s pecifications or to discontinue any produc t or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. Wolfson is not liable fo r applications assistance or customer product design. The customer is solely responsible for its se lection and use of Wolfson products . Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. Any prov ision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House

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w PD, Rev 4.7, August 2013

REVISION HISTORY

DATE REV ORIGINATOR CHANGES 04/04/12 4.6 JMacD Order codes changed from WM8255SEFL and WM8255SEFL/R to WM8255CSEFL/R and WM8255 CSEFL/R to reflect change to copper wire bonding. 19/08/13 4.7 JMacD Order codes WM8255CSEFL and WM8255CSEFL/R removed. 19/08/13 4.7 JMacD Package diagram DM109A removed.