WM72016 RAMTRON | Alldatasheet
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This is a product that has fixed target specifications but are Ramtron International Corporation subject to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Rev. 1.4 May 2011 Page 1 of 32 WM72016 16Kbit Secure F-RAM Memory with Gen-2 RFID Access & Serial Port Direct Memory Access
DESCRIPTION
The WM72016 is a RFID transponder IC with nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory, or F -RAM, is nonvolatile and performs reads and writes like a RAM. It provide s reliable data retention for 20 years while eliminating the complexities, ov erhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike EEPROM‟s, the WM72016 write operations are zero power – there is no power or speed premium paid for executing writes into the WM72016 as compared to read power and speed. Operation of the memory is fully symmetric: it has an equivalent read and write range. The WM72016‟s RFID interface is compatible with the EPC Class -1 Generation -2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.2.0 Specification for RFID Air Interface. The WM72016 is a two chip configurat ion offered in various forms: standard IC package or wafers. All specifications discussed here in are applicable to the combined chipset operation. Figure 1. System Block Diagram
FEATURES
16 Kbit Ferroelectric Nonvolatile RAM
Organized as 1024 x 16 bits Very High Read/Write Endurance (> 1014) 20-Year Data Retention Gamma Stability Demonstrated to > 30 kGy Symmetric Read/Write Operation Advanced High-Reliability Ferroelectric Process Interface and Security Features EPC Class 1 Gen2 ( ISO18000-6C) RFID Compatible Interface (revision 1.2.0) 192-Bit Memory: 96 -Bit Electronic Product Code™ (EPC), 32 -Bit Access P assword, 32 -Bit KILL Password, 64-Bit TID Memory (Factory Programmed and Locked) Inventory, Read, Write and Erase features Kill Command Block Permalock Command Access Command UHF carrier frequencies from 860 MHz to 960 MHz ISM band, ASK demodulation Tag-to-reader link frequencies up to 640Kbps Reader-to-tag asymptotical transmission rates up to 128Kbps Supports FM0 and MMS data encoding formats Serial Port Interface Custom Features Stored Address Pointer to Improve Data Write Speed Stored Address Pointer Lock Block Write Command Variable USER memory block size support Interrupt Generation Ultra Low Power Operation Memory Read/Write Sensitivity: < -6 dBm (typ.) Industry Standard Configurations Industrial Temperature -40 C to +85 C Bumped Wafers 8-pin UDFN WM72016 RFID Tag with F-RAM RFID Reader (Class-1 Gen-2)
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 2 of 32 PIN CONFIGURATION (UDFN PACKAGE) Top View (PCB Layout) Ser_clk Ser_dat1 Ser_dat0 Ser_CS ANT- ANT+ Vddr Vddraw 3.0 mm × 3.0 mm body, 0.65 mm pad pitch PIN DESCRIPTION Pin Name Pin Number Type Description ANT+, ANT- 7, 8 Input RFID Antenna. Connect to external RFID antenna terminal s. Connect ANT - to ex ternal RFID antenna terminal, a lso acts as ground. Ser_clk 1 Input Serial interface clock Ser_dat1, Ser_dat0 2, 3 I/O Serial interface bi-directional data Ser_CS 4 I/O Serial interface bi-directional chip select/interrupt Vddraw 5 PWR Power supply input pin. DC supply (2.1V to 3.0V) Vddr 6 PWR Power supply output pin. This supply is int ernally generated via the RF field . The Vddr and Vddraw pins are tied together for most applications. Contact the factory for other applications such as battery assisted systems.
applications of an RFID solution. memory and applied prior to enabling data transmission in or out of memory. and symmetrical characteristics. multiplied up within the Schottky array and then regulated to supply power to on-chip resources. processes commands to enable access in and out of F-RAM memory. Figure 2. Block Diagram
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 4 of 32 MEMORY MAP WM72016‟s memory is partitioned according to the logical and physical mapping shown in the table below. Table 1: Memory Map DSPI Address Gen-2 Memory Bank Gen-2 Address Word Pointer (EBV8) Description 0x000 RESERVED 0x000 0x00 Kill Password[31:16] 0x001 RESERVED 0x001 0x01 Kill Password[15:0] 0x002 RESERVED 0x002 0x02 Access Password[31:16] 0x003 RESERVED 0x003 0x03 Access Password[15:0] 0x004 EPC 0x000 0x00 CRC 0x005 EPC 0x001 0x01 PC 0x006 EPC 0x002 0x02 EPC - Word 0 (MSW) 0x007 EPC 0x003 0x03 EPC - Word 1 0x008 EPC 0x004 0x04 EPC - Word 2 0x009 EPC 0x005 0x05 EPC - Word 3 0x00A EPC 0x006 0x06 EPC - Word 4 0x00B EPC 0x007 0x07 EPC - Word 5 (LSW) 0x00C EPC 0x008 0x08 EPC - read memory 0x00D EPC 0x009 0x09 EPC - read memory 0x00E SERVICE 0x00A 0x0A RESERVED 0x00F SERVICE 0x00B 0x0B RESERVED 0x010 TID 0x000 0x00 TID - Word 0: xE201 0x011 TID 0x001 0x01 TID - Word 1: x6216 0x012 TID 0x002 0x02 TID - Word 2: Serial #1 0x013 TID 0x003 0x03 TID - Word 3: Serial #2 0x014 USER 0x000 0x00 RESERVED 0x015 USER 0x001 0x01 RFU 0x016 USER 0x002 0x02 Control/Status Register 0x017 USER 0x003 0x03 Working Stored Address Register 0x018 USER 0x004 0x04 0x019 USER 0x005 0x05 0x01A USER 0x006 0x06 USER Memory - Start 0x01B USER 0x007 0x07 0x0FE USER 0x0EA 0x816A 0x0FF USER 0x0EB 0x816B 0x100 USER 0x0EC 0x816C 0x101 USER 0x0ED 0x816D … … … … 0x1FE USER 0x1EA 0x836A 0x1FF USER 0x1EB 0x836B 0x200 USER 0x1EC 0x836C 0x201 USER 0x1ED 0x836D … … … … 0x3BA USER 0x3A6 0x8726 0x3BB USER 0x3A7 0x8727 16k Memory: END (BLK_SIZE = 1 word/block) 0x3BC USER 0x3A8 0x8728 0x3BD USER 0x3A9 0x8729 0x3BE USER 0x3AA 0x872A
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 5 of 32 DSPI Address Gen-2 Memory Bank Gen-2 Address Word Pointer (EBV8) Description … … … … 0x3DA USER 0x3C6 0x8746 0x3DB USER 0x3C7 0x8747 16k Memory: END (BLK_SIZE = 2 words/block) 0x3DC USER 0x3C8 0x8748 0x3DD USER 0x3C9 0x8749 0x3DE USER 0x3CA 0x874A … … … … 0x3EA USER 0x3D6 0x8756 0x3EB USER 0x3D7 0x8757 16k Memory: END (BLK_SIZE = 4 words/block) 0x3EC USER 0x3D8 0x8758 0x3ED USER 0x3D9 0x8759 0x3EE USER 0x3DA 0x875A … … … … 0x3F3 USER 0x3DF 0x875F 16k Memory: END (BLK_SIZE = 8 words/block) 0x3F4 USER 0x3E0 0x8760 0x3F5 USER 0x3E1 0x8761 0x3F6 USER 0x3E2 0x8762 0x3F7 USER 0x3E3 0x8763 16k Memory: END (BLK_SIZE = 16 words/block) 0x3F8 USER 0x3E4 0x8764 0x3F9 USER 0x3E5 0x8765 16k Memory: END (BLK_SIZE = 32 words/block) 0x3FA USER 0x3E6 0x8766 0x3FB USER 0x3E7 0x8767 (BLK_SIZE > 32 words/block) 0x3FC USER 0x3E8 0x8768 RESERVED 0x3FD USER 0x3E9 0x8769 RESERVED 0x3FE USER 0x3EA 0x876A RESERVED 0x3FF USER 0x3EB 0x876B RESERVED NOTE: When accessing the memory through the DSPI serial port, c are must be taken to ensure that reserved memory required to store critical parameters for the operation of the device is not altered. GEN2 WM72016 MEMORY BANKS The RFID memory banks reside in Ramtron‟s non -volatile F-RAM memory. F -RAM brings many benefits to the WM72016. The first benefit is the size of the memory itself – 16k-bit, most of which is available in the USER memory bank. F-RAM‟s impact on the Gen2 protocol is most dramatically seen when writing to WM72016 memory. Unlike EEPROM memory, no charge pump or memory soak time is required to write to WM72016 memory resulting in zero time and zero power penalties. The write cycle is completed immediately, allowing an interrogator to continue writing additional data to memory with no time penalty incurred due to the memory itself. A comparison between F-RAM and EEPROM memories is shown in Figure 3. The figure shows the minimum number of Gen2 instructions required to perform a SELECT, INVENTORY, and ACCESS sequence of commands to write a data word to memory. The same interrogator command sequence is trans mitted to the WM72016 and a n EEPROM-based RFID. The effect of the EEPROM time penalty is shown within the context of the protocol.
Figure 3. Gen2 Memory Write Cycle Comparison: F-RAM vs. EEPROM Memories serial port will continue to function normally. effect on the functionality of the DSPI serial port. are completely programmable. The Protocol Control field is shown in Figure 4.
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 8 of 32 USER Memory Bank: The USER memory bank comprises two special-function control words, factory-reserved words, and up to 993 available memory locations. Refer to Table 1 for detail on the WM72016 memory structure. The USER memory bank may be completely locked through the LOCK command. WM72016 also supports the BLOCKPERMALOCK command providing the ability to lock contiguous words of USER memo ry, with word block sizes as small as a single word up to a maximum block size of 128 words. The USER memory bank ships from the factory completely unlocked.
At the bit-boundary of two consecutive logic 0s. baseband bit period by 2, 4, or 8 as shown in Figure 7, Figure 8, and Figure 9.
0 T 2T
Figure 6. FM0 Data Encoding Figure 7. MMS2 Data Encoding Figure 8. MMS4 Data Encoding Figure 9. MMS8 Data Encoding
non-volatile memory. The register is located at physical address 0x016 or USER memory address 0x002. writing the Control/Status register word if it is to remain unlocked. Figure 10. Control/Status Register 15 LOCK Memory locking of this register.
14 PERMALOCK 0
13 RFU Reserved for future use 0
12 RFU Reserved for future use 0
11 RFU Reserved for future use 0
10 RFU Reserved for future use 0
9 RFU Reserved for future use 0
8 RFU Reserved for future use 0
6 BLKSIZ[2] USER memory block size.
5 BLKSIZ[1] 1
4 BLKSIZ[0] 0
3 WRPSTAT Indicates if the Working Stored Address has wrapped.
0 Wrapping has not occurred
1 Wrapping has occurred at least once
2 WRPEN Enables wrapping of the Working Stored Address when it reaches the
0 DISABLE memory wrapping
1 AUTOLOCK Enable Automatic Locking of all user memory between the start of USER
memory and the Working Stored Address register.
0 Auto-lock DISABLED
1 Auto-lock ENABLED
0 AUTOINCR Enable the Working Stored Address word to Auto-Increment when
performing an unaddressed write cycle.
0 DISABLE auto-increment of stored address register
1 ENABLE auto-increment of stored address register
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 11 of 32 Upon power up, WM72016‟s control logic reads the control word out of memory and configures itself accordingly. User applications may ch ange the control word as needed providing the register has not been permanently locked. The Control/Status word may be read by the application at any time. Register Locking: The LOCK a nd PERMALOCK control bits are implemented in a similar manner as locking bits used for Gen2 memory bank locking with the exception that the lock control bits are incorporated into the register they are locking. As such, attention needs to be pla ced on how the contents of the Control/Status word are written when the register is not completely unlocked. Table 4: Control/Status Word Locking LOCK PERMA- LOCK 0 0 Register unlocked. All control bits, including the LOCK and PERMALOCK bits can be written to from the OPEN or SECURED states. 0 1 Register permanently unlocked. All control bits can be written from the OPEN or SECURED states. The LOCK and PERMALOCK bits must be set to logic values 0 and 1 respectively when writing the Control/Status word. 1 0 Register locked. All control bits can be written to only from the SECURED state. The register cannot be written to in the OPEN state. The LOCK and PERMALOCK bits must be set to logic values 1 and 0 respectively when writing the Control/Status word. 1 1 Register permanently locked. The register cannot be written in any circumstance. Block Write Enable : The BLKWREN control bit enables usage of the WM72016 custom command BLOCKWRITE. The BLKWREN parameter is internally updated during power -on WM72016 initialization. In the event the host application toggles the state of BLKWREN either through the Gen2 or serial interfaces, a WM72016 power cycle is required to reflect the change. Block Size: The 3 BLKSIZ[2:0] control bits adjust the USER memory block sizes as shown in Table 5. This provides a host application the ultimate flexibility in determining a balance between the USER memory requirements and the granularity of the number of USER memory words per block. The larger the granularity of the block size, the greater amount of available USER memory. The effect of the block size on available USER memory is shown in Table 1. The total number of USER memory words available as a funct ion of the block size is shown in Table 5 below. It is of utmost importance that the 3 -bit block size is not modified once set, which would otherwise result in corruption of block permalock status bits. Table 5: Available USER Memory Memory BLKSIZ Words/Block Free USER Memory (words) 16k 000 1 931 16k 001 2 963 16k 010 4 979 16k 011 8 987 16k 100 16 991 16k 101 32 993 16k 110 64 993 16k 111 128 993 Wrap Status: The WRPSTAT status bit is asserted to a logic one when the following conditions are true: (a) WRPEN=1, AUTOINCR=1 and AUTOLOCK=0, (b) The contents of the Working Stored Address register address the last USER memory location, and (c) An unaddressed WRITE command is received. The WRPSTAT can be cleared by the RFID interrogator by writing a logic zero to the WRPSTAT bit.
Wrap Enable: Asserting the WRPEN control bit to a logic one enables the USER memory wrapping feature. time. The automatic locking feature can only be used when AUTOINCR is asserted to a logic one. interrogator to determine where free USER memory is located and manipulating the memory pointer itself. register is asserted to a logic one and an unaddressed write command is received. Figure 11. Working Stored Address Register 15 LOCK Memory locking of this register.
10 INITEN When asserted to a logic ‘1’, sets the contents of the Initial Stored
9 through 0 written to this register using a Gen2 write instruction.
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 15 of 32 INITIAL STORED ADDRESS The Initial Stored Address is a preset address pointer that is loaded into the Working Stored Address when a memory wrap occurs after an unaddressed write command is executed. A memory wrap only occurs if the WRPEN control bit is asserted to a logic one and the AUTOLOCK control bi t is cleared to a logic zero in the Control/Status register and the Working Stored Address points to the last free memory location in the USER memory bank (last memory location depends on the set block size). The contents of the Initial Stored Address may be altered by setting the INITEN bit to a logic one through a Gen2 write cycle to the Working Stored Address register – refer to Table 6 above . When the INITEN control bit is set during a write cycle, the contents of the Working Stored Address register in USER memory 0x003 are not affected. Use of an Initial Stored Address register provides flexibility when using the wrap enable feature of WM72016. It may be set to the start of USER memory, allowing the entire USER memory bank to be utilized. Alternatively, it may be set to a higher memory address within the USER memory bank. This mechanism would provide for a static USER memory bank and a dynamic USER memory bank as shown in Figure 16 below. In the example shown in Figure 16, the Working Stored Address points to address 0x3F8 after having written user_log_data[ n] with an unaddressed write command. The subsequent unaddressed write cycle will increment (wrap) the Working Stored Address to the value defined by the Initial Stored Address, defined in this example as 0x000A, and write the value user_log_data[ n+1] to USER memory bank 0x00A, over -writing the previous data contents user_log_data[0]. In the example shown, four memory locations are used for static memory, or memory that will not be over-written when a wrap condition has occurred.
Figure 16. Initial Stored Address Example – Block Size = 128 words/block The Initial Stored Address is factory-initialized with a value of 0x0006 (USER memory bank address 0x006).
descriptions of these commands. Figure 17. Block Write Syntax BLOCKWRITE commands do not support the auto -increment feature used for UNADDR_WRITE commands.
- A DSPI read/write cycle is initiated by asserting CS high followed by 16 clock cycles. The host drives the
transfer on the D0 and D1 signals every 8 clock cycles. Figure 20. DSPI Cycle second set of 8 CLK cycles. The write cycle is terminated by clearing the CS signa l. the entire data word, after which it clears the CS to a logic zero to terminate the read cycle. The syntax of the instruction word is detailed in Table 8.
cycle. RW is cleared to logic „0‟ for write cycle. Opcode OP 14..10 Instruction opcode. Address A 9..0 MaxArias physical memory address. then tri-states the D0 and D1 signals while receiving data from MaxArias memory. The opcode (OP) parameter is a 5-bit value that can take on the following values shown in Table 9. NORM 11001 Normal read/write instruction. INTEND 11101 Interrupt end instruction.
- NORM – normal opcode for all read/write instructions, and
- INTEND – DSPI serial port control register opcode.
Table 1. In the event that memory arbitration is required between the RFID and serial interfaces, the RFID memory required to store critical parameters for the operation of the device are not altered. improving bandwidth requirements.
Figure 21. DSPI Write Cycle Detail secondary DSPI serial interface. is present and to take control of the memory with no possibility of interruption from the RFID interface. terminate the interrupt and return control back to the RFID interface. microcontroller drives two clock cycles on the DSPI CLK to acknowledge and clear the WM72016 interrupt. The WM72016 has been power-cycled. value that is not 0x1234, the interrupt mechanism will be disabled until the WM72016 has been power -cycled. use these memory locations as part of the standard USER memory bank.
Figure 22. Gen2 Interrupt Generation
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 23 of 32 SPECIFICATIONS WM72016‟s RFID Interface conforms to the Specification for RFID Air Interface EPC Class -1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.2.0. Options and Exceptions are noted here: State Persistence Requirements WM72016 features infinite state retention for S1, S2, S3, and SL State f lags. State flag S0 has no persistence and will always return to state „A‟ upon a power cycle. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol Description Ratings Notes VDDR, VDDRAW Power Supply Voltage with respect to ANT- -1.0V to +4.5V VIN Voltage on any serial port pin with respect to ANT- -1.0V to +4.5V and VIN < VDD+1.0V TSTG Storage Temperature -55C to + 125C TOP Operating Temperature -40oC to +85oC TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD (ANT+, ANT-) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 500V 1kV 50V VESD (All other pins) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 1.5kV 1.5kV 200V ME Memory Endurance: Read or Write or Erase 1x1014 1 RFexp RF Exposure +10dBm (800 ~ 1000 MHz) Package Moisture Sensitivity Level MSL-2 1. A degradation in memory endurance may occur for VDDR_EXT levels beyond the maximum specification. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 24 of 32 RF Operating Characteristics (TA = -40 C to + 85 C unless otherwise specified) Symbol Parameter Min Typ Max Units Notes SR Read Sensitivity -6 dBm SW Write Sensitivity -6 dBm Fr Max Sustainable Read Rate @ SR 640 Kbits/s 1 Fw Max Sustainable Write Rate @ Sw 160 Kbits/s 1 tST Power-on time 1.0 1.5 ms Change in Modulator Reflection Coefficient TBD TBD ZIN Input Impedance @ fIN=915MHz 63 – j199 Ohms 2 Note: 1. Actual read & write speeds are constrained by the EPC Class 1 Gen2 data communication standard. 2. ZIN is measured at SR/SW.
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 26 of 32 DSPI Serial Port DC Characteristics (TA = -40C to + 85C unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDDR, VDDRAW Power Supply Pins 2.1 2.5 3.0 V 1 IDD Power Supply Operating Current 15 25 µA VIL Input Low Voltage -0.3 0.3 VDDR V VIH Input High Voltage 0.7 VDDR VDDR+0.3 V VOL Output Low Voltage - 0.3 V VOH Output High Voltage VDDR - 0.3 - V NOTES: 1. Measured at the pin. DSPI Serial Port AC Characteristics (TA = -40C to + 85C, VDD = 2.1V to 3.0V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes tPSU VDDR Setup Time 1.5 - ms tPH VDDR Hold Time 0 - ns tCSD Chip Select Setup to Data Valid Time 10 - ns tCSH Chip Select Hold Time 10 - ns tSU Data Setup Time 10 tCLK/2 - 10 ns tHD Data Hold Time 10 - ns tDD Read Data Valid Time 600 ns tCLK Clock Period 1.6 - µs tWD Instruction to Data Word Timing tCLK/2 - tACK Interrupt Acknowledge Setup Time 10 - ns
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 27 of 32 USER MEMORY BLOCK SIZE DEFINITION x000 x001 x002 x003 x004 x005 x006 x007 x008 x009 x00A x00B x00C x00D x00E x00F x010 x011 BLK:0 BLK:1 BLK_SIZ=111 BLK:0 BLK_SIZ=110 BLK:0 BLK:1 BLK_SIZ=101 BLK:0 BLK:1 BLK_SIZ=100 BLK:0 BLK:1 BLK:2 ... BLK_SIZ=011 BLK:0 BLK:1 BLK:2 BLK:3 BLK:4 ... BLK_SIZ=010 BLK:0 BLK:1 BLK:2 BLK:3 BLK:4 BLK:5 BLK:6 BLK:7 BLK:8 ... BLK_SIZ=001 BLK:0 BLK:1 BLK:2 BLK:3 BLK:4 BLK:5 BLK:6 BLK:7 BLK:8 BLK:9 BLK:10 BLK:11 BLK:12 BLK:13 BLK:14 BLK:15 BLK:16 BLK:17 BLK_SIZ=000 ... USER MEMORY ADDRESS x013 x012 x014 x017 x018 x01F x020 x03F x040 x07F x080 x0FF x100 ... ... ... ... ... ... BLK:1 ... ... ... ...
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 28 of 32 CIRCUIT EXAMPLE The WM72016 may be implemented in a manner similar to that shown below. WM72016 CLK CS Vddr ANT+ ANT- VDDR_EXT µP GND I/O I/O I/O I/O Bus termination may be required Vddraw Matching network NOTES: 1. RF performance of WM72016 is heavily dependent on matching impedance on the antenna port ANT+/ -. 2. External voltage VDDR_EXT may be applied to Vddraw to externally power the WM72016. VDDR_EXT must comply with specifications given in the DC Characteristics of t his datasheet. 3. In some cases, additional bus termination may be required on the WM72016 end of the DSPI serial bus. This is dependent on a number of factors, including bus length, bus impedance, connectors, processor drive voltage, I /O port drive strength , and I /O slew rate. Excessive ringing on the bus may generate voltages beyond specifications causing unpredictable performance characteristics.
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 29 of 32 SPECIFICATION & COMPLIANCE SUMMARY Refer to EPCTM Radio-Frequency Identity Protocols Class -1 Generation -2 UHF RFID Protocol for Communications at 860MHz-960MHz Version 1.2.0 for all critical RFID specifications. Link to specifications page: http://www.epcglobalus.org/Standards/EPCglobalSpecifications/tabid/335/Default.aspx
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 30 of 32 MECHANICAL DRAWINGS 8-pin UDFN (3.0 mm x 3.0 mm body, 0.65 mm pad pitch) Note: All dimensions in millimeters. Care must be taken to ensure PCB traces and vias are not placed within the exposed metal pad area. UDFN PACKAGE MARKING SCHEME FOR BODY SIZE 3mm X 3mm Legend: XXXXXXX= base part number (WM72016) LLLLLLLL= lot code R=revision, P=package (D=DFN), N=split designator (numeric) RIC=Ramtron Int‟l Corp, YY=year, WW=work week Example: WM72016, “Green” UDFN-8 package, Lot 0411702, Rev B., Year 2010, Work Week 12 WM72016 0411702 BD1 RIC1012 XXXXXXXX LLLLLLLL RPN RICYYWW
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 31 of 32
ORDERING INFORMATION
Note: Contact Ramtron for other ordering options, i.e. bumped die. Product Description Delivery & MOQ WM72016-6-DGTR 8-pin UDFN with 16Kb memory and DSPI serial interface Tape & Reel – 3000 units
WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port Rev. 1.4 May 2011 Page 32 of 32
REVISION HISTORY
0.1 12/12/2008 Initial release. 0.2 2/11/2009 Order information and package update 0.3 3/7/2010 Documentation updates 1.0 3/12/2010 Changed to Preliminary status. 1.1 8/23/2010 Changed read/write sensitivity specs. 1.2 9/7/2010 Changed input impedance and the test frequency. 1.3 4/11/2011 Documentation updates and clarifications. 1.4 5/25/2011 Modified Memory Map table on p. 5 (changed line entries for DSPI address 0x3FA – 0x3FB).