FM25L16

FM25L16_06 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• Unlimited Read/Write Cycles
• 45 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
• Up to 18 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• Low Voltage Operation 2.7-3.6V
• 1 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40°C to +85°C
• “Green”/RoHS 8-pin SOIC Package
• “Green”/RoHS 8-pin TDFN Package
• TDFN Footprint Conforms to TSSOP-8

Description

The FM25L16 is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25L16 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the device. The next bus cycle may commence without the need for data polling. The product offers virtually unlimited write endurance, orders of magnitude more endurance than EEPROM. FRAM also exhibits much lower power during writes than EEPROM. These capabilities make the FM25L16 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25L16 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25L16 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage VSS Ground

Ordering Information

FM25L16-G “Green”/RoHS 8-pin SOIC FM25L16-DG “Green”/RoHS 8-pin TDFN /CS SO /WP VSS VDD /HOLD SCK SI Top View 1 CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram register. A complete explanation of write protection is provided on pages 6 and 7.

• SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

• SO may be connected to SI for a single pin data interface.

Rev. 3.0 Aug. 2006 Page 3 of 14 Overview The FM25L16 is a serial FRAM memory. The memory array is logically organized as 2,048 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25L16 and a serial EEPROM with the same pinout is the FRAM’s superior write performance. Memory Architecture When accessing the FM25L16, the user addresses 2,048 locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. The upper 5 bits of the address range are ‘don’t care’ values. The complete address of 11-bits specifies each byte address uniquely. Most functions of the FM25L16 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25L16 due to its fast write cycle and high endurance as compared with EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25L16 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip select active. Serial Peripheral Interface – SPI Bus The FM25L16 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 18 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25L16 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25L16 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25L16 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25L16 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25L16 supports Modes 0 and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into the FM25L16 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive (high) after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

protect inadvertent changes to the block protect bits. Register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. operation is shown in Figure 10. but the SCK pin can toggle during a hold state.

Rev. 3.0 Aug. 2006 Page 9 of 14 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) 4kV 1kV Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 2.7 3.3 3.6 V IDD VDD Supply Current @ SCK = 1.0 MHz @ SCK = 18.0 MHz 0.15 3.0 0.3 5.5 mA mA ISB Standby Current - 1 µA 2 ILI Input Leakage Current - ±1 µA 3 ILO Output Leakage Current - ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V DD V VOH Output High Voltage @ IOH = -2 mA VDD – 0.8 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V VHYS Input Hysteresis (/CS and SCK only) 0.05 VDD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD. 4. Characterized but not 100% tested in production.

Rev. 3.0 Aug. 2006 Page 10 of 14 AC Parameters (TA = -40° C to + 85° C, CL = 30pF) V DD 2.7 to 3.0V V DD 3.0 to 3.6V Symbol Parameter Min Max Min Max Units Notes fCK SCK Clock Frequency 0 15 0 18 MHz tCH Clock High Time 30 25 ns 1 tCL Clock Low Time 30 25 ns 1 tCSU Chip Select Setup 10 10 ns tCSH Chip Select Hold 10 10 ns tOD Output Disable Time 20 20 ns 2 tODV Output Data Valid Time 30 23 ns tOH Output Hold Time 0 0 ns tD Deselect Time 60 60 ns tR Data In Rise Time 50 50 ns 1,3 tF Data In Fall Time 50 50 ns 1,3 tSU Data Setup Time 5 5 ns tH Data Hold Time 5 5 ns tHS /Hold Setup Time 10 10 ns tHH /Hold Hold Time 10 10 ns tHZ /Hold Low to Hi-Z 20 20 ns 2 tLZ /Hold High to Data Active 20 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. Characterized but not 100% tested in production. 3. Rise and fall times measured between 10% and 90% of waveform. Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V) Symbol Parameter Min Max Units Notes tPU Power Up (V DD min) to First Access (/CS low) 1 - ms tPD Last Access (/CS high) to Power Down (V DD min) 0 - µs tVR V DD Rise Time 50 - µs/V 1,2 tVF V DD Fall Time 100 - µs/V 1,2 Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CO Output Capacitance (SO) - 8 pF 1 CI Input Capacitance - 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. 2. Slope measured at any point on VDD waveform. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 5 ns Input and output timing levels 0.5 V DD Output Load Capacitance 30 pF

Rev. 3.0 Aug. 2006 Page 11 of 14 Serial Data Bus Timing /Hold Timing CS SCK SO HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing Data Retention (VDD = 2.7V to 3.6V, + 85° C) Parameter Min Max Units Notes Data Retention 45 - Years

Rev. 3.0 Aug. 2006 Page 12 of 14 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012, variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°- 8° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25L16, “Green” SOIC package, Year 2004, Work Week 38 FM25L16-G A40003G RIC0438 XXXXXXX-P LLLLLLL RICYYWW

Rev. 3.0 Aug. 2006 Page 13 of 14 8-pin TDFN (3.0mm x 6.4mm body, 0.65mm pitch) Pin 1 6.40 ±0.1 3.00 ±0.1 0.75 ±0.05 0.25 ±0.05 0.65 0.20 REF. Pin 1 ID 0.0 - 0.05 Exposed metal pad. Do not connect to anything, except Vss. 6.70 0.300.65 Recommended PCB Footprint 0.40 ±0.1 0.60 3.10 1.10 Note: All dimensions in millimeters. This package is footprint compatible with the 8-pin TSSOP. Legend: RIC=Ramtron Int’l Corp, G=”green” TDFN package XXXX=base part number LLLL= lot code YY=year, WW=work week Example: “Green” TDFN package, FM25L16, Lot 0003, Year 2004, Work Week 38 RICG 5L16 0003 0438 RICG XXXX LLLL YYWW

Rev. 3.0 Aug. 2006 Page 14 of 14

Revision History

0.1 3/16/04 Initial Release 0.2 6/2/04 Replaced TSSOP with TDFN package. 1.0 10/22/04 Changed to Preliminary status. Added clarification to TDFN package drawing. Changed AC timing reference to 0.5 V DD. Added Power Cycling parameters and diagram. 2.0 3/10/05 Changed to Pre-Production status. Added ESD and package MSL ratings. Changed Data Retention spec. 2.1 7/18/05 Changed AC timings. Adjusted Idd values. 2.2 6/1/06 Removed I DD 100KHz and 5MHz entries. Improved I DD limits for 1MHz and 18MHz.