FM25L256-DG

FM25L256 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Features

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• Unlimited Read/Write Cycles
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• Low Voltage Operation 3.0V – 3.6V
• 1 µA (typ) Standby Current Industry Standard Configurations
• Extended Temperature -25°C to +85°C
• 8-pin SOIC and 8-pin TDFN Packages
• “Green” Packaging Options

Description

The FM25L256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25L256 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the device. The next bus cycle may commence without the need for data polling. In addition, the product offers virtually unlimited write endurance. FRAM also exhibits much lower power consumption than EEPROM. These capabilities make the FM25L256 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25L256 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25L256 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an extended temperature range of -25°C to +85°C. Pin Configuration

Ordering Information

FM25L256-G “Green” 8-pin SOIC FM25L256-DG “Green” 8-pin TDFN /CS SO /WP VSS VDD /HOLD SCK SI Top View Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage (3.0 to 3.6V) VSS Ground CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram /WP Input Write Protect: This active low pin prevents write operations to the status register only. A complete explanation of write protection is provided on pages 6 and 7.

• SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

• SO may be connected to SI for a single pin data interface.

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 3 of 14 Overview The FM25L256 is a serial FRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25L256 and a serial EEPROM with the same pinout is the FRAM’s superior write performance and power consumption. Memory Architecture When accessing the FM25L256, the user addresses 32K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two- byte address. The upper bit of the address range is a “don’t care” value. The complete address of 15-bits specifies each byte address uniquely. Most functions of the FM25L256 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25L256 due to its fast write cycle and high endurance as compared to EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25L256 contains no power management circuits other than a simple internal power-on reset circuit. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip select active. Serial Peripheral Interface – SPI Bus The FM25L256 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25L256 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25L256 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25L256 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25L256 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25L256 supports only modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25L256 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

from VDD (min) to the first /CS low. Table 1. Op-Code Commands The FM25L256 will power up with writes disabled. register and writing the memory. register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. register has no effect on the state of this bit. 6 illustrates the WRDI command bus configuration. Figure 5. WREN Bus Configuration

WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. protected as shown in the following table. Table 3. Block Memory Write Protection protect inadvertent changes to the block protect bits. register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. value. The upper bit of the address is a “don’t care”. until the next falling edge of /CS. master issues 8 clocks, with one bit read out for each. edge of /CS terminates a READ op-code operation. A read operation is shown in Figure 10.

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 9 of 14 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 3kV 1kV 100V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -25°C to +85°C, VDD = 3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 3.0 - 3.6 V IDD Power Supply Current @ SCK = 1.0 MHz @ SCK = 20.0 MHz 0.3 5.0 mA mA ISB Standby Current @ TA = 25°C @ TA = 55°C @ TA = 70°C @ TA = 85°C 1.0 2.5 5.0 10.0 µA µA µA µA ILI Input Leakage Current - ±1 µA 3 ILO Output Leakage Current - ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V DD V VOH Output High Voltage @ IOH = -2 mA VDD – 0.8 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V VHYS Input Hysteresis 0.05 V DD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD. 4. This parameter is characterized but not 100% tested.

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 10 of 14 AC Parameters (TA = -25° C to +85° C, VDD = 3.0V to 3.6V, CL = 30pF) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 20 MHz tCH Clock High Time 22 ns 1 tCL Clock Low Time 22 ns 1 tCSU Chip Select Setup 10 ns tCSH Chip Select Hold 10 ns tOD Output Disable Time 20 ns 2 tODV Output Data Valid Time 22 ns tOH Output Hold Time 0 ns tD Deselect Time 60 ns tR Data In Rise Time 50 ns 1,3 tF Data In Fall Time 50 ns 1,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /Hold Setup Time 10 ns tHH /Hold Hold Time 10 ns tHZ /Hold Low to Hi-Z 20 ns 2 tLZ /Hold High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. This parameter is characterized but not 100% tested. 3. Rise and fall times measured between 10% and 90% of waveform. Power Cycle Timing (TA = -25° C to +85° C, VDD = 3.0V to 3.6V) Symbol Parameter Min Max Units Notes tPU Power Up (V DD min) to First Access (/CS low) 10 - ms tPD Last Access (/CS high) to Power Down (V DD min) 0 - µs tVR V DD Rise Time 50 - µs/V 1,2 tVF V DD Fall Time 100 - µs/V 1,2 Notes 1. Slope measured at any point on V DD waveform. 2. Ramtron cannot test or characterize all V DD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that V DD power up faster than 100ms through the range of 0.4V to 1.0V. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CO Output Capacitance (SO) - 8 pF 1 CI Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 5 ns Input and output timing levels 0.5 V DD Output Load Capacitance 30 pF

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 11 of 14 Serial Data Bus Timing CS SCK SI SO 1/tCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /Hold Timing CS SCK SO HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing VDD min tPU VDD CS tVR tPD tVF Data Retention (VDD = 3.0V to 3.6V) Parameter Min Max Units Notes Data Retention 10 - Years

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 12 of 14 Mechanical Drawing 8-pin SOIC (JEDEC MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°- 8° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package (S, G, DG), T= temp (C=comm., blank=ind.) LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25L256, Standard SOIC package, Extended temperature, Year 2005, Work Week 39 FM25L256-S A40003S RIC0539 XXXXXX-PT LLLLLLL RICYYWW

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 13 of 14 8-pin TDFN (4.0mm x 4.5mm body, 0.95mm pitch) Pin 1 4.00 ±0.1 4.50 ±0.1 0.75 ±0.05 0.40 ±0.05 0.95 0.20 REF. Pin 1 ID 0.0 - 0.05

2.85 REF

3.60 ±0.10 2.60 ±0.10 Exposed metal pad. Do not connect to anything except Vss. 0.30 ±0.1 4.30 0.50 0.95 Recommended PCB Footprint 0.50 2.70 3.70 Note: All dimensions in millimeters. Legend: R=Ramtron, G=”green” TDFN package, XXXX=base part number LLLL= lot code, T= temperature (C=commercial, blank=extended) YY=year, WW=work week Example: “Green” TDFN package, FM25L256, Extended temperature, Lot 0003, Year 2005, Work Week 39 RG5L25 0003 0539 RGXXXX LLLL_T YYWW

Alternative: FM25L256B NOT RECOMME NDED FOR NEW DESIGNS Alternative: FM25L256B FM25L256 Extended Temp. Rev. 2.3 March 2007 Page 14 of 14

Revision History

0.1 9/9/03 Initial release. 0.11 12/9/03 Reduced I DD spec limits. 0.12 1/7/04 Added t VR and t VF specs, “green” package, and modified Power Cycling diagram. 0.13 5/5/04 Changed t OD, tODV , and tLZ timing specs. Changed I SB spec limit. Changed tVR and tVF conditions. Changed voltage/temperature conditions in AC Parameters table. 1.0 8/12/04 Added DFN mechanical package drawing and ordering information. Added ISB limits at various temperatures. Changed AC timing reference to 0.5 V DD. Changed tODV spec. New rev. number to comply with new scheme. 1.1 9/21/04 Changed I DD limits. Added Power Down timing parameter and changed diagram. 1.2 3/9/05 Removed “preliminary” from DFN package drawing. Added note about powering down with /CS active (pg 3). Added ESD and package MSL ratings. 2.0 4/5/05 Changed to Pre-Production status. 2.1 7/20/05 Split into commercial and extended temp datasheets. Changed min. temp to -25C and V DD min to 3.0V. Added recommended pcb footprint to DFN package drawing. 2.2 9/14/05 Added power up note to Power Cycle Timing table. Package name change, from DFN to TDFN. 2.3 3/26/07 Not recommended for new designs. Use FM25L256B as an alternative.