Microcontroller

W90P710CD

Winbond

32-BIT ARM7TDMI-BASED MCU

Manufacturer: Winbond

Document: 552 Pages / 3Mb

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PDF pages: 552

Technical content

Publication Release Date: September 19, 2006 - 1 - Revision B2 W90P710CD/W90P710CDG 16/32-bit ARM microcontroller Product Data Sheet

Revision History

A 2005/12/02 Draft A.1 2005/12/21 Modify the register definition A.2 2006/01/17 Modify SD description A.3 2006/07/07 Update LCD C version design spec. Update Smartcard C version design spec. Add RTC 32.768K clock measurment apllication note. Add RTC application note. B 2006/07/26 Change EBI SDRAM control register SDCONFx[13] AUTOPR definition. Modify LCD register map section 7.2.2 Change 2 to 1 slave/device select lines Change SDIO to SD Add Electrical specification 2006/08/08 SDO change to SD page 11 SDIO change to SD page 33 “W99P710” change to “W90P710” page 245 Delete “it is same as the UART of W99740” page 333 Delete “it is same as the UART of W99702” page 332 Delete “note” page 337,338 ADD USB WakeUp control bit Update table 5.2 2006/09/19 Delete section 6

Publication Release Date: September 19, 2006 - 3 - Revision B2 Table of Contents- 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.3 6.3.1 6.3.2 6.3.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.8

4 - 6.8.1 6.8.2 6.8.3 6.9 6.9.1 6.9.2 6.9.3 6.10 6.10.1 6.10.2 6.10.3 6.11 6.11.1 6.11.2 6.11.3 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.13 6.13.1 6.13.2 6.13.3 6.14 6.14.1 6.14.2 6.15 6.15.1 6.15.2 6.16 6.16.1 6.16.2 6.17 6.17.1 6.17.2 6.17.3 6.18 6.18.1 6.18.2

Publication Release Date: September 19, 2006 - 5 - Revision B2 6.19 6.19.1 6.19.2 6.20 6.20.1 6.20.2 6.20.3 6.20.4 6.20.5 6.20.6 6.21 6.21.1 6.21.2 6.22 6.22.1 6.22.2 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 10.

6 - 1. GENERAL DESCRIPTION The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte D- cache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost sensitive and power sensitive applications. One 10/100 Mb MAC of Ethernet controller is built-in to reduce total system cost. A LCD controller is also built-in to support TFT and low cost STN LCD modules. With one USB 1.1 host controller, one USB 1.1 device controller, two smart card host controller, four independent UARTs, one Watchdog timer, up to 71 programmable I/O ports, PS/2 keyboard controller and an advanced interrupt controller, the W90P710 is particularly suitable for point-of-sale (POS), access control and data collector. The W90P710 also provides one AC97/I²S controller, one SD host controller, one 2-Channel GDMA, two 24-bit timers with 8-bit pre-scale, The external bus interface (EBI) controller provides for SDRAM, ROM/SRAM, flash memory and I/O devices. The System Manager includes an internal 32-bit system bus arbiter and a PLL clock controller. With a wide range of serial communication and Ethernet interfaces, the W90P710 is also suitable for communication gateways as well as many other general purpose applications. 2. FEATURES Architecture y Fully 16/32-bit RISC architecture y Little/Big-Endian mode supported y Efficient and powerful ARM7TDMI core y Cost-effective JTAG-based debug solution External Bus Interface y 8/16/32-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os y Support for SDRAM y Programmable access cycle (0-7 wait cycle) y Four-word depth write buffer for SDRAM write data y Cost-effective memory-to-peripheral DMA interface Instruction and Data Cache y Two-way, Set-associative, 4K-byte I-cache and 4K-byte D-cache y Support for LRU (Least Recently Used) Protocol y Cache can be configured as internal SRAM y Support Cache Lock function

Publication Release Date: September 19, 2006 - 7 - Revision B2 Ethernet MAC Controller y DMA engine with burst mode y MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) y Data alignment logic y Endian translation y 100/10-Mbit per second operation y Full compliance with IEEE standard 802.3 y RMII interface only y Station Management Signaling y On-Chip CAM (up to 16 destination addresses) y Full-duplex mode with PAUSE feature y Long/short packet modes y PAD generation LCD Controller (LCDC) (1) STN LCD Display y Supports 4-bit single scan Monochrome STN LCD panel, 8-bit single scan Monochrome STN LCD panel, 8-bit single scan Color STN LCD panel y Up to 16 gray levels display for Monochrome STN LCD panel y Up to 4096(12bpp) colors display for Color STN LCD panel y Virtual coloring method: Frame Rate Control (16-level) y Anti-flickering method: Time-based Dithering (2) TFT LCD Display y Supports Sync-type TFT LCD panel and Sync-type High-color TFT LCD panel y Supports direct or palettized color display (3) TV Encoder y Supports 8-bit YCbCr data output format to connect with external TV Encoder (4) LCD Preprocessing y Supports RGB Raw-data or packetd YUV422 format y Programmable parameters for different image size y Build in two FIFOs, FIFO 1 is for Video image and FIFO 2 is for OSD image. Each FIFO is 16 words deep

8 - (5) LCD Post processing y Support for one OSD (On-Screen-Display) overlay y Support various OSD function y Programmable parameters for different display panel (6) Others y Color-look up table size 256x32 bit for TFT used when displaying 1bpp, 2bpp, 4bpp, 8bpp image y Dedicated DMA for block transfer mode DMA Controller y 2-channel General DMA for memory-to-memory data transfers without CPU intervention y Initialed by a software or external DMA request y Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers y 4-data burst mode UART y Four UART (serial I/O) blocks with interrupt-based operation y Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive y Programmable baud rates y 1, ½ or 2 stop bits y Odd or even parity y Break generation and detection y Parity, overrun and framing error detection y X16 clock mode y UART1 supports Bluetooth, and UART2 supports IrDA1.0 SIR Timers y Two programmable 24-bit timers with 8-bit pre-scaler y One programmable 20 bit with selectable additional 8-bit prescaler Watchdog timer y One-shot mode, periodical mode or toggle mode operation Programmable I/Os y 71 programmable I/O ports y Pins individually configurable to input, output or I/O mode for dedicated signals y I/O ports are configurable for Multiple functions

Publication Release Date: September 19, 2006 - 9 - Revision B2 Advanced Interrupt Controller y 31 interrupt sources, including 6 external interrupt sources y Programmable normal or fast interrupt mode (IRQ, FIQ) y Programmable as either edge-triggered or level-sensitive for 6 external interrupt sources y Programmable as either low-active or high-active for 6 external interrupt sources y Priority methodology is encoded to allow for interrupt daisy-chaining y Automatically mask out the lower priority interrupt during interrupt nesting USB Host Controller y USB 1.1 compliant y Compatible with Open HCI 1.0 specification y Supports low-speed and full speed devices y Build-in DMA for real time data transfer y Two on-chip USB transceivers with one optionally shared with USB Device Controller USB Device Controller y USB 1.1 compliant y Support four USB endpoints including one control endpoint and 3 configurable endpoints for rich USB functions Two PLLs y The external clock can be multiplied by on-chip PLL to provide high frequency system clock y The input frequency range is 3-30MHz; 15MHz is preferred. y One PLL for both CPU and USB host/device controller y One PLL for LCD pixel clock and audio IIS 12.288/16.934MHz clock source y Programmable clock frequency Real Time Clock (RTC) y 32.768KHz operation y Time counter (second, minute, hour) and calendar counter (day, month, year) y Alarm register (second, minute, hour, day, month, year) y 12 or 24-hour mode selectable y Recognize leap year automatically y Day of the week counter y Frequency compensate register (FCR) y Beside FCR, all clock and alarm data expressed in BCD code y Support tick time interrupt

10 - 4-Channel PWM y Four 16-bit timers with PWM y Two 8-bit pre-scalers & Two 4-bit dividers y Programmable duty control of output waveform y Auto reload mode or one-shot pulse mode y Dead-zone generator I2C Master y Two Channel I2C y Compatible with Philips I2C standard, support master mode only y Support multi master operation y Clock stretching and wait state generation y Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer y Software programmable acknowledge bit y Arbitration lost interrupt, with automatic transfer cancellation y Start/Stop/Repeated Start/Acknowledge generation y Start/Stop/Repeated Start detection y Bus busy detection y Supports 7 bit addressing mode y Software mode I2C Universal Serial Interface (USI) y 1-Channel USI y Support USI (Microwire/SPI) master mode y Full duplex synchronous serial data transfer y Variable length of transfer word up to 32 bits y Provide burst mode operation, transmit/receive can be executed up to four times in one transfer y MSB or LSB first data transfer y Rx and Tx on both rising or falling edge of serial clock independently y Two slave/device select lines y Fully static synchronous design with one clock domain 2-Channel AC97/I2S Audio Codec Host Interface y AHB master port and an AHB slave port are offered in audio controller. y Always 8-beat incrementing burst y Always bus lock when 8-beat incrementing burst

Publication Release Date: September 19, 2006 - 11 - Revision B2 y When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically Smart Card Host Interface (SCHI) y ISO-7816 compliant y PC/SC T=0, T=1 compliant y 16-byte transmitter FIFO and 16-byte receiver FIFO y FIFO threshold interrupt to optimize system performance y Programmable transmission clock frequency y Versatile baud rate configuration y UART-like register file structure y General-purpose C4, C8 channels SD Host Interface y Directly connect to Secure Digital (SD, MMC) flash memory card. y Supports DMA function to accelerate the data transfer between the internal buffer, external SDRAM, and flash memory card. y Two 512 bytes internal buffers are embedded inside the controller. y No SPI mode. KeyPad Scan Interface y Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4 rows by 8 columns array without auxiliary component y Programmable debounce time y One or two keys scan with interrupt and three keys reset function. y Wakeup CPU from IDEL/Power Down mode PS2 Host Interface y APB slave consisted of PS2 protocol. y Connect IBM keyboard or bar-code reader through PS2 interface. y Provide hardware scan code to ASCII translation Power management y Programmable clock enables for individual peripheral y IDLE mode to halt ARM Core and keep peripheral working y Power-Down mode to stop all clocks included external crystal oscillator. y Exit IDLE by all interrupts y Exit Power-Down by keypad,USB device and external interrupts

12 - Operation Voltage Range y 3.0 ~ 3.6 V for IO Buffer y 1.62 ~ 1.98 V for Core Logic Operation Temperature Range y TBD Operating Frequency y Up to 80 MHz Package Type y 176-pin LQFP

Publication Release Date: September 19, 2006 - 13 - Revision B2 3. PIN DIAGRAM 140 165 160 155 150 145 175 170 VSS18 KPI_ROW[0]/VCLK/GPIO[30] KPI_COL[1]/VD[1]/GPIO[35] TXD1/GPIO[7] VDD33 MCKE nBTCS nSCS[1] nSCS[0] SCL0/SFRM/TIMER0/GPIO[11] SCL1/SCLK/KPI_ROW[3]/GPIO[13] SDA0/SSPTXD/TIMER1/GPIO[12] D[10]/TBUS[10] D[11]/TBUS[11] SDA1/SSPRXD/KPI_ROW[2]/GPIO[14] KPI_ROW[2]/VSYNC/GPIO[32] KPI_COL[7]/VD[7]/GPIO[41] KPI_ROW[3]/HSYNC/GPIO[33] KPI_ROW[1]/VDEN/GPIO[31] VDD18 nECS[1] nWAIT/TREQB nECS[0] nOE D[26]/VD[18]/GPIO[62] D[27]/VD[19]/GPIO[63] D[24]/VD[16]/GPIO[60] D[25]/VD[17]/GPIO[61] TDI VDD33 A[10]/TBUS[26] A[9]/TBUS[25] A[13]/TBUS[29] A[12]/TBUS[28] nIRQ[1]/GPIO[17] TCK TDO USB0VDD SC0_PWR/SD_DAT2/VD[13]/GPIO[25] SC0_RST/SD_DAT0/VD[15]/GPIO[27] SC0_CLK/SD_CLK/VD[16]/GPIO[28] SC0_DAT/SD_CMD/VD[17]/[GPIO[29] VSS18 VDD18 AC97_BITCLK/I2S_BITCLK/PWM[3]/RXD3/GPIO[4] AC97_SYNC/I2S_LRCLK/PWM[2]/TXD3/GPIO[3] AC97_DATAO/I2S_DATAO/PWM[1]/DSR3/GPIO[2] AC97_DATAI/I2S_DATAI/PWM[0]/DTR3/GPIO[1] nTRST EXTAL(15M) VDD33 SC0_PRES/SD_DAT1/VD[14]/GPIO[26] SC1_DAT/SD_DAT3/VD[12]/GPIO[24] EXTAL32 (32.768K) RTCVDD18 VSS33 XTAL32 (32.768K) AC97_nRESET/I2S_MCLK/GPIO[0] nWDOG/GPIO[15] VSS33 A[4]/TBUS[20] A[3]/TBUS[19] A[2]/TBUS[18] VDD33 D[28]/VD[20]/GPIO[64] D[30]/VD[22]/GPIO[66] A[21] VDD33 XTAL(15M) VSS33 A[18] A[17]/TREQA VDD18 A[8]/TBUS[24] A[7]/TBUS[23] A[6]/TBUS[22] A[5]/TBUS[21] KPI_COL[3]/VD[3]/GPIO[37] KPI_COL[0]/VD[0]/GPIO[34] nRESET PLL1VSS18 KPI_COL[2]/VD[2]/GPIO[36] KPI_COL[4]/VD[4]/GPIO[38] PLL0VSS18 PLL0VDD18 TEST A[20] A[19] VDD33 D[31]/VD[23]/GPIO[67] A[11]/TBUS[27] D[29]/VD[21]/GPIO[65] KPI_COL[6]/VD[6]/GPIO[40] KPI_COL[5]/VD[5]/GPIO[39] PHY_RXD[0]/GPIO[44]/KPI_COL[2]/VD[10] PHY_CRSDV/GPIO[43]/KPI_COL[1]/VD[9] PHY_RXERR/GPIO[42]/KPI_COL[0]/VD[8] SC1_PWR/nXDACK/VD[8]/GPIO[20] SC1_PRES/nXDREQ/VD[9]GPIO[21] SC1_RST/SD_CD/VD[10]/GPIO[22] SC1_CLK/SD_PWR/VD[11]/GPIO[23] VSS33 PLL1VDD18 A[1]/TBUS[17] A[0]/TBUS[16] PHY_MDC/GPIO[51]/KP_ROW[1]/VD[17] PHY_TXD[1]/GPIO[49]/KPI_COL[7]/VD[15] nIRQ[0]/GPIO[16] A[16]/TACK A[15]/TBUS[31] A[14]/TBUS[30] VSS18 TMS RXD1/GPIO[8] VSS33 RTS1/RXD2(IrDA)/PS2_DATA/GPIO[10] CTS1/TXD2(IrDA)/PS2_CLK/GPIO[9] nWE PHY_TXD[0]/GPIO[48]/KPI_COL[6]/VD[14] PHY_TXEN/GPIO[47]/KPI_COL[5]/VD[13] PHY_REFCLK/GPIO[46]/KPI_COL[4]/VD[12] PHY_RXD[1]/GPIO[45]/KPI_COL[3]/VD[11] VSS33 D[22]/VD[14]/GPIO[58] D[20]/VD[12]/GPIO[56] D[21]/VD[13]/GPIO[57] nWBE[0]/SDQM[0] D[13]/TBUS[13] D[19]/VD[11]/GPIO[55] nWBE[3]/SDQM[3]/GPIO[68] nWBE[1]/SDQM[1] D[23]/VD[15]/GPIO[59] nIRQ[3]/GPIO[19] nIRQ[2]/GPIO[18] D[18]/VD[10]/GPIO[54] D[14]/TBUS[14] D[15]/TBUS[15] VSS18 VDD18 D[17]/VD[9]/GPIO[53] D[16]/VD[8]/GPIO[52] VSS33 D[12]/TBUS[12] D[3]/TBUS[3] VDD33 nWBE[2]/SDQM[2]/GPIO[69] D[2]/TBUS[2] D[0]/TBUS[0] D[1]/TBUS[1] MCLK VDD33 nECS[2] nECS[3] nSRAS nSCAS VSS33 VDD33 135 TXD0/GPIO[5] DN0 DP0 RXD0/GPIO[6] USB1VSS DN1 USB1VDD DP1 D[6]/TBUS[6] 120 110 105 100 130 125 D[4]/TBUS[4] VSS33 D[5]/TBUS[5] USB0VSS D[9]/TBUS[9] D[7]/TBUS[7] D[8]/TBUS[8] PHY_MDIO/GPIO[50]/KPI_ROW[0]/VD[16] VDD33 115 W90P710 176 -pin LQFP VSS33 Fig 3.1 Pin Diagram

14 - 4. PIN ASSIGNMENT Table 4.1 W90P710 Pins Assignment PIN NAME 176-PIN LQFP Clock & Reset ( 5 pins ) EXTAL (15M) XTAL (15M) EXTAL32 (32.768K) XTAL32 (32.768K) nRESET JTAG Interface ( 5 pins ) TMS TDI TDO TCK nTRST External Bus Interface ( 72 pins ) A [21] 115 A [20:0] 113-110,108-106, 104-101,99-95, 93-89 D [31:16] / VD [23:8] / GPIO [67:52] 116-119,121-124, 149-156 D [15:0] 158,159,161-164, 166-170,172-176 nWBE [3:2] / SDQM [3:2] / GPIO[69:68] 146,145 nWBE [1;0] / SDQM [1:0] 144,143 nSCS [1:0] 136,135 nSRAS 137 nSCAS 138 MCKE 134 nSWE 142 MCLK 140 nWAIT/ GPIO[70] / nIRQ5 132 nBTCS 133 nECS [3] 125 nECS [2:0] 128-130 nOE 131

Publication Release Date: September 19, 2006 - 15 - Revision B2 Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP Ethernet Interface ( 10 pins ) PHY_MDC / GPIO [51] / KPROW[1] / VD[17] PHY_MDIO / GPIO [50] / KPROW[0] / LD[16] PHY_TXD [1:0] / GPIO[49:48] / KPCOL[7:6] / VD[15:14] 86,84 PHY_TXEN / GPIO [47] / KPCOL[5] / VD[13] PHY_REFCLK / GPIO [46] / KPCOL[4] / VD[12] PHY_RXD [1:0] / GPIO [45:44] / KPCOL[3:2] / VD[11:10] 81,79 PHY_CRSDV / GPIO [43] / KPCOL[1] / VD[9] PHY_RXERR / GPIO [42] / KPCOL[0] / VD[8] AC97/I2S/PWM/UART3 ( 5 pins ) AC97_nRESET / I2S_MCLK / GPIO [0] / USB_PWREN

16 - Table 4.1 W90P710 Pins Assignment (Continued) PIN NAME 176-PIN LQFP AC97/I2S/PWM/UART3 ( 5 pins ) AC97_DATAI / I2S_DATAI / PWM [0] / DTR3 / GPIO [1] AC97_DATAO / I2S_DATAO / PWM [1] / DSR3 / GPIO [2] AC97_SYNC / I2S_LRCLK / PWM [2] / TXD3 / GPIO [3] AC97_BITCLK / I2S_BITCLK / PWM [3] / RXD3 GPIO [4] USB Interface ( 4 pins ) DP0 DN 0 DP1 DN1 Miscellaneous ( 7 pins ) nIRQ [3:2] / GPIO [19:18] 148,147 nIRQ [1] / GPIO [17] / USB_OVRCUR nIRQ [0] / GPIO [16] nWDOG / GPIO [15] / USB_PWREN RTCVDD18

Publication Release Date: September 19, 2006 - 17 - Revision B2 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP I2C/USI(Microwire/SPI) ( 4 pins ) SCL0 / SFRM / Timer0 / GPIO [11] SDA0 / SSPTXD / Timer1 / GPIO [12] SCL1 / SCLK / GPIO [13] / KPROW[3] SDA1 / SSPRXD / GPIO [14] / KPROW[2] UART0/UART1/UART2/PS2 ( 6 pins ) TXD0 / GPIO [5] RXD0 / GPIO [6] TXD1 / GPIO [7] RXD1 / GPIO [8] CTS1 / TXD2(IrDA) / PS2_CLK / GPIO [9] RTS1 / RXD2(IrDA) / PS2_DATA / GPIO [10]

18 - Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP SCHI/SD/XDMA ( 10 pins ) SC0_DAT / SD_CMD / GPIO [29] / VD[17] SC0_CLK / SD_CLK / GPIO [28] / VD[16] SC0_RST / SD_DAT0 / GPIO [27] / VD[15] SC0_PRES / SD_DAT1 / GPIO [26] / VD[14] SC0_PWR / SD_DAT2 / GPIO [25] / VD[13] SC1_DAT / SD_DAT3 / GPIO [24] / VD[12] SC1_CLK / GPIO [23] / VD[11] SC1_RST / SD_CD / GPIO [22] / VD[10] SC1_PRES / nXDREQ / GPIO [21] / VD[9] SC1_PWR / nXDACK / GPIO [20] / VD[8]

Publication Release Date: September 19, 2006 - 19 - Revision B2 Table 4.1 W90P710 Pins Assignment (Continued) NAME 176-PIN LQFP LCDC ( 12 pins ) VD[7:0] / GPIO [41:34]/ KPCOL[7:0] 27-34 HSYNC / GPIO [33]/ KPROW[3] VSYNC / GPIO [32]/ KPROW[2] VDEN / GPIO [31]/ KPROW[1] VCLK / GPIO [30]/ KPROW[0] Power/Ground ( 36 pins ) VDD18 21,63,109,160 VSS18 22,38,64,105,157 VDD33 9,35,54,69,85,100, 120,127,139,165 VSS33 16,36,51,73,80,94, 114,126,141,171 USBVDD 1,8 USBVSS 4,5 PLLVDD18 39,42 PLLVSS18 40,41

20 - 5. PIN DESCRIPTION Table 5.1 W90P710 Pins Description PIN NAME IO TYPE

DESCRIPTION

Clock & Reset EXTAL (15M) I 15MHz External Clock / Crystal Input XTAL (15M) O 15MHz Crystal Output EXTAL32(32.768 I 32768Hz External Clock / Crystal Input(for RTC) XTAL32(32.768K) O 32768Hz Crystal Output(for RTC) nRESET IS System Reset, active-low JTAG Interface TCK IDS JTAG Test Clock, internal pull-down with 58K ohm TMS IUS JTAG Test Mode Select, internal pull-up with 70K ohm TDI IUS JTAG Test Data in, internal pull-up with 70K ohm TDO O JTAG Test Data out nTRST IUS JTAG Reset, active-low, internal pull-up with 70K ohm External Bus Interface A [21:18] O Address Bus (MSB) of external memory and IO devices. A [17:0] IOS Address Bus of external memory and IO devices. D [31:16] / VD[23:8] / GPIO [67:52] IOU Data Bus (MSB) of external memory and IO device, internal pull-up with 70K ohm. General Programmable In/Out Port GPIO[67:52]. D [15:0] / IOU Data Bus (LSB) of external memory and IO device. nWBE [3:0] / SDQM [3:0] / GPIO[69:68] IOU Write Byte Enable for specific device (nECS [3:0]). Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low. General Programmable In/Out Port [69:68] nSCS [1:0] O SDRAM chip select for two external banks, active-low. nSRAS O Row Address Strobe for SDRAM, active-low. nSCAS O Column Address Strobe for SDRAM, active-low. nSWE O SDRAM Write Enable, active-low MCKE O SDRAM Clock Enable, active-high MCLK O System Master Clock Out, SDRAM clock, output with slew-rate control nWAIT / GPIO[70] / nIRQ5 IOU External Wait, active-low. This pin indicates that the external devices need more active cycle during access operation. General Programmable In/Out Port GPIO[70]. If memory and IO devices in EBI do not need wait request, it can be configured as GPIO[7] or nIRQ5 nBTCS O ROM/Flash Chip Select, active-low. nECS [3:0] O External I/O Chip Select, active-low. nOE O ROM/Flash, External Memory Output Enable, active-low.

Publication Release Date: September 19, 2006 - 21 - Revision B2 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type PHY_MDC / GPIO [51] / KPROW[1] / VD[17] IOU RMII Management Data Clock for Ethernet. It is the reference clock of MDIO. Each MDIO data will be latched at the rising edge of MDC clock. General Programmable In/Out Port [51] Keypad ROW[1] scan output. LCD Pixel Data Output[17]. PHY_MDIO / GPIO [50] / KPROW[0] / VD[16] IO RMII Management Data I/O for Ethernet. It is used to transfer RMII control and status information between PHY and MAC. General Programmable In/Out Port [51] Keypad ROW[0] scan output. LCD Pixel Data Output[16]. PHY_TXD [1:0] / GPIO [49:48] / KPCOL[7:6] / VD[15] IOU 2-bit Transmit Data bus for Ethernet. General programmable In/Out Port [49:48] Keypad Column input [7:6], active low LCD Pixel Data Output[15]. PHY_TXEN / GPIO [47] / KPCOL[5] / VD[14:13] IOU PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble and shall remain asserted while all di-bits to be transmitted are presented. Of course, it is synchronized with PHY_REFCLK. General Programmable In/Out Port [47] Keypad column input [5], active low LCD Pixel Data Output[14:13]. PHY_REFCLK / GPIO [46] / KPCOL[4] / VD[12] IOS Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state. General Programmable In/Out port [46] Keypad column input [4], active low LCD Pixel Data Output[12]. PHY_RXD [1:0] / GPIO [45:44] / KPCOL[3:2] / VD[11:10] IOS 2-bit Receive Data bus for Ethernet. General Programmable In/Out Port [45:44] Keypad column input [3:2], active low LCD Pixel Data Output[11:10]. PHY_CRSDV / GPIO [43] / KPCOL[1] / VD[9] IOS Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of PHY_CRSDV synchronous to the cycle of PHY_REFCLK, and only on 2-bit receive data boundaries. General Programmable In/Out port [43] Keypad column input [1], active low LCD Pixel Data Output[9]. PHY_RXERR / GPIO [42] / KPCOL[0] / VD[8] IOS Receive Data Error for Ethernet. It indicates a data error detected by PHY.The assertion should be lasted for longer than a period of PHY_REFCLK. When PHY_RXERR is asserted, the MAC will report a CRC error. General programmable In/Out port [42] Keypad column input [0], active low LCD Pixel Data Output[8].

22 - Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type

AC97_nRESET / I2S_MCLK / GPIO [0] / nIRQ4 / USB_PWREN IOU AC97 CODEC Host Interface RESET Output. I2S CODEC Host Interface System Clock Output. General Purpose In/Out port [0] External interrupt request. USB host power enable output AC97_DATAI / I2S_DATAI / PWM [0] / DTR4 / GPIO [1] IOU AC97 CODEC Host Interface Data Input. I2S CODEC Host Interface Data Input. PWM Channel 0 Output. Data Terminal Ready for UART4. General Purpose In /Out port [1] AC97_DATAO / I2S_DATAO / PWM [1] / DSR4 / GPIO [2] IOU AC97 CODEC Host Interface Data Output. I2S CODEC Host Interface Data Output. PWM Channel 1 Output. Data Set Ready for UART4. General Purpose In/Out port [2] AC97_SYNC / I2S_LRCLK / PWM [2] / TXD4 / GPIO [3] IOU AC97 CODEC Host Interface Synchronous Pulse Output. I2S CODEC Host Interface Left/Right Channel Select Clock. PWM Channel 2 Output. Transmit Data for UART4. General Purpose In/Out port [3] AC97_BITCLK / I2S_BITCLK / PWM [3] / RXD4 / GPIO [4] IOS AC97 CODEC Host Interface Bit Clock Input. I2S CODEC Host Interface Bit Clock. PWM Channel 3 Output. Receive Data for UART4. General Purpose In/Out port [4]. USB Interface DP0 IO Differential Positive USB IO signal DN0 IO Differential Negative USB IO signal DP1 IO Differential Positive USB IO signal DN1 IO Differential Negative USB IO signal Miscellaneous nIRQ [3:2] / GPIO [19:18] IOU External Interrupt Request General Purpose I/O. nIRQ [1:0] / GPIO [17:16] USB_OVRCUR IOU External Interrupt Request General Purpose I/O nIRQ1 is used as USB host over-current detection input nWDOG / GPIO [15] / USB_PWREN IOU Watchdog Timer Timeout Flag and Keypad 3-keys reset output, active low General Purpose In/output USB host power switch enable output RTCVDD P RTC independent battery power (1.8V)

Publication Release Date: September 19, 2006 - 23 - Revision B2 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type I2C/USI(Microwire/SPI) SCL0 / SFRM / Timer0 / GPIO [11] IOU I2C Serial Clock Line 0. USI Serial Frame. Timer0 time out output. General Purpose In/Out port [11]. SDA0 / SSPTXD / Timer1 / GPIO [12] IOU I2C Serial Data Line 0 USI Serial Transmit Data Timer1 time out output General Purpose In/Out port [12] SCL1 / SCLK / GPIO [13] KPROW[3] IOU I2C Serial Clock Line 1 USI Serial Clock General Purpose In/Out port [13] Keypad row scan output [3] SDA1 / SSPRXD / GPIO [14] / KPROW[2] IDU I2C Serial Data Line 1 USI Serial Receive Data General Purpose In/Out port [14] Keypad scan output [2] UART0/UART1/UART2 TXD0 / GPIO [5] IOU UART0 Transmit Data. General Purpose In/Out [5] RXD0 / GPIO [6] IOU UART0 Receive Data. General Purpose In/Out [6] TXD1 / GPIO [7] IOU UART1 Transmit Data. General Purpose In/Out [7] RXD1 / GPIO [8] IOU UART1 Receive Data. General Purpose In/Out [8] CTS1/ TXD2(IrDA) / PS2_CLK / GPIO [9] IOU UART1 Clear To Send for Bluetooth application UART2 Transmit Data supporting SIR IrDA. PS2 Interface Clock Input/Output General Purpose In/Out [9] RTS1/ RXD2(IrDA) / PS2_DATA / GPIO [10] IOU UART1 Request To Send for Bluetooth application UART2 Receive Data supporting SIR IrDA. PS2 Interface Bi-Directional Data Line. General Purpose In/Out [10] SCHI/SD/XDMA SC0_DAT/ SD_CMD / GPIO [29] / VD[17] IOU Smart Card I/O Contact to Card 0. SD Mode – Command/Response; General Purpose In/Out [29] LCD Pixel Data Output[17]. SC0_CLK / SD_CLK / GPIO [28] / VD[16] IO Smart Card Clock Output to Card 0. SD Mode – Clock; General Purpose In/Out [28] LCD Pixel Data Output[16].

24 - Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type

SC0_RST / SD_DAT0 / GPIO [27] / VD[15] IO Smart Card Reset Output to Card 0. SD Mode – Data Line Bit 0; General Purpose In/Out [27] LCD Pixel Data Output[15]. SC0_PRES / SD_DAT1 / GPIO [26] VD[14] IO Smart Card 0 Presence Contact Input. SD Mode – Data Line Bit 1. General Purpose In/Out [26] LCD Pixel Data Output[14].] SC0_nPWR / SD_DAT2 / GPIO [25] / VD[13] IO Smart Card 0 Power FET Control Signal Output. SD Mode – Data Line Bit 2. General Purpose In/Out [25] LCD Pixel Data Output[13]. SC1_DAT / SD_DAT3 / GPIO [24] / VD[12] IO Smart Card I/O Contact to Card 1. SD Mode – Data Line Bit 3; General Purpose In/Out [24] LCD Pixel Data Output[12]. SC1_CLK / GPIO [23] / VD[11] IO Smart Card Clock Output to Card 1. General Purpose In/Out [23] LCD Pixel Data Output[11]. SC1_RST / SD_CD / GPIO [22] / VD[10] IO Smart Card Reset Output to Card 1. SD Mode – Card Detect. General Purpose In/Out [22] LCD Pixel Data Output[10]. SC1_PRES / nXDREQ / GPIO [21] / VD[9] IO Smart Card 1 Presence Contact Input. External DMA Request. General Purpose In/Out [21] LCD Pixel Data Output[9]. SC1_nPWR / nXDACK / GPIO [20] / VD[8] IO Smart Card 1 Power FET Control Signal Output. External DMA Acknowledgement. General Purpose In/Out [20] LCD Pixel Data Output[8]. LCD Interface VD [7:0] / GPIO [41:34]/ KPCOL[7:0] IOU LCD Pixel Data Output [7:0]. General Purpose In/Out [41:34] Keypad Column input [7:0], active low HSYNC / GPIO [33]/ KPROW[3] IOU Horizontal Sync General Purpose In/Out [33] Keypad ROW[3] scan output. VSYNC / GPIO [32]/ KPROW[2] IOU Vertical Sync General Purpose In/Out [32] Keypad ROW[2] scan output. VDEN / GPIO [31]/ KPROW[1] IOU Data Enable or Display Control Signal. General Purpose In/Out [31] Keypad ROW[1] scan output.

Publication Release Date: September 19, 2006 - 25 - Revision B2 Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type P Core Logic power (1.8V) VSS18 G Core Logic ground (0V) VDD33 P IO Buffer power (3.3V) VSS33 G IO Buffer ground (0V) USBVDD P USB power (3.3V) USBVSS G USB ground (0V) DVDD18 P PLL Digital power (1.8V) DVSS18 G PLL Digital ground (0V) AVDD18 P PLL Analog power (1.8V) AVSS18 G PLL Analog ground (0V)

26 - Table 5.2 W90P710 176-pin LQFP Multi-function List PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 USB1.1 Host/Device Interface USB1VDD USB1VDD DP1 DP1 DN1 DN1 USB1VSS USB1VSS USB0VSS USB0VSS DN0 DN0 DP0 DP0 USB0VDD USB0VDD VDD33 VDD33 UART[2:0]/PS2 Interface GPIO[5] GPIO[5] UART_TXD0 GPIO[6] GPIO[6] UART_RXD0 GPIO[7] GPIO[7] UART_TXD1 GPIO[8] GPIO[8] UART_RXD1 GPIO[9] GPIO[9] UART_TXD2 UART_CTS1 PS2_CLK GPIO[10] GPIO[10] UART_RXD2 UART_RTS1 PS2_DATA VSS33 VSS33 I2C/USI Interface GPIO[11] GPIO[11] I2C_SCL0 SSP_FRAM TIMER0 GPIO[12] GPIO[12] I2C_SDA0 SSP_TXD TIMER1 GPIO[13] GPIO[13] I2C_SCL1 SSP_RXD KPROW[2] GPIO[14] GPIO[14] I2C_SDA1 SSP_SCLK KPROW[3] VDD18 VDD18 VSS18 VSS18 LCD /KeyPad Interface GPIO[30] GPIO[30] LCD_VCLK KPROW[0] GPIO[31] GPIO[31] LCD_VDEN KPROW[1] GPIO[32] GPIO[32] LCD_VSYNC KPROW[2] GPIO[33] GPIO[33] LCD_HSYNC KPROW[3] GPIO[41] GPIO[41] LCD_VD[7] KPCOL[7]

Publication Release Date: September 19, 2006 - 27 - Revision B2 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 LCD /KeyPad Interface GPIO[40] GPIO[40] LCD_VD[6] KPCOL[6] GPIO[39] GPIO[39] LCD_VD[5] KPCOL[5] GPIO[38] GPIO[38] LCD_VD[4] KPCOL[4] GPIO[37] GPIO[37] LCD_VD[3] KPCOL[3] GPIO[36] GPIO[36] LCD_VD[2] KPCOL[2] GPIO[35] GPIO[35] LCD_VD[1] KPCOL[1] GPIO[34] GPIO[34] LCD_VD[0] KPCOL[0] VDD33 VDD33 VSS33 VSS33 System Reset nRESET nRESET VSS33 VSS33 PLL Power/Ground PLL0_VDD18 PLL0_VDD18 PLL0_VSS18 PLL0_VSS18 PLL1_VSS18 PLL1_VSS18 PLL1_VDD18 PLL1_VDD18 External IRQ[1:0]/USB Over Current GPIO[16] GPIO[16] nIRQ[0] GPIO[17] GPIO[17] nIRQ[1] USB_OVRCUR JTAG Interface TMS TMS TDI TDI TDO TDO TCK TCK nTRST nTRST WatchDog/USB Power Enable GPIO[15] GPIO[15] nWDOG USB_PWREN VSS33 VSS33

28 - Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 System/RTC Clock EXTAL(15M) EXTAL(15M) XTAL(15M) XTAL(15M) VDD33 VDD33 RTCVDD18 RTCVDD18 XTAL32 (32K) XTAL32 (32K) EXTAL32 (32K) EXTAL32 (32K) AC97/I2S/PWM/UART3 Interface GPIO[0] GPIO[0] AC97_nRESET IRQ4 USB_PWREN GPIO[1] GPIO[1] AC97_DATAI PWM0 UART_DTR3 GPIO[2] GPIO[2] AC97_DATAO PWM1 UART_DSR3 GPIO[3] GPIO[3] AC97_SYNC PWM2 UART_TXD3 GPIO[4] GPIO[4] AC97_BITCLK PWM3 UART_RXD3 VDD18 VDD18 VSS18 VSS18 SmartCard/SD/USB Power/XDMAREQ/LCD Interace GPIO[29] GPIO[29] SD_CMD SC0_IO LCD_VD[17] GPIO[28] GPIO[28] SD_CLK SC0_CLK LCD_VD[16] GPIO[27] GPIO[27] SD_DAT[0] SC0_RST LCD_VD[15] GPIO[26] GPIO[26] SD_DAT[1] SC0_PRES LCD_VD[14] VDD33 VDD33 GPIO[25] GPIO[25] SD_DAT[2] SC0_PWR LCD_VD[13] GPIO[24] GPIO[24] SD_DAT[3] SC1_IO LCD_VD[12] GPIO[23] GPIO[23] USBPWREN SC1_CLK LCD_VD[11] VSS33 VSS33 GPIO[22] GPIO[22] SD_CD SC1_RST LCD_VD[10] GPIO[21] GPIO[21] nXQREQ SC1_PRES LCD_VD[9] GPIO[20] GPIO[20] nXDACK SC1_PWR LCD_VD[8]

Publication Release Date: September 19, 2006 - 29 - Revision B2 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Ethernet RMII/KeyPad Interface GPIO[42] GPIO[42] PHY_RXERR KPCOL[0] LCD_VD[8] GPIO[43] GPIO[43] PHY_CRSDV KPCOL[1] LCD_VD[9] GPIO[44] GPIO[44] PHY_RXD[0] KPCOL[2] LCD_VD[10] VSS33 VSS33 GPIO[45] GPIO[45] PHY_RXD[1] KPCOL[3] LCD_VD[11] GPIO[46] GPIO[46] PHY_REFCLK KPCOL[4] LCD_VD[12] GPIO[47] GPIO[47] PHY_TXEN KPCOL[5] LCD_VD[13] GPIO[48] GPIO[48] PHY_TXD[0] KPCOL[6] LCD_VD[14] VDD33 VDD33 GPIO[49] GPIO[49] PHY_TXD[1] KPCOL[7] LCD_VD[15] GPIO[50] GPIO[50] PHY_MDIO KPROW[0] LCD_VD[16] GPIO[51] GPIO[51] PHY_MDC KPROW[1] LCD_VD[17] Memory Address/Data/Control A[0] A[0] A[1] A[1] A[2] A[2] A[3] A[3] A[4] A[4] VSS33 VSS33 A[5] A[5] A[6] A[6] A[7] A[7] A[8] A[8] A[9] A[9] 100 VDD33 VDD33 101 A[10] A[10] 102 A[11] A[11] 103 A[12] A[12] 104 A[13] A[13]

30 - Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 105 VSS18 VSS18 106 A[14] A[14] 107 A[15] A[15] 108 A[16] A[16] 109 VDD18 VDD18 110 A[17] A[17] 111 A[18] A[18] 112 A[19] A[19] 113 A[20] A[20] 114 VSS33 VSS33 115 A[21] A[21] 116 D[31] GPIO[67] D[31] LCD_VD[23] 117 D[30] GPIO[66] D[30] LCD_VD[22] 118 D[29] GPIO[65] D[29] LCD_VD[21] 119 D[28] GPIO[64] D[28] LCD_VD[20] 120 VDD33 VDD33 121 D[27] GPIO[63] D[27] LCD_VD[19] 122 D[26] GPIO[62] D[26] LCD_VD[18] 123 D[25] GPIO[61] D[25] LCD_VD[17] 124 D[24] GPIO[60] D[24] LCD_VD[16] 125 nECS[3] nECS[3] 126 VSS33 VSS33 127 VDD33 VDD33 128 nECS[2] nECS[2] 129 nECS[1] nECS[1] 130 nECS[0] nECS[0] 131 nOE nOE 132 nWAIT GPIO[71] nWAIT IRQ5 133 nBTCS nBTCS 134 MCKE MCKE

Publication Release Date: September 19, 2006 - 31 - Revision B2 Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 135 nSCS[0] nSCS[0] 136 nSCS[1] nSCS[1] 137 nSRAS nSRAS 138 nSCAS nSCAS 139 VDD33 VDD33 140 MCLK MCLK 141 VSS33 VSS33 142 nWE nWE 143 nWBE_SDQM[0] nWBE_SDQM[0] 144 nWBE_SDQM[1] nWBE_SDQM[1] 145 nWBE_SDQM[2] GPIO[69] nWBE_SDQM[2] 146 nWBE_SDQM[3] GPIO[68] nWBE_SDQM[3] 147 GPIO[18] GPIO[18] nIRQ[2] 148 GPIO[19] GPIO[19] nIRQ[3] 149 GPIO[59] GPIO[59] D[23] LCD_VD[15] 150 D[22] GPIO[58] D[22] LCD_VD[14] 151 D[21] GPIO[57] D[21] LCD_VD[13] 152 D[20] GPIO[56] D[20] LCD_VD[12] 152 D[20] GPIO[56] D[20] LCD_VD[12] 153 D[19] GPIO[55] D[19] LCD_VD[11] 154 D[18] GPIO[54] D[18] LCD_VD[10] 155 D[17] GPIO[53] D[17] LCD_VD[9] 156 D[16] GPIO[52] D[16] LCD_VD[8] 157 VSS18 VSS18 158 D[15] D[15] 159 D[14] D[14] 160 VDD18 VDD18 161 D[13] D[13] 162 D[12] D[12]

32 - Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 Memory Address/Data/Control 163 D[11] D[11] 164 D[10] D[10] 165 VDD33 VDD33 166 D[9] D[9] 167 D[8] D[8] 168 D[7] D[7] 169 D[6] D[6] 170 D[5] D[5] 171 VSS33 VSS33 172 D[4] D[4] 173 D[3] D[3] 174 D[2] D[2] 175 D[1] D[1] 176 D[0] D[0]

Publication Release Date: September 19, 2006 - 33 - Revision B2 6. FUNCTIONAL DESCRIPTION

6.1 ARM7TDMI CPU CORE

The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of general- purpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. The high instruction throughput and impressive real-time interrupt response are the major benefits. The ARM7TDMI CPU core has two instruction sets: (1) The standard 32-bit ARM set (2) A 16-bit THUMB set The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers are used to speed up exception processing. All the register specified in ARM instructions can address any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt, memory aborts, attempted execution of an undefined instruction and software interrupts. Address Register Address Incrementer Barrel Shifter Register Bank (31 x 32-bit registers) (6 status registers) 32 x8 Multiplier 32-bit ALU Writer Data Register Instruction Pipeline Read Data Register Thumb Instruction Decoder Instruction Decoder Control Logic Scan Control B Bus A Bus ALU Bus PC Bus Incrementer Bus A[31:0] D[31:0] Fig 6.1 ARM7TDMI CPU Core Block Diagram

34 -

6.2 System Manager

6.2.1 Overview The W90P710 System Manager has the following functions. y System memory map y Data bus connection with external memory y Product identifier register y Bus arbitration y PLL module y Clock select and power saving control register y Power-On setting 6.2.2 System Memory Map W90P710 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the On- Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable space: 0x0000_0000 ~ 0x7FDF_FFFF if Cache ON; non-cacheable space: 0x8000_0000 ~ 0xFFDF_FFFF). The size and location of each bank is determined by the register settings for “current bank base address pointer” and “current bank size”. Please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You can use bank control registers to assign a specific bank start address by setting the bank’s base pointer (13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer << 18” and the bank’s size is “current bank size”. In the event of an access requested to an address outside any programmed bank size, an abort signal is generated. The maximum accessible memory size of each external IO bank is 16M bytes (by word format), and 64M bytes on each SDRAM bank.

Publication Release Date: September 19, 2006 - 35 - Revision B2 ROM/FLASH 256KB - 16MB SDRAM Bank 0 2MB - 64MB SDRAM Bank 1 2MB - 64MB External I/O Bank 0 256KB - 16MB External I/O Bank 1 256KB - 16MB External I/O Bank 2 256KB - 16MB External I/O Bank 3 256KB - 16MB RESERVED RESERVED 8KB 512KB (Fixed) 0x7FF8.0000 0x0000_0000 0x7FFF_FFFF RESERVED 0x7FE0_0000 RESERVED 512KB (Fixed) 0x7FF0_0000 EBI Space ROM/FLASH 256KB - 32MB SDRAM Bank 0 2MB - 64MB SDRAM Bank 1 2MB - 64MB External I/O Bank 0 256KB - 16MB External I/O Bank 1 256KB - 16MB External I/O Bank 2 256KB - 16MB External I/O Bank 3 256KB - 16MB On-Chip RAM 4KB,4KB On-Chip APB Peripherals 8KB 512KB (Fixed) 0xFFF8_0000 0x8000_0000 0xFFFF_FFFF RESERVED 0xFFE0_0000 On-Chip AHB Peripherals 512KB (Fixed) 0xFFF0_0000 EBI Space Cacheable space Non-Cacheable space Fig6.2.1 System Memory Map

36 - Table 6.2.1 On-Chip Peripherals Memory Map BASE ADDRESS

0xFFF0_0000 Product Identifier Register (PDID) 0xFFF0_0004 Arbitration Control Register (ARBCON) 0xFFF0_0008 PLL Control Register 0(PLLCON0) 0xFFF0_000C Clock Select Register (CLKSEL) 0xFFF0_0010 PLL Control Register 1 (PLLCON1) 0xFFF0_0014 Audio IIS Clock Control Register (I2SCKCON) 0xFFF0_0020 IRQ Wakeup Control Register (IRQWAKEUPCON) 0xFFF0_0024 IRQ Wakeup Flag Register (IRQWAKEFLAG) 0xFFF0_0028 Power Manager Control Register (PMCON) 0xFFF0_0030 USB Transceiver Control Register (USBTXRCON) 0xFFF0_1000 EBI Control Register (EBICON) Control Registers 0xFFF0_1004 ROM/FLASH (ROMCON) Control Registers 0xFFF0_1008 SDRAM bank 0 – 1 Control Registers 0xFFF0_1018 External I/O 0 – 3 Control Registers 0xFFF0_2000 Cache Controller Control Registers 0xFFF0_3000 Ethernet MAC Controller Control Registers 0xFFF0_4000 GDMA 0 – 1 Control Registers 0xFFF0_5000 USB Host Controller Control Registers 0xFFF0_6000 USB Device Controller Control Registers 0xFFF0_7000 SD Host Controller Control Registers 0xFFF0_8000 LCD Controller Control Registers 0xFFF0_9000 AC97/I2S Controller Control Registers APB Peripherals 0xFFF8_0000 UART 0 (Tx, RX for console) 0xFFF8_0100 UART 1 (Tx, Rx, for blue-tooth) 0xFFF8_0200 UART 2 (blue-tooth CTS, RTS/ IrDA Tx, Rx) 0xFFF8_0300 UART 3 (micro-print DTR, DTS, Tx, Rx) 0xFFF8_1000 Timer 0 – 1, WDOG Timer 0xFFF8_2000 Interrupt Controller 0xFFF8_3000 GPIO 0xFFF8_4000 Real Time Clock Controller Control Registers (RTC) 0xFFF8_5000 Smart Card Host Interface Control Registers (SCHI) 0xFFF8_6000 I2C-0 Control Registers 0xFFF8_6100 I2C-1 Control Registers 0xFFF8_6200 USI Control Registers

Publication Release Date: September 19, 2006 - 37 - Revision B2 Table 6.2.1 On-Chip Peripherals Memory Map (Continued) BASE ADDRESS 0xFFF8_7000 Pulse Width Modulation (PWM) Control Registers 0xFFF8_8000 KeyPad Interface Control Register (KPI) 0xFFF8_9000 PS2 Control Registers 6.2.3 Address Bus Generation The W90P710 address bus generation is depended on the required data bus width of each memory bank. The data bus width is determined by DBWD bits in each bank’s control register. The maximum accessible memory size of each external IO bank is 16M bytes. Table 6.2.2 Address Bus Generation Guidelines DATA BUS EXTERNAL ADDRESS PINS WIDTH A [21:0] MAXIMUM ACCESSIBLE MEMORY SIZE 8-bit A21 – A0 (Internal) 4M bytes 16-bit A22 – A1 (Internal) 4M half-words 32-bit A23 – A2 (Internal) 4M words 6.2.4 Data Bus Connection with External Memory 6.2.4.1 Memory formats The W90P710 can be configured as big endian or little endian mode by pull up or down the external data bus D14 pin. If D14 is pull-up then it is a little endian mode, otherwise, it is a big endian mode. Little endian In little endian format, the lowest addressed byte in a word is considered the least significant byte of the word and the highest addressed byte is the most significant. So the byte at address 0 of the memory system connects to data lines 7 through 0. For a word aligned address A, Fig6.2.2 shows how the word at address A, the half-word at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when D14 pin is High. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Word at address A Half-word at address A+2 Half-word at address A Byte at address A+3 Byte at address A+2 Byte at address A+1 Byte at address A Fig6.2.2 Little endian addresses of bytes and half-words within words

38 - Big endian In Big endian format, the W90P710 stores the most significant byte of a word at the lowest numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects to data lines 31 through 24. For a word aligned address A, Fig6.2.3 shows how the word at address A, the half-word at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Word at address A Half-word at address A Half-word at address A+2 Byte at address A Byte at address A+1 Byte at address A+2 Byte at address A+3 Fig6.2.3 Big endian addresses of bytes and half-words within words 6.2.4.2 Connection of External Memory with Various Data Width The system diagram for W90P710 connecting with the external memory is shown in Fig6.2.4. Below tables (Table6.2.3 through Table6.2.14) show the program/data path between CPU register and the external memory using little / big endian and word/half-word/byte access. Fig6.2.4 Address/Data bus connection with external memory W90P710

Publication Release Date: September 19, 2006 - 39 - Revision B2 Fig6.2.5 CPU registers Read/Write with external memory Table 6.2.3 and Table 6.2.4 Using big-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.3 Word access write operation with Big Endian ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA WA WA WA Bit Number SD 31 0 ABCD 31 0 AB CD 31 0 A B C D Bit Number ED 31 0 ABCD 15 0 AB 15 0 CD 7 0 A 7 0 B 7 0 C 7 0 D XA WA WA WA+2 WA WA+1 WA+2 WA+3 nWBE [3-0] / SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA Bit Number XD 31 0 ABCD 15 0 AB 15 0 CD 7 0 A 7 0 B 7 0 C 7 0 D Bit Number Ext. Mem Data 31 0 ABCD 15 0 AB 15 0 CD 7 0 A 7 0 B 7 0 C 7 0 D Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write

40 - Table6.2.4 Word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 31 0 ABCD 31 0 CDAB 31 0 DCBA SA WA WA WA Bit Number SD 31 0 ABCD 31 0 CD AB 31 0 D C B A Bit Number ED 31 0 ABCD 31 0 CD XX 31 0 CD AB 31 0 D X X X 31 0 D C X X 31 0 D C B X 31 0 D C B A XA WA WA WA+2 WA WA+1 WA+2 WA+3 SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA Bit Number XD 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A Timing Sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read Table 6.2.5 and Table 6.2.6 Using big-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0,2,4,6,8,A,C,E HAL = Address whose LSB is 0,4,8,C HAU = Address whose LSB is 2,6,A,E X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.5 Half-word access write operation with Big Endian ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA HAL HAU HA HA Bit Number SD 31 0 CD CD 31 0 CD CD 31 0 CD CD 31 0 CD CD 31 0 CD CD Bit Number ED 31 0 CD CD 31 0 CD CD 31 0 CD CD 7 0 C 7 0 D XA HAL HAL HA HA HA+1 nWBE [3-0] / SDQM [3-0] AAUU UUAA XXAA XXXA XXXA Bit Number XD 31 0 CD CD 31 0 CD CD 15 0 CD 7 0 C 7 0 D Bit Number Ext. Mem Data 31 16 CD 15 0 CD 15 0 CD 7 0 C 7 0 D Timing Sequence 1st write 2nd write

Publication Release Date: September 19, 2006 - 41 - Revision B2 Table6.2.6 Half-word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 15 0 AB 15 0 CD 15 0 CD 15 0 DC SA HAL HAU HA HA Bit Number SD 15 0 AB 15 0 CD 15 0 CD 15 0 DC Bit Number ED 15 0 AB 15 0 CD 15 0 CD 15 0 DX 15 0 DC XA HAL HAL HA HA HA+1 SDQM [3-0] AAUU UUAA XXAA XXXA XXXA Bit Number XD 31 0 AB CD 31 0 AB CD 15 0 CD 7 0 D 7 0 C Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 7 0 D 7 0 C Timing Sequence 1st read 2nd read Table 6.2.7 and Table 6.2.8 Using big-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F

42 - Table6.2.7 Byte access write operation with Big Endian ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA BA0 BA1 BA2 BA3 BAL BAU BA Bit Number SD 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D Bit Number ED 31 24 D 23 16 D 15 8 D 7 0 D 15 8 D 7 0 D 7 0 D XA BA0 BA0 BA0 BA0 BAL BAL BA nWBE [3-0] / SDQM [3-0] AUUU UAUU UUAU UUUA XXAU XXUA XXXA Bit Number XD 31 0 D X X X 31 0 X D X X 31 0 X X D X 31 0 X X X D 15 0 D X 15 0 X D 7 0 D Bit Number Ext. Mem Data 31 24 D 23 16 D 15 8 D 7 0 D 15 8 D 7 0 D 7 0 D Timing Sequence Table6.2.8 Byte access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 7 0 A 7 0 B 7 0 C 7 0 D 7 0 C 7 0 D 7 0 D SA BA0 BA1 BA2 BA3 BAL BAU BA Bit Number SD 7 0 A 7 0 B 7 0 C 7 0 D 7 0 C 7 0 D 7 0 D Bit Number ED 7 0 A 15 8 B 23 16 C 31 24 D 7 0 C 15 8 D 7 0 D XA BA0 BA0 BA0 BA0 BAL BAL BA SDQM [3-0] AUUU UAUU UUAU UUUA XXAU XXUA XXXA Bit Number XD 31 0 ABCD 31 0 ABCD 31 0 ABCD 31 0 ABCD 15 0 CD 15 0 CD 7 0 D Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 7 0 D Timing Sequence

Publication Release Date: September 19, 2006 - 43 - Revision B2 Table 6.2.9 and Table 6.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.9 Word access write operation with little Endian Access Operation Write Operation (CPU Register Î External Memory) XD Width Word Half Word Byte Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA WA WA WA Bit Number SD 31 0 ABCD 31 0 AB CD 31 0 A B C D Bit Number ED 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A XA WA WA WA+2 WA WA+1 WA+2 WA+3 nWBE [3-0] / SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA Bit Number XD 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write Table6.2.10 Word access read operation with Little Endian Access Operation Read Operation (CPU Register Í External Memory) XD Width Word Half Word Byte Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA WA WA WA Bit Number SD 31 0 ABCD 31 0 AB CD 31 0 A B C D Bit Number ED 31 0 ABCD 31 0 XX CD 31 0 AB CD 31 0 X X X D 31 0 X X C D 31 0 X B C D 31 0 A B C D XA WA WA WA+2 WA WA+1 WA+2 WA+3 SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA Bit Number XD 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 15 0 AB 7 0 D 7 0 C 7 0 B 7 0 A Timing Sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read

44 - Table 6.2.11 and Table 6.2.12 Using little-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0,2,4,6,8,A,C,E HAL = Address whose LSB is 0,4,8,C HAU = Address whose LSB is 2,6,A,E X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.11 Half-word access write operation with little Endian Access Operation Write Operation (CPU Register Î External Memory) XD Width Word Half Word Byte Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA HAL HAU HA HA Bit Number SD 31 0 CD CD 31 0 CD CD 31 0 CD CD 31 0 CD CD 31 0 CD CD Bit Number ED 31 0 CD CD 31 0 CD CD 31 0 CD CD 7 0 D 7 0 C XA HAL HAL HA HA HA+1 nWBE [3-0] / SDQM [3-0] UUAA AAUU XXAA XXXA XXXA Bit Number XD 31 0 CD CD 31 0 CD CD 15 0 CD 7 0 D 7 0 C Bit Number Ext. Mem Data 15 0 CD 31 16 CD 15 0 CD 7 0 D 7 0 C Timing Sequence 1st write 2nd write Table6.2.12 Half-word access read operation with Little Endian Access Operation Read Operation (CPU Register Í External Memory) XD Width Word Half Word Byte Bit Number CPU Reg Data 15 0 CD 15 0 AB 15 0 CD 15 0 CD SA HAL HAU HA HA Bit Number SD 15 0 CD 15 0 AB 15 0 CD 15 0 CD Bit Number ED 15 0 CD 15 0 AB 15 0 CD 15 0 XD 15 0 CD XA HAL HAL HA HA HA+1 SDQM [3-0] UUAA AAUU XXAA XXXA XXXA Bit Number XD 31 0 AB CD 31 0 AB CD 15 0 CD 7 0 D 7 0 C Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 7 0 D 7 0 C Timing Sequence 1st read 2nd read

Publication Release Date: September 19, 2006 - 45 - Revision B2 Table 6.2.13 and Table 6.2.14 Using little-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F Table6.2.13 Byte access write operation with little Endian Access Operation Write Operation (CPU Register Î External Memory) XD Width Word Half Word Byte Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD 31 0 ABCD SA BA0 BA1 BA2 BA3 BAL BAU BA Bit Number SD 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D 31 0 D D D D Bit Number ED 7 0 D 15 8 D 23 16 D 31 24 D 7 0 D 15 8 D 7 0 D XA BA0 BA0 BA0 BA0 BAL BAL BA nWBE [3-0] / SDQM [3-0] UUUA UUAU UAUU AUUU XXUA XXAU XXXA Bit Number XD 31 0 X X X D 31 0 X X D X 31 0 X D X X 31 0 D X X X 15 0 X D 15 0 D X 7 0 D Bit Number Ext. Mem Data 7 0 D 15 8 D 23 16 D 31 24 D 7 0 D 15 8 D 7 0 D Timing Sequence Table6.2.14 Byte access read operation with Little Endian Access Operation Read Operation (CPU Register Í External Memory) XD Width Word Half Word Byte Bit Number CPU Reg Data 7 0 D 7 0 C 7 0 B 7 0 A 7 0 D 7 0 C 7 0 D SA BA0 BA1 BA2 BA3 BAL BAU BA Bit Number SD 7 0 D 7 0 C 7 0 B 7 0 A 7 0 D 7 0 C 7 0 D Bit Number ED 7 0 D 7 0 C 7 0 B 7 0 A 7 0 D 7 0 C 7 0 D XA BA0 BA0 BA0 BA0 BAL BAL BA SDQM [3-0] UUUA UUAU UAUU AUUU XXUA XXAU XXXA Bit Number XD 31 0 ABCD 31 0 ABCD 31 0 ABCD 31 0 ABCD 15 0 CD 15 0 CD 7 0 D Bit Number Ext. Mem Data 31 0 ABCD 15 0 CD 7 0 D Timing Sequence

46 - 6.2.5 Bus Arbitration The W90P710’s internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data transfers. Because the design of W90P710 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership. When bus mastership is granted to an internal function block or an external device, other pending requests are not acknowledged until the previous bus master has released the bus. W90P710 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode, depends on the ARBCON register PRTMOD bit setting. 6.2.5.1 Fixed Priority Mode In Fixed Priority Mode (PRTMOD=0, default value), to facilitate bus arbitration, priorities are assigned to each internal W90P710 function block. The bus controller arbitration requests for the bus mastership according to these fixed priorities. In the event of contention, mastership is granted to the function block with the highest assigned priority. These priorities are listed in Table 6.2.15. W90P710 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit 1 of the Arbitration Control Register (ARBCON), is set to “0”, the priority of ARM Core is fixed to lowest. If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still lowest and the IPACT=0, Bit 2 of the Arbitration Control Register (ARBCON) ； If there is an unmasked interrupt request, then the ARM Core’s priority is raised to first and IPACT=1. If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in the interrupt handler. The IPACT bit can be read and written. Writing with “0”, the IPACT bit is cleared, but it will be no effect as writing with “1”. Table 6.2.15 Bus Priorities for Arbitration in Fixed Priority Mode BUS FUNCTION BLOCK PRIORITY IPACT = 0 IPEN = 1 AND IPACT = 1 1 (Highest) Audio Controller (AC97 & I2S) ARM Core LCD Audio Controller (AC97 & I2S) General DMA0 LCD Controller General DMA1 General DMA0 EMC DMA General DMA1 SD EMC DMA USB Host SD USB Device USB Host 9(Lowest) ARM Core USB Device

Publication Release Date: September 19, 2006 - 47 - Revision B2 6.2.5.2 Rotate Priority Mode In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored). W90P710 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain the bus and that a retracted master does not lock up the bus. 6.2.6 Power management W90P710 provide three power management scenarios to reduce power consumption. The peripherals’ clocks can be enabled / disabled individually by controlling the co-responding bit in CLKSEL control register. Software can turn-off the unused modules’ clocks to saving the unnecessary power consumption. It also provides idle and power-down modes to reduce power consumption. Crystal Oscillator 480MHz PLL 16-bit Counter CLKS HCLK IDLE MIDLE PD HCLK_cache HCLK_memc HCLK_EMC EXTAL XTAL EnEMCclk EnLCDclk HCLK_LCD W90P710 Clock Generator Fig. 6.2.6 W90P710 system clock generation diagram IDLE MODE If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock to cache controller and ARM are stopped. W90P710 will exit idle state when nIRQ or nFIQ from any peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also be forced to enter idle state if both MIDLE and IDLE bits are set. Software must switch SDRAM into self-refresh mode before forcing memory to enter idle mode.

48 - FOUT (PLL) HCLK idle_state MCLK (ARM) HCLK (cache) IDLE Period HCLK (memc) Case1. IDLE=1, PD=0, MIDLE=0 Fig. 6.2.7 Clock management for system idle mode FOUT (PLL) HCLK idle_state MCLK (ARM) HCLK (cache) IDLE Period HCLK (memc) Case2. IDLE=1, PD=0, MIDLE=1 Fig. 6.2.8 Clock management for system and memory idle mode Power Down Mode This mode provides the minimum power consumption. When the W90P710 system is not working or waiting an external event, software can write PD bit “1” to turn off all the clocks includes system crystal oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode since the clock source is stopped. W90P710 will exit power down state when nIRQ/nFIQ is detected. W90P710 provides external interrupt nIRQ[3:0], keypad, and USB device interfaces to wakeup the system clock.

Publication Release Date: September 19, 2006 - 49 - Revision B2 HCLK (cache) Case3. IDLE=0, PD=1, MIDLE=0 EXTAL idle _state pd_state 65536 clocks HCLK wake up by pheripheral's interrupts Fig 6.2.9 Clock management for system power down mode and wake up 6.2.7 Power-On Setting After power on reset, there are eight Power-On setting pins to configure W90P710 system configuration. POWER-ON SETTING PIN Internal System Clock Select D15 Little/Big Endian Mode Select D14 Boot ROM/FLASH Data Bus Width D [13:12] Default (Always pull-up in normal operation) D [11:8] D15 pin：Internal System Clock Select If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock. If pin D15 is pull-up, the PLL output clock is used as internal system clock. D14 pin：Little/Big Endian Mode Select If pin D14 is pull-down, the external memory format is Big Endian mode. If pin D14 is pull-up, the external memory format is Little Endian mode. D [13:12] ： Boot ROM/FLASH Data Bus Width D [13:12] BUS WIDTH Pull-down Pull-down 8-bit Pull-down Pull-up 16-bit Pull-up Pull-down 32-bit Pull-up Pull-up RESERVED

50 - 6.2.8 System Manager Control Registers Map REGISTER ADDRESS R/W

0xFFF0_0000 R Product Identifier Register 0xX090_0710 ARBCON 0xFFF0_0004 R/W Arbitration Control Register 0x0000_0000 PLLCON0 0xFFF0_0008 R/W PLL Control Register 0 0x0000_2F01 CLKSEL 0xFFF0_000C R/W Clock Select Register 0x1FFF_3FX8 PLLCON1 0xFFF0_0010 R/W PLL Control Register 1 0x0001_0000 I2SCKCON 0xFFF0_0014 R/W Audio IIS Clock Control Register 0x0000_0000 IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register 0x0000_0000 IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register 0x0000_0000 PMCON 0xFFF0_0028 R/W Power Manager Control Register 0x0000_0000 USBTxrCON 0xFFF0_0030 R/W USB Transceiver Control Register 0x0000_0000 Product Identifier Register （PDID） This register is read only and lets software use to recognize certain characteristics of the chip ID and the version number. REGISTER ADDRESS R/W 0xFFF0_0000 R Product Identifier Register 0xX090_0710 PACKAGE VERSION CHPID CHPID CHPID

Publication Release Date: September 19, 2006 - 51 - Revision B2 BITS [31:30] PACKAGE Package Type Select These two bits are power-on setting latched from pin D[9:8] Package [31:30] Package Type 176-pin Package [29:24] VERSION Version of chip [23:0] CHIPID The chip identifier 0x090.0710 Arbitration Control Register (ARBCON) REGISTER ADDRESS R/W 0xFFF0_0004 R/W Arbitration Control Register 0x0000_0000 RESERVED RESERVED RESERVED RESERVED IPACT IPEN PRTMOD BITS [31:3] RESERVED [2] IPACT Interrupt priority active. When IPEN=”1”, this bit will be set when the ARM core has an unmasked interrupt request. This bit is available only when the PRTMOD=0. [1] IPEN Interrupt priority enable bit 0 = the ARM core has the lowest priority. 1 = enable to raise the ARM core priority to second This bit is available only when the PRTMOD=0. [0] PRTMOD Priority mode select 0 = Fixed Priority Mode (default) 1 = Rotate Priority Mode

52 - PLL Control Register0 （PLLCON0） W90P710 provides two clock generation options – crystal and oscillator. The external clock via EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock for the internal system clock, D15 pin must be pull-up. REGISTER ADDRESS R/W

0xFFF0_0008 R/W PLL Control Register 0x0000_2F01 RESERVED RESERVED PWDEN FBDV FBDV OTDV INDV BITS [31:17] RESERVED [16] PWDEN Power down mode enable 0 = PLL is in normal mode (default) 1 = PLL is in power down mode [15:7] FBDV PLL VCO output clock feedback divider Feedback Divider divides the output clock from VCO of PLL. [6:5] OTDV PLL output clock divider OTDV [6:5] DIVIDED BY [4:0] INDV PLL input clock divider Input divider divides the input reference clock into the PLL.

Publication Release Date: September 19, 2006 - 53 - Revision B2 Input Divider (NR) PFD Feedback Divider (NF) Charge Pump VCO Output Divider (NO) Clock Divider Selector EXTAL ECLKS OTDV[1:0] CLKS[2:0] PLL Internal System Clock INDV[4:0] FBDV[8:0] 48MHz Gen 480MHz USBCKS USB Module FIN FOUT GP0 Fig 6.2.8.1 System PLL block diagram The formula of output clock of PLL is: FOUT = FIN NO NR NF FOUT：Output clock of Output Divider FIN：External clock into the Input Divider NR：Input divider value (NR = INDV + 2) NF：Feedback divider value (NF = FBDV + 2) NO：Output divider value (NO = OTDV) Clock Select Register (CLKSEL) REGISTER ADDRESS R/W 0xFFF0_000C R/W Clock Select Register 0x1FFF_7FX8 RESERVED PS2 KPI SCH1 SCH0 SSP UART3 UART2 UART1 I2C1 I2C0 RTC PWM AC97 USBCKS USBD GDMA SD LCD EMC RESERVED WDT USBH TIMER UART ECLKS CLKS RESET

54 - BITS

[31:29] RESERVED [28] PS2 PS2 controller clock enable bit 0 = Disable PS2 controller clock 1 = Enable PS2 controller clock [27] KPI Keypad controller clock enable bit 0 = Disable keypad controller clock 1 = Enable keypad controller clock [26] SCH1 Smart Card Host controller 1 clock enable bit 0 = Disable smart card host controller 1 clock 1 = Enable smart card host controller 1 clock [25] SCH0 Smart Card Host controller 0 clock enable bit 0 = Disable smart card host controller 0 clock 1 = Enable smart card host controller 0 clock [24] USI USI controller clock enable bit 0 = Disable USI controller clock 1 = Enable USI controller clock [23] UART3 UART3 controller clock enable bit 0 = Disable UART3 controller clock 1 = Enable UART3 controller clock [22] UART2 UART2 controller clock enable bit 0 = Disable UART2 controller clock 1 = Enable UART2 controller clock [21] UART1 UART1 controller clock enable bit 0 = Disable UART1 controller clock 1 = Enable UART1 controller clock [20] I2C1 I2C1 controller clock enable bit 0 = Disable I2C1 controller clock 1 = Enable I2C1 controller clock [19] I2C0 I2C0 controller clock enable bit 0 = Disable I2C0 controller clock 1 = Enable I2C0 controller clock [18] RTC RTC unit clock enable bit 0 = Disable RTC controller clock 1 = Enable RTC controller clock

Publication Release Date: September 19, 2006 - 55 - Revision B2 Continued. BITS [17] PWM PWM controller clock enable bit 0 = Disable PWM controller clock 1 = Enable PWM controller clock [16] AC97 Audio Controller clock enable bit 0 = Disable AC97 controller clock 1 = Enable AC97 controller clock [15] USBCKS USB host/device 48MHz clock source Select bit 0 = USB clock 48MHz input from internal PLL (480MHz/10) 1 = USB clock 48MHz input from external GPIO0 pin, this pin direction must set to input. [14] USBD USB device clock enable bit 0 = Disable USB device controller clock 1 = Enable USB device controller clock [13] GDMA GDMA controller clock enable bit 0 = Disable GDMA clock 1 = Enable GDMA clock [12] SD SD host controller clock enable bit 0 = Disable SD controller clock 1 = Enable SD controller clock [11] LCD LCD controller clock enable bit 0 = Disable LCD controller clock 1 = Enable LCD controller clock [10] EMC EMC controller clock enable bit 0 = Disable EMC controller clock 1 = Enable EMC controller clock [9] RESERVED [8] WDT WDT clock enable bit 0 = Disable WDT counting clock 1 = Enable WDT counting clock [7] USBH USB host clock enable bit 0 = Disable USB host controller clock 1 = Enable USB host controller clock [6] TIMER Timer clock enable bit 0 = Disable timer clock 1 = Enable timer clock

56 - Continued. BITS

[5] UART0 UART0 controller clock enable bit 0 = Disable UART0 controller clock 1 = Enable UART0 controller clock [4] ECLKS External clock select 0 = External clock from EXTAL pin is used as system clock 1 = PLL output clock is used as system clock After power on reset, the content of ECLKS is the Power-On Setting value. You can program this bit to change the system clock source. [3:1] CLKS PLL output clock select CLKS [3:1] System clock

58.594 KHz*

24 MHz

48 MHz

60 MHz

80 MHz

Note: 1. This values are based on PLL output(FOUT) is 480MHz. 2. When 24Mhz ~ 80MHz is selected, the ECLKS bit must be set to 1. 3. About 58.594KHz setting, two steps are needed. First, clear ECLKS bit, and then clear CLKS. [0] RESET Software Reset bit This is a software reset control bit. Set logic 1 to generate an internal reset pulse. This bit is auto-clear to logic 0 at the end of the reset pulse.

Publication Release Date: September 19, 2006 - 57 - Revision B2 PLL Control Register 1（PLLCON1） W90P710 provides extra PLL for LCD controller programmable pixel clock and provide 12.288/16.934 MHz clock source to Audio Controller. It uses the same 15MHz crystal clock input source with system PLL mentioned above. REGISTER ADDRESS R/W 0xFFF0_0010 R/W PLL Control Register 1 0x0001_0000 RESERVED RESERVED PWDEN1 FBDV1 FBDV1 OTDV1 INDV1 BITS [31:17] RESERVED [16] PWDEN1 PLL1 power down enable 0 = PLL1 is in normal mode 1 = PLL1 is in power down mode (default) [15:7] FBDV1 PLL1 VCO output clock feedback divider Feedback Divider divides the output clock from VCO of PLL1. [6:5] OTDV1 PLL1 output clock divider OTDV1 [6:5] Divided by [4:0] INDV1 PLL1 input clock divider Input divider divides the input reference clock into the PLL1.

58 - Input Divider (NR) PFD Feedback Divider (NF) Charge Pump VCO Output Divider (NO) EXTAL OTDV1[1:0] PLL1 INDV1[4:0] FBDV1[8:0] 480MHz FIN FOUT to LCD controller to Audio Controller Fig 6.2.8.2 LCD PLL block diagram The formula of output clock of PLL is: FOUT = FIN NO NR NF FOUT：Output clock of Output Divider FIN：External clock into the Input Divider NR：Input divider value (NR = INDV1 + 2) NF：Feedback divider value (NF = FBDV1 + 2) NO：Output divider value (NO = OTDV1)

Publication Release Date: September 19, 2006 - 59 - Revision B2 IIS Clock Control Register (I2SCKCON) REGISTER ADDRESS R/W I2SCKCON 0xFFF0_0014 R/W I2S PLL clock Control Register 0x0000_0000 RESERVED RESERVED RESERVED IISPLLEN PRESCALE BITS [31:9] RESERVED [8] I2SPLLEN IIS PLL clock source enable Set this bit will enable PLL1 clock output to audio I2S clock input. 1 = Enable PLL1 clock source for audio I2S 0 = Disable PLL1 clock source for audio I2S [7:0] PRESCALE The PLL1 is shared with LCD controller, if both the LCD and I2S are using the PLL at the same time, software can using this prescaler to generate an appropriate clock nearly 12.288M or 16.934M. The clock is generated as below, and if PRESCALE =0, the PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO = PLL_FOUT/(PRESCALE +1)” IRQ Wakeup Control Register (IRQWAKECON) REGISTER ADDRESS R/W 0xFFF0_0020 R/W IRQ Wakeup Control Register 0x0000_0000 RESERVED RESERVED RESERVED IRQWAKEUPPOL IRQWAKEUPEN

60 - BITS

[31:8] RESERVED [7] IRQWAKEUPPOL[3] nIRQ3 wake up polarity 1 = nIRQ3 is high level wake up 0 = nIRQ3 is low level wake up [6] IRQWAKEUPPOL[2] nIRQ2 wake up polarity 1 = nIRQ2 is high level wake up 0 = nIRQ2 is low level wake up [5] IRQWAKEUPPOL[1] nIRQ1 wake up polarity 1 = nIRQ1 is high level wake up 0 = nIRQ1 is low level wake up [4] IRQWAKEUPPOL[0] nIRQ0 wake up polarity 1 = nIRQ0 is high level wake up 0 = nIRQ0 is low level wake up [3] IRQWAKEUPEN[3] nIRQ3 wake up enable bit 1 = nIRQ3 wake up enable 0 = nIRQ3 wake up disable [2] IRQWAKEUPEN[2] nIRQ2 wake up enable bit 1 = nIRQ2 wake up enable 0 = nIRQ2 wake up disable [1] IRQWAKEUPEN[1] nIRQ1 wake up enable bit 1 = nIRQ1 wake up enable 0 = nIRQ1 wake up disable [0] IRQWAKEUPEN[0] nIRQ0 wake up enable bit 1 = nIRQ0 wake up enable 0 = nIRQ0 wake up disable IRQ Wakeup Flag Register (IRQWAKEFLAG) REGISTER ADDRESS R/W IRQWAKEFLAG 0xFFF0_0024 R/W IRQ Wakeup Flag Register 0x0000_0000

Publication Release Date: September 19, 2006 - 61 - Revision B2 RESERVED RESERVED RESERVED RESERVED IRQWAKEFLAG This register is used to record the wakeup events, after clock recovery, software should check these flags to identify which nIRQ is used to wakeup the system. And clear the flags in IRQ interrupt sevice routine. BITS [31:4] RESERVED [3] IRQWAKEFLAG[3] nIRQ3 wake up flag 1 = Chip is waked up by nIRQ3 0 = No active [2] IRQWAKEFLAG[2] nIRQ2 wake up flag 1 = Chip is waked up by nIRQ2 0 = No active [1] IRQWAKEFLAG[1] nIRQ1 wake up flag 1 = Chip is waked up by nIRQ1 0 = No active [0] IRQWAKEFLAG[0] nIRQ0 wake up flag 1 = Chip is waked up by nIRQ0 0 = No active Power Management Control Register (PMCON) REGISTER ADDRESS R/W 0xFFF0_0028 R/W Power Management Control Register 0x0000_0000 RESERVED RESERVED RESERVED RESERVED MIDLE PD IDLE

62 - BITS

[31:3] RESERVED [2] MIDLE Memory controller IDLE enable Setting both MIDLE and IDLE bits HIGH will let memory controller enter IDLE mode, the clock source of memory controller will be halted while ARM CORE enter IDLE mode. 1=memory controller will be forced into IDLE mode, (clock of memory controller will be halted), when IDLE bit is set. 0 = memory controller still active when IDLE bit is set. NOTE: Software must let SDRAM enter self-refresh mode before enable this function because SDRAM MCLK will be stopped. [1] PD Power down enable Setting this bit HIGH will let W90P710 enter power saving mode. The clock source 15M crystal oscillator and PLLs are stopped to generate clock. User can use nIRQ[3:0], keypad and external RESET to wakeup W90P710. 1 = Enable power down 0 = Disable [0] IDLE IDLE mode enable Setting this bit HIGH will let ARM Core enter power saving mode. The peripherals can still keep working if the clock enable bit in CLKSEL is set. Any nIRQ or nFIQ to ARM Core will let ARM CORE to exit IDLE state. 1 = IDLE mode 0 = Disable USB Transceiver Control Register (USBTXRCON) REGISTER ADDRESS R/W N 0xFFF0_0030 R/W USB Transceiver Control Register 0x0000_0000 RESERVED RESERVED RESERVED RESERVED USBHnD

Publication Release Date: September 19, 2006 - 63 - Revision B2 BITS [31:1] RESERVED [0] USBHnD USBHnD[0]: USB transceiver control There are two USB1.1 built-in transceivers for data transmission. One is dedicated for USB host and the other is shared with USB device. Software can program this bit to switch the transceiver path. 1 = HOST 0 = Device

64 -

6.3 External Bus Interface

6.3.1 EBI Overview W90P710 supports External Bus Interface (EBI), which controls the access to the external memory (ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 22 bits. It supports 8-bit, 16-bit, and 32-bit external data bus width for each bank. The EBI has the following functions： y SDRAM controller y EBI control register y ROM/FLASH interface y External I/O interface y External bus mastership 6.3.2 SDRAM Controller The SDRAM controller module within W90P710 contains configuration registers 、 timing control registers、common control register and other logic to provide 8、16、32 bits SDRAM interface with a single 8、16、32 bits SDRAM device or two 8-bit devices wired to give a 16-bit data path or two 16-bit devices wired to give a 32-bit data path. The maximum size of each bank is 64M bytes, and maximum memory size can span up to 128MB. The SDRAM controller has the following features： y Supports up to 2 external SDRAM banks y Maximum size of each bank is 64M bytes y 8、16、32-bit data interface y Programmable CAS Latency： 1、2 and 3 y Fixed Burst Length： 1 y Sequential burst type y Auto Refresh Mode and Self Refresh Mode y Adjustable Refresh Rate y Power up sequence

Publication Release Date: September 19, 2006 - 65 - Revision B2 6.3.2.1 SDRAM Components Supported Table 6.3.2.1 SDRAM supported by W90P710 SIZE TYPE BANKS ROW ADDRESSING COLUMN ADDRESSING 16M bits 2Mx8 RA0~RA10 CA0~CA8 1Mx16 RA0~RA10 CA0~CA7 64M bits 8Mx8 RA0~RA11 CA0~CA8 4Mx16 RA0~RA11 CA0~CA7 2Mx32 RA0~RA10 CA0~CA7 128M bits 16Mx8 RA0~RA11 CA0~CA9 8Mx16 RA0~RA11 CA0~CA8 4Mx32 RA0~RA11 CA0~CA7 256M bits 32Mx8 RA0~RA12 CA0~CA9 16Mx16 RA0~RA12 CA0~CA8 AHB Bus Address Mapping to SDRAM Bus Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used; The HADDR prefixes have been omitted on the following tables. A14 ~ A0 are the Address pins of the W90P710 EBI interface; A14 and A13 are the Bank Select Signals of SDRAM. SDRAM Data Bus Width: 32-bit Total Type R x C R/C A14 (BS1) A13 (BS0) A12 A11 A10 16M 2Mx8 11x9 R 11* C 11* AP 25* 16M 1Mx16 11x8 R 10* C 10* AP 25* 10* 64M 8Mx8 12x9 R 11* C 11* 23* AP 25* 64M 4Mx16 12x8 R 11* C 11* 23* AP 25* 24* 64M 2Mx32 11x8 R 11* 23* C 11* 23* AP 25* 24* 128M* 16Mx8 12x10 R 11* C 11* 23* AP 128M 8Mx16 12x9 R 11* C 11* 23* AP 25* 128M 4Mx32 12x8 R 11* C 11* 23* AP 25* 10* 256M* 32Mx8 13x10 R C 24* 23* AP 26* 256M* 16Mx16 13x9 R C 24* 23* AP 26* 10*

66 - SDRAM Data Bus Width: 16-bit Total Type R x C R/C A14 (BS1) A13 (BS0) A12 A11 A10 16M 2Mx8 11x9 R 10* C 10* AP 24* 16M 1Mx16 11x8 R C AP 24* 64M 8Mx8 12x9 R 10* C 10* 22* AP 24* 64M 4Mx16 12x8 R 10* C 10* 22* AP 24* 23* 64M 2Mx32 11x8 R 10* 22* C 10* 22* AP 24* 23* 128M 16Mx8 12x10 R 10* C 10* 22* AP 128M 8Mx16 12x9 R 10* C 10* 22* AP 24* 128M 4Mx32 12x8 R 10* C 10* 22* AP 24* 256M* 32Mx8 13x10 R C 23* 22* AP 25* 256M 16Mx16 13x9 R C 23* 22* AP 25*

Publication Release Date: September 19, 2006 - 67 - Revision B2 SDRAM Data Bus Width: 8-bit Total Type R x C R/C A14 (BS1) A13 (BS0) A12 A11 A10 16M 2Mx8 11x9 R C AP 23* 16M 1Mx16 11x8 R C AP 23* 64M 8Mx8 12x9 R C 21* AP 23* 64M 4Mx16 12x8 R C 21* AP 23* 22* 64M 2Mx32 11x8 R 21* C 21* AP 23* 22* 128M 16Mx8 12x10 R C 21* AP 128M 8Mx16 12x9 R C 21* AP 23* 128M 4Mx32 12x8 R C 21* AP 23* 256M 32Mx8 13x10 R C 22* 21* AP 256M 16Mx16 13x9 R C 22* 21* AP 24* 6.3.2.2 SDRAM Power Up Sequence The SDRAM must be initialized predefined manner after power on.W90P710 SDRAM Controller automatically executes the commands needed for initialion and set the mode register of each bank to default value. The default value is： — Burst Length = 1 — Burst Type = Sequential (fixed) — CAS Latency = 2 — Write Burst Length = Burst (fixed) The value of mode register can be changed after power up sequence by setting the value of corresponding bank’s configuration register “LENGTH” and “LATENCY” bits and set the MRSET bit enable to execute the Mode Register Set command.

68 - 6.3.2.3 SDRAM Interface M CLK M CK E n SC S[1 :0 ] n SR A S n S C A S n S W E n S D Q M [3 :0 ] A [2 1 :0 ] D [31 :0] A [1 0:0 ] D Q [[31 :0] D Q M [3:0 ] n W E nC A S nR A S n C S B S 0 B S 1 CLK C K E W 9 0 P 7 1 0 A 1 3 A 1 4 A [1 0:0 ] n SC S 0 S D R A M 6 4 M b 5 1 2 K x4 x3 2 n S D Q M [3 :0 ] Fig 6.3.1 SDRAM Interface 6.3.3 EBI Control Registers Map REGISTER ADDRESS R/W

0xFFF0_1000 R/W EBI control register 0x0001_0000 ROMCON 0xFFF0_1004 R/W ROM/FLASH control register 0x0000_0XFC SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800 SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800 SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000 SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000 EXT0CON 0xFFF0_1018 R/W External I/O 0 control register 0x0000_0000 EXT1CON 0xFFF0_101C R/W External I/O 1 control register 0x0000_0000 EXT2CON 0xFFF0_1020 R/W External I/O 2 control register 0x0000_0000 EXT3CON 0xFFF0_1024 R/W External I/O 3 control register 0x0000_0000 CKSKEW 0xFFF0_1F00 R/W Clock skew control register (for testing) 0xXXXX_0038

Publication Release Date: September 19, 2006 - 69 - Revision B2 EBI Control Register (EBICON) REGISTER ADDRESS R/W 0xFFF0_1000 R/W EBI control register 0x0001_0000 RESERVED EXBE3 EXBE2 EXBE1 EXBE0 RESERVED REFEN REFMOD CLKEN REFRAT REFRAT WAITVT LITTLE BITS [31:28] RESERVED [27] EXBE3 External IO bank 3 byte enable This function is used for some devices that with high and low bytes enable signals to control which byte will be write or mask data output when read. For this kind device, software can set this bit HIGH to implement this function. Detail pin interconnection is showed as Fig6.3.8. 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM. 0 = nWBE[3:0] pin is byte write strobe signal. [26] EXBE2 External IO bank 2 byte enable The bit function description is the same as EXBE3 above. 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM. 0 = nWBE[3:0] pin is byte write strobe signal. [25] EXBE1 External IO bank 1 byte enable The bit function description is the same as EXBE3 above. 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM 0 = nWBE[3:0] pin is byte write strobe signal

70 - Continued. BITS

[24] EXBE0 External IO bank 0 byte enable This bit function description is the same as EXBE3 above. 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM 0 = nWBE[3:0] pin is byte write strobe signal [23:19] RESERVED [18] REFEN Enable SDRAM refresh cycle for SDRAM bank0 & bank1 This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is according to REFRAT bits. 1 = Enable refresh function 0 = Disable refresh function [17] REFMOD Refresh mode of SDRAM for SDRAM bank Defines the refresh mode type of external SDRAM bank Software can write this bit “1” to force SDRAM enter self-refresh mode. 0 = Auto refresh mode 1 = Self refresh mode NOTE: If any read/write to SDRAM occurs then this bit will be cleared to “0” by hardware automatically and SDRAM will enter auto-refresh mode. [16] CLKEN Clock enable for SDRAM Enables the SDRAM clock enable (CKE) control signal 0 = Disable (power down mode) 1 = Enable （Default） [15:3] REFRAT Refresh count value for SDRAM The SDRAM Controller automatically provides an auto refresh cycle for every refresh period programmed into the REFRAT bits when the REFEN bit of each bank is set The refresh period is calculated as fMCLK value period =

Publication Release Date: September 19, 2006 - 71 - Revision B2 Continued. BITS [2:1] WAITVT Valid time of nWAIT signal W90P710 recognizes the nWAIT signal at the next “nth” MCLK rising edge after the nOE or nWBE active cycle. WAITVT bits determine the n. WAITVT [2:1] nth MCLK [0] LITTLE Little Endian mode After power on reset, the content of LITTLE is the Power-On Setting value from D14 pin. If pin D14 is pull-down, the external memory format is Big Endian mode. If pin D14 is pull-up, the external memory format is Little Endian mode. For more detail, refer to Power-On Setting of System Manager. NOTE: This bit is read only. ROM/Flash Control Register （ROMCON） REGISTER ADDRESS R/W 0xFFF0_1004 R/W ROM/FLASH control register 0x0000_0XFC BASADDR BASADDR SIZE RESERVED tPA tACC BTSIZE PGMODE

72 - BITS

[31:19] BASADDR Base address pointer of ROM/Flash bank The start address is calculated as ROM/Flash bank base pointer << 18. The base address pointer together with the “SIZE” bits constitutes the whole address range of each bank. [18:16] SIZE The size of ROM/FLASH memory SIZE [10:8] Byte 256K 512K 16M RESERVED [15:12] RESERVED [11:8] tPA Page mode access cycle time tPA[11:8] MCLK tPA[11:8] MCLK [7:4] tACC Access cycle time tACC[11:8] MCLK tACC[11:8] MCLK

Publication Release Date: September 19, 2006 - 73 - Revision B2 Continued. BITS [3:2] BTSIZE Boot ROM/FLASH data bus width This ROM/Flash bank is designed for a boot ROM. BASADDR bits determine its start address. The external data bus width is determined by the data bus signals D [13:12] power-on setting. BTSIZE [3:2] Bus Width D [13:12] Bus Width 8-bit Pull-down Pull-down 8-bit 16-bit Pull-down Pull-up 16-bit 32-bit Pull-up Pull-down 32-bit RESERVED Pull-up Pull-up RESERVED [1:0] PGMODE Page mode configuration PGMODE [1:0] Mode Normal ROM 4 word page 8 word page 16 word page Fig6.3.2 ROM/FLASH Read Operation Timing

74 - Fig 6.3.3 ROM/FLASH Page Read Operation Timing Configuration Registers（SDCONF0/1） The configuration registers enable software to set a number of operating parameters for the SDRAM controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1 respectively. Each bank can have a different configuration. REGISTER ADDRESS R/W

0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800 SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800 BASADDR BASADDR RESERVED MRSET RESERVED AUTOPR LATENCY RESERVED COMPBK DBWD COLUMN SIZE

Publication Release Date: September 19, 2006 - 75 - Revision B2 BITS [31:19] BASADDR Base address pointer of SDRAM bank 0/1 The start address is calculated as SDRAM bank 0/1 base pointer << 18. The SDRAM base address pointer together with the “SIZE” bits constitutes the whole address range of each SDRAM bank. [18:16] RESERVED [15] MRSET SDRAM Mode register set command for SDRAM bank 0/1 This bit set will issue a mode register set command to SDRAM. [14] RESERVED [13] AUTOPR Auto pre-charge mode of SDRAM for SDRAM bank 0/1 Enable the auto pre-charge function of external SDRAM bank 0/1 1= Auto pre-charge 0 = No auto pre-charge [12:11] LATENCY The CAS Latency of SDRAM bank 0/1 Defines the CAS latency of external SDRAM bank 0/1 LATENCY [12:11] MCLK REVERSED [10:8] RESERVED [7] COMPBK Number of component bank in SDRAM bank 0/1 Indicates the number of component bank (2 or 4 banks) in external SDRAM bank 0/1. 0 = 2 banks 1 = 4 banks [6:5] DBWD Data bus width for SDRAM bank 0/1 Indicates the external data bus width connect with SDRAM bank 0/1 If DBWD = 00, the assigned SDRAM access signal is not generated i.e. disable. DBWD [6:5] Bits Bank disable 8-bit (byte) 16-bit (half-word) 32-bit (word)

76 - Continued. BITS

[4:3] COLUMN Number of column address bits in SDRAM bank 0/1 Indicates the number of column address bits in external SDRAM bank 0/1. COLUMN [4:3] Bits REVERSED [2:0] SIZE Size of SDRAM bank 0/1 Indicates the memory size of external SDRAM bank 0/1 SIZE [2:0] Size of SDRAM （Byte） Bank disable 16M 32M 64M REVERSED Timing Control Registers （SDTIME0/1） W90P710 offers the flexible timing control registers to control the generation and processing of the control signals and can achieve you use different speed of SDRAM REGISTER ADDRESS R/W 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000 SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000

Publication Release Date: September 19, 2006 - 77 - Revision B2 RESERVED RESERVED RESERVED tRCD tRDL tRP tRAS BITS [31:11] RESERVED [10:8] tRCD SDRAM bank 0/1, /RAS to /CAS delay tRCD [10:8] MCLK [7:6] tRDL SDRAM bank 0/1, Last data in to pre-charge command tRDL [7:6] MCLK [5:3] tRP SDRAM bank 0/1, Row pre-charge time tRP [5:3] MCLK

78 - Continued. BITS

[2:0] tRAS SDRAM bank 0/1, Row active time tRAS [2:0] MCLK Fig 6.3.4 Access timing 1 of SDRAM Fig 6.3.5 Access timing 2 of SDRAM

Publication Release Date: September 19, 2006 - 79 - Revision B2 External I/O Control Registers（EXT0CON – EXT3CON） The W90P710 supports an external device control without glue logic. It is very cost effective because address decoding and control signals timing logic are not needed. Using these control registers you can configure special external I/O devices for providing the low cost external devices control solution. REGISTER ADDRESS R/W 0xFFF0_1018 R/W External I/O 0 control register 0x0000_0000 EXT1CON 0xFFF0_101C R/W External I/O 1 control register 0x0000_0000 EXT2CON 0xFFF0_1020 R/W External I/O 2 control register 0x0000_0000 EXT3CON 0xFFF0_1024 R/W External I/O 3 control register 0x0000_0000 BASADDR BASADDR SIZE ADRS tACC tCOH tACS tCOS DBWD BITS [31:11] BASADDR Base address pointer of external I/O bank 0~3 The start address of each external I/O bank is calculated as “BASADDR” base pointer << 18. Each external I/O bank base address pointer together with the “SIZE” bits constitutes the whole address range of each external I/O bank. [18:16] SIZE The size of the external I/O bank 0~3 SIZE [18:16] Byte 256K 512K 16M REVERSED

80 - Continued. BITS

[15] ADRS Address bus alignment for external I/O bank 0~3 When ADRS is set, external address (A21~A0) bus is alignment to byte address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting. [14:11] tACC Access cycles of external I/O bank 0~3 This parameter means nWE, nWBE and nOE active time clock. Detail timing tACC[14:11] MCLK tACC[14:11] MCLK Reversed [10:8] tCOH Chip selection hold time of external I/O bank 0~3 This parameters control nWBE and nOE hold time. Detail timing diagram tCOH [10:8] MCLK

Publication Release Date: September 19, 2006 - 81 - Revision B2 Continued. BITS [7:5] tACS Address set-up before nECS for external I/O bank 0~3 tACS [7:5] MCLK [4:2] tCOS Chip selection set-up time of external I/O bank 0~3 When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated. tCOS [4:2] MCLK [1:0] DBWD Programmable data bus width for external I/O bank 0~3 DBWD [1:0] Width of Data Bus Disable bus 8-bit 16-bit 32-bit

82 - Fig 6.3.6 External I/O write operation timing Fig 6.3.7 External I/O read operation timing

Publication Release Date: September 19, 2006 - 83 - Revision B2 A[21:0] D[31:0] nWBE_SDQM[1] nECSn nWE A[21:0] DQ[15:0] nOE nCS nWE nOE nUB nLB nWBE_SDQM[0] W90P710 2Mx16 SRAM Fig. 6.3.8 External IO bank with 16-bit SRAM Clock Skew Control Register （CKSKEW） Register Address R/W 0xFFF0_1F00 R/W Clock skew control register 0xXXXX_0018 DLH_CLK_REF DLH_CLK_REF RESVERED SWPON DLH_CLK_SKEW MCLK_O_D

84 - BITS

[31:16] DLH_CLK_REF Latch DLH_CLK clock tree by HCLK positive edge The SDRAM MCLK is generated by inserting a delay (XOR2) chain in HCLK positive or negedge edge to adjust the MCLK skew. So software can read these bits to expore MCLK and HCLK relationship. [31:24] is used for positive edge and [23:16] is for negedge edge. [15:9] RESERVED [8] SWPON SDRAM Initialization by Software Set this bit “1” will issue a SDRAM power on default setting command sequence like system power on, this bit will be auto-clear by hardware while SDRAM initialization finish. [7:4] DLH_CLK_SKEW Data latch Clock Skew Adjustment Due to PC board loading or too many devices connect to external address and data bus, it may causes SDRAM can not work correctly at high frequency (usually, 80MHz) software can control MCLK_O_D[3:0] to adjust address and data bus to adjust setup/hold time. DLH_CLK_SKEW[7:4] Gate Delay DLH_CLK_SKEW[7:4] Gate Delay P-0 N-0 P-1 N-1 P-2 N-2 P-3 N-3 P-4 N-4 P-5 N-5 P-6 N-6 P-7 N-7 NOTE: P-x means Data latched Clock shift “X” gates delays by refer MCLKO positive edge, N-x means Data latched Clock shift “X” gates delays by refer MCLKO negative edge.

Publication Release Date: September 19, 2006 - 85 - Revision B2 Continued. BITS [3:0] MCLK_O_D MCLK output delay adjustment MCLK_O_D [3:0] Gate Delay MCLK_O_D [3:0] Gate Delay P-0 N-0 P-1 N-1 P-2 N-2 P-3 N-3 P-4 N-4 P-5 N-5 P-6 N-6 P-7 N-7 NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK negative edge. MCLK is the output pin of MCLKO, which is an internal signal on chip.

86 -

6.4 Cache Controller

The W90P710 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The I- Cache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these two caches are configured two-way set associative addressing. Each cache has four words cache line size. When a miss occurs, four words must be fetched consecutively from external memory. The replacement algorithm is a LRU (Least Recently Used). If disabling the I-Cache / D-Cache, these cache memories can be treated as On-Chip RAM. The W90P710 also provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data. 6.4.1 On-Chip RAM If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has 4KB On-Chip RAM, its start address is 0xFFE01000. If I-Cache is disabled, there has 4KB On-Chip RAM and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has 8KB On-Chip RAM starting from 0xFFE00000. The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in Cache Control Register (CAHCON). Table6.4.1 The size and start address of On-Chip RAM ON-CHIP RAM ICAEN DCAEN SIZE START ADDRESS 8KB 0xFFE0_0000 4KB 0xFFE0_0000 4KB 0xFFE0.1000 Unavailable 6.4.2 Non-Cacheable Area Although the cache affects the entire 2GB system memory, it is sometimes necessary to define non- cacheable areas when the consistency of data stored in memory and the cache must be ensured. To support this, the W90P710 provides a non-cacheable area control bit in the address field, A[31]. If A[31] in the ROM/FLASH, SDRAM, or external I/O bank’s access address is “0”, then the accessed data is cacheable. If the A [31] value is “1”, the accessed data is non-cacheable.

Publication Release Date: September 19, 2006 - 87 - Revision B2 6.4.3 Instruction Cache The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction request from the instruction unit in the core. In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The first word received from the bus is the requested instruction. The cache forwards this instruction to the instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When I-Cache is disabled, the cache memory is served as 4KB On-chip RAM. The I-Cache is always disabled on reset. The following is a list of the instruction cache features： y 4K bytes instruction cache y Two-way set associative y Four words in a cache line y LRU replacement policy y Lockable on a per-line basis y Critical word first, burst access Instruction Cache Operation On an instruction fetch, bits 10-4 of the instruction’s address point into the cache to retrieve the tags and data of one set. The tags from both ways are then compared against bits 30-11 of the instruction’s address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is not valid, it is a cache miss. Instruction Cache Hit In case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line whose tag matches. The instruction is immediately transferred to the instruction unit of the core. Instruction Cache Miss On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4- word burst transfer read request. A cache line is then selected to receive the data that will be coming from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the selected set is invalid, then the least recently used line is selected for replacement. Locked lines are never replaced. The transfer begins with the word requested by the instruction unit (critical word first), followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound). Instruction Cache Flushing The W90P710 does not support external memory snooping. Therefore, if self-modifying code is written, the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is automatically flushed during reset.

88 - Instruction Cache Load and Lock The W90P710 supports a cache-locking feature that can be used to lock critical sections of code into I- Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line command. To load and lock instruction, the following sequence should be followed: Write the start address of the instructions to be locked into CAHADR register. Set LDLK and ICAH bits in the CAHCON register. Increased the address by 16 and written into CAHADR register. Set LDLK and ICAH bits in the CAHCON register. Repeat the steps 3 and 4, until the desired instructions are all locked. When using I-Cache load and lock command, there are some notes should be cared. y The programs executing load and lock operation should be held in a non-cacheable area of memory. y The cache should be enabled and interrupts should be disabled. y Software must flush the cache before execute load and lock to ensure that the code to be locked down is not already in the cache. Instruction Cache Unlock The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line is cleared to “0”. W90P710 has two unlock command, unlock line and unlock all. The unlock line operation is performed on a cache line granularity. In case the line is found in the cache, it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the cache, no operation is done and the command terminates with no exception. To unlock one line the following unlock line sequence should be followed: Write the address of the line to be unlocked into the CAHADR Register. Set the ULKS and ICAH bits in the CAHCON register. The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA and ICAH bits.

Publication Release Date: September 19, 2006 - 89 - Revision B2 6.4.4 Data Cache The W90P710 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache is designed for buffer write-through mode of operation and a least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM. The D-Cache is always disabled on reset. The following is a list of the data cache features： y 4K bytes data cache y Two-way set associative y Four words in a cache line y LRU replacement policy y Lockable on a per-line basis y Critical word first, burst access y Buffer Write-through mode y 8 words write buffer y Drain write buffer Data Cache Operation On a data fetch, bits 10-4 of the data’s address point into the cache to retrieve the tags and data of one set. The tags from both ways are then compared against bits 30-11 of the data’s address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is not valid, it is a cache miss. Data Cache Read Read Hit：On a cache hit, the requested word is immediately transferred to the core. Read Miss：A line in the cache is selected to hold the data, which will be fetched from memory. The selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the missed data (critical word first), followed by the remaining word in the line, then by the word at the beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to the core. Data Cache Write As buffer write-through mode, store operations always update memory. The buffer write-through mode is used when external memory and internal cache images must always agree.

90 - Write Hit：Data is written into both the cache and write buffer. The processor then continues to access the cache, while the cache controller simultaneously downloads the contents of the write buffer to main memory. This reduces the effective write memory cycle time from the time required for a main memory cycle to the cycle time of the high-speed cache. Write Miss：Data is only written into write buffer, not to the cache (write no allocate). Data Cache Flushing The W90P710 allows flushing of the data cache under software control. The data cache may be invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register. Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the “V” bit of the line is cleared to “0”. The D-cache is automatically flushed during reset. Data Cache Load and Lock The W90P710 supports a cache-locking feature that can be used to lock critical sections of data into D- Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction SRAM. The locked lines are not replaced during misses and it is not affected by flush per line command. To load and lock data, the following sequence should be followed: Write the start address of the data to be locked into CAHADR register. Set LDLK and DCAH bits in the CAHCON register. Increased the address by 16 and written into CAHADR register. Set LDLK and DCAH bits in the CAHCON register. Repeat the steps 3 and 4, until the desired data are all locked. When using D-Cache load and lock command, there are some notes should be cared. y The programs executing load and lock operation should be held in a non-cacheable area of memory. y The cache should be enabled and interrupts should be disabled. y Software must flush the cache before execute load and lock to ensure that the data to be locked down is not already in the cache. Data Cache Unlock The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line is cleared to “0”. W90P710 has two unlock command, unlock line and unlock all. The unlock line operation is performed on a cache line granularity. In case the line is found in the cache, it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the cache, no operation is done and the command terminates with no exception. To unlock one line the following unlock line sequence should be followed: Write the address of the line to be unlocked into the CAHADR Register. Set the ULKS and DCAH bits in the CAHCON register.

Publication Release Date: September 19, 2006 - 91 - Revision B2 The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA and DCAH bits. 6.4.5 Write Buffer The W90P710 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF register, and the buffer is disabled and flushed on reset. Drain write buffer To force data, this is in write buffer, to be written to external main memory. This operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues. To perform this command, you can set the DRWB and DCAH bits in CAHCON register. 6.4.6 Cache Control Registers Map REGISTER ADDRESS R/W 0xFFF0_2000 R/W Cache configuration register 0x0000_0000 CAHCON 0xFFF0_2004 R/W Cache control register 0x0000_0000 CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000 CTEST0 0xFFF6_0000 R/W Cache test register 0 0x0000_0000 CTEST1 0xFFF6_0004 R Cache test register 1 0x0000_0000 Configuration Register (CAHCNF) Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write buffer. REGISTER ADDRESS R/W 0xFFF0_2000 R/W Cache configuration register 0x0000_0000

92 - RESERVED RESERVED RESERVED RESERVED WRBEN DCAEN ICAEN BITS

[31:3] RESERVED [2] WRBEN Write buffer enable Write buffer is disabled after reset. 1 = Enable write buffer 0 = Disable write buffer [1] DCAEN D-Cache enable D-Cache is disabled after reset. 1 = Enable D-cache 0 = Disable D-cache [0] ICAEN I-Cache enable I-Cache is disabled after reset. 1 = Enable I-cache 0 = Disable I-cache Control Register (CAHCON) Cache controller supports one Control register used to control the following operations. y Flush I-Cache and D-Cache y Load and lock I-Cache and D-Cache y Unlock I-Cache and D-Cache y Drain write buffer These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command set bit will be cleared to “0” automatically.

Publication Release Date: September 19, 2006 - 93 - Revision B2 REGISTER ADDRESS R/W 0xFFF0_2004 R/W Cache control register 0x0000_0000 RESERVED RESERVED RESERVED DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH BITS [31:8] RESERVED [7] DRWB Drain write buffer Forces write buffer data to be written to main memory. [6] ULKS Unlock I-Cache/D-Cache single line Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. [5] ULKA Unlock I-Cache/D-Cache entirely Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared to 0. [4] LDLK Load and Lock I-Cache/D-Cache Loads the instruction or data from external memory and locks into cache. Both WAY and ADDR bits in CAHADR register must be specified. [3] FLHS Flush I-Cache/D-Cache single line Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. [2] FLHA Flush I-Cache/D-Cache entirely To flush the entire I-Cache/D-Cache, also flushes any locked-down code. If the I-Cache/D-Cache contains locked down code, the programmer must flush lines individually [1] DCAH D-Cache selected When set to “1”, the command set is executed with D-Cache. [0] ICAH I-Cache selected When set to “1”, the command set is executed with I-Cache.

94 - NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid command and no operation is done and the command terminates with no exception. The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no operation is done and the command terminates with no exception. Address Register (CAHADR) W90P710 Cache Controller supports one address register. This address register is used with the command set in the control register (CAHCON) by specifying instruction/data address. REGISTER ADDRESS R/W

0xFFF0_2008 R/W Cache address register 0x0000_0000 WAY ADDR ADDR ADDR ADDR BITS [31] WAY Way selection 0 = Way0 is selected 1 = Way1 is selected [30:0] ADDR The absolute address of instruction or data

Publication Release Date: September 19, 2006 - 95 - Revision B2 Cache Test Register 0 (CTEST0) Cache test control register that configures the cache and tag ram testing enable or disable. In addition, this register controls the built-in-self-test (BIST) function of SRAM. REGISTER ADDRESS R/W 0xFFF6_0000 R/W Cache test register 0 0x0000_0000 RESERVED RESERVED BISTEN RESERVED BST_GP3 BST_GP2 BST_GP1 BST_GP0 RESERVED CATEST BITS [31:16] RESERVED [15] BISTEN BIST mode enable When set to “1”, BIST mode will be enabled, the selected memory groups begins to be tested by BIST. [14:12] RESERVED [11] BIST_GP3 Memory group 3 is selected to test by BIST When set to “1”, memory group 3, including data cache tag ram way 0 and way 1, are selected to be tested by BIST. [10] BIST_GP2 Memory group 2 is selected to test by BIST When set to “1”, memory group 2, including program cache tag ram way 0 and way 1, are selected to be tested by BIST. [9] BIST_GP1 Memory group 1 is selected to test by BIST When set to “1”, memory group 1, including data cache ram way 0 and way 1, are selected to be tested by BIST. [8] BIST_GP0 Memory group 0 is selected to test by BIST When set to “1”, memory group 0, including program cache ram way 0 and way 1, are selected to be tested by BIST. [7:0] RESERVED ** Note: The 4 memory groups can be selected and tested simultaneously by BIST.

96 - Cache Test Register 1 (CTEST1) Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST is finish and all of bank of SRAM are tested successfully will be presented in this register. Register Address R/W

0xFFF6_0004 R Cache test register 1 0x0000_0000 FINISH RESERVED RESERVED RESERVED BFAIL7 BFAIL6 BFAIL5 BFAIL4 BFAIL3 BFAIL2 BFAIL1 BFAIL0 BITS [31] FINISH BIST completed This bit is “0” initially. When BIST mode enabled, this bit will be “1” after BIST test completed. The values of BFAIL0-7 are valid only after FINISH = 1. [30:8] RESERVED [7] BFAIL7 BIST test fail for data cache tag ram way 1 If this bit equals to “1”, it indicates the data cache tag ram for way 1 is tested fail by BIST. “0” means the test is passed. [6] BFAIL6 BIST test fail for data cache tag ram way 0 If this bit equals to “1”, it indicates the data cache tag ram for way 0 is tested fail by BIST. “0” means the test is passed. [5] BFAIL5 BIST test fail for instruction cache tag ram way 1 If this bit equals to “1”, it indicates the instruction cache tag ram for way 1 is tested fail by BIST. “0” means the test is passed. [4] BFAIL4 BIST test fail for instruction cache tag ram way 0 If this bit equals to “1”, it indicates the instruction cache tag ram for way 0 is tested fail by BIST. “0” means the test is passed. [3] BFAIL3 BIST test fail for data cache ram way 1 If this bit equals to “1”, it indicates the data cache ram for way 1 is tested fail by BIST. “0” means the test is passed.

Publication Release Date: September 19, 2006 - 97 - Revision B2 Continued. BITS [2] BFAIL2 BIST test fail for data cache ram way 0 If this bit equals to “1”, it indicates the data cache ram for way 0 is tested fail by BIST. “0” means the test is passed. [1] BFAIL1 BIST test fail for instruction cache ram way 1 If this bit equals to “1”, it indicates the instruction cache ram for way 1 is tested fail by BIST. “0” means the test is passed. [0] BFAIL0 BIST test fail for instruction cache ram way 0 If this bit equals to “1”, it indicates the instruction cache ram for way 0 is tested fail by BIST. “0” means the test is passed.

6.5 Ethernet MAC Controller

The W90P710 provides an Ethernet MAC Controller (EMC) for LAN application. This EMC has its DMA controller, transmit FIFO, and receive FIFO. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller and status controller. The EMC only supports RMII (Reduced MII) interface to connect with PHY operating on 50MHz REF_CLK.

Features

y Supports IEEE Std. 802.3 CSMA/CD protocol. y Supports both half and full duplex for 10M/100M bps operation. y Supports RMII interface. y Supports MII Management function. y Supports pause and remote pause function for flow control. y Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception. y Supports 16 entries CAM function for Ethernet MAC address recognition. y Supports internal loop back mode for diagnostic. y Supports 256 bytes embedded transmit and receive FIFO. y Supports DMA function.

98 - 6.5.1 EMC Functional Description MII Management State Machine The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management interface, software can access the control and status registers of the external PHY chip. Tow programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII Management Data Control and Address Register) are for MII management function. Set the bit BUSY of MIIDA register will trigger the MII management state machine. After the MII management cycle is finished, the BUSY bit will be cleared automatically. Media Access Control (MAC) The function of W90P710 MAC fully meets the requirements defined by the IEEE802.3u specification. The following paragraphs will describe the frame structure and the operation of the transmission and receive. The transmission data frame sent from the transmit DMA will be encapsulated by the MAC before transmitting onto the MII bus. The sent data will be assembled with the preamble, the start frame delimiter (SFD), the frame check sequence and the padding for enforcing those less than 64 bytes to meet the minimum size frame and CRC sequence. The out going frame format will be as following 110101010 --- 10101010 10101011 d0 d1 d2 - dn Padding CRC31 CRC30 --- CRC0 As mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern “10101010” and the SFD is a one byte 10101011 data. The padding data will be all 0 value if the sent data frame is less than 64 bytes. The padding disable function specified in the bit P of the transmit descriptor is used to control if the MAC needs to pad data at the end of frame data or not when the transmitted data frame is less than 64 bytes. The padding data will not be appended if the padding disable bit is set to be high. The bits CRC0 ... CRC31 are the 32 bits cyclic redundancy check (CRC) sequence. The CRC encoding is defined by the following polynomial specified by the IEEE802.3. This 32 bits CRC appending function will be disabled if the Inhibit CRC of the transmission descriptor is set to high. The MAC also performs many other transmission functions specified by the IEEE802.3, including the inter-frame spacing function, collision detection, collision enforcement, collision back off and retransmission. The collision back-off timer is a function of the integer slot time, 512 bit times. The number of slot times to delay between the current transmissions attempts to the next attempt is determined by a uniformly distributed random integer algorithm specified by the IEEE802.3. The MAC performs the receive functions specified by the IEEE 802.3 including the address recognition function, the frame check sequence validation, the frame disassembly, framing and collision filtering.

Publication Release Date: September 19, 2006 - 99 - Revision B2 EMC Descriptors A link-list data structure named as descriptor is used to keep the control, status and data information of each frame. Through the descriptor, CPU and EMC exchange the information for frame reception and transmission. Two different descriptors are defined in W90P710. One named as Rx descriptor for frame reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of four words. There is much information kept in the descriptors and details are described as below. 6.5.1.1 Rx Buffer Descriptor O Rx Status Receive Byte Count Receive Buffer Starting Address BO Reserved Next Rx Descriptor Starting Address Rx Descriptor Word 0 Owner Reserved Reserved RP ALIE RXGD PTLE Reserved CRCE RXINTR RBC RBC Owner [31:30]: Ownership The ownership field defines which one, the CPU or EMC, is the owner of each Rx descriptor. Only the owner has right to modify the Rx descriptor and the others can read the Rx descriptor only. 00: The owner is CPU 01: Undefined 10: The owner is EMC 11: Undefined If the O=2’b10 indicates the EMC RxDMA is the owner of Rx descriptor and the Rx descriptor is available for frame reception. After the frame reception completed, if the frame needed NAT translation, EMC RxDMA modify ownership field to 2’b11. Otherwise, the ownership field will be modified to 2’b00.

100 - If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing the frame, it modifies the ownership field to 2’b10 and releases the Rx descriptor to EMC RxDMA. Rx Status [29:16]: Receive Status This field keeps the status for frame reception. All status bits are updated by EMC. In the receive status, bits 29 to 23 are undefined and reserved for the future. RP [22]: Runt Packet The RP indicates the frame stored in the data buffer pointed by Rx descriptor is a short frame (frame length is less than 64 bytes). 1’b0: The frame is not a short frame. 1’b1: The frame is a short frame. ALIE [21]: Alignment Error The ALIE indicates the frame stored in the data buffer pointed by Rx descriptor is not a multiple of byte. 1’b0: The frame is a multiple of byte. 1’b1: The frame is not a multiple of byte. RXGD [20]: Frame Reception Complete The RXGD indicates the frame reception has completed and stored in the data buffer pointed by Rx descriptor. 1’b0: The frame reception not complete yet. 1’b1: The frame reception completed. PTLE [19]: Packet Too Long The PTLE indicates the frame stored in the data buffer pointed by Rx descriptor is a long frame (frame length is greater than 1518 bytes). 1’b0: The frame is not a long frame. 1’b1: The frame is a long frame. CRCE [17]: CRC Error The CRCE indicates the frame stored in the data buffer pointed by Rx descriptor incurred CRC error. 1’b0: The frame doesn’t incur CRC error. 1’b1: The frame incurred CRC error.

Publication Release Date: September 19, 2006 - 101 - Revision B2 RXINTR [16]: Receive Interrupt The RXINTR indicates the frame stored in the data buffer pointed by Rx descriptor caused an interrupt condition. 1’b0: The frame doesn’t cause an interrupt. 1’b1: The frame caused an interrupt. RBC [15:0]: Receive Byte Count The RBC indicates the byte count of the frame stored in the data buffer pointed by Rx descriptor. The four bytes CRC field is also included in the receive byte count. But if the SPCRC of register MCMDR is enabled, the four bytes CRC field will be excluded from the receive byte count. Rx Descriptor Word 1 RXBSA RXBSA RXBSA RXBSA BO RXBSA [31:2]: Receive Buffer Starting Address The RXBSA indicates the starting address of the receive frame buffer. The RXBSA is used to be the bit 31 to 2 of memory address. In other words, the starting address of the receive frame buffer always located at word boundary. BO [1:0]: Byte Offset The BO indicates the byte offset from RXBSA where the received frame begins to store. If the BO is 2’b01, the starting address where the received frame begins to store is RXBSA+2’b01, and so on.

102 - Rx Descriptor Word 2 Reserved Reserved Reserved Reserved The Rx descriptor word 2 keeps obsolete information for MAC translation. Therefore, these information bits are undefined and should be ignored. Rx Descriptor Word 3 NRXDSA NRXDSA NRXDSA NRXDSA NRXDSA [31:0]: Next Rx Descriptor Starting Address The Rx descriptor is a link-list data structure. Consequently, NRXDSA is used to keep the starting address of the next Rx descriptor. The bits [1:0] will be ignored by EMC. So, all Rx descriptor must locate at word boundary memory address.

Publication Release Date: September 19, 2006 - 103 - Revision B2 6.5.1.2 Tx Buffer Descriptor 3 2 O Reserved I C P Transmit Buffer Starting Address BO Tx Status Transmit Byte Count Next Tx Descriptor Starting Address Tx Descriptor Word 0 Owner Reserved Reserved Reserved Reserved IntEn CRCApp PadEn Owner [31]: Ownership The ownership field defines which one, the CPU or EMC, is the owner of each Tx descriptor. Only the owner has right to modify the Tx descriptor and the other can read the Tx descriptor only. 0: The owner is CPU 1: The owner is EMC If the O=1’b1 indicates the EMC TxDMA is the owner of Tx descriptor and the Tx descriptor is available for frame transmission. After the frame transmission completed, EMC TxDMA modify ownership field to 1’b0 and return the ownership of Tx descriptor to CPU. If the O=1’b0 indicates the CPU is the owner of Tx descriptor. After the CPU prepares new frame to wait transmission, it modifies the ownership field to 1’b1 and releases the Tx descriptor to EMC TxDMA. IntEn [2]: Transmit Interrupt Enable The IntEn controls the interrupt trigger circuit after the frame transmission completed. If the IntEn is enabled, the EMC will trigger interrupt after frame transmission completed. Otherwise, the interrupt doesn’t be triggered. 1’b0: Frame transmission interrupt is masked. 1’b1: Frame transmission interrupt is enabled.

104 - CRCApp [1]: CRC Append The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes CRC checksum will be appended to frame at the end of frame transmission. 1’b0: 4-bytes CRC appending is disabled. 1’b1: 4-bytes CRC appending is enabled. PadEN [0]: Padding Enable The PadEN control the PAD bits appending while the length of transmission frame is less than 60 bytes. If PadEN is enabled, EMC does the padding automatically. 1’b0: PAD bits appending is disabled. 1’b1: PAD bits appending is enabled. Tx Descriptor Word 1 TXBSA TXBSA TXBSA TXBSA BO TXBSA [31:2]: Transmit Buffer Starting Address The TXBSA indicates the starting address of the transmit frame buffer. The TXBSA is used to be the bit 31 to 2 of memory address. In other words, the starting address of the transmit frame buffer always located at word boundary. BO [1:0]: Byte Offset The BO indicates the byte offset from TXBSA where the transmit frame begins to read. If the BO is 2’b01, the starting address where the transmit frame begins to read is TXBSA+2’b01, and so on.

Publication Release Date: September 19, 2006 - 105 - Revision B2 Tx Descriptor Word 2 CCNT Reserved SQE PAU TXHA LC TXABT NCS EXDEF TXCP Reserved DEF TXINTR TBC TBC CCNT [31:28]: Collision Count The CCNT indicates the how many collision occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1. SQE [26]: SQE Error The SQE indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. The SQE error check will only be done while both bit EnSQE of MCMDR is enabled and EMC is operating on 10Mbps half-duplex mode. 1’b0: No SQE error found at end of packet transmission. 1’b0: SQE error found at end of packet transmission. PAU [25]: Transmission Paused THE PAU INDICATES THE NEXT NORMAL PACKET transmission process will be paused temporally because EMC received a PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to transmit a PAUSE control frame out. 1’b0: Next normal packet transmission process will go on. 1’b1: Next normal packet transmission process will be paused. TXHA [24]: Transmission Halted The TXHA indicates the next normal packet transmission process will be halted because the bit TXON of MCMDR is disabled be S/W. 1’b0: Next normal packet transmission process will go on. 1’b1: Next normal packet transmission process will be halted.

106 - LC [23]: Late Collision The LC indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. 1’b0: No collision occurred in the outside of 64 bytes collision window. 1’b1: Collision occurred in the outside of 64 bytes collision window. TXABT [22]: Transmission Abort The TXABT indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMC is operating on half-duplex mode. 1’b0: Packet doesn’t incur 16 consecutive collisions during transmission. 1’b1: Packet incurred 16 consecutive collisions during transmission. NCS [21]: No Carrier Sense The NCS indicates the MII I/F signal CRS doesn’t active at the start of or during the packet transmission. The NCS is only available while EMC is operating on half-duplex mode. 1’b0: CRS signal actives correctly. 1’b1: CRS signal doesn’t active at the start of or during the packet transmission. EXDEF [20]: Defer Exceed The EXDEF indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NDEF of MCMDR is disabled, and EMC is operating on half-duplex mode. 1’b0: Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). 1’b1: Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). TXCP [19]: Transmission Complete The TXCP indicates the packet transmission has completed correctly. 1’b0: The packet transmission doesn’t complete. 1’b1: The packet transmission has completed. DEF [17]: Transmission Deferred The DEF indicates the packet transmission has deferred once. The DEF is only available while EMC is operating on half-duplex mode. 1’b0: Packet transmission doesn’t defer. 1’b1: Packet transmission has deferred once.

Publication Release Date: September 19, 2006 - 107 - Revision B2 TXINTR [16]: Transmit Interrupt The TXINTR indicates the packet transmission caused an interrupt condition. 1’b0: The packet transmission doesn’t cause an interrupt. 1’b1: The packet transmission caused an interrupt. TBC [15:0]: Transmit Byte Count The TBC indicates the byte count of the frame stored in the data buffer pointed by Tx descriptor for transmission. Tx Descriptor Word 3 NTXDSA NTXDSA NTXDSA NTXDSA NTXDSA [31:0]: Next Tx Descriptor Starting Address The Tx descriptor is a link-list data structure. Consequently, NTXDSA is used to keep the starting address of the next Tx descriptor. The bits [1:0] will be ignored by EMC. So, all Tx descriptor must locate at word boundary memory address.

108 - 6.5.2 EMC Register Mapping The EMC implements many registers and the registers are separated into three types, the control registers, the status registers and diagnostic registers. The control registers are used by S/W to pass control information to EMC. The status registers are used to keep EMC operation status for S/W. And, the diagnostic registers are used for debug only. EMC Registers REGISTER ADDRESS R/W

CONTROL REGISTERS (44) CAMCMR 0xFFF0_3000 R/W CAM Command Register 0x0000_0000 CAMEN 0xFFF0_3004 R/W CAM Enable Register 0x0000_0000 CAM0M 0xFFF0_3008 R/W CAM0 Most Significant Word Register 0x0000_0000 CAM0L 0xFFF0_300C R/W CAM0 Least Significant Word Register 0x0000_0000 CAM1M 0xFFF0_3010 R/W CAM1 Most Significant Word Register 0x0000_0000 CAM1L 0xFFF0_3014 R/W CAM1 Least Significant Word Register 0x0000_0000 CAM2M 0xFFF0_3018 R/W CAM2 Most Significant Word Register 0x0000_0000 CAM2L 0xFFF0_301C R/W CAM2 Least Significant Word Register 0x0000_0000 CAM3M 0xFFF0_3020 R/W CAM3 Most Significant Word Register 0x0000_0000 CAM3L 0xFFF0_3024 R/W CAM3 Least Significant Word Register 0x0000_0000 CAM4M 0xFFF0_3028 R/W CAM4 Most Significant Word Register 0x0000_0000 CAM4L 0xFFF0_302C R/W CAM4 Least Significant Word Register 0x0000_0000 CAM5M 0xFFF0_3030 R/W CAM5 Most Significant Word Register 0x0000_0000 CAM5L 0xFFF0_3034 R/W CAM5 Least Significant Word Register 0x0000_0000 CAM6M 0xFFF0_3038 R/W CAM6 Most Significant Word Register 0x0000_0000 CAM6L 0xFFF0_303C R/W CAM6 Least Significant Word Register 0x0000_0000 CAM7M 0xFFF0_3040 R/W CAM7 Most Significant Word Register 0x0000_0000 CAM7L 0xFFF0_3044 R/W CAM7 Least Significant Word Register 0x0000_0000 CAM8M 0xFFF0_3048 R/W CAM8 Most Significant Word Register 0x0000_0000 CAM8L 0xFFF0_304C R/W CAM8 Least Significant Word Register 0x0000_0000 CAM9M 0xFFF0_3050 R/W CAM9 Most Significant Word Register 0x0000_0000 CAM9L 0xFFF0_3054 R/W CAM9 Least Significant Word Register 0x0000_0000 CAM10M 0xFFF0_3058 R/W CAM10 Most Significant Word Register 0x0000_0000 CAM10L 0xFFF0_305C R/W CAM10 Least Significant Word Register 0x0000_0000 CAM11M 0xFFF0_3060 R/W CAM11 Most Significant Word Register 0x0000_0000 CAM11L 0xFFF0_3064 R/W CAM11 Least Significant Word Register 0x0000_0000

Publication Release Date: September 19, 2006 - 109 - Revision B2 Continued. REGISTER ADDRESS R/W CONTROL REGISTERS (44) CAM12M 0xFFF0_3068 R/W CAM12 Most Significant Word Register 0x0000_0000 CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register 0x0000_0000 CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register 0x0000_0000 CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register 0x0000_0000 CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register 0x0000_0000 CAM14L 0xFFF0_307C R/W CAM14 Least Significant Word Register 0x0000_0000 CAM15M 0xFFF0_3080 R/W CAM15 Most Significant Word Register 0x0000_0000 CAM15L 0xFFF0_3084 R/W CAM15 Least Significant Word Register 0x0000_0000 TXDLSA 0xFFF0_3088 R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC RXDLSA 0xFFF0_308C R/W Receive Descriptor Link List Start Address Register 0xFFFF_FFFC MCMDR 0xFFF0_3090 R/W MAC Command Register 0x0000_0000 MIID 0xFFF0_3094 R/W MII Management Data Register 0x0000_0000 MIIDA 0xFFF0_3098 R/W MII Management Control and Address Register 0x0090_0000 FFTCR 0xFFF0_309C R/W FIFO Threshold Control Register 0x0000_0101 TSDR 0xFFF0_30A0 W Transmit Start Demand Register Undefined RSDR 0xFFF0_30A4 W Receive Start Demand Register Undefined DMARFC 0xFFF0_30A8 R/W Maximum Receive Frame Control Register 0x0000_0800 MIEN 0xFFF0_30AC R/W MAC Interrupt Enable Register 0x0000_0000 Status Registers (11) MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register 0x0000_0000 MGSTA 0xFFF0_30B4 R/W MAC General Status Register 0x0000_0000 MPCNT 0xFFF0_30B8 R/W Missed Packet Count Register 0x0000_7FFF MRPC 0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000 MRPCC 0xFFF0_30C0 R MAC Receive Pause Current Count Register 0x0000_0000 MREPC 0xFFF0_30C4 R MAC Remote Pause Count Register 0x0000_0000 DMARFS 0xFFF0_30C8 R/W DMA Receive Frame Status Register 0x0000_0000

110 - Continued. REGISTER ADDRESS R/W

Status Registers (11) CTXDSA 0xFFF0_30CC R Current Transmit Descriptor Start Address Register 0x0000_0000 CTXBSA 0xFFF0_30D0 R Current Transmit Buffer Start Address Register 0x0000_0000 CRXDSA 0xFFF0_30D4 R Current Receive Descriptor Start Address Register 0x0000_0000 CRXBSA 0xFFF0_30D8 R Current Receive Buffer Start Address Register 0x0000_0000 Diagnostic Registers (7) RXFSM 0xFFF0_3200 R Receive Finite State Machine Register 0x0081_1101 TXFSM 0xFFF0_3204 R Transmit Finite State Machine Register 0x0101_1101 FSM0 0xFFF0_3208 R Finite State Machine Register 0 0x0001_0101 FSM1 0xFFF0_320C R Finite State Machine Register 1 0x1100_0100 DCR 0xFFF0_3210 R/W Debug Configuration Register 0x0000_003F DMMIR 0xFFF0_3214 R Debug Mode MAC Information Register 0x0000_0000 BISTR 0xFFF0_3300 R/W BIST Mode Register 0x0000_0000

Publication Release Date: September 19, 2006 - 111 - Revision B2 6.5.2.1 Register Details CAM Command Register (CAMCMR) The EMC of W90P710 supports CAM function for destination MAC address recognition. The CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet reception. Register Address R/W 0xFFF0_3000 R/W CAM Command Register 0x0000_0000 Reserved Reserved Reserved Reserved ECMP CCAM ABP AMP AUP BITS DESCRIPTIONS [31:5] Reserved [4] ECMP The ECMP(Enable CAM Compare) controls the enable of CAM comparison function for destination MAC address recognition. If S/W wants to receive a packet with specific destination MAC address, configures the MAC address into anyone of 16 CAM entries, then enables that CAM entry and set ECMP to 1. 1’b0: Disable CAM comparison function for destination MAC address recognition. 1’b1: Enable CAM comparison function for destination MAC address recognition. [3] CCAM The CCAM(Complement CAM Compare) controls the complement of the CAM comparison result. If the ECMP and CCAM are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped. And the incoming packet with destination MAC address doesn’t configured in any CAM entry will be received. 1’b0: The CAM comparison result doesn’t be complemented. 1’b1: The CAM comparison result will be complemented.

112 - Continued. BITS DESCRIPTIONS [2] ABP The Accept Broadcast Packet controls the broadcast packet reception. If ABP is enabled, EMC receives all incoming packet it’s destination MAC address is a broadcast address. 1’b0: EMC receives packet depends on the CAM comparison result. 1’b1: EMC receives all broadcast packets. [1] AMP The Accept Multicast Packet controls the multicast packet reception. If AMP is enabled, EMC receives all incoming packet it’s destination MAC address is a multicast address. 1’b0: EMC receives packet depends on the CAM comparison result. 1’b1: EMC receives all multicast packets. [0] AUP The Accept Unicast Packet controls the unicast packet reception. If AUP is enabled, EMC receives all incoming packet it’s destination MAC address is a unicast address. 1’b0: EMC receives packet depends on the CAM comparison result. 1’b1: EMC receives all unicast packets. CAMCMR Setting and Comparison Result CAMCMR Setting and Comparison Result The following table is the address recognition result in different CAMCMR configuration. The column Result shows the incoming packet type that can pass the address recognition in specific CAM configuration. The C, U, M and B represents the: C: It indicates the destination MAC address of incoming packet has been configured in CAM entry. U: It indicates the incoming packet is a unicast packet. M: It indicates the incoming packet is a multicast packet. B: It indicates the incoming packet is a broadcast packet.

Publication Release Date: September 19, 2006 - 113 - Revision B2 ECMP CCAM AUP AMP ABP RESULT No Packet B M M B C U C U B C U M C U M B C U M B C U M B C U M B C U M B C U M B C U M B C U M B C U M B C C B C M C N B C U C U B C U M C U M B U M B U M B U M B U M B C U M B C U M B C U M B C U M B

114 - CAM Enable Register (CAMEN) The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before it can participate in the destination MAC address recognition. REGISTER ADDRESS R/W

0xFFF0_3004 R/W CAM Enable Register 0x0000_0000 Reserved Reserved CAM15EN CAM14EN CAM13EN CAM12EN CAM11EN CAM10EN CAM9EN CAM8EN CAM7EN CAM6EN CAM5EN CAM4EN CAM3EN CAM2EN CAM1EN CAM0EN BITS DESCRIPTIONS [31:16] Reserved [15:13] CAM15EN CAM14EN CAM13EN The CAM entry 13, 14 and 15 are for PAUSE control frame transmission. If S/W wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first. [12] CAM12EN CAM entry 12 is enabled 1’b0: CAM entry 12 disabled. 1’b1: CAM entry 12 enabled. [11] CAM11EN CAM entry 11 is enabled 1’b0: CAM entry 11 disabled. 1’b1: CAM entry 11 enabled. [10] CAM10EN CAM entry 10 is enabled 1’b0: CAM entry 10 disabled. 1’b1: CAM entry 10 enabled.

Publication Release Date: September 19, 2006 - 115 - Revision B2 Continued. BITS DESCRIPTIONS [9] CAM9EN CAM entry 9 is enabled 1’b0: CAM entry 9 disabled. 1’b1: CAM entry 9 enabled. [8] CAM8EN CAM entry 8 is enabled 1’b0: CAM entry 8 disabled. 1’b1: CAM entry 8 enabled. [7] CAM7EN CAM entry 7 is enabled 1’b0: CAM entry 7 disabled. 1’b1: CAM entry 7 enabled. [6] CAM6EN CAM entry 6 is enabled 1’b0: CAM entry 6 disabled. 1’b1: CAM entry 6 enabled. [5] CAM5EN CAM entry 5 is enabled 1’b0: CAM entry 5 disabled. 1’b1: CAM entry 5 enabled. [4] CAM4EN CAM entry 4 is enabled 1’b0: CAM entry 4 disabled. 1’b1: CAM entry 4 enabled. [3] CAM3EN CAM entry 3 is enabled 1’b0: CAM entry 3 disabled. 1’b1: CAM entry 3 enabled. [2] CAM2EN CAM entry 2 is enabled 1’b0: CAM entry 2 disabled. 1’b1: CAM entry 2 enabled. [1] CAM1EN CAM entry 1 is enabled 1’b0: CAM entry 1 disabled. 1’b1: CAM entry 1 enabled. [0] CAM0EN CAM entry 0 is enabled 1’b0: CAM entry 0 disabled. 1’b1: CAM entry 0 enabled.

116 - CAM Entry Registers (CAMxx) REGISTER ADDRESS R/W

0xFFF0_3008 R/W CAM0 Most Significant Word Register 0x0000_0000 CAM0L 0xFFF0_300C R/W CAM0 Least Significant Word Register 0x0000_0000 CAM1M 0xFFF0_3010 R/W CAM1 Most Significant Word Register 0x0000_0000 CAM1L 0xFFF0_3014 R/W CAM1 Least Significant Word Register 0x0000_0000 CAM2M 0xFFF0_3018 R/W CAM2 Most Significant Word Register 0x0000_0000 CAM2L 0xFFF0_301C R/W CAM2 Least Significant Word Register 0x0000_0000 CAM3M 0xFFF0_3020 R/W CAM3 Most Significant Word Register 0x0000_0000 CAM3L 0xFFF0_3024 R/W CAM3 Least Significant Word Register 0x0000_0000 CAM4M 0xFFF0_3028 R/W CAM4 Most Significant Word Register 0x0000_0000 CAM4L 0xFFF0_302C R/W CAM4 Least Significant Word Register 0x0000_0000 CAM5M 0xFFF0_3030 R/W CAM5 Most Significant Word Register 0x0000_0000 CAM5L 0xFFF0_3034 R/W CAM5 Least Significant Word Register 0x0000_0000 CAM6M 0xFFF0_3038 R/W CAM6 Most Significant Word Register 0x0000_0000 CAM6L 0xFFF0_303C R/W CAM6 Least Significant Word Register 0x0000_0000 CAM7M 0xFFF0_3040 R/W CAM7 Most Significant Word Register 0x0000_0000 CAM7L 0xFFF0_3044 R/W CAM7 Least Significant Word Register 0x0000_0000 CAM8M 0xFFF0_3048 R/W CAM8 Most Significant Word Register 0x0000_0000 CAM8L 0xFFF0_304C R/W CAM8 Least Significant Word Register 0x0000_0000 CAM9M 0xFFF0_3050 R/W CAM9 Most Significant Word Register 0x0000_0000 CAM9L 0xFFF0_3054 R/W CAM9 Least Significant Word Register 0x0000_0000 CAM10M 0xFFF0_3058 R/W CAM10 Most Significant Word Register 0x0000_0000 CAM10L 0xFFF0_305C R/W CAM10 Least Significant Word Register 0x0000_0000 CAM11M 0xFFF0_3060 R/W CAM11 Most Significant Word Register 0x0000_0000 CAM11L 0xFFF0_3064 R/W CAM11 Least Significant Word Register 0x0000_0000 CAM12M 0xFFF0_3068 R/W CAM12 Most Significant Word Register 0x0000_0000 CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register 0x0000_0000 CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register 0x0000_0000 CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register 0x0000_0000 CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register 0x0000_0000 CAM14L 0xFFF0_307C R/W CAM14 Least Significant Word Register 0x0000_0000 CAM15M 0xFFF0_3080 R/W CAM15 Most Significant Word Register 0x0000_0000 CAM15L 0xFFF0_3084 R/W CAM15 Least Significant Word Register 0x0000_0000

Publication Release Date: September 19, 2006 - 117 - Revision B2 CAMxM MAC Address Byte 5 (MSB) MAC Address Byte 4 MAC Address Byte 3 MAC Address Byte 2 BITS DESCRIPTIONS [31:0] CAMxM The CAMxM(CAMx Most Significant Word) keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address. For example, if the MAC address 00-50-BA-33-BA-44 is kept in CAM entry 1, the register CAM1M is 32’h0050_BA33 and CAM1L is 32’hBA44_0000.

118 - CAMxL MAC Address Byte 1 MAC Address Byte 0 (LSB) Reserved Reserved BITS DESCRIPTIONS [31:16] CAMxL The CAMxL(CAMx Least Significant Word) keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address. For example, if the MAC address 00-50-BA-33-BA-44 is kept in CAM entry 1, the register CAM1M is 32’h0050_BA33 and CAM1L is 32’hBA44_0000. [15:0] Reserved CAM15M Length/Type (MSB) Length/Type OP-Code (MSB) OP-Code

Publication Release Date: September 19, 2006 - 119 - Revision B2 BITS DESCRIPTIONS [31:0] Length/Type Length/Type Field of PAUSE Control Frame In the PAUSE control frame, a length/type field is defined and will be 16’h8808. [15:0] OP-Code OP Code Field of PAUSE Control Frame In the PAUSE control frame, an op code field is defined and will be 16’h0001. CAM15L Operand (MSB) Operand Reserved Reserved BITS DESCRIPTIONS [31:16] Operand Pause Parameter, In the PAUSE control frame, an operand field is defined and controls how much time the destination Ethernet MAC Controller is paused. The unit of the operand is the slot time, the 512 bits time. [15:0] Reserved

120 - Transmit Descriptor Link List Start Address Register (TXDLSA) The Tx descriptor defined in EMC is a link-list data structure. The TXDLSA keeps the starting address of this link-list. In other words, the TXDLSA keeps the starting address of the 1st Tx descriptor. S/W must configure TXDLSA before enable bit TXON of MCMDR register. Register Address R/W

0xFFF0_3088 R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC TXDLSA TXDLSA TXDLSA TXDLSA BITS DESCRIPTIONS [31:0] TXDLSA The TXDLSA(Transmit Descriptor Link-List Start Address) keeps the start address of transmit descriptor link-list. If the S/W enables the bit TXON of MCMDR register, the content of TXDLSA will be loaded into the current transmit descriptor start address register (CTXDSA). The TXDLSA doesn’t be updated by EMC. During the operation, EMC will ignore the bits [1:0] of TXDLSA. This means that each Tx descriptor always must locate at word boundary memory address. Receive Descriptor Link List Start Address Register (RXDLSA) The Rx descriptor defined in EMC is a link-list data structure. The RXDLSA keeps the starting address of this link-list. In other words, the RXDLSA keeps the starting address of the 1st Rx descriptor. S/W must configure RXDLSA before enable bit RXON of MCMDR register. REGISTER ADDRESS R/W 0xFFF0_308C R/W Receive Descriptor Link List Start Address Register 0xFFFF_FFFC

Publication Release Date: September 19, 2006 - 121 - Revision B2 RXDLSA RXDLSA RXDLSA RXDLSA BITS DESCRIPTIONS [31:0] RXDLSA The RXDLSA(Receive Descriptor Link-List Start Address) keeps the start address of receive descriptor link-list. If the S/W enables the bit RXON of MCMDR register, the content of RXDLSA will be loaded into the current receive descriptor start address register (CRXDSA). The RXDLSA doesn’t be updated by EMC. During the operation, EMC will ignore the bits [1:0] of RXDLSA. This means that each Rx descriptor always must locate at word boundary memory address. MAC Command Register (MCMDR) The MCMDR provides the control information for EMC. Some command settings affect both frame transmission and reception, such as bit FDUP, the full/half duplex mode selection, or bit OPMOD, the 100/10M bps mode selection. Some command settings control frame transmission and reception separately, likes bit TXON and RXON. REGISTER ADDRESS R/W 0xFFF0_3090 R/W MAC Command Register 0x0000_0000 Reserved SWR Reserved LBK OPMOD EnMDC FDUP EnSQE SDPZ Reserved NDEF TXON Reserved SPCRC AEP ACP ARP ALP RXON

122 - BITS DESCRIPTIONS [31:25] Reserved [24] SWR The SWR (Software Reset) implements a reset function to make the EMC return default state. The SWR is a self-clear bit. This means after the software reset finished, the SWR will be cleared automatically. Enable SWR can also reset all control and status registers, except for OPMOD bit of MCMDR register. The EMC re-initial is needed after the software reset completed. 1’b0: Software reset completed. 1’b1: Enable software reset. [23:22] Reserved [21] LBK The LBK (Internal Loop Back Select) enables the EMC operating on internal loop-back mode. If the LBK is enabled, the packet transmitted out will be loop-backed to Rx. If the EMC is operating on internal loop-back mode, it also means the EMC is operating on full- duplex mode and the value of FDUP of MCMDR register is ignored. Beside, the LBK doesn’t be affected by SWR bit. 1’b0: The EMC operates in normal mode. 1’b1: The EMC operates in internal loop-back mode. [20] OPMOD The Operation Mode Select defines the EMC is operating on 10M or 100M bps mode. The OPMOD doesn’t be affected by SWR bit. 1’b0: The EMC operates on 10Mbps mode. 1’b1: The EMC operates on 100Mbps mode. [19] EnMDC The Enable MDC Clock Generation controls the MDC clock generation for MII Management Interface. If the EnMDC is set to 1, the MDC clock generation is enabled. Otherwise, the MDC clock generation is disabled. Consequently, if S/W wants to access the registers of external PHY through MII Management Interface, the EnMDC must be set to high. 1’b0: Disable MDC clock generation. 1’b1: Enable MDC clock generation. [18] FDUP The Full Duplex Mode Select controls that EMC is operating on full or half duplex mode. 1’b0: The EMC operates on half duplex mode. 1’b1: The EMC operates on full duplex mode.

Publication Release Date: September 19, 2006 - 123 - Revision B2 Continued. BITS DESCRIPTIONS [17] EnSQE The Enable SQE Checking controls the enable of SQE checking. The SQE checking is only available while EMC is operating on 10M bps and half duplex mode. In other words, the EnSQE cannot affect EMC operation, if the EMC is operating on 100M bps or full duplex mode. 1’b0: Disable SQE checking while EMC is operating on 10Mbps and half duplex mode. 1’b1: Enable SQE checking while EMC is operating on 10Mbps and half duplex mode. [16] SDPZ The Send PAUSE Frame controls the PAUSE control frame transmission. If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set. Then, set SDPZ to 1 enables the PAUSE control frame transmission. The SDPZ is a self-clear bit. This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. It is recommended that only enables SPDZ while EMC is operating on full duplex mode. 1’b0: The PAUSE control frame transmission has completed. 1’b1: Enable EMC to transmit a PAUSE control frame out. [15:10] Reserved [9] NDEF The No Defer controls the enable of deferral exceed counter. If NDEF is set to high, the deferral exceed counter is disabled. The NDEF is only useful while EMC is operating on half duplex mode. 1’b0: The deferral exceed counter is enabled. 1’b1: The deferral exceed counter is disabled.

124 - Continued. BITS DESCRIPTIONS [8] TXON The Frame Transmission ON controls the normal packet transmission of EMC. If the TXON is set to high, the EMC starts the packet transmission process, including the Tx descriptor fetching, packet transmission and Tx descriptor modification. It is must to finish EMC initial sequence before enable TXON. Otherwise, the EMC operation is undefined. If the TXON is disabled during EMC is transmitting a packet out, the EMC stops the packet transmission process after the current packet transmission finished. 1’b0: The EMC stops packet transmission process. 1’b1: The EMC starts packet transmission process. [7:6] Reserved [5] SPCRC The Strip CRC Checksum controls if the length of incoming packet is calculated with 4 bytes CRC checksum. If the SPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. 1’b0: The 4 bytes CRC checksum is included in packet length calculation. 1’b1: The 4 bytes CRC checksum is excluded in packet length calculation. [4] AEP The Accept CRC Error Packet controls the EMC accepts or drops the CRC error packet. If the AEP is set to high, the incoming packet with CRC error will be received by EMC as a good packet. 1’b0: The CRC error packet will be dropped by EMC. 1’b1: The CRC error packet will be accepted by EMC. [3] ACP The Accept Control Packet controls the control frame reception. If the ACP is set to high, the EMC will accept the control frame. Otherwise, the control frame will be dropped. It is recommended that S/W only enable AEP while EMC is operating on full duplex mode. 1’b0: The control frame will be dropped by EMC. 1’b1: The control frame will be accepted by EMC.

Publication Release Date: September 19, 2006 - 125 - Revision B2 Continued. BITS DESCRIPTIONS [2] ARP The Accept Runt Packet controls the runt packet, which length is less than 64 bytes, reception. If the ARP is set to high, the EMC will accept the runt packet. Otherwise, the runt packet will be dropped. 1’b0: The runt packet will be dropped by EMC. 1’b1: The runt packet will be accepted by EMC. [1] ALP The Accept Long Packet controls the long packet, which packet length is greater than 1518 bytes, reception. If the ALP is set to high, the EMC will accept the long packet. Otherwise, the long packet will be dropped. 1’b0: The long packet will be dropped by EMC. 1’b1: The long packet will be accepted by EMC. [0] RXON The Frame Reception ON controls the normal packet reception of EMC. If the RXON is set to high, the EMC starts the packet reception process, including the Rx descriptor fetching, packet reception and Rx descriptor modification. It is must to finish EMC initial sequence before enable RXON. Otherwise, the EMC operation is undefined. If the RXON is disabled during EMC is receiving an incoming packet, the EMC stops the packet reception process after the current packet reception finished. 1’b0: The EMC stops packet reception process. 1’b1: The EMC starts packet reception process. MII Management Data Register (MIID) The EMC provides MII management function to access the control and status registers of the external PHY. The MIID register is used to store the data that will be written into the registers of external PHY for write command or the data that is read from the registers of external PHY for read command. REGISTER ADDRESS R/W 0xFFF0_3094 R/W MII Management Data Register 0x0000_0000

126 - Reserved Reserved MIIData MIIData BITS DESCRIPTIONS [31:16] Reserved [15:0] MIIData The MII Management Data is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command. MII Management Control and Address Register (MIIDA) The EMC provides MII management function to access the control and status registers of the external PHY. The MIIDA register is used to keep the MII management command information, like the register address, external PHY address, MDC clocking rate, read/write etc. REGISTER ADDRESS R/W

0xFFF0_3098 R/W MII Management Control and Address Register 0x0090_0000 Reserved MDCCR MDCON PreSP BUSY Write Reserved PHYAD Reserved PHYRAD

Publication Release Date: September 19, 2006 - 127 - Revision B2 BITS DESCRIPTIONS [31:24] Reserved [23:20] MDCCR The MDC Clock Rating controls the MDC clock rating for MII Management I/F. period for MDC shall be 400ns. In other words, the maximum frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus clock, the HCLK. Consequently, for different HCLKs the different ratios are required to generate appropriate MDC clock. The following table shows relationship between HCLK and MDC clock in different MDCCR configurations. The THCLK indicates the period of HCLK. [19] MDC The MDC Clock ON Always controls the MDC clock generation. If the MDCON is set to high, the MDC clock actives always. Otherwise, the MDC will only active while S/W issues a MII management command. 1’b0: The MDC clock will only active while S/W issues a MII management command. 1’b1: The MDC clock actives always. [18] PreSP The Preamble Suppress controls the preamble field generation of MII management frame. If the PreSP is set to high, the preamble field generation of MII management frame is skipped. 1’b0: Preamble field generation of MII management frame is not skipped. 1’b1: Preamble field generation of MII management frame is skipped. [17] BUSY The Busy Bit controls the enable of the MII management frame generation. If S/W wants to access registers of external PHY, it set BUSY to high and EMC generates the MII management frame to external PHY through MII Management I/F. The BUSY is a self-clear bit. This means the BUSY will be cleared automatically after the MII management command finished. 1’b0: The MII management has finished. 1’b1: Enable EMC to generate a MII management command to external PHY. [16] Write The Write Command defines the MII management command is a read or write. 1’b0: The MII management command is a read command. 1’b1: The MII management command is a write command. [15:13] Reserved

128 - Continued. BITS DESCRIPTIONS [12:8] PHYAD The PHY Address keeps the address to differentiate which external PHY is the target of the MII management command. [7:5] Reserved [4:0] PHYRAD The PHY Register Address keeps the address to indicate which register of external PHY is the target of the MII management command. MDCCR [23:20] MDC CLOCK PERIOD MDC CLOCK FREQUENCY 4’b0000 4 x THCLK HCLK/4 4’b0001 6 x THCLK HCLK/6 4’b0010 8 x THCLK HCLK/8 4’b0011 12 x THCLK HCLK/12 4’b0100 16 x THCLK HCLK/16 4’b0101 20 x THCLK HCLK/20 4’b0110 24 x THCLK HCLK/24 4’b0111 28 x THCLK HCLK/28 4’b1000 30 x THCLK HCLK/30 4’b1001 32 x THCLK HCLK/32 4’b1010 36 x THCLK HCLK/36 4’b1011 40 x THCLK HCLK/40 4’b1100 44 x THCLK HCLK/44 4’b1101 48 x THCLK HCLK/48 4’b1110 54 x THCLK HCLK/54 4’b1111 60 x THCLK HCLK/60 MII Management Function Frame Format function is used for the purpose of controlling the PHY and gathering status from the PHY. The MII management frame format is shown as follow.

Publication Release Date: September 19, 2006 - 129 - Revision B2 Management frame fields PRE ST OP PHYAD REGAD TA DATA IDLE READ 1…1 AAAAA RRRRR DDDDDDDDDDDDDDDD Z WRITE 1…1 AAAAA RRRRR DDDDDDDDDDDDDDDD Z MII Management Function Configure Sequence READ WRITE Set appropriate MDCCR. Set PHYAD and PHYRAD. Set Write to 1’b0 Set bit BUSY to 1’b1 to send a MII management frame out. Wait BUSY to become 1’b0. Read data from MIID register. Finish the read command. Write data to MIID register Set appropriate MDCCR. Set PHYAD and PHYRAD. Set Write to 1’b1 Set bit BUSY to 1’b1 to send a MII management frame out. Wait BUSY to become 1’b0. Finish the write command. FIFO Threshold Control Register (FFTCR) The FFTCR defines the high and low threshold of internal FIFOs, including TxFIFO and RxFIFO. The threshold of internal FIFOs is related to EMC request generation and when the frame transmission starts. The FFTCR also defines the burst length of AHB bus cycle for system memory access. REGISTER ADDRESS R/W 0xFFF0_309C R/W FIFO Threshold Control Register 0x0000_0101 Reserved Reserved BLength Reserved Reserved TxTHD Reserved RxTHD

130 - BITS DESCRIPTIONS [31:22] Reserved [21:20] Blength The DMA Burst Length defines the burst length of AHB bus cycle while EMC accesses system memory. 2’b00: 4 words 2’b01: 8 words 2’b10: 16 words 2’b11: 16 words [19:10] Reserved [9:8] TxTHD The TxFIFO Low Threshold controls when TxDMA requests internal arbiter for data transfer between system memory and TxFIFO. The TxTHD defines not only the low threshold of TxFIFO, but also the high threshold. The high threshold is the twice of low threshold always. During the packet transmission, if the TxFIFO reaches the high threshold, the TxDMA stops generate request to transfer frame data from system memory to TxFIFO. If the frame data in TxFIFO is less than low threshold, TxDMA starts to transfer frame data from system memory to TxFIFO. The TxTHD also defines when the TxMAC starts to transmit frame out to network. The TxMAC starts to transmit the frame out while the TxFIFO first time reaches the high threshold during the transmission of the frame. If the frame data length is less than TxFIFO high threshold, the TxMAC starts to transmit the frame out after the frame data are all inside the TxFIFO. 2’b00: Undefined. 2’b01: TxFIFO low threshold is 64B and high threshold is 128B. 2’b10: TxFIFO low threshold is 80B and high threshold is 160B. 2’b11: TxFIFO low threshold is 96B and high threshold is 192B. [7:2] Reserved [1:0] RxTHD The RxFIFO High Threshold controls when RxDMA requests internal arbiter for data transfer between RxFIFO and system memory. The RxTHD defines not only the high threshold of RxFIFO, but also the low threshold. The low threshold is the half of high threshold always. During the packet reception, if the RxFIFO reaches the high threshold, the RxDMA starts to transfer frame data from RxFIFO to system memory. If the frame data in RxFIFO is less than low threshold, RxDMA stops to transfer the frame data to system memory. 2’b00: Depend on the burst length setting. If the burst length is 8 words, high threshold is 8 words, too. 2’b01: RxFIFO high threshold is 64B and low threshold is 32B. 2’b10: RxFIFO high threshold is 128B and low threshold is 64B. 2’b11: RxFIFO high threshold is 192B and low threshold is 96B.

Publication Release Date: September 19, 2006 - 131 - Revision B2 Transmit Start Demand Register (TSDR) If the Tx descriptor is not available for use of TxDMA after the TXON of MCMDR register is enabled, the FSM (Finite State Machine) of TxDMA enters the Halt state and the frame transmission is halted. After the S/W has prepared the new Tx descriptor for frame transmission, it must issue a write command to TSDR register to make TxDMA leave Halt state and contiguous frame transmission. The TSDR is a write only register and read from this register is undefined. The write to TSDR register has took effect only while TxDMA stayed at Halt state. Register Address R/W 0xFFF0_30A0 W Transmit Start Demand Register Undefined BITS DESCRIPTIONS [31:0] Reserved Receive Start Demand Register (RSDR) If the Rx descriptor is not available for use of RxDMA after the RXON of MCMDR register is enabled, the FSM (Finite State Machine) of RxDMA enters the Halt state and the frame reception is halted. After the S/W has prepared the new Rx descriptor for frame reception, it must issue a write command to RSDR register to make RxDMA leave Halt state and contiguous frame reception. The RSDR is a write only register and read from this register is undefined. The write to RSDR register has took effect only while RxDMA stayed at Halt state. REGISTER ADDRESS R/W 0xFFF0_30A4 W Receive Start Demand Register Undefined BITS DESCRIPTIONS [31:0] Reserved Maximum Receive Frame Control Register (DMARFC) The DMARFC defines the maximum frame length for a received frame that can be stored in the system memory. It is recommend that only use this register while S/W wants to receive a frame which length is greater than 1518 bytes. REGISTER ADDRESS R/W 0xFFF0_30A8 R/W Maximum Receive Frame Control Register 0x0000_0800

132 - Reserved Reserved RXMS RXMS BITS DESCRIPTIONS [31:16] Reserved [15:0] RXMS The Maximum Receive Frame Length defines the maximum frame length for received frame. If the frame length of received frame is greater than RXMS, and bit EnDFO of MIEN register is also enabled, the bit DFOI of MISTA register is set and the Rx interrupt is triggered. It is recommended that only use RXMS to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes. MAC Interrupt Enable Register (MIEN) The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR for frame reception and TXINTR for frame transmission, are generated from EMC to CPU. REGISTER ADDRESS R/W

0xFFF0_30AC R/W MAC Interrupt Enable Register 0x0000_0000 Reserved EnTxBErr EnTDU EnLC EnTXABT EnNCS EnEXDEF EnTXCP EnTXEMP EnTXINTR Reserved EnCFR Reserved EnRxBErr EnRDU EnDEN EnDFO EnMMP EnRP EnALIE EnRXGD EnPTLE EnRXOV EnCRCE EnRXINTR

Publication Release Date: September 19, 2006 - 133 - Revision B2 BITS DESCRIPTIONS [31:25] Reserved [24] EnTxBErr The Enable Transmit Bus Error Interrupt controls the TxBErr interrupt generation. If TxBErr of MISTA register is set, and both EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TxBErr of MISTA register is set. 1’b0: TxBErr of MISTA register is masked from Tx interrupt generation. 1’b1: TxBErr of MISTA register can participate in Tx interrupt generation. [23] EnTDU The Enable Transmit Descriptor Unavailable Interrupt controls the TDU interrupt generation. If TDU of MISTA register is set, and both EnTDU and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TDU of MISTA register is set. 1’b0: TDU of MISTA register is masked from Tx interrupt generation. 1’b1: TDU of MISTA register can participate in Tx interrupt generation. [22] EnLC The Enable Late Collision Interrupt controls the LC interrupt generation. If LC of MISTA register is set, and both EnLC and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnLC or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the LC of MISTA register is set. 1’b0: LC of MISTA register is masked from Tx interrupt generation. 1’b1: LC of MISTA register can participate in Tx interrupt generation. [21] EnTXABT The Enable Transmit Abort Interrupt controls the TXABT interrupt generation. If TXABT of MISTA register is set, and both EnTXABT and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXABT or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXABT of MISTA register is set. 1’b0: TXABT of MISTA register is masked from Tx interrupt generation. 1’b1: TXABT of MISTA register can participate in Tx interrupt generation.

134 - Continued. BITS DESCRIPTIONS [20] EnNCS The Enable No Carrier Sense Interrupt controls the NCS interrupt generation. If NCS of MISTA register is set, and both EnNCS and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnNCS or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the NCS of MISTA register is set. 1’b0: NCS of MISTA register is masked from Tx interrupt generation. 1’b1: NCS of MISTA register can participate in Tx interrupt generation. [19] EnEXDEF The Enable Defer Exceed Interrupt controls the EXDEF interrupt generation. If EXDEF of MISTA register is set, and both EnEXDEF and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnEXDEF or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the EXDEF of MISTA register is set. 1’b0: EXDEF of MISTA register is masked from Tx interrupt generation. 1’b1: EXDEF of MISTA register can participate in Tx interrupt generation. [18] EnTXCP The Enable Transmit Completion Interrupt controls the TXCP interrupt generation. If TXCP of MISTA register is set, and both EnTXCP and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXCP or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXCP of MISTA register is set. 1’b0: TXCP of MISTA register is masked from Tx interrupt generation. 1’b1: TXCP of MISTA register can participate in Tx interrupt generation. [17] EnTXEMP The Enable Transmit FIFO Underflow Interrupt controls the TXEMP interrupt generation. If TXEMP of MISTA register is set, and both EnTXEMP and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXEMP or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXEMP of MISTA register is set. 1’b0: TXEMP of MISTA register is masked from Tx interrupt generation. 1’b1: TXEMP of MISTA register can participate in Tx interrupt generation.

Publication Release Date: September 19, 2006 - 135 - Revision B2 Continued. BITS DESCRIPTIONS [16] EnTXINTR The EnTXINTR controls the Tx interrupt generation. If Enable Transmit Interrupt is enabled and TXINTR of MISTA register is high, EMC generates the Tx interrupt to CPU. If EnTXINTR is disabled, no Tx interrupt is generated to CPU even the status bits 17~24 of MISTA are set and the corresponding bits of MIEN are enabled. In other words, if S/W wants to receive Tx interrupt from EMC, this bit must be enabled. And, if S/W doesn’t want to receive any Tx interrupt from EMC, disables this bit. 1’b0: TXINTR of MISTA register is masked and Tx interrupt generation is disabled. 1’b1: TXINTR of MISTA register is unmasked and Tx interrupt generation is enabled. [15] Reserved [14] EnCFR The Enable Control Frame Receive Interrupt controls the CFR interrupt generation. If CFR of MISTA register is set, and both EnCFR and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnCFR or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the CFR of MISTA register is set. 1’b0: CFR of MISTA register is masked from Rx interrupt generation. 1’b1: CFR of MISTA register can participate in Rx interrupt generation. [13:12] Reserved [11] EnRxBErr The Enable Receive Bus Error Interrupt controls the RxBerr interrupt generation. If RxBErr of MISTA register is set, and both EnRxBErr and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRxBErr or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RxBErr of MISTA register is set. 1’b0: RxBErr of MISTA register is masked from Rx interrupt generation. 1’b1: RxBErr of MISTA register can participate in Rx interrupt generation. [10] EnRDU The Enable Receive Descriptor Unavailable Interrupt controls the RDU interrupt generation. If RDU of MISTA register is set, and both EnRDU and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRDU or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RDU of MISTA register is set. 1’b0: RDU of MISTA register is masked from Rx interrupt generation. 1’b1: RDU of MISTA register can participate in Rx interrupt generation.

136 - Continued. BITS DESCRIPTIONS [9] EnDEN The Enable DMA Early Notification Interrupt controls the DENI interrupt generation. If DENI of MISTA register is set, and both EnDEN and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the DENI of MISTA register is set. 1’b0: DENI of MISTA register is masked from Rx interrupt generation. 1’b1: DENI of MISTA register can participate in Rx interrupt generation. [8] EnDFO The Enable Maximum Frame Length Interrupt controls the DFOI interrupt generation. If DFOI of MISTA register is set, and both EnDFO and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnDFO or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the DFOI of MISTA register is set. 1’b0: DFOI of MISTA register is masked from Rx interrupt generation. 1’b1: DFOI of MISTA register can participate in Rx interrupt generation. [7] EnMMP The Enable More Missed Packet Interrupt controls the MMP interrupt generation. If MMP of MISTA register is set, and both EnMMP and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnMMP or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the MMP of MISTA register is set. 1’b0: MMP of MISTA register is masked from Rx interrupt generation. 1’b1: MMP of MISTA register can participate in Rx interrupt generation. [6] EnRP The Enable Runt Packet Interrupt controls the RP interrupt generation. If RP of MISTA register is set, and both EnRP and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRP or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RP of MISTA register is set. 1’b0: RP of MISTA register is masked from Rx interrupt generation. 1’b1: RP of MISTA register can participate in Rx interrupt generation. [5] EnALIE The Enable Alignment Error Interrupt controls the ALIE interrupt generation. If ALIE of MISTA register is set, and both EnALIE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnALIE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the ALIE of MISTA register is set. 1’b0: ALIE of MISTA register is masked from Rx interrupt generation. 1’b1: ALIE of MISTA register can participate in Rx interrupt generation.

Publication Release Date: September 19, 2006 - 137 - Revision B2 Continued. BITS DESCRIPTIONS [4] EnRXGD The Enable Receive Good Interrupt controls the RXGD interrupt generation. If RXGD of MISTA register is set, and both EnRXGD and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRXGD or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RXGD of MISTA register is set. 1’b0: RXGD of MISTA register is masked from Rx interrupt generation. 1’b1: RXGD of MISTA register can participate in Rx interrupt generation. [3] EnPTLE The Enable Packet Too Long Interrupt controls the PTLE interrupt generation. If PTLE of MISTA register is set, and both EnPTLE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnPTLE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the PTLE of MISTA register is set. 1’b0: PTLE of MISTA register is masked from Rx interrupt generation. 1’b1: PTLE of MISTA register can participate in Rx interrupt generation. [2] EnRXOV The Enable Receive FIFO Overflow Interrupt controls the RXOV interrupt generation. If RXOV of MISTA register is set, and both EnRXOV and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRXOV or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RXOV of MISTA register is set. 1’b0: RXOV of MISTA register is masked from Rx interrupt generation. 1’b1: RXOV of MISTA register can participate in Rx interrupt generation. [1] EnCRCE The Enable CRC Error Interrupt controls the CRCE interrupt generation. If CRCE of MISTA register is set, and both EnCRCE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnCRCE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the CRCE of MISTA register is set. 1’b0: CRCE of MISTA register is masked from Rx interrupt generation. 1’b1: CRCE of MISTA register can participate in Rx interrupt generation.

138 - Continued. BITS DESCRIPTIONS [0] EnRXINTR The Enable Receive Interrupt controls the Rx interrupt generation. If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx interrupt is generated to CPU even the status bits 1~14 of MISTA are set and the corresponding bits of MIEN are enabled. In other words, if S/W wants to receive Rx interrupt from EMC, this bit must be enabled. And, if S/W doesn’t want to receive any Rx interrupt from EMC, disables this bit. 1’b0: RXINTR of MISTA register is masked and Rx interrupt generation is disabled. 1’b1: RXINTR of MISTA register is unmasked and Rx interrupt generation is enabled. MAC Interrupt Status Register (MISTA) The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO status and also NATA processing status. The statuses kept in MISTA will trigger the reception or transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the status and also clears the interrupt. REGISTER ADDRESS R/W

0xFFF0_30B0 R/W MAC Interrupt Status Register 0x0000_0000 Reserved TxBErr TDU LC TXABT NCS EXDEF TXCP TXEMP TXINTR Reserved CFR Reserved RxBErr RDU DENI DFOI MMP RP ALIE RXGD PTLE RXOV CRCE RXINTR

Publication Release Date: September 19, 2006 - 139 - Revision B2 BITS DESCRIPTIONS [31:25] Reserved [24] TxBErr The Transmit Bus Error Interrupt high indicates the memory controller replies ERROR response while EMC access system memory through TxDMA during packet transmission process. Reset EMC is recommended while TxBErr status is high. If the TxBErr is high and EnTxBErr of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TxBErr status. 1’b0: No ERROR response is received. 1’b1: ERROR response is received. [23] TDU The Transmit Descriptor Unavailable Interrupt high indicates that there is no available Tx descriptor for packet transmission and TxDMA will stay at Halt state. Once, the TxDMA enters the Halt state, S/W must issues a write command to TSDR register to make TxDMA leave Halt state while new Tx descriptor is available. If the TDU is high and EnTDU of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TDU status. 1’b0: Tx descriptor is available. 1’b1: Tx descriptor is unavailable. [22] LC The Late Collision Interrupt high indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. If the LC is high and EnLC of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the LC status. 1’b0: No collision occurred in the outside of 64 bytes collision window. 1’b1: Collision occurred in the outside of 64 bytes collision window.

140 - Continued. BITS DESCRIPTIONS [21] TXABT The Transmit Abort Interrupt high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMC is operating on half-duplex mode. If the TXABT is high and EnTXABT of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXABT status. 1’b0: Packet doesn’t incur 16 consecutive collisions during transmission. 1’b1: Packet incurred 16 consecutive collisions during transmission. [20] NCS The No Carrier Sense Interrupt high indicates the MII I/F signal CRS doesn’t active at the start of or during the packet transmission. The NCS is only available while EMC is operating on half-duplex mode. If the NCS is high and EnNCS of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the NCS status. 1’b0: CRS signal actives correctly. 1’b1: CRS signal doesn’t active at the start of or during the packet transmission. [19] EXDEF The Defer Exceed Interrupt high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NDEF of MCMDR is disabled, and EMC is operating on half-duplex mode. If the EXDEF is high and EnEXDEF of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the EXDEF status. 1’b0: Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). 1’b1: Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).

Publication Release Date: September 19, 2006 - 141 - Revision B2 Continued. BITS DESCRIPTIONS [18] TXCP The Transmit Completion Interrupt indicates the packet transmission has completed correctly. If the TXCP is high and EnTXCP of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXCP status. 1’b0: The packet transmission doesn’t complete. 1’b1: The packet transmission has completed. [17] TXEMP The Transmit FIFO Underflow Interrupt high indicates the TxFIFO underflow occurred during packet transmission. While the TxFIFO underflow occurred, the EMC will retransmit the packet automatically without S/W intervention. If the TxFIFO underflow occurred often, it is recommended that modify TxFIFO threshold control, the TxTHD of FFTCR register, to higher level. If the TXEMP is high and EnTXEMP of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXEMP status. 1’b0: No TxFIFO underflow occurred during packet transmission. 1’b0: TxFIFO underflow occurred during packet transmission. [16] TXINTR The Transmit Interrupt indicates the Tx interrupt status. If TXINTR high and its corresponding enable bit, EnTXINTR of MISTA register, is also high indicates the EMC generates Tx interrupt to CPU. If TXINTR is high but EnTXINTR of MISTA is disabled, no Tx interrupt is generated. The TXINTR is logic OR result of the bits 17~24 in MISTA register do logic AND with the corresponding bits in MIEN register. In other words, if one of the bits 17~24 in MISTA register is high and its corresponding enable bit in MIEN register is also enabled, the TXINTR will be high. Because the TXINTR is a logic OR result, clears bits 17~24 of MISTA register makes TXINTR be cleared, too. 1’b0: No status of bits 17~24 in MISTA is set or no enable of bits 17~24 in MIEN is turned on. 1’b1: At least one status of bits 17~24 in MISTA is set and its corresponding enable bit is turned on. [15] Reserved

142 - Continued. BITS DESCRIPTIONS [14] CFR The Control Frame Receive Interrupt high indicates EMC receives a flow control frame. The CFR only available while EMC is operating on full duplex mode. If the CFR is high and EnCFR of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the CFR status. 1’b0: The EMC doesn’t receive the flow control frame. 1’b1: The EMC receives a flow control frame. [13:12] Reserved [11] RxBErr The Receive Bus Error Interrupt high indicates the memory controller replies ERROR response while EMC access system memory through RxDMA during packet reception process. Reset EMC is recommended while RxBErr status is high. If the RxBErr is high and EnRxBErr of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RxBErr status. 1’b0: No ERROR response is received. 1’b1: ERROR response is received. [10] RDU The Receive Descriptor Unavailable Interrupt high indicates that there is no available Rx descriptor for packet reception and RxDMA will stay at Halt state. Once, the RxDMA enters the Halt state, S/W must issues a write command to RSDR register to make RxDMA leave Halt state while new Rx descriptor is available. If the RDU is high and EnRDU of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RDU status. 1’b0: Rx descriptor is available. 1’b1: Rx descriptor is unavailable. [9] DENI The DMA Early Notification Interrupt high indicates the EMC has received the Length/Type field of the incoming packet. If the DENI is high and EnDENI of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the DENI status. 1’b0: The Length/Type field of incoming packet has not received yet. 1’b1: The Length/Type field of incoming packet has received.

Publication Release Date: September 19, 2006 - 143 - Revision B2 Continued. BITS DESCRIPTIONS [8] DFOI The Maximum Frame Length Interrupt high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped. If the DFOI is high and EnDFO of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the DFOI status. 1’b0: The length of the incoming packet doesn’t exceed the length limitation configured in DMARFC. 1’b1: The length of the incoming packet has exceeded the length limitation configured in DMARFC. [7] MMP The More Missed Packet Interrupt high indicates the MPCNT, Missed Packet Count, has overflow. If the MMP is high and EnMMP of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the MMP status. 1’b0: The MPCNT has not rolled over yet. 1’b1: The MPCNT has rolled over yet. [6] RP Runt Packet Interrupt The RP high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped. If the ARP of MCMDR register is set, the short packet is regarded as a good packet and RP will not be set. If the RP is high and EnRP of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RP status. 1’b0: The incoming frame is not a short frame or S/W wants to receive a short frame. 1’b1: The incoming frame is a short frame and dropped. [5] ALIE The Alignment Error Interrupt high indicates the length of the incoming frame is not a multiple of byte. If the ALIE is high and EnALIE of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the ALIE status. 1’b0: The frame length is a multiple of byte. 1’b1: The frame length is not a multiple of byte.

144 - Continued. BITS DESCRIPTIONS [4] RXGD The Receive Good Interrupt high indicates the frame reception has completed. If the RXGD is high and EnRXGD of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RXGD status. 1’b0: The frame reception has not complete yet. 1’b1: The frame reception has completed. [3] PTLE The Packet Too Long Interrupt high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. If the ALP of MCMDR register is set, the long packet will be regarded as a good packet and PTLE will not be set. If the PTLE is high and EnPTLE of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the PTLE status. 1’b0: The incoming frame is not a long frame or S/W wants to receive a long frame. 1’b1: The incoming frame is a long frame and dropped. [2] RXOV The Receive FIFO Overflow Interrupt high indicates the RxFIFO overflow occurred during packet reception. While the RxFIFO overflow occurred, the EMC drops the current receiving packer. If the RxFIFO overflow occurred often, it is recommended that modify RxFIFO threshold control, the RxTHD of FFTCR register, to higher level. If the RXOV is high and EnRXOV of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RXOV status. 1’b0: No RxFIFO overflow occurred during packet reception. 1’b0: RxFIFO overflow occurred during packet reception. [1] CRCE The CRC Error Interrupt high indicates the incoming packet incurred the CRC error and the packet is dropped. If the AEP of MCMDR register is set, the CRC error packet will be regarded as a good packet and CRCE will not be set. If the CRCE is high and EnCRCE of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the CRCE status. 1’b0: The frame doesn’t incur CRC error. 1’b1: The frame incurred CRC error.

Publication Release Date: September 19, 2006 - 145 - Revision B2 Continued. BITS DESCRIPTIONS [0] RXINTR The Receive Interrupt indicates the Rx interrupt status. If RXINTR high and its corresponding enable bit, EnRXINTR of MISTA register, is also high indicates the EMC generates Rx interrupt to CPU. If RXINTR is high but EnRXINTR of MISTA is disabled, no Rx interrupt is generated. The RXINTR is logic OR result of the bits 1~14 in MISTA register do logic AND with the corresponding bits in MIEN register. In other words, if one of the bits 1~14 in MISTA register is high and its corresponding enable bit in MIEN register is also enabled, the RXINTR will be high. Because the RXINTR is a logic OR result, clears bits 1~14 of MISTA register makes RXINTR be cleared, too. 1’b0: No status of bits 1~14 in MISTA is set or no enable of bits 1~14 in MIEN is turned on. 1’b1: At least one status of bits 1~14 in MISTA is set and its corresponding enable bit is turned on. MAC General Status Register (MGSTA) The MGSTA also keeps the statuses of EMC. But the statuses in the MGSTA will not trigger any interrupt. The MGSTA is a write clear register and write 1 to corresponding bit clears the status. REGISTER ADDRESS R/W 0xFFF0_30B4 R/W MAC General Status Register 0x0000_0000 Reserved Reserved Reserved TXHA SQE PAU DEF CCNT Reserved RFFull RXHA CFR

146 - BITS DESCRIPTIONS [31:12] Reserved [11] TXHA The Transmission Halted high indicates the next normal packet transmission process will be halted because the bit TXON of MCMDR is disabled be S/W. 1’b0: Next normal packet transmission process will go on. 1’b1: Next normal packet transmission process will be halted. [10] SQE The Signal Quality Error high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. The SQE error check will only be done while both bit EnSQE of MCMDR is enabled and EMC is operating on 10Mbps half-duplex mode. 1’b0: No SQE error found at end of packet transmission. 1’b0: SQE error found at end of packet transmission. [9] PAU The Transmission Paused high indicates the next normal packet transmission process will be paused temporally because EMC received a PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to transmit a PAUSE control frame out. 1’b0: Next normal packet transmission process will go on. 1’b1: Next normal packet transmission process will be paused. [8] DEF The Deferred Transmission high indicates the packet transmission has deferred once. The DEF is only available while EMC is operating on half- duplex mode. 1’b0: Packet transmission doesn’t defer. 1’b1: Packet transmission has deferred once. [7:4] CCNT The Collision Count indicates the how many collision occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1. [3] Reserved [2] RFFull The RxFIFO Full indicates the RxFIFO is full due to four 64-byte packets are kept in RxFIFO and the following incoming packet will be dropped. 1’b0: The RxFIFO is not full. 1’b1: The RxFIFO is full and the following incoming packet will be dropped. [1] RXHA The Receive Halted high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W. 1’b0: Next normal packet reception process will go on. 1’b1: Next normal packet reception process will be halted. [0] CFR The Control Frame Received high indicates EMC receives a flow control frame. The CFR only available while EMC is operating on full duplex mode. 1’b0: The EMC doesn’t receive the flow control frame. 1’b1: The EMC receives a flow control frame.

Publication Release Date: September 19, 2006 - 147 - Revision B2 Missed Packet Count Register (MPCNT) The MPCNT keeps the number of packets that were dropped due to various types of receive errors. The MPCNT is a read clear register. In addition, S/W also can write an initial value to MPCNT and the missed packet counter will start counting from that initial value. If the missed packet counter is overflow, the MMP of MISTA will be set. REGISTER ADDRESS R/W 0xFFF0_30B8 R/W Missed Packet Count Register 0x0000_7FFF Reserved Reserved MPC MPC BITS DESCRIPTIONS [31:16] Reserved [15:0] MPC The Miss Packet Count indicates the number of packets that were dropped due to various types of receive errors. The following type of receiving error makes missed packet counter increase: Incoming packet is incurred RxFIFO overflow. Incoming packet is dropped due to RXON is disabled. Incoming packet is incurred CRC error. MAC Receive Pause Count Register (MRPC) The EMC of W90P710 supports the PAUSE control frame reception and recognition. If EMC received a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored in the MRPC register. The MRPC register will keep the same while Tx of EMC is pausing due to the PAUSE control frame is received. The MRPC is read only and write to this register has no effect.

148 - REGISTER ADDRESS R/W

0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000 Reserved Reserved MRPC MRPC BITS DESCRIPTIONS [31:16] Reserved [15:0] MRPC The MAC Receive Pause Count keeps the operand field of the PAUSE control frame. It indicates how many slot time (512 bit time) the Tx of EMC will be paused. MAC Receive Pause Current Count Register (MRPCC) The EMC of W90P710 supports the PAUSE control frame reception and recognition. If EMC received a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored into a down count timer. The MRPCC shows the current value of that down count timer for S/W to know how long the Tx of EMC will be paused. The MRPCC is read only and write to this register has no effect. REGISTER ADDRESS R/W 0xFFF0_30C0 R MAC Receive Pause Current Count Register 0x0000_0000

Publication Release Date: September 19, 2006 - 149 - Revision B2 Reserved Reserved MRPCC MRPCC BITS DESCRIPTIONS [31:16] Reserved [15:0] MRPCC The MAC Receive Pause Current Count shows the current value of that down count timer. If a new PAUSE control frame is received before the timer count down to zero, the new operand of the PAUSE control frame will be stored into the down count timer and the timer starts count down from the new value. MAC Remote Pause Count Register (MREPC) The EMC of W90P710 supports the PAUSE control frame transmission. After the PAUSE control frame is transmitted out completely, a timer starts to count down from the value of operand of the transmitted PAUSE control frame. The MREPC shows the current value of this down count timer. The MREPC is read only and write to this register has no effect. REGISTER ADDRESS R/W 0xFFF0_30C4 R MAC Remote Pause Count Register 0x0000_0000 Reserved Reserved MREPC MREPC

150 - BITS DESCRIPTIONS [31:16] Reserved [15:0] MREPC The MAC Remote Pause Count shows the current value of the down count timer that starts to count down from the value of operand of the transmitted PAUSE control frame. DMA Receive Frame Status Register (DMARFS) The DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. This register is writing clear and writes 1 to corresponding bit clears the bit. REGISTER ADDRESS R/W

0xFFF0_30C8 R/W DMA Receive Frame Status Register 0x0000_0000 Reserved Reserved RXFLT RXFLT BITS DESCRIPTIONS [31:16] Reserved [15:0] RXFLT The Receive Frame Length/Type keeps the Length/Type field of each incoming Ethernet packet. If the bit EnDEN of MIEN is enabled and the Length/Type field of incoming packet has received, the bit DENI of MISTA will be set and trigger interrupt. And, the content of Length/Type field will be stored in RXFLT.

Publication Release Date: September 19, 2006 - 151 - Revision B2 Current Transmit Descriptor Start Address Register (CTXDSA) The CTXDSA keeps the start address of Tx descriptor that is used by TxDMA currently. The CTXDSA is read only and write to this register has no effect. REGISTER ADDRESS R/W 0xFFF0_30CC R Current Transmit Descriptor Start Address Register 0x0000_0000 CTXDSA CTXDSA CTXDSA CTXDSA BITS DESCRIPTIONS [31:0] CTXDSA Current Transmit Descriptor Start Address Current Transmit Buffer Start Address Register (CTXBSA) The CTXDSA keeps the start address of Tx frame buffer that is used by TxDMA currently. The CTXBSA is read only and write to this register has no effect. REGISTER ADDRESS R/W 0xFFF0_30D0 R Current Transmit Buffer Start Address Register 0x0000_0000 CTXBSA CTXBSA CTXBSA CTXBSA

152 - BITS DESCRIPTIONS [31:0] CTXBSA Current Transmit Buffer Start Address Current Receive Descriptor Start Address Register (CRXDSA) The CRXDSA keeps the start address of Rx descriptor that is used by RxDMA currently. The CRXDSA is read only and write to this register has no effect. REGISTER ADDRESS R/W

0xFFF0_30D4 R Current Receive Descriptor Start Address Register 0x0000_0000 CRXDSA CRXDSA CRXDSA CRXDSA BITS DESCRIPTIONS [31:0] CRXDSA Current Receive Descriptor Start Address Current Receive Buffer Start Address Register (CRXBSA) The CRXBSA keeps the start address of Rx frame buffer that is used by RxDMA currently. The CRXBSA is read only and write to this register has no effect. REGISTER ADDRESS R/W 0xFFF0_30D8 R Current Receive Buffer Start Address Register 0x0000_0000

Publication Release Date: September 19, 2006 - 153 - Revision B2 CRXBSA CRXBSA CRXBSA CRXBSA BITS DESCRIPTIONS [31:0] CRXBSA Current Receive Buffer Start Address Receive Finite State Machine Register (RXFSM) The RXFSM shows the current value of the FSM (Finite State Machine) of RxDMA and RxFIFO controller. The RXFSM is read only and write to it has no effect. The RXFSM is used only for debug. REGISTER ADDRESS R/W 0xFFF0_3200 R Receive Finite State Machine Register 0x0081_1101 RX_FSM RX_FSM Reserved RxBuf_FSM RXFetch_FSM RXClose_FSM RFF_FSM

154 - BITS DESCRIPTIONS [31:23] RX_FSM RxDMA FSM [22] Reserved [21:16] RXBuf_FSM Receive Buffer FSM [15:12] RXFetch_FSM Receive Descriptor Fetch FSM [11:8] RXClose_FSM Receive Descriptor Close FSM [7:0] RFF_FSM RxFIFO Controller FSM Transmit Finite State Machine Register (TXFSM) The TXFSM shows the current value of the FSM (Finite State Machine) of TxDMA and TxFIFO controller. The TXFSM is read only and write to it has no effect. The TXFSM is used only for debug. REGISTER ADDRESS R/W

0xFFF0_3204 R Transmit Finite State Machine Register 0x0101_1101 TX_FSM Reserved TxBuf_FSM TXFetch_FSM TXClose_FSM Reserved TFF_FSM

Publication Release Date: September 19, 2006 - 155 - Revision B2 BITS DESCRIPTIONS [31:24] TX_FSM TxDMA FSM [23:22] Reserved [21:16] TXBuf_FSM Transmit Buffer FSM [15:12] TXFetch_FSM Transmit Descriptor Fetch FSM [11:8] TXClose_FSM Transmit Descriptor Close FSM [7:5] Reserved [4:0] TFF_FSM TxFIFO Controller FSM Finite State Machine Register 0 (FSM0) The FSM0 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM0 is read only and write to it has no effect. The FSM0 is used only for debug. REGISTER ADDRESS R/W 0xFFF0_3208 R Finite State Machine Register 0 0x0001_0101 Reserved TXMAC_FSM TXMAC_FSM Reserved TXDefer_FSM STA_FSM BITS DESCRIPTIONS [31:26] Reserved [25:16] TXMAC_FSM TxMAC FSM [15:14] Reserved [13:8] TXDefer_FSM Transmit Defer Process FSM [7:0] STA_FSM MII Management I/F FSM

156 - Finite State Machine Register 1 (FSM1) The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug. Register Address R/W

0xFFF0_320C R Finite State Machine Register 1 0x1100_0100 Reserved ARB_FSM TxPause_FSM Reserved Reserved AHB_FSM Reserved BITS DESCRIPTIONS [31] Reserved [30:28] ARB_FSM Internal Arbiter FSM [27:24] TxPause_FSM Transmit PAUSE Control Frame FSM [23:14] Reserved [13:8] AHB_FSM [13:8]: AHB Master FSM [7:0] RESERVED Debug Configuration Register (DCR) The DCR is for debug only to multiplex different signal group out. In FPGA emulation, the signals are outputted to probe pins in emulation board. In real chip, the signals are outputted through the GPIO pins. Register Address R/W 0xFFF0_3210 R/W Debug Configuration Register 0x0000_003f

Publication Release Date: September 19, 2006 - 157 - Revision B2 Reserved Enable Reserved Reserved Out Config BITS DESCRIPTIONS [31:24] Reserved [23:22] Enable The Function Enable outputs two function enable signals to external stimulus circuit. At this stage, only the bit 22 is used for external random collision generator. The random collision generator used only in FPGA emulation. [21:8] Reserved [7:6] Out The Flag Out provides two output flags to trigger Logic Analyzer for debug. These two bits can be written at any time. [5:0] Config The Configuration controls which group of internal signals can be multiplexed out for debug. Each group includes 16 signals. CONFIG SIGNALS CONFIG SIGNALS 6’h00 OUT [6], TransDone, GrantLost, Trans_CTR [4:0], LAST, TransCtrExpire, DMode_AHB_CS [5:0] 6’h01 OUT [6], DMode_TxBuf_CS [6:0] DMode_TXFSM_CS [7:0] 6’h02 OUT [6], DMode_RXBuf_CS [5:0], DMode_RXFSM_CS [8:0] 6’h03 OUT [6], TXFIFO_HT, TXFIFO_LT, DMode_TFF_CS [4:0], DMode_RFF_CS [7:0] 6’h04 TxBuf_DRDY, TFF_WPTR [5:0], TX_START, TXSTART, READ, TFF_RPTR [5:0] 6’h05 WRITE, RFF_WPTR [5:0], RXFIFO_HT, RXFIFO_LT, RxBuf_ACK, RFF_RPTR [5:0]

158 - Continued. CONFIG SIGNALS CONFIG SIGNALS 6’h06 R0_PTLE, RxStart, SFD, WasSFD, RxFrame, WrByte, Rx_OvFlow, 1’b0, R0_RBC [7:0] 6’h07 R0_CRCE, RX_DV_In, SynStart, R0_DB, Rx_OvFlow, WRITECTR [2:0], RxByte [7:0] 6’h08 Reserved 6’h09 Reserved 6’h0A OUT [7:6], RegMISTA_Rx_W, RXERR_sync, R0_CRCE, R0_PTLE, R0_RP, RegMISTA_Tx_W, T0_EXDEF, T0_TXABT, T0_CCNT [3:0], 2’b00 6’h0B OUT [7:6], MCMDR_SDPZ_Clr, RegMCMDR_SDPZ_Clr, DMode_Pause_CS [3:0], MacCtlFra, PauseFra, PauseTx, MacCtlFra_sync, PauseFra_sync, PAUSE, Pause_en, FDUP 6’h0C OUT [7:6], FrameWPtr [1:0], FrameRPtr [1:0], RFF_One, FrameWPtr_Inc, FrameRPtr_Inc, Rounding, NexPktStartPtr [5:0] 6’h0D OUT [7:6], ARB_REQ_Set, ARB_REQ_Clr, DMode_ARB_CS [2:0], TransDone, GrantLost, TransCtrExpire, Trans_CTR [4:0], BURST 6’h0E R0_CRCE, Rx_OvFlow, R0_MRE, CRCERR, DAMATCH, RxFrame, SFD, RxMIIErr, SynStart, Hi_Lo_Syn, New_DataValid, L_RxFrame, RxStart, DataValid, Hi_Lo, RX_DV_In 6’h0F OUT [6], WRITE, RFF_WPTR [5:0], RxReuse, RxBuf_ACK, RFF_RPTR [5:0] 6’h10 WRITE, RFF_CS [7:1], RFF_WPTR [5:0], RXERR_sync, RxReuse 6’h11 OUT [6], TX_CLK, TX_EN, TXD [3:0], RX_CLK, RX_DV, RX_ER, RXD [3:0], CRS, COL 6’h12 OUT [6], TXSTART, TX_START, DMode_TFF_CS [4:0], TXSTART_Set, TXSTART_Clr, TXSTART_Re_Set, FrameWaiting, Deferring, COL, TXCOL, TXCOL_sync 6’h13 OUT [6], DMode_TxBuf_CS[6:0], DMode_TFF_CS[4:0], TXFIFO_UF, TXFIFO_HT, TXOK_sync 6’h14 OUT [6], READ, READ_sync, READ_Mask, ReadMask_sync, TFF_RPTR [5:0], DMode_TFF_CS [4:0] 6’h15

Publication Release Date: September 19, 2006 - 159 - Revision B2 Debug Mode MAC Information Register (DMMIR) The DMMIR keeps the information of MAC module for debug. REGISTER ADDRESS R/W 0xFFF0_3214 R Debug Mode MAC Information Register 0x0000_0000 Reserved Reserved RBC RBC BITS DESCRIPTIONS [31:16] Reserved [15:0] RBC Receive Byte Count BIST Mode Register (BISTR) The BISTR controls the BIST (Built In Self Test) for embedded SRAM, 256B for RxFIFO and 256B for TxFIFO. REGISTER ADDRESS R/W 0xFFF0_3300 R/W BIST Mode Register 0x0000_0000 Reserved Reserved Reserved Reserved BistFail Finish BMEn

160 - BITS DESCRIPTIONS [31:5] Reserved [3:2] BistFail The BIST Fail indicates if the BIST test fails or succeeds. If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation. If BistFail[2] high indicates the embedded SRAM for TxFIFO BIST test failed. If BistFail[3] high indicates the embedded SRAM for RxFIFO BIST test failed. The BistFail is a write clear field. Write 1 to this field clears the content and write 0 has no effect. [1] Finish The BIST Operation Finish indicates the end of the BIST operation. When BIST controller finishes all operations, this bit will be high. The Finish is a write clear field. Write 1 to this field clears the content and write 0 has no effect. [0] BMEn The BIST Mode Enable is used to enable the BIST operation. If high enables the BIST controller to do embedded SRAM test. This bit is also used to do the reset for BIST circuit. It is necessary to reset the BIST circuit one clock cycle at least in order to initialize the BIST properly. The BMEn can be disabled by write 0.

Publication Release Date: September 19, 2006 - 161 - Revision B2

6.6 GDMA Controller

The W90P710 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs the following data transfers without the CPU intervention: y Memory-to-memory (memory to/from memory) y Memory –to – IO y IO- to -memory The on-chip GDMA can be started by the software or external DMA request nXDREQ. Software can also be used to restart the GDMA operation after it has been stopped. The CPU can recognize the completion of a GDMA operation by software polling or when it receives an internal GDMA interrupt. The W90P710 GDMA controller can increment source or destination address, decrement them as well, and conduct 8- bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. The GDMA includes the following features y AMBA AHB compliant y Supports 4-data burst mode to boost performance y Provides support for external GDMA device y Demand mode speeds up external GDMA operations 6.6.1 GDMA Functional Description The GDMA directly transfers data between source and destination. The GDMA starts to transfer data after it receives service requests from nXDREQ signal or software. When the entire data have been transferred completely, the GDMA becomes idle. Nevertheless, if another transfer is needed, then the GDMA must be programmed again. There are three transfer modes: Single Mode Single mode requires a GDMA request for each data transfer. A GDMA request (nXDREQ or software) causes one byte, one half-word, or one word to transfer if the 4-data burst mode is disabled, or four times of transfer width is the 4-data burst mode is enabled. Block Mode The assertion of a single GDMA request causes all of the data to be transferred in a single operation. The GDMA transfer is completed when the current transfer count register reaches zero. Demand Mode The GDMA continues transferring data until the GDMA request input nXDREQ becomes inactive.

162 - 6.6.2 GDMA Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER ADDRESS R/W

GDMA_CTL0 0xFFF0_4000 R/W Channel 0 Control Register 0x0000_0000 GDMA_SRCB0 0xFFF0_4004 R/W Channel 0 Source Base Address Register 0x0000_0000 GDMA_DSTB0 0xFFF0_4008 R/W Channel 0 Destination Base Address Register 0x0000_0000 GDMA_TCNT0 0xFFF0_400C R/W Channel 0 Transfer Count Register 0x0000_0000 GDMA_CSRC0 0xFFF0_4010 R Channel 0 Current Source Address Register 0x0000_0000 GDMA_CDST0 0xFFF0_4014 R Channel 0 Current Destination Address Register 0x0000_0000 GDMA_CTCNT0 0xFFF0_4018 R Channel 0 Current Transfer Count Register 0x0000_0000 Channel 1 GDMA_CTL1 0xFFF0_4020 R/W Channel 1 Control Register 0x0000_0000 GDMA_SRCB1 0xFFF0_4024 R/W Channel 1 Source Base Address Register 0x0000_0000 GDMA_DSTB1 0xFFF0_4028 R/W Channel 1 Destination Base Address Register 0x0000_0000 GDMA_TCNT1 0xFFF0_402C R/W Channel 1 Transfer Count Register 0x0000_0000 GDMA_CSRC1 0xFFF0_4030 R Channel 1 Current Source Address Register 0x0000_0000 GDMA_CDST1 0xFFF0_4034 R Channel 1 Current Destination Address Register 0x0000_0000 GDMA_CTCNT1 0xFFF0_4038 R Channel 1 Current Transfer Count Register 0x0000_0000 Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1) REGISTER ADDRESS R/W GDMA_CTL0 0xFFF0_4000 R/W Channel 0 Control Register 0x0000_0000 GDMA_CTL1 0xFFF0_4020 R/W Channel 1 Control Register 0x0000_0000 RESERVED TC_WIDTH REQ_SEL REQ_ATV ACK_ATV RW_TC SABNDERR DABNDERR GDMAERR AUTOIEN TC BLOCK SOFTREQ DM RESERVED TWS SBMS RESERVED BME SIEN SAFIX DAFIX SADIR DADIR GDMAMS RESERVED GDMAEN

Publication Release Date: September 19, 2006 - 163 - Revision B2 BITS DESCRIPTIONS [31] RESERVED [30:28] TC_WIDTH nRTC/nWTC active width selection, from 1 to 7 HCLK cycles. [27:26] REQ_SEL External request pin selection, if GDMAMS [3:2]=00, REQ_SEL will be don’t care. If REQ_SEL [27:26]=00, external request don’t use. If REQ_SEL [27:26]=01, use nXDREQ. If REQ_SEL [27:26]=10, external request don’t use. If REQ_SEL [27:26]=11, external request don’t use. [25] REQ_ATV nXDREQ High/Low active selection 1’b0 = nXDREQ is LOW active. 1’b1 = nXDREQ is HIGH active. [24] ACK_ATV nXDACK High/Low active selection 1’b0 = nXDACK is LOW active. 1’b1 = nXDACK is HIGH active. [23] RW_TC Read/Write terminal count output selection. 1’b0 = output to nRTC. 1’b1 = output to nWTC. [22] SABNDERR Source address Boundary alignment Error flag If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00 If TWS [13:12]=01, GDMA_SRCB [0] should be 0 The address boundary alignment should be depended on TWS [13:12]. 1’b0 = the GDMA_SRCB is on the boundary alignment. 1’b1 = the GDMA_SRCB not on the boundary alignment The SABNDERR register bits just can be read only. [21] DABNDERR Destination address Boundary alignment Error flag If TWS [13:12]=10, GDMA_DSTB [1:0] should be 00 If TWS [13:12]=01, GDMA_DSTB [0] should be 0 The address boundary alignment should be depended on TWS [13:12]. 1’b0 = the GDMA_DSTB is on the boundary alignment. 1’b1 = the GDMA_DSTB not on the boundary alignment The DABNDERR register bits just can be read only. [20] GDMATERR GDMA Transfer Error 1’b0 = No error occurs 1’b1 = Hardware sets this bit on a GDMA transfer failure Transfer error will generate GDMA interrupt

164 - Continued BITS DESCRIPTIONS [19] AUTOIEN Auto initialization Enable 1’b0 = Disables auto initialization 1’b1 Enables auto initialization, the GDMA_CSRC0/1, GDMA_CDST0/1,and GDMA_CTCNT0/1 registers are updated by the GDMA_SRC0/1,GDMA_DST0/1,and GDMA_TCNT0/1 registers automatically when transfer is complete. [18] TC Terminal Count 1’b0 = Channel does not expire 1’b1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 0. TC [18] is the GDMA interrupt flag. TC [18] or GDMATERR[20] will generate interrupt [17] BLOCK Bus Lock 1’b0 = Unlocks the bus during the period of transfer 1’b1 = Locks the bus during the period of transfer [16] SOFTREQ Software Triggered GDMA Request Software can request the GDMA transfer service by setting this bit to 1. This bit is automatically cleared by hardware when the transfer is completed. This bit is available only while GDMAMS [3:2] register bits are set on software mode (memory to memory). [15] DM Demand Mode 1’b0 = Normal external GDMA mode 1’b1 = When this bit is set to 1, the external GDMA operation is speeded up. When external GDMA device is operating in the demand mode, the GDMA transfers data as long as the external GDMA request signal nXDREQ is active. The amount of data transferred depends on how long the nXDREQ is active. When the nXDREQ is active and GDMA gets the bus in Demand mode, DMA holds the system bus until the nXDREQ signal becomes non-active. Therefore, the period of the active nXDREQ signal should be carefully tuned such that the entire operation does not exceed an acceptable interval (for example, in a DRAM refresh operation). [14] Reserved

Publication Release Date: September 19, 2006 - 165 - Revision B2 Continued BITS DESCRIPTIONS [11] SBMS Single/Block Mode Select 1’b0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation. 1’b1 = Selects block mode. It requires a single external GDMA request during the atomic GDMA operation. An atomic GDMA operation is defined as the sequence of GDMA operations until the transfer count register reaches zero. [10] Reserved [9] BME Burst Mode Enable 1’b0 = Disables the 4-data burst mode 1’b1 = Enables the 4-data burst mode FF there are 16 words to be transferred, and BME [9]=1, the GDMA_TCNT should be 0x04; However, if BME [9]=0, the GDMA_TCNT should be 0x10. [8] SIEN Stop Interrupt Enable 1’b0 = Do not generate an interrupt when the GDMA operation is stopped 1’b1 = Interrupt is generated when the GDMA operation is stopped [7] SAFIX Source Address Fixed 1’b0 = Source address is changed during the GDMA operation 1’b1 = Do not change the destination address during the GDMA operation. This feature can be used when data were transferred from a single source to multiple destinations. [6] DAFIX Destination Address Fixed 1’b0 = Destination address is changed during the GDMA operation 1’b1 = Do not change the destination address during the GDMA operation. This feature can be used when data were transferred from multiple sources to a single destination. [5] SADIR Source Address Direction 1’b0 = Source address is incremented successively 1’b1 = Source address is decremented successively

166 - Continued BITS DESCRIPTIONS [4] DADIR Destination Address Direction 1’b0 = Destination address is incremented successively 1’b1 = Destination address is decremented successively [3:2] GDMAMS GDMA Mode Select 00 = Software mode (memory-to-memory) 01 = External nXDREQ mode for external device 10 = Reserved 11 = Reserved [1] Reserved [0] GDMAEN GDMA Enable 1’b0 = Disables the GDMA operation 1’b1 = Enables the GDMA operation; this bit will be clear automatically when the transfer is complete on AUTOIEN [19] register bit is on Disable mode. Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1) The GDMA channel starts reading its data from the source address as defined in this source base address register. REGISTER ADDRESS R/W

GDMA_SRCB0 0xFFF0_4004 R/W Channel 0 Source Base Address Register 0x0000_0000 GDMA_SRCB1 0xFFF0_4024 R/W Channel 1 Source Base Address Register 0x0000_0000 SRC_BASE_ADDR [31:24] SRC_BASE_ADDR [23:16] SRC_BASE_ADDR [15:8] SRC_BASE_ADDR [7:0] BITS DESCRIPTIONS [31:0] SRC_BASE_ADDR 32-bit Source Base Address

Publication Release Date: September 19, 2006 - 167 - Revision B2 Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA_DSTB1) Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1) The GDMA channel starts writing its data to the destination address as defined in this destination base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address. REGISTER ADDRESS R/W GDMA_DSTB0 0xFFF0_4008 R/W Channel 0 Destination Base Address Register 0x0000_0000 GDMA_DSTB1 0xFFF0_4028 R/W Channel 1 Destination Base Address Register 0x0000_0000 DST_BASE_ADDR [31:24] DST_BASE_ADDR [23:16] DST_BASE_ADDR [15:8] DST_BASE_ADDR [7:0] BITS DESCRIPTIONS [31:0] DST_BASE_ADDR 32-bit Destination Base Address Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) REGISTER ADDRESS R/W GDMA_TCNT0 0xFFF0_400C R/W Channel 0 Transfer Count Register 0x0000_0000 GDMA_TCNT1 0xFFF0_402C R/W Channel 1 Transfer Count Register 0x0000_0000 Reserved TFR_CNT [23:16] TFR_CNT [15:8] TFR_CNT [7:0]

168 - BITS DESCRIPTIONS [31:24] Reserved [23:0] TFR_CNT The TFR_CNT represents the required number of GDMA transfers. The maximum transfer count is 16M –1. Channel 0/1 Current Source Register (GDMA_CSRC0, GDMA_CSRC1) REGISTER ADDRESS R/W

GDMA_CSRC0 0xFFF0_4010 R Channel 0 Current Source Address Register 0x0000_0000 GDMA_CSRC1 0xFFF0_4030 R Channel 1 Current Source Address Register 0x0000_0000 CURRENT_SRC_ADDR [31:24] CURRENT_SRC_ADDR [23:16] CURRENT_SRC_ADDR [15:8] CURRENT_SRC_ADDR [7:0] BITS DESCRIPTIONS [31:0] CURRENT_SRC_ADDR The 32-bit Current Source Address indicates the source address where the GDMA transfer is just occurring. During a block transfer, the GDMA determines the successive source addresses by adding to or subtracting from the source base address. Depending on the settings you make to the control register, the current source address will remain the same or will be incremented or decremented.

Publication Release Date: September 19, 2006 - 169 - Revision B2 Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) REGISTER ADDRESS R/W GDMA_CDST0 0xFFF0_4014 R Channel 0 Current Destination Address Register 0x0000_0000 GDMA_CDST1 0xFFF0_4034 R Channel 1 Current Destination Address Register 0x0000_0000 CURRENT_DST_ADDR [31:24] CURRENT_DST_ADDR [23:16] CURRENT_DST_ADDR [15:8] CURRENT_DST_ADDR [7:0] BITS DESCRIPTIONS [31:0] CURRENT_DST_ADDR The 32-bit Current Destination Address indicates the destination address where the GDMA transfer is just occurring. During a block transfer, the GDMA determines the successive destination addresses by adding to or subtracting from the destination base address. Depending on the settings you make to the control register, the current destination address will remain the same or will be incremented or decremented. Channel 0/1 Current Transfer Count Register (GDMA_CTCNT0, GDMA_CTCNT1) The Current transfer count register indicates the number of transfer being performed. REGISTER ADDRESS R/W GDMA_CTCNT0 0xFFF0_4018 R Channel 0 Current Transfer Count Register 0x0000_0000 GDMA_CTCNT1 0xFFF0_4038 R Channel 1 Current Transfer Count Register 0x0000_0000

170 - Reserved CURENT_TFR_CNT [23:16] CURRENT_TFR_CNT [15:8] CURRENT_TFR_CNT [7:0] BITS DESCRIPTIONS [31:24] Reserved [23:0] CURRENT_TFR_CNT Current Transfer Count register The current transfer count register indicates the number of transfer being performed

Publication Release Date: September 19, 2006 - 171 - Revision B2

6.7 USB Host Controller

The Universal Serial Bus (USB) is a low-cost, low-to-mid-speed peripheral interface standard intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a high- bandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a network of peripheral devices. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. Peripherals may be attached, configured, used, and detached, while the host and other peripherals continue operation (i.e. hot plug and unplug is supported). A major design goal of the USB standard was to allow flexible, plug-and-play networks of USB devices. In any USB network, there will be only one host, but there can be many devices and hubs. The USB Host Controller has the following features:

Open Host Controller Interface (OHCI) Revision 1.0 compatible.
USB Revision 1.1 compatible
Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices.
Handles all the USB protocol.
Built-in DMA for real-time data transfer
Multiple low power modes for efficient power management 6.7.1 USB Host Functional Description 6.7.1.1 AHB Interface The OpenHCI Host Controller is connected to the system by the AHB bus. The design requires both master and slave bus operations. As a master, the Host Controller is responsible for running cycles on the AHB bus to access EDs and TDs as well as transferring data between memory and the local data buffer. As a slave, the Host Controller monitors the cycles on the AHB bus and determines when to respond to these cycles. Configuration and non-real-time control access to the Host Controller operational registers are through the AHB bus slave interface. 6.7.1.2 Host Controller List Processing The List Processor manages the data structures from the Host Controller Driver and coordinates all activity within the Host Controller. Frame Management Frame Management is responsible for managing the frame specific tasks required by the USB specification and the OpenHCI specification. These tasks are: 1) Management of the OpenHCI frame specific Operational Registers 2) Operation of the Largest Data Packet Counter. 3) Performing frame qualifications on USB Transaction requests to the SIE. 4) Generate SOF token requests to the SIE.

172 - Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific event sets a specific bit in the HcInterruptStatus register. Host Controller Bus Master The Host Controller Bus Master is the central block in the data path. The Host Controller Bus Master coordinates all access to the AHB Interface. There are two sources of bus mastering within Host Controller: the List Processor and the Data Buffer Engine. Data Buffer The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a combination of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword AHB Holding Register. 6.7.1.3 USB Interface The USB interface includes the integrated Root Hub with two external ports, Port 1 and Port 2 as well as the Serial Interface Engine (SIE) and USB clock generator. The interface combines responsibility for executing bus transactions requested by the HC as well as the hub and port management specified by USB. 6.7.2 USB Host Controller Registers Map REGISTER ADDRESS R/W

Publication Release Date: September 19, 2006 - 173 - Revision B2 Continued. REGISTER ADDRESS R/W 0xFFF0_5030 R/W Host Controller Done Head Register 0x0000_0000 HcFmInterval 0xFFF0_5034 R/W Host Controller Frame Interval Register 0x0000_2EDF HcFrameRemaining 0xFFF0_5038 R Host Controller Frame Remaining Register 0x0000_0000 HcFmNumber 0xFFF0_503C R Host Controller Frame Number Register 0x0000_0000 HcPeriodicStart 0xFFF0_5040 R/W Host Controller Periodic Start Register 0x0000_0000 HcLSThreshold 0xFFF0_5044 R/W Host Controller Low Speed Threshold Register 0x0000_0628 HcRhDescriptorA 0xFFF0_5048 R/W Host Controller Root Hub Descriptor A Register 0x0100_0002 HcRhDescriptorB 0xFFF0_504C R/W Host Controller Root Hub Descriptor B Register 0x0000_0000 HcRhStatus 0xFFF0_5050 R/W Host Controller Root Hub Status Register 0x0000_0000 HcRhPortStatus [1] 0xFFF0_5054 R/W Host Controller Root Hub Port Status [1] 0x0000_0000 HcRhPortStatus [2] 0xFFF0_5058 R/W Host Controller Root Hub Port Status [2] 0x0000_0000 USB Configuration Registers TestModeEnable 0xFFF0_5200 R/W USB Test Mode Enable Register 0x0XXX_XXXX OperationalModeEnable 0xFFF0_5204 R/W USB Operational Mode Enable Register 0x0000_0000

174 - Host Controller Revision Register REGISTER OFFSET ADDRESS R/W

0xFFF0_5000 R Host Controller Revision Register 0x0000_0010 Reserved Reserved Reserved Revision BITS [31:8] Reserved Reserved. Read/Write 0's [7:0] Revision Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.0 specification. (X.Y = XYh) Host Controller Control Register REGISTER ADDRESS R/W 0xFFF0_5004 R/W Host Controller Control Register 0x0000_0000 Reserved Reserved Reserved RWCE RWC IR HCFS BLE CLE ISE PLE CBR

Publication Release Date: September 19, 2006 - 175 - Revision B2 BITS [31:11] Reserved Reserved. Read/Write 0's [10] RWCE RemoteWakeupConnectedEnable If a remote wakeup signal is supported, this bit enables that operation. Since there is no remote wakeup signal supported, this bit is ignored. [9] RWC RemoteWakeupConnected This bit indicated whether the HC supports a remote wakeup signal. This implementation does not support any such signal. The bit is hard-coded to ‘0.’ [8] INR InterruptRouting This bit is used for interrupt routing: 0: Interrupts routed to normal interrupt mechanism (INT). 1: Interrupts routed to SMI. [7:6] HCFS HostControllerFunctionalState This field sets the Host Controller state. The Controller may force a state change from USB SUSPEND to USB RESUME after detecting resume signaling from a downstream port. States are: 00: USB RESET 01: USBRESUME 10: USBOPERATIONAL 11: USBSUSPEND [5] BLE BulkListEnable When set this bit enables processing of the Bulk list. [4] CLE Control Listenable When set this bit enables processing of the Control list. [3] ISE Isochronous Enable When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED. [2] PLE Periodic Listenable When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame. [1:0] CBR ControlBulkServiceRatio Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1 where N is the number of Control Endpoints (i.e. ‘00’ = 1 Control Endpoint; ‘11’ = 3 Control Endpoints)

176 - Host Controller Command Status Register REGISTER ADDRESS R/W

HcCommandStatus 0xFFF0_5008 R/W Host Controller Command Status Register 0x0000_0000 Reserved Reserved Reserved Reserved OCR BLF CLF HCR BITS [31:18] Reserved Reserved [17:16] SOC ScheduleOverrunCount This field is increment every time the SchedulingOverrun bit in HcInterruptStatus is set. The count wraps from ‘11’ to ‘00.’ [15:4] Reserved Reserved. Read/Write 0's [3] OCR OwnershipChangeRequest When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit is cleared by software. [2] BLF BulkListFilled Set to indicate there is an active ED on the Bulk List. The bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk List. [1] CLF ControlListFilled Set to indicate there is an active ED on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. [0] HCR HostControllerReset This bit is set to initiate the software reset. This bit is cleared by the Host Controller, upon completed of the reset operation.

Publication Release Date: September 19, 2006 - 177 - Revision B2 Host Controller Interrupt Status Register All bits are set by hardware and cleared by software. REGISTER ADDRESS R/W HcInterruptStatus 0xFFF0_500C R/W Host Controller Interrupt Status Register 0x0000_0000 Reserved OCH Reserved Reserved Reserved Reserved RHSC FNO URE RDT SOF WDH SCO BITS [31] Reserved Reserved [30] OCH OwnershipChange This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. [29:7] Reserved [6] RHSC RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed. [5] FNO FrameNumberOverflow Set when bit 15 of FrameNumber changes value. [4] URE UnrecoverableError This event is not implemented and is hard-coded to ‘0.’ Writes are ignored. [3] RDT ResumeDetected Set when Host Controller detects resume signaling on a downstream port. [2] SOF StartOfFrame Set when the Frame Management block signals a ‘Start of Frame’ event.

178 - Continued. BITS

[1] WDH WritebackDoneHead Set after the Host Controller has written HcDoneHead to HccaDoneHead. [0] SCHO SchedulingOverrun Set when the List Processor determines a Schedule Overrun has occurred. Host Controller Interrupt Enable Register Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit unchanged. REGISTER ADDRESS R/W 0xFFF0_5010 R/W Host Controller Interrupt Enable Register 0x0000_0000 MIE OCE Reserved Reserved Reserved Reserved RHCE FNOE UREE RDTE SOFE WDHE SCHOE BITS [31] MIE MasterInterruptEnable This bit is a global interrupt enable. A write of ‘1’ allows interrupts to be enabled via the specific enable bits listed above. [30] OCE OwnershipChangeEnable 0: Ignore 1: Enable interrupt generation due to Ownership Change. [29:7] Reserved Reserved. Read/Write 0's [6] RHSCE RootHubStatusChangeEnable 0: Ignore 1: Enable interrupt generation due to Root Hub Status Change.

Publication Release Date: September 19, 2006 - 179 - Revision B2 Continued. BITS [5] FNOE FrameNumberOverflowEnable 0: Ignore 1: Enable interrupt generation due to Frame Number Overflow. [4] UREE UnrecoverableErrorEnable This event is not implemented. All writes to this bit are ignored. [3] RDTE ResumeDetectedEnable 0: Ignore 1: Enable interrupt generation due to Resume Detected. [2] SOFE StartOfFrameEnable 0: Ignore 1: Enable interrupt generation due to Start of Frame. [1] WDHE WritebackDoneHeadEnable 0: Ignore 1: Enable interrupt generation due to Write-back Done Head. [0] SCHOE SchedulingOverrunEnable 0: Ignore 1: Enable interrupt generation due to Scheduling Overrun. Host Controller Interrupt Disable Register Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit unchanged. REGISTER ADDRESS R/W 0xFFF0_5014 R/W Host Controller Interrupt Disable Register 0x0000_0000 MIE OCE Reserved Reserved Reserved Reserved RHSCE FNOE UREE RDTE SOFE WDHE SCHOE

180 - BITS

[31] MIE MasterInterruptEnable Global interrupt disable. A write of ‘1’ disables all interrupts. [30] OCE OwnershipChangeEnable 0: Ignore 1: Disable interrupt generation due to Ownership Change. [29:7] Reserved Reserved. Read/Write 0's [6] RHSCE RootHubStatusChangeEnable 0: Ignore 1: Disable interrupt generation due to Root Hub Status Change. [5] FNOE FrameNumberOverflowEnable 0: Ignore 1: Disable interrupt generation due to Frame Number Overflow. [4] UREE UnrecoverableErrorEnable This event is not implemented. All writes to this bit will be ignored. [3] RDTE ResumeDetectedEnable 0: Ignore 1: Disable interrupt generation due to Resume Detected. [2] SOFE StartOfFrameEnable 0: Ignore 1: Disable interrupt generation due to Start of Frame. [1] WDHE WritebackDoneHeadEnable 0: Ignore 1: Disable interrupt generation due to Write-back Done Head. [0] SCHOE SchedulingOverrunEnable 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun.

Publication Release Date: September 19, 2006 - 181 - Revision B2 Host Controller Communication Area Register REGISTER ADDRESS R/W 0xFFF0_5018 R/W Host Controller Communication Area Register 0x0000_0000 HCCA HCCA HCCA Reserved BITS [31:8] HCCA HCCA Pointer to HCCA base address. [7:0] Reserved Reserved Host Controller Period Current ED Register REGISTER ADDRESS R/W 0xFFF0_501C R/W Host Controller Period Current ED Register 0x0000_0000 PCED PCED PCED PCED BITS [31:4] PCED PeriodCurrentED. Pointer to the current Periodic List ED. [3:0] Reserved Reserved. Read/Write 0's

182 - Host Controller Control Head ED Register REGISTER ADDRESS R/W

0xFFF0_5020 R/W Host Controller Control Head ED Register 0x0000_0000 CHED CHED CHED CHED Reserved BITS [31:4] CHED ControlHeadED Pointer to the Control List Head ED. [3:0] Reserved Reserved Host Controller Control Current ED Register REGISTER OFFSET ADDRESS R/W 0xFFF0_5024 R/W Host Controller Control Current ED Register 0x0000_0000 CCED CCED CCED CCED Reserved BITS [31:4] CCED ControlCurrentED Pointer to the current Control List ED. [3:0] Reserved Reserved. Read/Write 0's

Publication Release Date: September 19, 2006 - 183 - Revision B2 Host Controller Bulk Head ED Register REGISTER OFFSET ADDRESS R/W 0xFFF0_5028 R/W Host Controller Bulk Head ED Register 0x0000_0000 BHED BHED BHED BHED Reserved BITS [31:4] BHED BulkHeadED. Pointer to the Bulk List Head ED. [3:0] Reserved Reserved. Read/Write 0's Host Controller Bulk Current ED Register REGISTER OFFSET ADDRESS R/W 0xFFF0_502C R/W Host Controller Bulk Current ED Register 0x0000_0000 BCED BCED BCED BCED Reserved BITS [31:4] BCED BulkCurrentED. Pointer to the current Bulk List ED. [3:0] Reserved Reserved. Read/Write 0's

184 - Host Controller Done Head Register REGISTER ADDRESS R/W

0xFFF0_5030 R/W Host Controller Done Head Register 0x0000_0000 DOHD DOHD DOHD DOHD Reserved BITS [31:4] DOHD DoneHead. Pointer to the current Done List Head ED. [3:0] Reserved Reserved. Read/Write 0's Host Controller Frame Interval Register REGISTER ADDRESS R/W 0xFFF0_5034 R/W Host Controller Frame Interval Register 0x0000_2ED F FINTVT FSLDP FSLDP Reserved FINTV FINTV

Publication Release Date: September 19, 2006 - 185 - Revision B2 BITS This bit is toggled by HCD when it loads a new value into Frame Interval. [30:16] FSLDP FSLargestDataPacket This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. [15:14] Reserved Reserved. Read/Write 0's [13:0] FINTV Frame Interval This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. Host Controller Frame Remaining Register REGISTER ADDRESS R/W 0xFFF0_5038 R Host Controller Frame Remaining Register 0x0000_0000 FRMT Reserved Reserved Reserved FRM FRM BITS [31] FRMT FrameRemainingToggle Loaded with FrameIntervalToggle when Frame Remaining is loaded. [30:14] Reserved Reserved. Read/Write 0's [13:0] FRM Frame Remaining When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.

186 - Host Controller Frame Number Register REGISTER ADDRESS R/W

0xFFF0_503C R Host Controller Frame Number Register 0x0000_0000 Reserved Reserved FRMN FRMN BITS [31:16] Reserved Reserved. Read/Write 0's [15:0] FRMN FrameNumber This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining. The count rolls over from ‘000Fh’ to ‘0h.’ Host Controller Periodic Start Register REGISTER ADDRESS R/W 0xFFF0_5040 R/W Host Controller Periodic Start Register 0x0000_0000 Reserved Reserved PERST PERST

Publication Release Date: September 19, 2006 - 187 - Revision B2 BITS [31:14] Reserved Reserved. Read/Write 0's [13:0] PERST PeriodicStart This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. Host Controller Low Speed Threshold Register REGISTER ADDRESS R/W 0xFFF0_5044 R/W Host Controller Low Speed Threshold Register 0x0000_0628 Reserved Reserved Reserved LsThreshold LsTreshold BITS [31:12] Reserved Rsvd. Read/Write 0's [11:0] LsTreshold LSThreshold This field contains a value used by the Frame Management block to determine whether or not a low speed transaction can be started in the current frame. Host Controller Root Hub Descriptor A Register This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. This bit should not be written during normal operation. REGISTER ADDRESS R/W 0xFFF0_5048 R/W Host Controller Root Hub Descriptor A Register 0x0100.0002

188 - POTPGT Reserved Reserved OCPM OCPM DEVT NPSW PSWM NDSP BITS

[31:24] POTPGT PowerOnToPowerGoodTime This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms. Only bits [25:24] is implemented as R/W. The remaining bits are read only as ‘0’. It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided. This field should be written to support system implementation. This field should always be written to a non-zero value. [23:13] Reserved Reserved. Read/Write 0's [12] NOCP NoOverCurrentProtection Global over-current reporting implemented in HYDRA-2. This bit should be written to support the external system port over-current implementation. 0 = Over-current status is reported 1 = Over-current status is not reported [11] OCPM OverCurrentProtectionMode Global over-current reporting implemented in HYDRA-2. This bit should be written 0 and is only valid when NoOverCurrentProtection is cleared. 0 = Global Over-Current 1 = Individual Over-Current [10] DEVT DeviceType table of none-4is not a compound device. [9] NPSW NoPowerSwitching Global power switching implemented in HYDRA-2. This bit should be written to support the external system port power switching implementation. 0 = Ports are power switched. 1 = Ports are always powered on. [8] PSWM PowerSwitchingMode Global power switching mode implemented in HYDRA-2. This bit is only valid when NoPowerSwitching is cleared. This bit should be written '0'. 0 = Global Switching 1 = Individual Switching [7:0] NDSP NumberDownstreamPorts table of none-4 supports two downstream ports.

Publication Release Date: September 19, 2006 - 189 - Revision B2 Host Controller Root Hub Descriptor B Register This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation. REGISTER ADDRESS R/W HcRhDescriptorB 0xFFF0_504C R/W Host Controller Root Hub Descriptor B Register 0x0000_0000 PPCM PPCM DEVRM DEVRM BITS [31:16] PPCM PortPowerControlMask Global-power switching. This field is only valid if NoPowerSwitching is cleared and PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). 0 = Device not removable 1 = Global-power mask Port Bit relationship - Unimplemented ports are reserved, read/write '0'. 0 : Reserved 1 : Port 1 2 : Port 2 ... 15 : Port 15 [15:0] DEVRM DeviceRemoveable table of none-4 ports default to removable devices. 0 = Device not removable 1 = Device removable Port Bit relationship 0 : Reserved 1 : Port 1 2 : Port 2 ... 15 : Port 15 Unimplemented ports are reserved, read/write '0'.

190 - Host Controller Root Hub Status Register This register is reset by the USBRESET state. REGISTER OFFSET ADDRESS R/W

0xFFF0_5050 R/W Host Controller Root Hub Status Register 0x0000_0000 Reserved Reserved OVIC LPSC DRWE Reserved Reserved OVRCI LOPS BITS [31] CRWE (Write) ClearRemoteWakeupEnable Writing a '1' to this bit clears DeviceRemoteWakeupEnable. Writing a '1' has no effect. [30:18] Reserved Reserved. Read/Write 0's [17] OVIC OverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit. Writing a '0' has no effect. [16] LPSC (Read) LocalPowerStatusChange Not supported. Always read '0'. (Write) SetGlobalPower Write a '1' issues a SetGlobalPower command to the ports. Writing a '0' has no effect. [15] DRWE (Read) DeviceRemoteWakeupEnable This bit enables ports' ConnectStatusChange as a remote wakeup event. 0 = Disabled 1 = Enabled (Write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoteWakeupEnable. Writing a '0' has no effect. [14:2] Reserved Reserved. Read/Write 0's

Publication Release Date: September 19, 2006 - 191 - Revision B2 Continued. BITS [1] OVRCI OverCurrentIndicator This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared. 0 = No over-current condition 1 = Over-current condition [0] LOPS (Read) LocalPowerStatus Not Supported. Always read '0'. (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect. Host Controller Root Hub Port Status [1][2] This register is reset by the USBRESET state. REGISTER ADDRESS R/W HcRhPortStatus [1] 0xFFF0_5054 R/W Host Controller Root Hub Port Status [1] 0x0000_0000 HcRhPortStatus [2] 0xFFF0_5058 R/W Host Controller Root Hub Port Status [2] 0x0000_0000 Reserved Reserved PRSC POCIC PSSC PESC CSC Reserved LSDA PPS Reserved SPR CPS SPS SPE DRM BITS [31:21] Reserved Reserved. Read/Write 0's [20] PRSC PortResetStatusChange This bit indicates that the port reset signal has completed. 0 = Port reset is not complete. 1 = Port reset is complete.

192 - Continued. BITS

[19] POCIC PortOverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit. Writing a '0' has no effect. [18] PSSC PortSuspendStatusChange This bit indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed. 1 = Port resume is complete. [17] PESC PortEnableStatusChange This bit indicates that the port has been disabled due to a hardware event (cleared PortEnableStatus). 0 = Port has not been disabled. 1 = PortEnableStatus has been cleared. [16] CSC ConnectStatusChange This bit indicates a connect or disconnect event has been detected. Writing a '1' clears this bit. Writing a '0' has no effect. 0 = No connect/disconnect event. 1 = Hardware detection of connect/disconnect event. Note: If DeviceRemoveable is set, this bit resets to '1'. [15:10] Reserved Reserved. Read/Write 0's [9] LSDA (Read) LowSpeedDeviceAttached This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device 1 = Low Speed device (Write) ClearPortPower Writing a '1' clears PortPowerStatus. Writing a '0' has no effect [8] PPS (Read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode. 0 = Port power is off. 1 = Port power is on. Note: If NoPowerSwitching is set, this bit is always read as '1'. (Write) SetPortPower Writing a '1' sets PortPowerStatus. Writing a '0' has no effect. [7:5] Reserved Reserved. Read/Write 0's [4] SPR (Read) PortResetStatus 0 = Port reset signal is not active. 1 = Port reset signal is active. (Write) SetPortReset Writing a '1' sets PortResetStatus. Writing a '0' has no effect.

Publication Release Date: September 19, 2006 - 193 - Revision B2 Continued. BITS [3] CPS (Read) PortOverCurrentIndicator table of none-2 supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0 = No over-current condition 1 = Over-current condition (Write) ClearPortSuspend Writing a '1' initiates the selective resume sequence for the port. Writing a '0' has no effect. [2] SPS (Read) PortSuspendStatus 0 = Port is not suspended 1 = Port is selectively suspended (Write) SetPortSuspend Writing a '1' sets PortSuspendStatus. Writing a '0' has no effect. [1] SPE (Read) PortEnableStatus 0 = Port disabled. 1 = Port enabled. (Write) SetPortEnable Writing a '1' sets PortEnableStatus. Writing a '0' has no effect. [0] DRM (Read) CurrentConnectStatus 0 = No device connected. 1 = Device connected. NOTE: If DeviceRemoveable is set (not removable) this bit is always '1'. (Write) ClearPortEnable Writing '1' a clears PortEnableStatus. Writing a '0' has no effect. USB Operational Mode Enable Register This register selects which operational mode is enabled. Bits defined as write-only are read as 0's. REGISTER ADDRESS R/W OperationalModeEnable 0xFFF0_5204 R/W USB Operational Mode Enable Register 0x0000_000

194 - Reserved Reserved Reserved SIEPD Reserved OVRCUR Reserved DBREG BITS BIT DESCRIPTION [31:9] Reserved Reserved. Read/write 0 [8] SIEPD SIE Pipeline Disable When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor. This is a failsafe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz. [7:4] Reserved Reserved. Read/write 0 [3] OVRCURP OVRCURP (over current indicator polarity) When the OVRCURP bit is clear, the OVRCUR non-inverted to input into USB host controller. In contrast, when the OVRCURP bit is set, the OVRCUR inverted to input into USB host controller. [2:1] Reserved Reserved. Read/write 0 [0] DBREG Data Buffer Region 16 When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes. 6.7.3 HCCA 6.7.4 Endpoint Descriptor 6.7.5 Transfer Descriptor

6.8 USB Device Controller

The USB controller interfaces the AHB bus and the USB bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller through the AHB slave interface. For IN or OUT transfer, the USB controller needs to write data to memory or read data from memory through the AHB master interface. The USB controller also contains the USB transceiver to interface the USB.

Publication Release Date: September 19, 2006 - 195 - Revision B2 6.8.1 USB Endpoints It consists of four endpoints, designated EP0, EPA, EPB and EPC. Each is intended for a particular use as described below: EP0: the default endpoint uses control transfer (In/Out) to handle configuration and control functions required by the USB specification. Maximum packed size is 16 bytes. EPA: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint. EPB: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint. EPC: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint. 6.8.2 Standard device request The USB controller has built-in hard-wired state machine to automatically respond to USB standard device request. It also supports to detect the class and vendor requests. For Get Descriptor request and Class or Vendor command, the firmware will control these procedures. 6.8.3 USB Device Register Description USB Control Register (USB_CTL) REGISTER ADDRESS R/W USB_CTL 0xFFF0_6000 R/W USB control register 0x0000_0000 Reserved Reserved Reserved WakeUp CCMD VCMD SIE_RCV SUS_TST RWU_EN SUSP USB_RST USB_EN

196 - BITS DESCRIPTIONS [31:9] Reserved [8] WakeUp 0: no effect. 1: Generating remote wake-up signal to drive a K-state on USB bus. This function to bring the suspended USB bus to activation with resume state. [7] CCMD USB Class Command Decode Control Enable 0: Disable, the H/W circuit doesn’t need to decode USB class command. It will return a stall status when it received a USB Class Command. 1: Enable, the H/W circuit decodes USB class command. It will assert an interrupt event when it received a USB Class Command. [6] VCMD USB Vendor Command Decode Enable 0: Disable, the H/W circuit doesn’t need to decode USB vendor command. It will return a stall status when it received a USB Vendor Command. 1: Enable, the H/W circuit decodes USB vendor command. It will assert an interrupt event when it received a USB Vendor Command. [5] SIE_RCV USB SIE Differential RCV Source 0: RCV generated by the SIE 1: RCV generated by the USB transceiver [4] SUS_TST USB Suspend Accelerate Test 0: Normal Operation 1: USB Suspend Accelerate Test (Only for Test) [3] RWU_EN USB Remote Wake-up Enable 0: Disable USB Remote Wake-Up Detect 1: Enable USB Remote Wake-Up Detect [2] SUSP USB Suspend Detect Enable 0: Disable USB Suspend Detect 1: Enable USB Suspend Detect [1] USB_RS T USB Engine Reset 0: Normal operation 1: Reset USB Engine [0] USB_EN USB Engine Enable 0: disable USB Engine 1: enable USB Engine Note: set this bit to “0”, the device is absent from host. After set this bit to “1”, the host will detect a device attached.

Publication Release Date: September 19, 2006 - 197 - Revision B2 USB Class or Vendor command Register (USB_CVCMD) REGISTER ADDRESS R/W USB_CVCMD 0xFFF0_6004 R/W USB class or vendor command register 0x0000_0000 Reserved Reserved Reserved Reserved CVI_LG BITS DESCRIPTIONS [31:5] Reserved [4:0] CVI_LG Byte Length for Class and Vendor Command and Get Descriptor Return Data Packet USB Interrupt Enable Register (USB_IE) REGISTER ADDRESS R/W USB_IE 0xFFF0_6008 R/W USB interrupt enable register 0x0000_0000 Reserved Reserved RUM_CLKI RST_ENDI USB_CGI USB_BTI CVSI CDII CDOI VENI CLAI GSTRI GCFGI GDEVI ERRI RUMI SUSI RSTI

198 - BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKI Interrupt enable for RESUME (for clock is stopped) 0: Disable 1: Enable [14] RST_ENDI Interrupt enable for USB reset end 0: Disable 1: Enable [13] USB_CGI Interrupt Enable for Device Configured 0: Disable 1: Enable Note: the interrupt occurs when device configured or dis-configured. [12] USB_BTI Interrupt Enable for USB Bus Transition 0: Disable 1: Enable [11] CVSI Interrupt Enable Control for Status Phase of Class or Vendor Command 0: Disable 1: Enable [10] CDII Interrupt Enable Control for Data-In of Class or Vendor Command 0: Disable 1: Enable [9] CDOI Interrupt Enable Control for Data-Out of Class or Vendor Command 0: Disable 1: Enable [8] VENI Interrupt Enable Control for USB Vendor Command 0: Disable 1: Enable [7] CLAI Interrupt Enable Control for USB Class Command 0: Disable 1: Enable [6] GSTRI Interrupt Enable Control for USB Get_String_Descriptor Command 0: Disable 1: Enable

Publication Release Date: September 19, 2006 - 199 - Revision B2 Continued. BITS DESCRIPTIONS [5] GCFGI Interrupt Enable Control for USB Get_Configuration_Descriptor Command 0: Disable 1: Enable [4] GDEVI Interrupt Enable Control for USB Get_Device_Descriptor Command 0: Disable 1: Enable [3] ERRI Interrupt Enable Control for USB Error Detect 0: Disable 1: Enable [2] RUMI Interrupt Enable Control for USB Resume Detect 0: Disable 1: Enable [1] SUSI Interrupt Enable Control for USB Suspend Detect 0: Disable 1: Enable [0] RSTI Interrupt Enable Control for USB Reset Command Detect 0: Disable 1: Enable USB Interrupt status Register (USB_IS) REGISTER ADDRESS R/W USB_IS 0xFFF6_000C R USB interrupt status register 0x0000_0000 Reserved Reserved RUM_CLKS RSTENDS USB_CGS USB_BTS CVSS CDIS CDOS VENS CLAS GSTRS GCFGS GDEVS ERRS RUMS SUSS RSTS

200 - BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKS Interrupt status for RESUME (for clock is stopped) 0: No Interrupt Generated 1: Interrupt Generated [14] RSTENDS Interrupt status for USB reset end 0: No Interrupt Generated 1: Interrupt Generated [13] USB_CGS Interrupt Status for USB Device Configured 0: No Interrupt Generated 1: Interrupt Generated(configured and dis-configured) [12] USB_BTS Interrupt Status for USB Bus Transition 0: No Interrupt Generated 1: Interrupt Generated [11] CVSS Interrupt Status for Status Phase of Class or Vendor Command 0: No Interrupt Generated 1: Interrupt Generated [10] CDIS Interrupt Status for Data-In of Class or Vendor Command 0: No Interrupt Generated 1: Interrupt Generated [9] CDOS Interrupt Status for Data-Out of Class or Vendor Command 0: No Interrupt Generated 1: Interrupt Generated [8] VENS Interrupt Status for USB Vendor Command 0: No Interrupt Generated 1: Interrupt Generated [7] CLAS Interrupt Status for USB Class Command 0: No Interrupt Generated 1: Interrupt Generated

Publication Release Date: September 19, 2006 - 201 - Revision B2 Continued. BITS DESCRIPTIONS [6] GSTRS Interrupt Status for USB Get_String_Descriptor Command 0: No Interrupt Generated 1: Interrupt Generated [5] GCFGS Interrupt Status for USB Get_Configuration_Descriptor Command 0: No Interrupt Generated 1: Interrupt Generated [4] GDEVS Interrupt Status for USB Get_Device_Descriptor Command 0: No Interrupt Generated 1: Interrupt Generated [3] ERRS Interrupt Status for USB Error Detect 0: No Interrupt Generated 1: Interrupt Generated [2] RUMS Interrupt Status for USB Resume Detect 0: No Interrupt Generated 1: Interrupt Generated [1] SUSS Interrupt Status for USB Suspend Detect 0: No Interrupt Generated 1: Interrupt Generated [0] RSTS Interrupt Status for USB Reset Command Detect 0: No Interrupt Generated 1: Interrupt Generated USB Interrupt Status Clear (USB_IC) REGISTER ADDRESS R/W USB_IC 0xFFF6_0010 R/W USB interrupt status clear register 0x0000_0000

202 - Reserved Reserved RUM_CLKC RSTENDC USB_CGC USB_BTC CVSC CDIC CDOC VENC CLAC GSTRC GCFGC GDEVC ERRC RUMC SUSC RSTC BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKC Interrupt status clear for RESUME (for clock is stopped) 0: NO Operation 1: Clear Interrupt Status [14] RSTENDC Interrupt status clear for USB reset end 0: NO Operation 1: Clear Interrupt Status [13] USB_CGC Interrupt Status Clear for USB Device Configured 0: NO Operation 1: Clear Interrupt Status [12] USB_BTC Interrupt Status Clear for USB Bus Transition 0: NO Operation 1: Clear Interrupt Status [11] CVSC Interrupt Status Clear for Status Phase of Class or Vendor Command 0: NO Operation 1: Clear Interrupt Status [10] CDIC Interrupt Status Clear for Data-In of Class or Vendor Command 0: NO Operation 1: Clear Interrupt Status [9] CDOC Interrupt Status Clear for Data-Out of Class or Vendor Command 0: NO Operation 1: Clear Interrupt Status

Publication Release Date: September 19, 2006 - 203 - Revision B2 Continued. BITS DESCRIPTIONS [8] VENC Interrupt Status Clear for USB Vendor Command 0: NO Operation 1: Clear Interrupt Status [7] CLAC Interrupt Status Clear for USB Class Command 0: NO Operation 1: Clear Interrupt Status [6] GSTRC Interrupt Status Clear for USB Get_String_Descriptor Command 0: NO Operation 1: Clear Interrupt Status [5] GCFGC Interrupt Status Clear for USB Get_Configuration_Descriptor Command 0: NO Operation 1: Clear Interrupt Status [4] GDEVC Interrupt Status Clear for USB Get_Device_Descriptor Command 0: NO Operation 1: Clear Interrupt Status [3] ERRC Interrupt Status Clear for USB Error Detect 0: NO Operation 1: Clear Interrupt Status [2] RUMC Interrupt Status Clear for USB Resume Detect 0: NO Operation 1: Clear Interrupt Status [1] SUSC Interrupt Status Clear for USB Suspend Detect 0: NO Operation 1: Clear Interrupt Status [0] RSTC Interrupt Status Clear for USB Reset Command Detect 0: NO Operation 1: Clear Interrupt Status USB Interface and String Register (USB_IFSTR) REGISTER ADDRESS R/W USB_IFSTR 0xFFF06014 R/W USB interface and string register 0x0000_0000

204 - Reserved Reserved Reserved STR6_EN STR5_EN STR4_EN STR3_EN STR2_EN STR1_EN INF4_EN INF3_EN INF2_EN INF1_EN BITS DESCRIPTIONS [31:10] Reserved [9] STR6_EN USB String Descriptor-6 Control 0: Disable 1: Enable [8] STR5_EN USB String Descriptor-5 Control 0: Disable 1: Enable [7] STR4_EN USB String Descriptor-4 Control 0: Disable 1: Enable [6] STR3_EN USB String Descriptor-3 Control 0: Disable 1: Enable [5] STR2_EN USB String Descriptor-2 Control 0: Disable 1: Enable [4] STR1_EN USB String Descriptor-1 Control 0: Disable 1: Enable

Publication Release Date: September 19, 2006 - 205 - Revision B2 Continued. BITS DESCRIPTIONS [3] INF4_EN USB Interface-4 Control 0: Disable 1: Enable [2] INF3_EN USB Interface-3 Control 0: Disable 1: Enable [1] INF2_EN USB Interface-2 Control 0: Disable 1: Enable [0] INF1_EN USB Interface-1 Control 0: Disable 1: Enable USB Control transfer-out port 0 (USB_ODATA0) REGISTER ADDRESS R/W USB_ODATA0 0xFFF06018 R USB control transfer-out port 0 register 0x0000_0000 ODATA0 ODATA0 ODATA0 ODATA0 BITS DESCRIPTIONS [31:0] ODATA0 Control Transfer-out data 0

206 - USB Control transfer-out port 1 (USB_ODATA1) REGISTER ADDRESS R/W

USB_ODATA1 0xFFF0601C R USB control transfer-out port 1 register 0x0000_0000 ODATA1 ODATA1 ODATA1 ODATA1 BITS DESCRIPTIONS [31:0] ODATA1 Control Transfer-out data 1 USB Control transfer-out port 2 (USB_ODATA2) REGISTER ADDRESS R/W USB_ODATA2 0xFFF06020 R USB control transfer-out port 2 register 0x0000_0000 ODATA2 ODATA2 ODATA2 ODATA2 BITS DESCRIPTIONS [31:0] ODATA2 Control Transfer-out data 2

Publication Release Date: September 19, 2006 - 207 - Revision B2 USB Control transfer-out port 3 (USB_ODATA3) REGISTER ADDRESS R/W USB_ODATA3 0xFFF06024 R USB control transfer-out port 3 register 0x0000_0000 ODATA3 ODATA3 ODATA3 ODATA3 BITS DESCRIPTIONS [31:0] ODATA3 Control Transfer-out data 3 USB Control transfer-in data port0 Register (USB_IDATA0) REGISTER ADDRESS R/W USB_IDATA0 0xFFF06028 R/W USB transfer-in data port0 register 0x0000_0000 IDATA0 IDATA0 IDATA0 IDATA0 BITS DESCRIPTIONS [31:6] IDATA0 Control transfer-in data0

208 - USB Control transfer-in data port 1 Register (USB_IDATA1) REGISTER ADDRESS R/W

USB_IDATA1 0xFFF0602C R/W USB control transfer-in data port 1 0x0000_0000 IDATA1 IDATA1 IDATA1 IDATA1 BITS DESCRIPTIONS [31:6] IDATA1 Control transfer-in data1 USB Control transfer-in data port 2 Register (USB_IDATA2) REGISTER ADDRESS R/W USB_IDATA2 0xFFF06030 R/W USB control transfer-in data port 2 0x0000_0000 IDATA2 IDATA2 IDATA2 IDATA2 BITS DESCRIPTIONS [31:6] IDATA2 Control transfer-in data2

Publication Release Date: September 19, 2006 - 209 - Revision B2 USB Control transfer-in data port 3 Register (USB_IDATA3) REGISTER ADDRESS R/W USB_IDATA3 0xFFF06034 R/W USB control transfer-in data port 3 0x0000_0000 IDATA3 IDATA3 IDATA3 IDATA3 BITS DESCRIPTIONS [31:6] IDATA3 Control transfer-in data3 USB SIE Status Register (USB_SIE) REGISTER ADDRESS R/W USB_SIE 0xFFF06038 R USB SIE status Register 0x0000_0000 Reserved Reserved Reserved Reserved USB_DPS USB_DMS

210 - BITS DESCRIPTIONS [31:2] Reserved [1] USB_DPS USB Bus D+ Signal Status 0: USB Bus D+ Signal is low 1: USB Bus D+ Signal is high [0] USB_DMS USB Bus D- Signal Status 0: USB Bus D- Signal is low 1: USB Bus D- Signal is high USB Engine Register (USB_ENG) REGISTER ADDRESS R/W

USB_ENG 0xFFF0603C R/W USB Engine Register 0x0000_0000 Reserved Reserved Reserved Reserved SDO_RD CV_LDA CV_STL CV_DAT BITS DESCRIPTIONS [31:4] Reserved [3] SDO_RD Setup or Bulk-Out Data Read Control 0: NO Operation 1: Read Setup or Bulk-Out Data from USB Host NOTE: this bit will auto clear after 32 HCLK [2] CV_LDA USB Class and Vendor Command Last Data Packet Control 0: NO Operation 1: Last Data Packet for Data Input of Class and Vendor Command NOTE: this bit will auto clear after 32 HCLK

Publication Release Date: September 19, 2006 - 211 - Revision B2 Continued. BITS DESCRIPTIONS [1] CV_STL USB Class and Vendor Command Stall Control 0: NO Operation 1: Return Stall for Class and Vendor Command NOTE: this bit will auto clear after 32 HCLK [0] CV_DAT USB Class and Vendor Command return data control 0: NO Operation 1: The Data Packet for Data Input of Class and Vendor Command or Get Descriptor command is ready. NOTE: this bit will auto clear after 32 HCLK USB Control Register (USB_CTLS) REGISTER ADDRESS R/W USB_CTLS 0xFFF06040 R USB control transfer status register 0x0000_0000 Reserved Reserved CONF Reserved CTLRPS ITS DESCRIPTIONS [31:16] Reserved [15:8] CONF USB configured value [7:5] Reserved [4:0] CTLRPS Control transfer received packet size

212 - USB Configured Value Register (USB_CONFD) REGISTER ADDRESS R/W

USB_CONFD 0xFFF06044 R/W USB Configured Value register 0x0000_0000 Reserved Reserved Reserved CONFD BITS DESCRIPTIONS [31:8] Reserved [7:0] CONFD Software configured value USB Endpoint A Information Register (EPA_INFO) REGISTER ADDRESS R/W EPA_INFO 0xFFF06048 R/W USB endpoint A information register 0x0000_0000 Reserved EPA_TYPE EPA_DIR Reserved EPA_MPS EPA_MPS EPA_ALT EPA_INF EPA_CFG EPA_NUM

Publication Release Date: September 19, 2006 - 213 - Revision B2 BITS DESCRIPTIONS [31] Reserved [30:29] EPA_TYPE Endpoint A type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] EPA_DIR Endpoint A direction 0: OUT 1: IN [27:26] Reserved [25:16] EPA_MPS Endpoint A max. packet size [15:12] EPA_ALT Endpoint A alternative setting (READ ONLY) [11:8] EPA_INF Endpoint A interface [7:4] EPA_CFG Endpoint A configuration [3:0] EPA_NUM Endpoint A number USB Endpoint A Control Register (EPA_CTL) REGISTER ADDRESS R/W EPA_CTL 0xFFF0604C R/W USB endpoint A control register 0x0000_0000 Reserved Reserved Reserved Reserved EPA_ZERO EPA_STL_CLR EPA_THRE EPA_STL EPA_RDY EPA_RST EPA_EN

214 - BITS DESCRIPTIONS [31:6] Reserved [6] EPA_ZERO Send zero length packet to HOST [5] EPA_STL_CLR CLEAR the Endpoint A stall(WRITE ONLY) [4] EPA_THRE Endpoint A threshold (only for ISO) 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] EPA_STL Set the Endpoint A stall [2] EPA_RDY The memory is ready for Endpoint A to access [1] EPA_RST Endpoint A reset [0] EPA_EN Endpoint A enable USB Endpoint A interrupt enable Register (EPA_IE) REGISTER ADDRESS R/W

EPA_IE 0xFFF06050 R/W USB endpoint A Interrupt Enable register 0x0000_0000 Reserved Reserved Reserved Reserved EPA_CF_IE EPA_BUS_ERR_IE EPA_DMA_IE EPA_ALT_IE EPA_TK_IE EPA_STL_IE

Publication Release Date: September 19, 2006 - 215 - Revision B2 BITS DESCRIPTIONS [31:6] Reserved [5] EPA_CF_IE Endpoint A clear feature interrupt enable [4] EPA_BUS_ERR_IE Endpoint A system bus error interrupt enable [3] EPA_DMA_IE Endpoint A DMA transfer complete interrupt enable [2] EPA_ALT_IE Endpoint A alternate setting interrupt enable [1] EPA_TK_IE Endpoint A token input interrupt enable [0] EPA_STL_IE Endpoint A stall interrupt enable USB Endpoint A Interrupt Clear Register (EPA_IC) REGISTER ADDRESS R/W EPA_IC 0xFFF06054 W USB endpoint A interrupt clear register 0x0000_0000 Reserved Reserved Reserved Reserved EPA_DMA_IC EPA_ALT_IC EPA_TK_IC EPA_STL_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPA_CF_INT_IC Endpoint A clear feature interrupt clear [4] EPA_BUS_ERR_IC Endpoint A system bus error interrupt clear [3] EPA_DMA_IC Endpoint A DMA transfer complete interrupt clear

216 - Continued. BITS DESCRIPTIONS [2] EPA_ALT_IC Endpoint A alternate setting interrupt clear [1] EPA_TK_IC Endpoint A token input interrupt clear [0] EPA_STL_IC Endpoint A stall interrupt clear USB Endpoint A Interrupt Status Register (EPA_IS) REGISTER ADDRESS R/W

EPA_IS 0xFFF06058 R USB endpoint A interrupt status register 0x0000_0000 Reserved Reserved Reserved Reserved EPA_DMA_IS EPA_ALT_IS EPA_TK_IS EPA_STL_IS BITS DESCRIPTIONS [31:6] Reserved [5] EPA_CF_IS Endpoint A clear feature interrupt status [4] EPA_BUS_ERR_IS Endpoint A system bus error interrupt status [3] EPA_DMA_IS Endpoint A DMA transfer complete interrupt status [2] EPA_ALT_IS Endpoint A alternative setting interrupt status [1] EPA_TK_IS Endpoint A token interrupt status [0] EPA_STL_IS Endpoint A stall interrupt status

Publication Release Date: September 19, 2006 - 217 - Revision B2 USB Endpoint A Address Register (EPA_ADDR) REGISTER ADDRESS R/W EPA_ADDR 0xFFF0605C R/W USB endpoint A address register 0x0000_0000 EPA_ADDR EPA_ADDR EPA_ADDR EPA_ADDR BITS DESCRIPTIONS [31:0] EPA_ADDR Endpoint A transfer address USB Endpoint A transfer length Register (EPA_LENTH) REGISTER ADDRESS R/W EPA_LENTH 0xFFF06060 R/W USB endpoint A transfer length register 0x0000_0000 Reserved Reserved EPA_LENTH EPA_LENTH EPA_LENTH

218 - BITS DESCRIPTIONS [31:20] Reserved [19:0] EPA_LENTH Endpoint A transfer length USB Endpoint B Information Register (EPB_INFO) REGISTER ADDRESS R/W

EPB_INFO 0xFFF06064 R/W USB endpoint B information register 0x0000_0000 Reserved EPB_TYPE EPB_DIR Reserved EPB_MPS EPB_MPS EPB_ALT EPB_INF EPB_CFG EPB_NUM BITS DESCRIPTIONS [31] Reserved [30:29] EPB_TYPE Endpoint B type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] EPB_DIR Endpoint B direction 0: OUT 1: IN [27:26] Reserved [25:16] EPB_MPS Endpoint B max. packet size

Publication Release Date: September 19, 2006 - 219 - Revision B2 Continued. BITS DESCRIPTIONS [15:12] EPB_ALT Endpoint B alternative setting (READ ONLY) [11:8] EPB_INF Endpoint B interface [7:4] EPB_CFG Endpoint B configuration [3:0] EPB_NUM Endpoint B number USB Endpoint B Control Register (EPB_CTL) REGISTER ADDRESS R/W EPB_CTL 0xFFF06068 R/W USB endpoint B control register 0x0000_0000 Reserved Reserved Reserved Reserved EPB_ZERO EPB_STL_CLR EPB_THRE EPB_STL EPB_RDY EPB_RST EPB_EN BITS DESCRIPTIONS [31:7] Reserved [6] EPB_ZERO Send zero length packet back to HOST [5] EPB_STL_CLR Clear the Endpoint B stall(WRITE ONLY) [4] EPB_THRE Endpoint B threshold (only for ISO) 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] EPB_STL Set the Endpoint B stall

220 - Continued. BITS DESCRIPTIONS [2] EPB_RDY The memory is ready for Endpoint B to access [1] EPB_RST Endpoint B reset [0] EPB_EN Endpoint B enable USB Endpoint B interrupt enable Register (EPB_IE) REGISTER ADDRESS R/W

EPB_IE 0xFFF0606C R/W USB endpoint B Interrupt Enable register 0x0000_0000 Reserved Reserved Reserved Reserved EPB_CF_IE EPB_BUS_ERR_IE EPB_DMA_IE EPB_ALT_IE EPB_TK_IE EPB_STL_IE BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IE Endpoint B clear feature interrupt enable [4] EPB_BUS_ERR_IE Endpoint B system bus error interrupt enable [3] EPB_DMA_IE Endpoint B DMA transfer complete interrupt enable [2] EPB_ALT_IE Endpoint B alternate setting interrupt enable [1] EPB_TK_IE Endpoint B token input interrupt enable [0] EPB_STL_IE Endpoint B stall interrupt enable

Publication Release Date: September 19, 2006 - 221 - Revision B2 USB Endpoint B Interrupt Clear Register (EPB_IC) REGISTER ADDRESS R/W EPB_IC 0xFFF06070 W USB endpoint B interrupt clear register 0x0000_0000 Reserved Reserved Reserved Reserved EPB_CF_IC EPB_BUS_ERR_IC EPB_DMA_IC EPB_ALT_IC EPB_TK_IC EPB_STL_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IC Endpoint B clear feature interrupt clear [4] EPB_BUS_ERR_IC Endpoint B system bus error interrupt clear [3] EPB_DMA_IC Endpoint B DMA transfer complete interrupt clear [2] EPB_ALT_IC Endpoint B alternate setting interrupt clear [1] EPB_TK_IC Endpoint B token input interrupt clear [0] EPB_STL_IC Endpoint B stall interrupt clear USB Endpoint B Interrupt Status Register (EPB_IS) REGISTER ADDRESS R/W EPB_IS 0xFFF06074 R USB endpoint B interrupt status register 0x0000_0000

222 - Reserved Reserved Reserved Reserved EPB_CF_IS EPB_BUS_ERR_IS EPB_DMA_IS EPB_ALT_IS EPB_TK_IS EPB_STL_IS BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IS Endpoint B clear feature interrupt status [4] EPB_DMA_IS Endpoint B system bus error interrupt status [3] EPB_DMA_IS Endpoint B DMA transfer complete interrupt status [2] EPB_ALT_IS Endpoint B alternative setting interrupt status [1] EPB_TK_IS Endpoint B token interrupt status [0] EPB_STL_IS Endpoint B stall interrupt status USB Endpoint B Address Register (EPB_ADDR) REGISTER ADDRESS R/W

EPB_ADDR 0xFFF06078 R/W USB endpoint B address register 0x0000_0000 EPB_ADDR EPB_ADDR EPB_ADDR EPB_ADDR

Publication Release Date: September 19, 2006 - 223 - Revision B2 BITS DESCRIPTIONS [31:0] EPB_ADDR Endpoint B transfer address USB Endpoint B transfer length Register (EPB_LENTH) REGISTER ADDRESS R/W EPB_LENTH 0xFFF0607C R/W USB endpoint B transfer length register 0x0000_0000 Reserved Reserved EPB_LENTH EPB_LENTH EPB_LENTH BITS DESCRIPTIONS [31:20] Reserved [19:0] EPB_LENTH Endpoint B transfer length USB Endpoint C Information Register (EPC_INFO) REGISTER ADDRESS R/W EPC_INFO 0xFFF06080 R/W USB endpoint C information register 0x0000_0000

224 - Reserved EPC_TYPE EPC_DIR Reserved EPC_MPS EPC_MPS EPC_ALT EPC_INF EPC_CFG EPC_NUM BITS DESCRIPTIONS [31] Reserved [30:29] EPC_TYPE Endpoint C type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] EPC_DIR Endpoint C direction 0: OUT 1: IN [27:26] Reserved [25:16] EPC_MPS Endpoint C max. packet size [15:12] EPC_ALT Endpoint C alternative setting (READ ONLY) [11:8] EPC_INF Endpoint C interface [7:4] EPC_CFG Endpoint C configuration [3:0] EPC_NUM Endpoint C number

Publication Release Date: September 19, 2006 - 225 - Revision B2 USB Endpoint C Control Register (EPC_CTL) REGISTER ADDRESS R/W EPC_CTL 0xFFF06084 R/W USB endpoint C control register 0x0000_0000 Reserved Reserved Reserved Reserved EPC_ZERO EPC_STL_CLR EPC_THRE EPC_STL EPC_RDY EPC_RST EPC_EN BITS DESCRIPTIONS [31:7] Reserved [6] EPC_ZERO Send zero length packet back to HOST [5] EPC_STL_CLR Clear the Endpoint C stall(WRITE ONLY) [4] EPC_THRE Endpoint C threshold (only for ISO) 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] EPC_STL Set the Endpoint C stall [2] EPC_RDY The memory is ready for Endpoint C to access [1] EPC_RST Endpoint C reset [0] EPC_EN Endpoint C enable

226 - USB Endpoint C interrupt enable Register (EPC_IE) REGISTER ADDRESS R/W

EPC_IE 0xFFF06088 R/W USB endpoint C Interrupt Enable register 0x0000_0000 Reserved Reserved Reserved Reserved EPC_CF_IE EPC_BUS_ERR_IE EPC_DMA_IE EPC_ALT_IE EPC_TK_IE EPC_STL_IE BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IE Endpoint C clear feature interrupt enable [4] EPC_DMA_IE Endpoint C system bus error interrupt enable [3] EPC_DMA_IE Endpoint C DMA transfer complete interrupt enable [2] EPC_ALT_IE Endpoint C alternate setting interrupt enable [1] EPC_TK_IE Endpoint C token input interrupt enable [0] EPC_STL_IE Endpoint C stall interrupt enable USB Endpoint C Interrupt Clear Register (EPC_IC) REGISTER ADDRESS R/W EPC_IC 0xFFF0608C W USB endpoint C interrupt clear register 0x0000_0000

Publication Release Date: September 19, 2006 - 227 - Revision B2 Reserved Reserved Reserved Reserved EPC_CF_IC EPC_BUS_ERR_IC EPC_DMA_IC EPC_ALT_IC EPC_TK_IC EPC_STL_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IC Endpoint C clear feature interrupt clear [4] EPC_DMA_IC Endpoint C system bus error interrupt clear [3] EPC_DMA_IC Endpoint C DMA transfer complete interrupt clear [2] EPC_ALT_IC Endpoint C alternate setting interrupt clear [1] EPC_TK_IC Endpoint C token input interrupt clear [0] EPC_STL_IC Endpoint C stall interrupt clear USB Endpoint C Interrupt Status Register (EPC_IS) REGISTER ADDRESS R/W EPC_IS 0xFFF06090 R USB endpoint C interrupt status register 0x0000_0000

228 - Reserved Reserved Reserved Reserved EPC_CF_IS EPC_BUS_ERR_IS EPC_DMA_IS EPC_ALT_IS EPC_TK_IS EPC_STL_IS BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IS Endpoint C clear feature interrupt status [4] EPC_BUS_ERR_IS Endpoint A system bus error interrupt status [3] EPC_DMA_IS Endpoint A DMA transfer complete interrupt status [2] EPC_ALT_IS Endpoint A alternative setting interrupt status [1] EPC_TK_IS Endpoint A token interrupt status [0] EPC_STL_IS Endpoint A stall status USB Endpoint C Address Register (EPC_ADDR) REGISTER ADDRESS R/W

EPC_ADDR 0xFFF0_6094 R/W USB endpoint C address register 0x0000_0000 EPC_ADDR EPC_ADDR EPC_ADDR EPC_ADDR

Publication Release Date: September 19, 2006 - 229 - Revision B2 BITS DESCRIPTIONS [31:0] EPC_ADDR Endpoint C transfer address USB Endpoint C transfer length Register (EPC_LENTH) REGISTER ADDRESS R/W EPC_LENTH 0xFFF0_6098 R/W USB endpoint C transfer length register 0x0000_0000 Reserved Reserved EPC_LENTH EPC_LENTH EPC_LENTH BITS DESCRIPTIONS [31:20] Reserved [19:0] EPC_LENTH Endpoint C transfer length USB Endpoint A Remain transfer length Register (EPA_XFER) REGISTER ADDRESS R/W EPA_XFER 0xFFF0_609C R/W USB endpoint A remain transfer length register 0x0000_0000

230 - Reserved Reserved EPA_XFER EPA_XFER EPA_XFER BITS DESCRIPTIONS [31:20] Reserved [19:0] EPA_XFER Endpoint A remain transfer length USB Endpoint A Remain packet length Register (EPA_PKT) REGISTER ADDRESS R/W

EPA_PKT 0xFFF0_60A0 R/W USB endpoint A remain packet length register 0x0000_0000 Reserved Reserved Reserved EPA_PKT EPA_PKT BITS Descriptions [31:10] Reserved [9:0] EPA_PKT Endpoint A remain packet length

Publication Release Date: September 19, 2006 - 231 - Revision B2 USB Endpoint B Remain transfer length Register (EPB_XFER) REGISTER ADDRESS R/W EPB_XFER 0xFFF0_60A4 R/W USB endpoint B remain transfer length register 0x0000_0000 Reserved Reserved EPB_XFER EPB_XFER EPB_XFER BITS DESCRIPTIONS [31:20] Reserved [19:0] EPB_XFER Endpoint B remain transfer length USB Endpoint B Remain packet length Register (EPB_PKT) REGISTER ADDRESS R/W EPB_PKT 0xFFF0_60A8 R/W USB endpoint B remain packet length register 0x0000_0000 Reserved Reserved Reserved EPB_PKT EPB_PKT

232 - BITS DESCRIPTIONS [31:10] Reserved [9:0] EPB_PKT Endpoint B remain packet length USB Endpoint C Remain transfer length Register (EPC_XFER) REGISTER ADDRESS R/W

EPC_XFER 0xFFF0_60AC R/W USB endpoint C remain transfer length register 0x0000_0000 Reserved Reserved EPC_XFER EPC_XFER EPC_XFER BITS DESCRIPTIONS [31:20] Reserved [19:0] EPC_XFER Endpoint C remain transfer length USB Endpoint C Remain packet length Register (EPC_PKT) REGISTER ADDRESS R/W EPC_PKT 0xFFF0_60B0 R/W USB endpoint C remain packet length register 0x0000_0000

Publication Release Date: September 19, 2006 - 233 - Revision B2 Reserved Reserved Reserved EPC_PKT EPC_PKT BITS DESCRIPTIONS [31:10] Reserved [9:0] EPC_PKT Endpoint C remain packet length

234 -

6.9 SD Host Controller

The SD host controller of W90P710 supports Secure Digital card devices (SD, MMC). The SD host- controller also supports DMA function to reduce the intervention of CPU for data transfer between flash memory card and system memory. There are two 512B internal buffers embedded in the SD host controller to buffer the data temporally for DMA transfer between flash memory card and system memory. The SD host controller features are shown as below: y Directly connect to Secure Digital (SD, MMC) flash memory card. y Supports DMA function to accelerate the data transfer between the internal buffer, external SDRAM, and flash memory card. y Two 512 bytes internal buffers are embedded inside of the SD host controller. y No SPI mode. 6.9.1 Functional Description SD host controller provides three signals, CLK, CMD and DAT[3:0], to all SD cards. CLK is a clock output signal. CMD and DAT[3:0] are bi-direction command and data signals, respectively. The frequency of CLK is equal to (engine clock frequency)/(SD_CLK+1), where SD_CLK is the value of the SD clock control register. To save power, CLK is active only when there are activities between SD host controller and SD cards. Otherwise, CLK keeps inactive state (LOW). According to the SD specification, SD host controller provides several operations to communicate with SD Cards efficiently. The CPU writes to the SD access control register to setup the operations. When the command output enable bit of SD access control register is set, SD host controller transfers a 48-bit command to one or more SD cards. When the transfer is done, this bit is reset to 0 automatically. For a 48-bits command, the 6-bits command number is coming from SD CMD code register and the 32-bits command argument is coming from SD command argument 1-4 registers. All other bits (including start bit, end bit and the CRC-7bits) are generated by SD host controller H/W circuit. When the response input enable bit of SD access control register is set, SD host controller waits for a 48-bit response form one or more SD card. When a 48-bit response is received, this bit is reset to 0 automatically. The first 40 bits of the received response are stored into SD received response token1 – 5 registers. The last 8 bits are CRC-7 bits and end bit. SD host controller H/W circuit checks CRC-7 and reports the result to SD status register. When the data input enable bit of SD access control register is set, SD host controller waits for a block of data from a specific SD card. When a block of data is received, this bit is cleared to 0 automatically. The received block of data is stored into the system memory and the address is starting from the address specified by S/W.

Publication Release Date: September 19, 2006 - 235 - Revision B2 SD host controller checks the associated CRC-16 bits and reports the result to SD status register. If the data-input interrupt is enabled, an interrupt will occur when the data transfer is finished. The data input status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify a data-input interrupt by reading this bit. When the data output enable bit of SD access control register is set, SD host controller transfers a block of data to a specific MMC card. When the data transfer is finished, this bit is cleared to 0 automatically. Before the data is transferred, the data to be transmitted must be stored into system memory and the S/W must specified the starting address where the data is stored. SD host controller will generate the associated CRC-16 bits by itself. After the data is transmitted, it also check the CRC-status response from the SD card. The check result is stored into the SD status register. If the data-output interrupt is enabled, an interrupt will occur when the data transfer is finished. The data output status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify a data-output interrupt by reading this bit. When the response R2 input enable bit of SD access control register is set, SD host controller transfers a block of data to a specific SD card. When the data transfer is finished and this bit is set, SD host controller will waits for a 136-bit R2 response from SD card. When the R2 response is completely received, the bit is reset to 0 automatically. y The received data of R2 response token (136-bit) is stored into the system memory, starting from the address specified by software. y SD host controller checks the CRC-7 and reports the result to SD status register. When the 74-clock cycles output enable bit of SD access control register is set, SD host controller generates 74 clock cycles without any CMD or DAT activity. After the 74 clock cycles have been generated, the bit is reset to 0 automatically.

236 - 6.9.2 Register Mapping REGISTER ADDRESS R/W

SD Registers (6) SDGCR 0xFFF0_0000 R/W SD Global Control Register 0x0000_0000 SDDSA 0xFFF0_0004 R/W SD DMA Transfer Starting Address Register 0x0000_0000 SDBCR 0xFFF0_7008 R/W SD DMA Byte Count Register 0x0000_0000 SDGIER 0xFFF0_700C R/W SD Global Interrupt Enable Register 0x0000_0000 SDGISR 0xFFF0_7010 R/W SD Global Interrupt Status Register 0x0000_0000 SDBIST 0xFFF0_7014 R/W SD BIST Register 0x0000_0000 Secure Digital Registers (8) SDICR 0xFFF0_7300 R/W SD Interface Control Register 0x0000_0000 SDHIIR 0xFFF0_7304 R/W SD Host Interface Initial Register 0x0000_0018 SDIIER 0xFFF0_7308 R/W SD Interface Interrupt Enable Register 0x0000_0000 SDIISR 0xFFF0_730C R/W SD Interface Interrupt Status Register 0x0000_00XX SDAUG 0xFFF0_7310 R/W SD Command Argument Register 0x0000_0000 SDRSP0 0xFFF0_7314 R SD Receive Response Token Register 0xXXXX_XXXX SDRSP1 0x0000_0318 R SD Receive Response Token Register 0x0000_XXXX SDBLEN 0xFFF0_731C R/W SD Block Length Register 0x0000_0000 Internal Buffer Access Register (256) FB0_0 ….. FB0_127 0xFFF0_7400 ….. 0xFFF0_75FC R/W Flash Buffer 0 Undefined FB1_0 ….. FB1_127 0xFFF0_7800 ….. 0xFFF0_79FC R/W Flash Buffer 1 Undefined

Publication Release Date: September 19, 2006 - 237 - Revision B2 6.9.3 SD Register Description SD Gloal Control Register (SDGCR) REGISTER ADDRESS R/W 0xFFF0_7000 R/W SD Global Control Register 0x0000_0000 Reserved Reserved Reserved RdSel Reserved WrSel DMARd DMAWr SWRST SDEN BITS DESCRIPTIONS [31:11] Reserved [10:8] RdSel Read Select This field indicates which of DMA or SD host controller can read data from buffer 0 or buffer 1. 3’b000: DMA can read buffer 0 (Default) 3’b011: SD host controller can read buffer 0 3’b100: DMA can read buffer 1 3’b111: SD host controller can read buffer 1 [6:4] WrSel Write Select This field indicates which of DMA, SD host controller can write data into buffer 0 or buffer 1. 3’b000: DMA can write buffer 0 (Default) 3’b011: SD host controller can write buffer 0 3’b100: DMA can write buffer 1 3’b111: SD host controller can write buffer 1

238 - Continued. BITS DESCRIPTIONS [3] DMARd DMA Read Enable Set this bit high enables the DMA to transfer data from external SDRAM to internal buffer. This bit will be cleared automatically after DMA operation finished. Write 0 to this bit has no effect. 1’b0: No DMA operation (Default) 1’b1: Enable DMA read operation [2] DMAWr DMA Write Enable Set this bit high enables the DMA to transfer data from internal buffer into external SDRAM. This bit will be cleared automatically after DMA operation finished. Write 0 to this bit has no effect. 1’b0: No DMA operation (Default) 1’b1: Enable DMA write operation [1] SWRST Software Reset Set this bit high will reset only the logic circuit of SD host controller and has no effect on all control registers. 1’b0: No operation (Default) 1’b1: Enable software reset [0] SDEN SD Function Enable Set this bit high enables the SD host controller operation. If this bit is cleared, all operations are disabled and SD host controller only responses to control register access. 1’b0: Disable SD host controller (Default) 1’b1: Enable SD host controller

Publication Release Date: September 19, 2006 - 239 - Revision B2 SD DMA Transfer Starting Address Register (SDDSA) REGISTER ADDRESS R/W 0xFFF0_7004 R/W SD DMA Transfer Starting Address Register 0x0000_0000 DMASA DMASA DMASA DMASA BITS DESCRIPTIONS [31:0] DMASA DMA Transfer Starting Address This field defines the address of external SDRAM where DMA reads/writes data from/to.

240 - SD DMA Byte Count Register (SDBCR) REGISTER ADDRESS R/W

0xFFF0_7008 R/W SD DMA Byte Count Register 0x0000_0000 Reserved Reserved Reserved BCNT BCNT BITS DESCRIPTIONS [31:12] Reserved [11:0] BCNT DMA Transfer Byte Count This field defines the byte count of DMA Transfer between internal flash buffer and external SDRAM. SD Global Interrupt Enable Register (SDGIER) REGISTER ADDRESS R/W 0xFFF0_70 R/W SD Global Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved ERRIEN DRdIEN DWrIEN SDHIIEN Reserved Reserved SDGIEN

Publication Release Date: September 19, 2006 - 241 - Revision B2 BITS DESCRIPTIONS [31:7] Reserved [6] ERRIEN Bus Error Interrupt Enable [5] DRdIEN DMA Read Interrupt Enable This bit controls the SD host controller interrupt generation from the interrupt of the DMA read operation. 1’b0: DMA read interrupt is masked from SD host controller interrupt generation 1’b1: DMA read interrupt can participate in SD host controller interrupt generation [4] DWrIEN DMA Write Interrupt Enable This bit controls the SD host controller interrupt generation from the interrupt of the DMA write operation. 1’b0: DMA write interrupt is masked from SD host controller interrupt generation 1’b1: DMA write interrupt can participate in SD host controller interrupt generation [3] SDHIIEN Secure Digital Host Controller Interface Interrupt Enable This bit controls the SD host controller interrupt generation from the interrupt of Secure Digital host controller. 1’b0: Secure Digital host controller’s interrupt is masked from SD host controller interrupt generation 1’b1: Secure Digital host controller’s interrupt can participate in SD host controller interrupt generation [0] SDGIEN SD Host Global Interrupt Enable This bit controls the interrupt generation of SD host controller Globally. 1’b0: Disable SDI host controller interrupt generation globally 1’b1: Enable SD host controller interrupt generation globally

242 - SD global Interrupt Status Register (SDGISR) REGISTER ADDRESS R/W

0xFFF0_7010 R/W SD Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved ERRINT DRdINT DWrINT SDHIINT Reserved Reserved SDGINT BITS DESCRIPTIONS [31:7] Reserved [6] ERRINT Bus Error Interrupt Status [5] DRdINT DMA Read Interrupt Status This bit indicates the DMA read transfer (from external SDRAM to internal buffer) has finished. 1’b0: No DMA read transfer completion 1’b1: DMA read transfer completed [4] DWrINT DMA Write Interrupt Status This bit indicates the DMA write transfer (from internal buffer to external SDRAM) has finished. 1’b0: No DMA write transfer completion 1’b1: DMA write transfer completed [3] SDHIINT Secure Digital Host Controller Interface Interrupt Status This bit indicates there is an interrupt status from Secure Digital host controller. 1’b0: No interrupt status from Secure Digital host controller interface. 1’b1: There is an interrupt status from Secure Digital host controller Interface [0] SDGINT SD Host Global Interrupt Status This bit is the wired-OR of SDHINT, DWrINT and DRdINT. 1’b0: No SD host controller interrupt notification 1’b1: There is an SD host controller interrupt status

Publication Release Date: September 19, 2006 - 243 - Revision B2 SD BIST Register (SDBIST) REGISTER ADDRESS R/W 0xFFF0_7014 R/W SD BIST Register 0x0000_0000 Reserved Reserved Reserved Reserved BistFail Finish BISTEN BITS DESCRIPTIONS [31:4] Reserved [3:2] BistFail BIST Fail The BistFail indicates if the BIST test fails or succeeds. If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation. The BistFail is a write clear field. Write 1 to this field clears the content and write 0 has no effect. [1] Finish BIST Operation Finish It indicates the end of the BIST operation. When BIST controller finishes all operations, this bit will be set high. This bit is a write clear field. Write 1 to this field clears the content and write 0 has no effect. [0] BISTEN BIST Enable The BISTEN is used to enable the BIST operation. If high enables the BIST controller to do embedded SRAM test. This bit is also used to do the reset for BIST circuit. It is necessary to reset the BIST circuit one clock cycle at least in order to initialize the BIST properly. The BISTEN can be disabled by write 0.

244 - SD Interface Control Register (SDICR) REGISTER ADDRESS R/W

0xFFF0_7300 R/W SD Interface Control Register 0x0000_0000 Reserved Reserved SD_CS Reserved CMD_CODE CLK_KEEP 8CLK_OE 74CLK_OE R2_EN DO_EN DI_EN RI_EN CO_EN BITS DESCRIPTIONS [31:16] Reserved [15] SD_CS SD Card Select Control 0=Select SD card-0 1=Select SD card-1 It is fixed to 0 at W90P710 [13:8] CMD_CODE SD Command Code This register contains the SD command code (00H – 3FH). [7] CLK_KEEP SD Clock Enable 0=Disable SD clock generation 1=SD clock always keeps free running. [6] 8CLK_OE

8 Clock Cycles Output Enable

0=Disable 1=Enable, SD host controller output 8 clock cycles When the operation is finished, this bit is automatically cleared to “0” by H/W circuit.

Publication Release Date: September 19, 2006 - 245 - Revision B2 Continued. BITS DESCRIPTIONS [5] 74CLK_OE

74 Clock Cycle Output Enable

0=Disable 1=Enable, SD host controller outputs 74 clock cycles When the operation is finished, this bit is automatically cleared to “0” by H/W circuit. [4] R2_EN Response R2 Input Enable 0=Disable 1=Enable, SD host controller will wait to receive a response R2 from DS card and store the response data into flash buffer. When the R2 response operation is finished, this bit is automatically cleared to “0” by H/W circuit. [3] DO_EN Data Output Enable 0=Disable 1=Enable, SD host controller will transfer a single block data and the CRC-16 code to SD card. When the data output operation is finished, this bit is automatically cleared to “0” by H/W circuit. [2] DI_EN Data Input Enable 0=Disable 1=Enable, SD host controller will wait to receive a single block data and the CRC-16 code from SD card. When the data input operation is finished, this bit is automatically cleared to “0” by H/W circuit. [1] RI_EN Response Input Enable 0=Disable 1=Enable, SD host controller will wait to receive a response from SD card. When the response operation is finished, this bit is automatically cleared to “0” by H/W circuit. [0] CO_EN Command Output Enable 0=Disable 1=Enable, SD host controller will transfer a command to SD card. When the command operation is finished, this bit is automatically cleared to “0” by H/W circuit.

246 - SD Host interface Initial Register (SDHIIR) REGISTER ADDRESS R/W

0xFFF0_7304 R/W SD Host Interface Initial Register 0x0000_0018 Reserved Reserved Reserved SPD SD_CLK BITS DESCRIPTIONS [31:9] Reserved [8] SPD Data Bus Width Control 0=1-bit data bus 1=4-bit data bus [7:0] SD_CLK SD Clock Control The frequency of SD clock will be equal to (Input Clock/(SD_CLK+1)). The SD_CLK = 8’h00 is reserved. SD Interface Interrupt Enable Register (SDIIER) REGISTER ADDRESS R/W 0xFFF0_7308 R/W SD Interface Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved SD_IEN DAT0_IEN CD_IEN DO_IEN DI_IEN

Publication Release Date: September 19, 2006 - 247 - Revision B2 BITS DESCRIPTIONS [31:5] Reserved [4] SD_IEN SD Interrupt Status Enable 0=Disable SD_IS interrupt generation 1=Enable SD_IS interrupt generation [3] DAT0_IEN SD DAT0 Level Transition Interrupt Status Enable 0=Disable DAT0_STS interrupt generation 1=Enable DAT0_STS interrupt generation [2] CD_IEN CD# Interrupt Status Enable 0=Disable CD_IS interrupt generation 1=Enable CD_IS interrupt generation [1] DO_IEN Data Output Interrupt Status Enable 0=Disable DO_IS interrupt generation 1=Enable DO_IS interrupt generation [0] DI_IEN Data Input Interrupt Status Enable 0=Disable DI_IS interrupt generation 1=Enable DI_IS interrupt generation SD Interface Interrupt Status Register (SDIISR) Register Address R/W 0xFFF0_730C R/W SD Interface Interrupt Status Register 0x0000_00XX Reserved Reserved Reserved DAT1_IS_ SD_DATA0 DAT0_STS CD_ R2_CRC7 CRC CRC-16 CRC-7 CD_IS DO_IS DI_IS

248 - BITS DESCRIPTIONS [31:11] Reserved [10] DAT1_IS_ SD Interrupt Value Status 0 = SD interrupt at interrupt period. Write 1 to clear this status bit (set DAT1_IS_ to 1). 1 = no SD interrupt at interrupt period. If SD_IEN is set and DAT1_IS_ is 0, an interrupt request will be generated. Interrupt period is defined: (1) If SD data bus width is 1 and DAT[1] is unused, the interrupt period is any time on DAT[1] (2) If SD data bus width is 4, the interrupt period is at the single clock that is 2 clocks after the End bit of data block [9] SD_DATA0 SD DAT0 Value [8] DAT0_STS SD Level Transition Status 0=No level transition 1=DAT0 value changes from high to low or low to high. Write 1 to clear this status bit. [7] CD_ Card Detection Indicator [6] R2_CRC7 Response R2 CRC-7 Check Status 0=Fault 1=OK [5] CRC CRC Check Result Status 0=Fault 1=OK [4] CRC-16 CRC-16 Check Result Status 0=Fault 1=OK [3] CRC-7 CRC-7 Check Result Status 0=Fault 1=OK

Publication Release Date: September 19, 2006 - 249 - Revision B2 Continued. BITS DESCRIPTIONS [2] CD_IS CD# Interrupt Status 0=No Interrupt Generated 1=Interrupt Generated Note: Write “1” into this bit will clear the interrupt status. [1] DO_IS Data Output Interrupt Status 0=No Interrupt Generated 1=Interrupt Generated Note: Write “1” into this bit will clear the interrupt status. [0] DI_IS Data Input Interrupt Status 0=No Interrupt Generated 1=Interrupt Generated Note: Write “1” into this bit will clear the interrupt status. SD Command Argument Register (SDAUG) REGISTER ADDRESS R/W 0xFFF0_7310 R/W SD Command Argument Register 0x0000_0000 SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG BITS DESCRIPTIONS [31:0] SD_CMD_ARG SD Command Argument This register contains a 32-bit value specifies the argument of SD command from host controller to card.

250 - SD Receive Response Token Register 0 (SDRSP0) REGISTER ADDRESS R/W

0xFFF0_7314 R SD Receive Response Token Register 0 0xXXXX_XXXX SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 BITS DESCRIPTIONS [31:0] SD_RDP_TK0 SD Receive Response Token 0 SD host controller will receive a response token for getting a reply from SD card. This register records the bit 47-16 of the response token. SD Receive Response Token Register 1 (SDRSP1) REGISTER ADDRESS R/W 0xFFF0_7318 R SD Receive Response Token Register 1 0x0000_XXXX Reserved Reserved Reserved SD_RSP_TK1

Publication Release Date: September 19, 2006 - 251 - Revision B2 BITS DESCRIPTIONS [31:8] Reserved [7:0] SD_RSP_TK1 SD Receive Response Token 1 SD host controller will receive a response token for getting a reply from SD card. This register records the bit 15-8 of the response token. SD Block Length Register (SDBLEN) REGISTER ADDRESS R/W 0xFFF0_731C R/W SD Block Length Register 0x0000_0000 Reserved Reserved Reserved SDBLEN SDBLEN BITS DESCRIPTIONS [31:9] Reserved [8:0] SDBLEN SD BLOCK LENGTH A 9-bit value specifies the SD transfer byte count. Flash Buffer 0 Registers (FB0_0 ~ FB0_127) REGISTER ADDRESS R/W FB0_0 ….. FB0_1274 0xFFF0_7400 ….. 0xFFF0_75FC R/W Flash Buffer 0 Undefined

252 - FBuf0 FBuf0 FBuf0 FBuf0 BITS DESCRIPTIONS [31:0] FBuf0 Flash Buffer 0 These register ports supports the data read from embedded flash buffer 0. The embedded flash buffer size is 512 bytes, the 128 words. Consequently, the address range for flash buffer 0 is from 0xFFF0_7400 to 0xFFF0_75FC. Flash Buffer 1 Registers (FB1_0 ~ FB1_127) REGISTER ADDRESS R/W

FB1_0 ….. FB1_1274 0xFFF0_7800 ….. 0xFFF0_79FC R/W Flash Buffer 1 Undefined FBuf1 FBuf1 FBuf1 FBuf1 BITS DESCRIPTIONS [31:0] FBuf1 Flash Buffer 1 These register ports supports the data read from embedded flash buffer 1. The embedded flash buffer size is 512 bytes, the 128 words. Consequently, the address range for flash buffer 1 is from 0xFFF0_7800 to 0xFFF0_79FC.

Publication Release Date: September 19, 2006 - 253 - Revision B2

6.10 LCD Controller

6.10.1 Main Features

y Supports 4-bit single scan Monochrome STN LCD panel, 8-bit single scan Monochrome STN LCD panel, 8-bit single scan Color STN LCD panel (all Sync-type) y Up to 16 gray levels display for Monochrome STN LCD panel y Up to 4096(12bpp) colors display for Color STN LCD panel y Virtual coloring method: Frame Rate Control (16-level ) y Anti-flickering method: Time-based Dithering TFT LCD Display y Supports Sync-type TFT LCD panel and Sync-type High-color TFT LCD panel y Supports direct or palettized color display TV Encoder y Supports 8-bit CCIR 601 YCbCr data output format to connect with external TV Encoder LCD Preprocessing y Supports RGB Raw-data or packetd YUV422 format y Programmable parameters for different image size y Build in two FIFOs, FIFO 1 is for Video image and FIFO 2 is for OSD image. Each FIFO is 16 words deep LCD Post processing y Support for one OSD (On Screen Display) overlay y Support various OSD function y Programmable parameters for different display panel Others y Color lookup table size 256x32 bit for TFT used when displaying 1bpp, 2bpp, 4bpp, 8bpp image y Dedicated DMA for block transfer mode

254 -

6.10.2 LCD Register MAP

0XFFF0_8000 R/W LCD Control 0x0000_0000 LCD Interrupt Control LCDINTENB 0xFFF0_8004 R/W LCD Interrupt Enable 0x0000_0000 LCDINTS 0xFFF0_8008 R LCD Interrupt Status 0x0000_0000 LCDINTC 0xFFF0_800C W LCD Interrupt Clear 0x0000_0000 LCD Pre-processing OSDUPSCF 0xFFF0_8010 R/W OSD Horizontal/Vertical up-scaling factor 0x0000_0000 VDUPSCF 0xFFF0_8014 R/W Video Horizontal/Vertical up- scaling factor 0x0000_0000 OSDDNSCF 0xFFF0_8018 R/W OSD Horizontal/Vertical down- scaling factor 0x0000_0000 VDDNSCF 0xFFF0_801C R/W Video Horizontal/Vertical down- scaling factor 0x0000_0000 LCD FIFO Control FIFOCON 0xFFF0_8020 R/W FIFOs control 0x0000_0000 FIFOSTATUS 0xFFF0_8024 R FIFOs status 0x0000_0000 FIFO1PRM 0xFFF0_8028 R/W FIFO1 parameters 0x0000_0000 FIFO2PRM 0xFFF0_802C R/W FIFO2 parameters 0x0000_0000 FIFO1SADDR 0xFFF0_8030 R/W FIFO1 start address 0x0000_0000 FIFO2SADDR 0xFFF0_8034 R/W FIFO2 start address 0x0000_0000 FIFO1DREQCNT 0xFFF0_8038 R/W FIFO1 data request count 0x0000_0000 FIFO2DREQCNT 0xFFF0_803C R/W FIFO2 data request count 0x0000_0000 FIFO1CURADR 0xFFF0_8040 R FIFO1 current access address 0x0000_0000 FIFO2CURADR 0xFFF0_8044 R FIFO2 current access address 0x0000_0000 FIFO1RELACOLCNT 0xFFF0_8048 R/W FIFO1 real column count 0x0000_0000 FIFO2RELACOLCNT 0xFFF0_804C R/W FIFO2 real column count 0x0000_0000 Color Generation VDLUTENTRY1 0xFFF0_8050 R/W Video lookup table entry index 1 0x0000_0000 VDLUTENTRY2 0xFFF0_8054 R/W Video lookup table entry index 2 0x0000_0000 VDLUTENTRY3 0xFFF0_8058 R/W Video lookup table entry index 3 0x0000_0000 VDLUTENTRY4 0xFFF0_805C R/W Video lookup table entry index 4 0x0000_0000

Publication Release Date: September 19, 2006 - 255 - Revision B2 LCD Register MAP, continued REGISTER ADDRESS R/W 0xFFF0_8060 R/W OSD lookup table entry index 1 0x0000_0000 OSDLUTENTRY2 0xFFF0_8064 R/W OSD lookup table entry index 2 0x0000_0000 OSDLUTENTRY3 0xFFF0_8068 R/W OSD lookup table entry index 3 0x0000_0000 OSDLUTENTRY4 0xFFF0_806C R/W OSD lookup table entry index 4 0x0000_0000 DITHP1 0xFFF0_8070 R/W Gray level dithered data duty pattern 1 0x0101_0001 DITHP2 0xFFF0_8074 R/W Gray level dithered data duty pattern 2 0x1111_0841 DITHP3 0xFFF0_8078 R/W Gray level dithered data duty pattern 3 0x4949_2491 DITHP4 0xFFF0_807C R/W Gray level dithered data duty pattern 4 0x5555_52A5 DITHP5 0xFFF0_8080 R/W Gray level dithered data duty pattern 5 0xB6B6_B556 DITHP6 0xFFF0_8084 R/W Gray level dithered data duty pattern 6 0xEEEE_DB6E DITHP7 0xFFF0_8088 R/W Gray level dithered data duty pattern 7 0xEFEF_EFBE LCD Post-processing DDISPCP 0xFFF0_8090 R/W Dummy Display Color Pattern 0x0000_0000 VWINS 0xFFF0_8094 R/W Video Window Starting Coordinate 0x0000_0000 VWINE 0xFFF0_8098 R/W Video Window Ending Coordinate 0x0000_0000 OSDWINS 0xFFF0_809C R/W OSD Window Starting Coordinate 0x0000_0000 OSDWINE 0xFFF0_80A0 R/W OSD Window Ending Coordinate 0x0000_0000 OSDOVCN 0xFFF0_80A4 R/W OSD Overlay Control 0x0000_0000 OSDCKP 0xFFF0_80A8 R/W OSD Overlay Color-Key Pattern 0x0000_0000 OSDCKM 0xFFF0_80AC R/W OSD Overlay Color-Key Mask 0x0000_0000 LCD Timing Generation LCDTCON1 0xFFF0_80B0 R/W LCD Timing Control 1 0x0000_0000 LCDTCON2 0xFFF0_80B4 R/W LCD Timing Control 2 0x0000_0000 LCDTCON3 0xFFF0_80B8 R/W LCD Timing Control 3 0x0000_0000 LCDTCON4 0xFFF0_80BC R/W LCD Timing Control 4 0x0000_0000 LCDTCON5 0xFFF0_80C0 R/W LCD Timing Control 5 0x0000_0000 LCDTCON6 0xFFF0_80C4 R LCD Timing Control 6 0x0000_0000 Lookup Table SRAM Build In Self Test BIST 0xFFF0_80D0 R/W 0x0000_0000 Lookup Table SRAM 0xFFF0_0100 0xFFF0_84FF R/W Look-Up Table RAM 0xXXXX_XXXX

256 -

6.10.3 LCD Special Register Description

6.10.3.1 LCD Controller

LCD Control Register (LCDCON) REGISTER ADDRESS R/W 0xFFF0_8000 R/W LCD control 0x0000_0000 Reserved PPRST LCDRST Reserved LUTWREN OSDEN LCDCEN LCDMON8 LCDBW YUV_nRGB TVEN PIXELSEQ TFTTYPE LCDTFT Reserved YUVSEQ RGBSEQ LCDBUS OSDLUTEN OSDBPP VDLUTEN VDBPP BITS DESCRIPTIONS [31:30] Reserved Reserved [29] PPRST LCD Pre-Processor Reset 0 = Disable, normal operation 1 = Only reset the LCD Pre-Processor, clear FIFO, AHB protocol re-start. [28] LCDRST LCD Controller Reset(except Control Registers) 0 = Disable, normal operation 1 = Reset the whole LCD Controller include LCD Timing Generator [27] Reserved Reserved [26] LUTWREN Lookup Table SRAM Write/Read Enable 0 = Disable 1 = Enable [25] OSDEN OSD Function Control 0 = Disable 1 = Enable [24] LCDCEN LCD Controller Enable 0 = Disable VSYNC, HSYNC, VCLK, VD, and VDEN 1 = Enable VSYNC, HSYNC, VCLK, VD, and VDEN

Publication Release Date: September 19, 2006 - 257 - Revision B2 Continued BITS DESCRIPTIONS [23] LCDMON8 Monochrome LCD has an 8-bit interface 0 = mono LCD use 4-bit interface 1 = mono LCD use 8-bit interface [22] LCDBW STN LCD is monochrome 0 = STN LCD is color 1 = STN LCD is monochrome [21] YUV_nRGB Image stored in memory device is YUV format or RGB format 0 = RGB format 1 = YUV format If this bit is set to 1, VDBPP and OSDBPP must be set to 101 ( 16bpp ) [20] TVEN External TV encoder Enable 0 = Normal operation 1 = Convert RGB to YCbCr for external TV encoder [19:18] PIXELSEQ Display pixel sequence for sync-type TFT 00 = R1 G1 B2 R2 G3 R3 01 = R1 G2 B3 R4 G5 B6 10 = R1 G1 B1 R2 G2 B2 11 = Reserved [17] TFTTYPE TFT Type Select 0 = Sync-type High Color TFT LCD 1 = Sync-type TFT LCD [16] LCDTFT LCD is TFT 0 = LCD is an STN display 1 = LCD is a TFT display [15:14] Reserved Reserved [13:12] YUV_SEQ YUV output sequence( only used at TV-Encoder) 00 = UYVY 01 = YUYV 10 = VYUY 11 = YVYU [11:10] RGBSEQ LCD Line Data Sequence( only used at Sync-Type non High Color TFT) 00 = First line data is RGB, second line data is GBR 01 = First line data is BGR, second line data is RBG 10 = First line data is GBR, second line data is RGB 11 = First line data is RBG, second line data is BGR

258 - Continued BITS DESCRIPTIONS [9:8] LCDBUS LCD Data output re-map( Only used at Sync-type High Color TFT) 00 = Databus is 24bit 01 = Databus is 18bit 10 = Databus is 8bit 11 = Reserved [7] OSDLUTEN OSD Lookup Table Enable 0 = display OSD color directly from image 1 = display OSD color from lookup table [6:4] OSDBPP OSD image bits per pixel 000 = 1 bpp 2-gray level 001 = 2 bpp 4-gray level 010 = 4 bpp 16-gray level 011 = 8 bpp RGB332 100 = 12 bpp RGB444 101 = 16 bpp RGB565 110 = 18 bpp RGB666 111 = 24 bpp RGB888 [3] VDLUTEN Video Lookup Table Enable 0 = display Video color directly from image 1 = display Video color from lookup table [2:0] VDBPP Video image bits per pixel 000 = 1 bpp 2-gray level 001 = 2 bpp 4-gray level 010 = 4 bpp 16-gray level 011 = 8 bpp RGB332 100 = 12 bpp RGB444 101 = 16 bpp RGB565 110 = 18 bpp RGB666 111 = 24 bpp RGB888 Output format of LCD Panel Sync-type High Color TFT: Fig. 6.10.3.1 Sync-type High Color TFT output format

Publication Release Date: September 19, 2006 - 259 - Revision B2 Sync-type TFT: Fig. 6.10.3.2 Sync-type TFT output format TV-Encoder: Fig. 6.10.3.3 TV-Enocder output format Color STN: Fig. 6.10.3.4 Color STN output format

260 - Monochrome STN with 4-bit data bus: Fig. 6.10.3.5 Monochrome STN output format - 1 Monochrome STN with 8-bit data bus: Fig. 6.10.3.6 Monochrome STN output format - 2 Only when LUTWREN is enabled, Lookup Table SRAM can be read / write by CPU. If LUTWREN is disabled, Lookup Table SRAM is accessed by LCD Controller. Palette function can’t be enabled for STN panel. Because the Lookup Table SRAM is only 256 x32 bit, so , if one of Video or OSD image is 8bpp, both the VDLUTEN and OSDLUTEN can only be enabled when the Palette Table of Video is the same as OSD. If VDLUTEN or OSDLUTEN is enabled, LCD Controller will output data from Lookup Table SRAM for 8bpp, 4bpp, 2bpp, 1bpp image. Else, LCD Controller will treat 8bpp data as RGB332, 4bpp as 16 gray-level, 2bpp as 4 gray-level, 1bpp as 2 gray-level (black or white). At normally, LCD Databus output is RGB888, 24bit. If LCDBUS is set to 01, LCD Databus output is RGB666, 18bit. If LCDBUS is set to 10, LCD Databus output is RGB332, 8bit. The other bit will be

Publication Release Date: September 19, 2006 - 261 - Revision B2 replaced with zero. Please refer to GPIO chapter to setting this register. This is only used for Sync- type High Color TFT because it’s databus is large over 8bit. Databus of other panel is only 8bit so don’t need to setting this register. VD 23 22 21 20 19 18 17 LCDBUS = 00 R[7:0] G[7:0] B[7:0] LCDBUS = 01 R[7:2] G[7:2] B[7:2] LCDBUS = 10 R[7:5] G[7:5] B[7:6]

6.10.3.2 LCD Interrupt Control

There are enable register, clear register, status register for every interrupt type. Enable Mask set/clear register will branch firmware into interrupt sub-routine. Firmware can read Status register to identify which interrupt generate now. Write Clear register will clear the interrupt status. Status register will be set even if firmware disable the Enable register. Main-routine can read Status register and write Clear register. LCD Interrupt Enable Register (LCDINTENB) REGISTER ADDRESS R/W 0xFFFF0_0004 R/W LCD interrupt enable 0x0000_0000 Reserved Reserved UNDREN2 UNDREN1 AHBEREN Reserved Reserved HSEN VSEN VLFINEN2 VFFINEN2 VLFINEN1 VFFINEN1

262 - BITS DESCRIPTIONS [31:19] Reserved Reserved [18] UNDREN2 FIFO2 UNDERRUN interrupt enable [17] UNDREN1 FIFO1 UNDERRUN interrupt enable [16] AHBEREN AHB ERROR interrupt enable [15:6] Reserved Reserved [5] HSEN HSYNC interrupt enable [4] VSEN VSYNC interrupt enable [3] VLFINEN2 FIFO2 VLINE FINISH interrupt enable [2] VFFINEN2 FIFO2 VFRAME FINISH interrupt enable [1] VLFINEN1 FIFO1 VLINE FINISH interrupt enable [0] VFFINEN1 FIFO1 VFRAME FINISH interrupt enable LCD Interrupt Status Register (LCDINTS) REGISTER ADDRESS R/W

0xFFF0_8008 R LCD interrupt status 0x0000_0000 Reserved Reserved UNDRIS2 UNDRIS1 AHBERIS Reserved Reserved HSIS VSIS VLFINIS2 VFFINIS2 VLFINIS1 VFFINIS1

Publication Release Date: September 19, 2006 - 263 - Revision B2 BITS DESCRIPTIONS [31:20] Reserved Reserved [18] UNDRIS2 FIFO2 have no data for output to Panel [17] UNDRIS1 FIFO1 have no data for output to Panel [16] AHBERIS AHB master bus error status [15:6] Reserved Reserved [5] HSIS Timing Generator output a HSYNC pulse [4] VSIS Timing Generator output a VSYNC pulse [3] VLFINIS2 FIFO2 transfer one line stream complete [2] VFFINIS2 FIFO2 transfer one frame stream complete [1] VLFINIS1 FIFO1 transfer one line stream complete [0] VFFINIS1 FIFO1 transfer one frame stream complete LCD Controller is an AHB Master at AMBA and fetching video data from an AHB Slave such as SDRAM or FLASH memory. If AHB Slave response ERROR for LCD Controller’s data request, AHBERIS will be set. If the data rate of output to LCD Panel is too fast and the data rate of fetch data from AMBA is too slow; there are no data in FIFO for LCD Panel’s request, UNDRISx will be set. LCD Timing Generation register need to be re-configured. HSIS and VSIS provide information for firmware to know the status of LCD Panel. VLFINISx and VFFINISx provide information for firmware to know how much data FIFO have fetched. LCD Interrupt Clear Register (LCDINTC) REGISTER ADDRESS R/W 0xFFF0_800C W LCD interrupt clear 0x0000_0000

264 - Reserved Reserved UNDRIC2 UNDRIC1 AHBERIC Reserved Reserved HSIC VSIC VLFINIC2 VFFINIC2 VLFINIC1 VFFINIC1 BITS DESCRIPTIONS [31:20] Reserved Reserved [18] UNDRIC2 Clear FIFO2 UNDERRUN interrupt [17] UNDRIC1 Clear FIFO1 UNDERRUN interrupt [16] AHBERIC Clear MBERROR interrupt [15:6] Reserved Reserved [5] HSIC Clear HSYNC interrupt [4] VSIC Clear VSYNC interrupt [3] VLFINIC2 Clear FIFO2 VLINEFINSH interrupt [2] VFFINIC2 Clear FIFO2 VFRAMFINSH interrupt [1] VLFINIC1 Clear FIFO1 VLINEFINSH interrupt [0] VFFINIC1 Clear FIFO1 VFRAMFINSH interrupt

Publication Release Date: September 19, 2006 - 265 - Revision B2

6.10.3.3 LCD Pre-processing

OSD Up-Scaling Factor Register (OSDUPSCF) REGISTER ADDRESS R/W 0xFFF0_8010 R/W OSD Horizontal/Vertical up-scaling 0x0000_0000 Reserved Reserved Reserved Reserved OSDHUP OSDVUP Reserved BITS DESCRIPTIONS [31:5] Reserved Reserved [4:3] OSDHUP OSD Stream Horizontal Up-scaling 00=1x 01=2x 10=4x [2:1] OSDVUP OSD Stream Vertical Up-scaling 00=1x 01=2x 10=4x [0] Reserved Reserved Video Up-Scaling Factor Register (VDUPSCF) REGISTER ADDRESS R/W 0xFFF0_8014 R/W Video Horizontal/Vertical up-scaling 0x0000_0000

266 - Reserved Reserved Reserved Reserved VDHUP VDVUP Reserved BITS DESCRIPTIONS [31:5] Reserved Reserved [4:3] VDHUP Video Horizontal Up-scaling control 00=1x 01=2x 10=4x [2:1] VDVUP Video Vertical Up-scaling control 00=1x 01=2x 10=4x [0] Reserved Reserved OSD Down-Scaling Factor Register (OSDDNSCF) REGISTER ADDRESS R/W

0xFFF0_8018 R/W OSD Horizontal/Vertical down-scaling 0x0000_0000 OSDVDNN OSDVDNM OSDHDNN OSDHDNM

Publication Release Date: September 19, 2006 - 267 - Revision B2 BITS DESCRIPTIONS [31:24] OSDVDNN An 8-bit value specifies the numerator part (N) of the vertical down- scaling factor. [23:16] OSDVDNM An 8-bit value specifies the numerator part (M) of the vertical down- scaling factor. [15:8] OSDHDNN An 8-bit value specifies the numerator part (N) of the Horizontal down-scaling factor. [7:0] OSDHDNM An 8-bit value specifies the numerator part (M) of the Horizontal down-scaling factor. Video Down-Scaling Factor Register (VDDNSCF) REGISTER ADDRESS R/W 0xFFF0_801C R/W Video Horizontal/Vertical down-scaling factor 0x0000_0000 VDVDNN VDVDNM VDHDNN VDHDNM BITS DESCRIPTIONS [31:24] VDVDNN An 8-bit value specifies the numerator part (N) of the vertical down- scaling factor. [23:16] VDVDNM An 8-bit value specifies the numerator part (M) of the vertical down- scaling factor. [15:8] VDHDNN An 8-bit value specifies the numerator part (N) of the Horizontal down-scaling factor. [7:0] VDHDNM An 8-bit value specifies the numerator part (M) of the Horizontal down-scaling factor. Up-Scaling or Down-Scaling, firmware can choose only one function of it. If both factor register is configured, the behavior of LCD Controller is undefined.

268 -

6.10.3.4 LCD FIFOs Controller

FIFO Control Register (FIFOCON) REGISTER ADDRESS R/W 0xFFF0_8020 R/W FIFOs control 0x0000_0000 Reserved OSDBPP24S W OSDBPP18S W OSDHSWP OSDBSWP Reserved VDBPP24SW VDBPP18SW VDHSWP VDBSWP Reserved Reserved FIFOEN BITS DESCRIPTIONS [31:28] Reserved Reserved [27] OSDBPP24SW OSD image 24bpp swap control bit 0=Swap Disable 1=Swap Enable [26] OSDBPP18SW OSD image 18bpp swap control bit 0=Swap Disable 1=Swap Enable [25] OSDHSWP OSD half-word swap control bit. 0 = Swap Disable 1 = Swap Enable [24] OSDBSWP OSD byte swap control bit. 0 = Swap Disable 1 = Swap Enable [23:20] Reserved Reserved [19] VDBPP24SW Video image 24bpp swap control bit 0=Swap Disable 1=Swap Enable

Publication Release Date: September 19, 2006 - 269 - Revision B2 Continued BITS DESCRIPTIONS [18] VDBPP18SW Video image 18bpp swap control bit 0=Swap Disable 1=Swap Enable [17] VDHSWP Video half-word swap control bit. 0 = Swap Disable 1 = Swap Enable [16] VDBSWP Video byte swap control bit. 0 = Swap Disable 1 = Swap Enable [15:2] Reserved Reserved [1:0] FIFOEN FIFOs transfer data enable x1 = FIFO1 transfer enable x0=FIFO1 transfer disable 1x = FIFO2 transfer enable 0x=FIFO2 transfer disable FIFO Status Register (FIFOSTATUS) REGISTER ADDRESS R/W 0xFFF0_8024 R FIFOs status 0x0000_0000 Reserved Reserved Reserved Reserved MASTERID BITS DESCRIPTIONS [31:2] Reserved Reserved [1:0] MASTERID Currently, the data bus master 01 = FIFO1 grant the bus 11 = FIFO2 grant the bus

270 - FIFO1 Parameter Register (FIFO1PRM) REGISTER ADDRESS R/W

0xFFF0_8028 R/W FIFO1 parameters 0x0000_0000 F1STRIDE[15:8] F1STRIDE[7:0] Reserved Reserved F1LOCK F1BURSTY F1TRANSZ BITS DESCRIPTIONS [31:16] F1STRIDE Video frame buffer stride 16-bit value specifies the word offset of memory address of vertically adjacent line for FIFO1 fetching. [15:5] Reserved Reserved [4] F1LOCK FIFO1 lock transfer enable 0 = Disable 1 = Enable [3:2] F1BURSTY FIFO1 burst transfer type 00 =4 data burst mode 01 =8 data burst mode 10 =16 data burst mode [1:0] F1TRANSZ FIFO1 data width per-transfer 00=one byte 01=half word 10=one word FIFO2 Parameter Register (FIFO2PRM) REGISTER ADDRESS R/W 0xFFF0_802C R/W FIFO2 parameters 0x0000_0000

Publication Release Date: September 19, 2006 - 271 - Revision B2 F2STRIDE[15:8] F2STRIDE[7:0] Reserved Reserved F2LOCK F2BURSTY F2TRANSZ BITS DESCRIPTIONS [31:16] F2STRIDE Video frame buffer stride 16-bit value specifies the word offset of memory address of vertically adjacent line for FIFO2 fetching. [15:5] Reserved Reserved [4] F2LOCK FIFO2 lock transfer enable 0 = Disable 1 = Enable [3:2] F2BURSTY FIFO2 burst transfer type 00 =4 data burst mode 01 =8 data burst mode 10 =16 data burst mode [1:0] F2TRANSZ FIFO2 data width per-transfer 00=one byte 01=half word 10=one word FIFO1 Start Address Register (FIFO1SADDR) REGISTER ADDRESS R/W 0xFFF0_8030 R/W FIFO1 start address 0x0000_0000 FIFO1SADDR[31:24] FIFO1SADDR[23:16] FIFO1SADDR[15:8] FIFO1SADDR[7:0]

272 - BITS DESCRIPTIONS [31:0] FIFO1SADDR These bits indicate the source address of the bank location for the LCD frame buffer in the system memory. FIFO2 Start Address Register (FIFO2SADDR) REGISTER ADDRESS R/W

0xFFF0_8034 R/W FIFO2 start address 0x0000_0000 FIFO2SADDR[31:24] FIFO2SADDR[23:16] FIFO2SADDR[15:8] FIFO2SADDR[7:0] BITS DESCRIPTIONS [31:0] FIFO2SADDR These bits indicate the source address of the bank location for the LCD frame buffer in the system memory. FIFO1 Request Count Register (FIFO1DREQCNT) REGISTER ADDRESS R/W FIFO1DREQCNT 0xFFF0_8038 R/W FIFO1 request count 0x0000_0000 FIFO1COLCNT[31:24] FIFO1COLCNT[23:16] FIFO1ROWCNT[15:8] FIFO1ROWCNT[7:0]

Publication Release Date: September 19, 2006 - 273 - Revision B2 BITS DESCRIPTIONS [31:16] FIFO1COLCNT These bits indicate the FIFO1 request count per-line of video [15:0] FIFO1ROWCNT These bits indicate the FIFO1 request count per-frame of video FIFO2 Request Count Register (FIFO2DREQCNT) REGISTER ADDRESS R/W 0xFFF0_803C R/W FIFO2 data request count 0x0000_0000 FIFO2COLCNT[31:24] FIFO2COLCNT[23:16] FIFO2ROWCNT[15:8] FIFO2ROWCNT[7:0] BITS DESCRIPTIONS [31:16] FIFO2COLCNT These bits indicate the FIFO2 request count per-line of video [15:0] FIFO2ROWCNT These bits indicate the FIFO2 request count per-frame of video FIFO1 Current Access Address Register (FIFO1CURADR) REGISTER ADDRESS R/W FIFO1CURADR 0xFFF0_8040 R FIFO1 current access address 0x0000_0000

274 - FIFO1CURADR[31:24] FIFO1CURADR[23:16] FIFO1CURADR[15:8] FIFO1CURADR[7:0] BITS DESCRIPTIONS [31:0] FIFO1CURADR Contains the approximate current FIFO1 access data address FIFO2 Current Access Address Register (FIFO2CURADR) REGISTER ADDRESS R/W

FIFO2CURADR 0xFFF0_8044 R FIFO2 current access address 0x0000_0000 FIFO2CURADR[31:24] FIFO2CURADR[23:16] FIFO2CURADR[15:8] FIFO2CURADR[7:0] BITS DESCRIPTIONS [31:0] FIFO2CURADR Contains the approximate current FIFO2 access data address

Publication Release Date: September 19, 2006 - 275 - Revision B2 FIFO1 Real Column Count Register (F1REALCULCNT) REGISTER ADDRESS R/W 0xFFF0_8048 R/W FIFO1 real column count 0x0000_0000 Reserved Reserved F1REALCOLCNT[15:8] F1REALCOLCNT[7:0] BITS DESCRIPTIONS [31:16] Reserved Reserved [15:0] F1REALCOLCNT These bits indicate the FIFO1 real column count per-frame of video FIFO2 Real Column Count (F2REALCULCNT) REGISTER ADDRESS R/W FIFO2REALCULCNT 0xFFF0_804C R/W FIFO2 real column count 0x0000_0000 Reserved Reserved F2REALCOLCNT[15:8] F2REALCOLCNT[7:0]

276 - BITS DESCRIPTIONS [31:16] Reserved Reserved [15:0] F2REALCOLCNT These bits indicate the FIFO2 real column count per-line of video 24bpp image format: (BSWP=0, HSWP=0, BPP24SWP=0) D[31:24] D[23:0] 0000H Dummy Bit Pixel 1 0004H Dummy Bit Pixel 2 0008H Dummy Bit Pixel 3 ………. (BSWP=0, HSWP=0, BPP24SWP=1) D[31:8] D[7:0] 0000H Pixel 1 Dummy Bit 0004H Pixel 2 Dummy Bit 0008H Pixel 3 Dummy Bit ………. 18bpp image format: (BSWP=0, HSWP=0, BPP18SWP=0) D[31:18] D[17:0] 0000H Dummy Bit Pixel 1 0004H Dummy Bit Pixel 2 0008H Dummy Bit Pixel 3 ……….

Publication Release Date: September 19, 2006 - 277 - Revision B2 (BSWP=0, HSWP=0, BPP18SWP=1) D[31:18] D[17:0] 0000H Pixel 1 Dummy Bit 0004H Pixel 2 Dummy Bit 0008H Pixel 3 Dummy Bit ………. 16bpp image format: (BSWP=0, HSWP=0) D[31:16] D[15:0] 0000H Pixel 2 Pixel 1 0004H Pixel 4 Pixel 3 0008H Pixel 6 Pixel 5 ………. (BSWP=0, HSWP=1) D[31:16] D[15:0] 0000H Pixel 1 Pixel 2 0004H Pixel 3 Pixel 4 0008H Pixel 5 Pixel 6 ……….

278 - 12bpp image format: (BSWP=0, HSWP=0) D[31:28] P[27:16] P[15:12] D[11:0] 0000H Dummy Bit Pixel 2 Dummy Bit Pixel 1 0004H Dummy Bit Pixel 4 Dummy Bit Pixel 3 0008H Dummy Bit Pixel 6 Dummy Bit Pixel 5 ………. (BSWP=0, HSWP=1) D[31:28] P[27:16] P[15:12] D[11:0] 0000H Dummy Bit Pixel 1 Dummy Bit Pixel 2 0004H Dummy Bit Pixel 3 Dummy Bit Pixel 4 0008H Dummy Bit Pixel 5 Dummy Bit Pixel 6 ………. 8bpp image format: (BSWP=0, HSWP=0) D[31:24] P[23:16] P[15:8] D[7:0] 0000H Pixel 4 Pixel 3 Pixel 2 Pixel 1 0004H Pixel 8 Pixel 7 Pixel 6 Pixel 5 0008H Pixel 12 Pixel 11 Pixel 10 Pixel 9 ………. (BSWP=1, HSWP=0) D[31:24] P[23:16] P[15:8] D[7:0] 0000H Pixel 1 Pixel 2 Pixel 3 Pixel 4 0004H Pixel 5 Pixel 6 Pixel 7 Pixel 8 0008H Pixel 9 Pixel 10 Pixel 11 Pixel 12 ……….

Publication Release Date: September 19, 2006 - 279 - Revision B2 4bpp image format: (BSWP=0, HSWP=0) D[31:28] P[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 0000H Pixel 7 Pixel 8 Pixel 5 Pixel 6 Pixel 3 Pixel 4 Pixel 1 Pixel 2 0004H Pixel 15 Pixel 16 Pixel 13 Pixel 14 Pixel 11 Pixel 12 Pixel 9 Pixel 10 (BSWP=1, HSWP=0) D[31:28] P[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 0000H Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 0004H Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 Pixel 16 2bpp image format: (BSWP=0, HSWP=0) 0000H D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 13 Pixel 14 Pixel 15 Pixel 16 Pixel 9 Pixel 10 Pixel 11 Pixel 12 D[15:14] P[13:12] D[11:10] D[9:8] D[7:6] D[5:4] D[3:2] D[1:0] Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 0004H D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 29 Pixel 30 Pixel 31 Pixel 32 Pixel 25 Pixel 26 Pixel 27 Pixel 28 D[15:14] P[13:12] D[11:10] D[9:8] D[7:6] D[5:4] D[3:2] D[1:0] Pixel 21 Pixel 22 Pixel 23 Pixel 24 Pixel 17 Pixel 18 Pixel 19 Pixel 20 …….

280 - (BSWP=1, HSWP=0) 0000H D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 D[15:14] P[13:12] D[11:10] D[9:8] D[7:6] D[5:4] D[3:2] D[1:0] Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 Pixel 16 0004H D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 17 Pixel 18 Pixel 19 Pixel 20 Pixel 21 Pixel 22 Pixel 23 Pixel 24 D[15:14] P[13:12] D[11:10] D[9:8] D[7:6] D[5:4] D[3:2] D[1:0] Pixel 25 Pixel 26 Pixel 27 Pixel 28 Pixel 29 Pixel 30 Pixel 31 Pixel 32 1bpp image format: (BSWP=0, HSWP=0) 0000H D[31] P[30] D[29] D[28] D[27] D[26] D[25] D[24] Pixel 25 Pixel 26 Pixel 27 Pixel 28 Pixel 29 Pixel 30 Pixel 31 Pixel 32 D[23] P[22] D[21] D[20] D[19] D[18] D[17] D[16] Pixel 17 Pixel 18 Pixel 19 Pixel 20 Pixel 21 Pixel 22 Pixel 23 Pixel 24 D[15] P[14] D[13] D[12] D[11] D[10] D[9] D[8] Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 Pixel 16 D[7] P[6] D[5] D[4] D[3] D[2] D[1] D[0] Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8

Publication Release Date: September 19, 2006 - 281 - Revision B2 (BSWP=0, HSWP=0) 0000H D[31] P[30] D[29] D[28] D[27] D[26] D[25] D[24] Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 D[23] P[22] D[21] D[20] D[19] D[18] D[17] D[16] Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 Pixel 16 D[15] P[14] D[13] D[12] D[11] D[10] D[9] D[8] Pixel 17 Pixel 18 Pixel 19 Pixel 20 Pixel 21 Pixel 22 Pixel 23 Pixel 24 D[7] P[6] D[5] D[4] D[3] D[2] D[1] D[0] Pixel 25 Pixel 26 Pixel 27 Pixel 28 Pixel 29 Pixel 30 Pixel 31 Pixel 32 ………. If there is an image with size 480*480, 24bpp, stored in memory device with starting address is 0x30000000. 24bpp means there are 4bytes a pixel (real color 3bytes and dummy data 1byte). So: FIFO1SADDR = 0x30000000 FIFO1COLCNT = 0x01E0 FIFO1ROWCNT = 0x01E0 FIFO1REALCOLCNT = 0x01E0 The unit of FIFOCOLCNT is word. So, if the image is 16bpp, FIFO1COLCNT and FIFO1REALCOLCNT are modified to 0x00F0 because under 16bpp mode, a word contains two pixel data. When FIFO received the value which FIFOCOLCNT specified, VLINEFINSH interrupt is generated and (1) Row counter will increase 1. When row counter received the value which FIFOROWCNT specified, VFRAMFINSH interrupt is generated. So, FIFOROWCNT have no concern with BPP. (2) FIFOSTRIDE will be load in and add to current accessing address Column counter counts the FIFO writing pulse. If Horizontal Up-Scaling factor is 2X, FIFO will extract a pixel data to two pixel data internal. So if Horizontal Up-Scaling function is enabled, FIFOCOLCNT need to divided again or VLINEFINSH interrupt will generated after FIFO have received two column data and FIFOROWCNT and VFRAMFINSH interrupt will be influenced too. The same with Horizontal Down-Scaling function, so it’s recommend that Horizontal Down- Scaling Factor M is a multiple of 4. When VFRAMEFINSH interrupt generated, FIFO will fetch image data re-start at FIFO1SADDR.

282 - Fig. 6.10.5.7 FIFO parameter example If there is an image with size 480*480, 24bpp, stored in memory device with starting address is 0x30000000, and connected with a 480*480 LCD Panel, and user wants to show whole image on LCD Panel, the setting of registers are: FIFO1SADDR = 0x30000000 FIFO1COLCNT = 0x01E0 FIFO1ROWCNT = 0x01E0 FIFO1REALCOLCNT = 0x01E0 If the LCD Controller connected with a 240*240 LCD Panel or user only wants to show a part (red line region, 240*240) of the whole image on a 480*480 LCD Panel, the setting of registers are: FIFO1SADDR = 0x3001C3E0 (0x30000000 + 4*(480*60+120) = 0x3001C3E0) FIFO1COLCNT = 0x00F0 FIFO1ROWCNT = 0x00F0 FIFOSTRIDE = 0x03C0 (240*4 = 0x03C0) FIFO1REALCOLCNT = 0x00F0 After setting register complete, enable FIFO and then FIFO will fetch the image data according to the register value. In additional, if the image in FIFO is small than the LCD Panel, DISPWYS, DISPWXS, DISPWYE, DISPWXE must be configured. Usually, FIFO Real Column Count is the same with FIFO Column Count. But if horizontal down- scaling function is enabled (factor M is not equal with N), FIFO Real Column Count specify the column count of original image, and FIFO Column Count specify the column count of the scaled image. If There is a picture with N BPP and horizontal width X pixel, the word-count W of this picture is: 480 pixels 480 pixels

Publication Release Date: September 19, 2006 - 283 - Revision B2 N BPP W (WORD)

1 BPP (Black / White)

X % 32

2 BPP (4 gray-level)

X % 16

4 BPP (16 gray-level)

X % 8

8 BPP ( RGB 332)

X % 4

12 BPP (RGB 444)

X % 2

16 BPP (RGB 565)

X % 2

18 BPP (RGB 666)

X % 1

24 BPP (RGB 888)

X % 1 The first limitation is W must be a integer. The second limitation is W must be a multiple of 8 for Color STN panel. W can be a multiple of 4, 8 or 16 for other kind of panel. If W is a multiple of 4, the register value of F1BURSTY (FIFO1PRM register) must be set to 00. If W is a multiple of 8, the register value of F1BURSTY (FIFO1PRM register) must be set to 01. If W is a multiple of 16, the register value of F1BURSTY (FIFO1PRM register) must be set to 10. If there is a picture with N BPP and horizontal width X pixel which is not following the limitation, define R is quotient of W, and S is quotient of R % 16. Then the value of F1COLCNT (F1DREQCNT register) can be set to D = (S + 1) * 16, DISPWXE can be set to X. Define E = D * 4. When software is writing the picture raw data into SDRAM and reach the address of X * 4, software must jump to address E + 1 and then keep on writing data.

6.10.3.5 Color Generation

Video Lookup Table Entry Index 1 Register (VDLUTENTY1) REGISTER ADDRESS R/W 0xFFF0_8050 R/W Video lookup table entry index 1 0x0000_0000 VDLUTENTY1[31:24] VDLUTENTY1[23:16] VDLUTENTY1[15:8] VDLUTENTY1[7:0]

284 - BITS DESCRIPTIONS [31:0] VDLUTENTY1 Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLUTENTY1[7:0] 01 = VDLUTENTY1[15:8] 10 = VDLUTENTY1[23:16] 11 = VDLUTENTY1[31:24] Video Lookup Table Entry Index 2 Register (VDLUTENTY2) REGISTER ADDRESS R/W

VDLUTENTY2 0xFFF0_8054 R/W Video lookup table entry index 2 0x0000_0000 VDLUTENTY2[31:24] VDLUTENTY2[23:16] VDLUTENTY2[15:8] VDLUTENTY2[7:0] BITS DESCRIPTIONS [31:0] VDLUTENTY2 Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLUTENTY2[7:0] 01 = VDLUTENTY2[15:8] 10 = VDLUTENTY2[23:16] 11 = VDLUTENTY2[31:24]

Publication Release Date: September 19, 2006 - 285 - Revision B2 Video Lookup Table Entry Index 3 Register (VDLUTENTY3) REGISTER ADDRESS R/W VDLUTENTY3 0xFFF0_8058 R/W Video lookup table entry index 3 0x0000_0000 VDLUTENTY3[31:24] VDLUTENTY3[23:16] VDLUTENTY3[15:8] VDLUTENTY3[7:0] BITS DESCRIPTIONS [31:0] VDLUTENTY3 Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLUTENTY3[7:0] 01 = VDLUTENTY3[15:8] 10 = VDLUTENTY3[23:16] 11 = VDLUTENTY3[31:24] Video Lookup Table Entry Index 4 Register (VDLUTENTY4) REGISTER ADDRESS R/W VDLUTENTY4 0xFFF0_805C R/W Video lookup table entry index 4 0x0000_0000 VDLUTENTY4[31:24] VDLUTENTY4[23:16] VDLUTENTY4[15:8] VDLUTENTY4[7:0]

286 - BITS DESCRIPTIONS [31:0] VDLUTENTY4 Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLUTENTY4[7:0] 01 = VDLUTENTY4[15:8] 10 = VDLUTENTY4[23:16] 11 = VDLUTENTY4[31:24] OSD Lookup Table Entry Index 1 Register (OSDLUTENTRY1) REGISTER ADDRESS R/W

0xFFF0_8060 R/W OSD lookup table entry index 1 0x0000_0000 OSDLUTENTRY1[31:24] OSDLUTENTRY1[23:16] OSDLUTENTRY1[15:8] OSDLUTENTRY1[7:0] BITS DESCRIPTIONS [31:0] OSDLUTENTRY1 Theses bits define address of Lookup Table SRAM when OSD pixel data is 00 = OSDLUTENTRY1[7:0] 01 = OSDLUTENTRY1[15:8] 10 = OSDLUTENTRY1[23:16] 11 = OSDLUTENTRY1[31:24]

Publication Release Date: September 19, 2006 - 287 - Revision B2 OSD Lookup Table Entry Index 2 Register (OSDLUTENTRY2) REGISTER ADDRESS R/W 0xFFF0_8064 R/W OSD lookup table entry index 2 0x0000_0000 OSDLUTENTRY2[31:24] OSDLUTENTRY2[23:16] OSDLUTENTRY2[15:8] OSDLUTENTRY2[7:0] BITS DESCRIPTIONS [31:0] OSDLUTENTRY2 Theses bits define address of Lookup Table SRAM when pixel OSD data is 00 = OSDLUTENTRY2[7:0] 01 = OSDLUTENTRY2[15:8] 10 = OSDLUTENTRY2[23:16] 11 = OSDLUTENTRY2[31:24] OSD Lookup Table Entry Index 3 Register (OSDLUTENTRY3) REGISTER ADDRESS R/W 0xFFF0_8068 R/W OSD lookup table entry index 3 0x0000_0000 OSDLUTENTRY3[31:24] OSDLUTENTRY3[23:16] OSDLUTENTRY3[15:8] OSDLUTENTRY3[7:0]

288 - BITS DESCRIPTIONS [31:0] OSDLUTENTRY3 Theses bits define address of Lookup Table SRAM when OSD pixel data is 00 = OSDLUTENTRY3[7:0] 01 = OSDLUTENTRY3[15:8] 10 = OSDLUTENTRY3[23:16] 11 = OSDLUTENTRY3[31:24] OSD Lookup Table Entry Index 4 Register (OSDLUTENTRY4) REGISTER ADDRESS R/W

0xFFF0_806C R/W OSD lookup table entry index 4 0x0000_0000 OSDLUTENTRY4[31:24] OSDLUTENTRY4[23:16] OSDLUTENTRY4[15:8] OSDLUTENTRY4[7:0] BITS DESCRIPTIONS [31:0] OSDLUTENTRY4 Theses bits define address of Lookup Table SRAM when OSD pixel data is 00 = OSDLUTENTRY4[7:0] 01 = OSDLUTENTRY4[15:8] 10 = OSDLUTENTRY4[23:16] 11 = OSDLUTENTRY4[31:24] Dithering Pattern 1 Register (DITHP1) REGISTER ADDRESS R/W 0xFFF0_8070 R/W Gray level dithered data duty pattern 1 0x0101_0001

Publication Release Date: September 19, 2006 - 289 - Revision B2 DP2[15:8] DP2[7:0] DP1[15:8] DP1[7:0] BITS DESCRIPTIONS [31:16] DP2 Recommended pattern value for “4’b0010” gray level 0000 0001 0000 0001 [15:0] DP1 Recommended pattern value for “4’b0001” gray level 0000 0000 0000 0001 Dithering Pattern 2 Register (DITHP2) REGISTER ADDRESS R/W 0xFFF0_8074 R/W Gray level dithered data duty pattern 2 0x1111_0841 DP4[15:8] DP4[7:0] DP3[15:8] DP3[7:0] BITS DESCRIPTIONS [31:16] DP4 Recommended pattern value for “4’b0100” gray level 0001 0001 0001 0001 [15:0] DP3 Recommended pattern value for “4’b0011” gray level 0000 1000 0100 0001

290 - Dithering Pattern 3 Register (DITHP3) REGISTER ADDRESS R/W

0xFFF0_8078 R/W Gray level dithered data duty pattern 3 0x4949_2491 DP6[15:8] DP6[7:0] DP5[15:8] DP5[7:0] BITS DESCRIPTIONS [31:16] DP6 Recommended pattern value “4’’b0110” gray level 0100 1001 0100 1001 [15:0] DP5 Recommended pattern value “4’’b0101” gray level 0010 0100 1001 0001 Dithering Pattern 4 Register (DITHP4) REGISTER ADDRESS R/W 0xFFF0_807C R/W Gray level dithered data duty pattern 4 0x5555_52A5 DP8[15:8] DP8[7:0] DP7[15:8] DP7[7:0]

Publication Release Date: September 19, 2006 - 291 - Revision B2 BITS DESCRIPTIONS [31:16] DP8 Recommended pattern value “4’’b1000” gray level 0101 0101 0101 0101 [15:0] DP7 Recommended pattern value “4’’b0111” gray level 0101 0010 1010 1001 Dithering Pattern 5 Register (DITHP5) REGISTER ADDRESS R/W 0xFFF0_8080 R/W Gray level dithered data duty pattern 5 0xB6B6_B556 DP10[15:8] DP10[7:0] DP9[15:8] DP9[7:0] BITS DESCRIPTIONS [31:16] DP10 Recommended pattern value “4’’b1010” gray level 1011 0110 1011 0110 [15:0] DP9 Recommended pattern value “4’’b1001” gray level 1011 0101 0101 0110 Dithering Pattern 6 Register (DITHP6) REGISTER ADDRESS R/W 0xFFF0_8084 R/W Gray level dithered data duty pattern 6 0xEEEE_DB6E

292 - DP12[15:8] DP12[7:0] DP11[15:8] DP11[7:0] BITS DESCRIPTIONS [31:16] DP12 Recommended pattern value “4’’b1100” gray level 1110 1110 1110 1110 [15:0] DP11 Recommended pattern value “4’’b1011” gray level 1101 1011 0110 1110 Dithering Pattern 7 Register (DITHP7) REGISTER ADDRESS R/W

0xFFF0_8088 R/W Gray level dithered data duty pattern 7 0xFEFE_EFBE DP14[15:8] DP14[7:0] DP13[15:8] DP13[7:0] BITS DESCRIPTIONS [31:16] DP14 Recommended pattern value “4’’b1110” gray level 1111 1110 1111 1110 [15:0] DP13 Recommended pattern value “4’’b1101” gray level 1110 1111 1011 1110 The 4bpp flow is the same with 2bpp.

Publication Release Date: September 19, 2006 - 293 - Revision B2 PIXEL DATA OF 4BPP IMAGE THE ADDRESS VALUE WHICH WILL INPUT LOOKUP TABLE SRAM 0 (0000) LUTENTY1[7:0] 1 (0001) LUTENTY1[15:8] 2 (0010) LUTENTY1[23:16] 3 (0011) LUTENTY1[31:24] 4 (0100) LUTENTY2[7:0] 5 (0101) LUTENTY2[15:8] 6 (0110) LUTENTY2[23:16] 7 (0111) LUTENTY2[31:24] 8 (1000) LUTENTY3[7:0] 9 (1001) LUTENTY3[15:8] 10 (1010) LUTENTY3[23:16] 11 (1011) LUTENTY3[31:24] 12 (1100) LUTENTY4[7:0] 13 (1101) LUTENTY4[15:8] 14 (1110) LUTENTY4[23:16] 15 (1111) LUTENTY4[31:24] When the image is 8bpp, the pixel data will directly be treated as the Lookup Table SRAM address STN 16-leve gray number & relative Time-based dithering Frame No Duty Cycle #10 #11 #12 #13 #14 #15 #16 Probability Symbol “9” instead of pixel turn-on, other is turn-off.

294 -

6.10.3.6 LCD Post-processing

Dummy Display Color Pattern Register (DDISPCP) REGISTER ADDRESS R/W 0xFFF0_8090 R/W Dummy Display Color Pattern 0x0000_0000 Reserved GRAY DDISPR DDISPG DDISPB BITS DESCRIPTIONS [31] Reserved Reserved [30:24] GRAY Replenish bit for 8bpp when LUTEN is disable [23:16] DDISPR LCD dummy display data of R component [15:8] DDISPG LCD dummy display data of G component [7:0] DDISPB LCD dummy display data of B component Video Windows Starting Coordinate Register (VWINS) REGISTER ADDRESS R/W 0xFFF0_8094 R/W Video Window Starting Coordinate 0x0000_0000

Publication Release Date: September 19, 2006 - 295 - Revision B2 VWYS[31:24] VWYS[23:16] VWXS[15:8] VWXS[7:0] BITS DESCRIPTIONS [31:16] VWYS Video Window Y-Start A 16-bit value specifies the vertical starting pixel positions of the LCD display window. [15:0] VWXS Video Window X-Start A 16-bit value specifies the horizontal starting pixel positions of the LCD display window. Video Windows Ending Coordinate Register (VWINE) REGISTER ADDRESS R/W 0xFFF0_8098 R/W Video Window Ending Coordinate 0x0000_0000 VWYE[31:24] VWYE[23:16] VWXE[15:8] VWXE[7:0]

296 - BITS DESCRIPTIONS [31:16] VWYE Video Window Y-End A 16-bit value specifies the vertical last pixel positions of the LCD display window. [15:0] VWXE Video Window X-End A 16-bit value specifies the horizontal last pixel positions of the LCD display window. OSD Windows Starting Coordinate Register (OSDWINS) REGISTER ADDRESS R/W

0xFFF0_809C R/W OSD Window Starting Coordinate 0x0000_0000 OSDWYS[15:8] OSDWYS[7:0] OSDWXS[15:8] OSDWXS[7:0] BITS DESCRIPTIONS [31:16] OSDWYS OSD Window Y-Start A 16-bit value specifies the vertical starting pixel positions of the OSD window. [15:0] OSDWXS OSD Window X-Start A 16-bit value specifies the horizontal starting pixel positions of the OSD window. OSD Windows Ending Coordinate Register (OSDWINE) REGISTER ADDRESS R/W 0xFFF0_80A0 R/W OSD Window Ending Coordinate 0x0000_0000

Publication Release Date: September 19, 2006 - 297 - Revision B2 OSDWYE[15:8] OSDWYE[7:0] OSDWXE[15:8] OSDWXE[7:0] BITS DESCRIPTIONS [31:16] OSDWYE OSD Window Y-End A 16-bit value specifies the vertical last pixel positions of the OSD window. [15:0] OSDWXE OSD Window X-End A 16-bit value specifies the horizontal last pixel positions of the OSD window. OSD Overlay Control Register (OSDOVCN) REGISTER ADDRESS R/W 0xFFF0_80A4 R/W OSD Overlay Control 0x0000_0000 Reserved BLICNT Reserved OSDBLI OSDCKY Reserved VASYNW OCR1 OCR0

298 - BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] BLICNT OSD Blinking Cycle Time An 8-bit value specifies the OSD blinking cycle time (unit: Vsync) [15:10] Reserved Reserved [9] OSDBLI OSD Blinking Control 0 = Disable 1 = Enable [8] OSDCKY OSD Color Key Control 0 = Disable 1 = Enable [7] Reserved Reserved [6:4] VASYNW Video Synthesis Weighting Synthesized video= [Video x VASYNW+ OSD x (8-VASYNW)]/8 [3:2] OCR1 Video/OSD overlay control 1 When display region with OSD window, color-key condition match 00 = Display video data 01 = Display OSD data 10 = Display synthesized (Video+OSD) data [1:0] OCR0 Video/OSD overlay control 0 When display region with OSD window, color-key condition un-match 00 = Display video data 01 = Display OSD data 10 = Display synthesized (Video+OSD) data OSD Overlay Color Key Pattern Register (OSDOVCKP) REGISTER ADDRESS R/W

0xFFF0_80A8 R/W OSD Overlay Color-Key Pattern 0x0000_0000 Reserved OSDRKYP OSDGKYP OSDBKYP

Publication Release Date: September 19, 2006 - 299 - Revision B2 BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] OSDRKYP OSD data comparing of R component according to the source color format [15:8] OSDGKYP OSD data comparing of G component according to the source color format [7:0] OSDBKYP OSD data comparing of B component according to the source color format OSD Overlay Color Key Mask Register (OSDOVCKM) REGISTER ADDRESS R/W 0xFFF0_80AC R/W OSD Overlay Color-Key Mask 0x0000_0000 Reserved OSDRKYM OSDGKYM OSDBKYM BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] OSDRKYM For color-key pattern mask of R component according to the source color format [15:8] OSDGKYM For color-key pattern mask of G component according to the source color format [7:0] OSDBKYM For color-key pattern mask of B component according to the source color format

300 -

6.10.3.7 LCD Timing Generation

LCD Timing Control 1 Register (LCDTCON1) REGISTER ADDRESS R/W 0xFFF0_80B0 R/W LCD Timing Control 1 0x0000_0000 Reserved HSPW[9:4] HSPW[3:0] HBPD[9:6] HBPD[5:0] HFPD[9:8] HFPD[7:0] BITS DESCRIPTIONS [31:30] Reserved Reserved [29:20] HSPW Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. [19:10] HBPD Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. [9:0] HFPD Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. LCD Timing Control 2 Register (LCDTCON2) REGISTER ADDRESS R/W 0xFFF0_80B4 R/W LCD Timing Control 2 0x0000_0000

Publication Release Date: September 19, 2006 - 301 - Revision B2 PPL[15:8] PPL[7:0] LPP[15:8] LPP[7:0] BITS DESCRIPTIONS [31:16] PPL Pixel Per-Line The PPL bit field specifies the number of pixels in each line or row of screen. [15:0] LPP Lines Per-Panel The LPP bit field specifies the number of active lines per screen. LCD Timing Control 3 Register (LCDTCON3) REGISTER ADDRESS R/W 0xFFF0_80B8 R/W LCD Timing Control Register 3 0x0000_0000 Reserved VSPW[9:4] VSPW[3:0] VBPD[9:6] VBPD[5:0] VFPD[9:8] VFPD[7:0]

302 - BITS DESCRIPTIONS [31:30] Reserved Reserved [29:20] VSPW Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. [19:10] VBPD Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. [9:0] VFPD Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. LCD Timing Control 4 Register (LCDTCON4) REGISTER ADDRESS R/W

0xFFF0_80BC R/W LCD Timing Control 4 0x0000_0000 Reserved PCD[9:7] PCD[6:0] Reserved Reserved PLLRDY LCDPRESC CLKSEL BITS DESCRIPTIONS [31:27] Reserved Reserved [26:17] PCD The ten-bit PCD field is used to derive the LCD panel clock frequency VCLK from LCD controller clock: VCLK=LCDCLK/(PCD+2) [16:9] Reserved Reserved [8] PLLRDY Indicate LCDC that PLL is ready, can switch pixel clock source to PLL clock [7:1] LCDPRESC These bits pre-scale counter the LCD controller clock Scale_CLK = PLL_FIN / ( 2*( LCDPRESC + 1 ) ) [0] CLKSEL This bit driver the LCD controller clock source. 0 = external PLL clock 1 = AHB Bus clock

Publication Release Date: September 19, 2006 - 303 - Revision B2 LCD Timing Control 5 Register (LCDTCON5) REGISTER ADDRESS R/W LCDTCON5 0xFFF0_80C0 R/W LCD Timing Control 5 0x0000_0000 Reserved Reserved ACBF Reserved Reserved MMODE INVVCLK INVHSYN INVVSYN INVVDEN BITS DESCRIPTIONS [31:21] Reserved Reserved [20:16] ACBF Determine the toggle rate of the VDEN AC bias pin).The AC bias pin frequency is only applicable to STN display. Program this field with the number of line clocks between each toggle. [15:5] Reserved Reserved [4] MMODE Determine the toggle rate of the VDEN 0 = Each Frame 1 = The rate defined by the ACBF. [3] INVVCLK This bit controls the polarity of the VCLK active edge. 0 = Panel signal is transit at VCLK rising edge 1 = Panel signal is transit at VCLK falling edge [2] INVHSYNC This bit indicates the HSYNC pulse polarity. 0 = Normal 1 = Inverted [1] INVVSYNC This bit indicates the VSYNC pulse polarity. 0 = Normal 1 = Inverted [0] INVVDEN This bit indicates the VDEN signal polarity. 0 = Normal 1 = Inverted

304 - LCD Timing Control 6 Register (LCDTCON6) REGISTER ADDRESS R/W

0xFFF0_80C4 R LCD Timing Control 6 0x0000_0000 PPLCURENT[15:8] PPLCURENT[7:0] LPPCURENT[15:8] LPPCURENT[7;0] BITS DESCRIPTIONS [31:16] PPLCURENT Pixel number which LCD Controller is outputting to LCD Panel [15:0] LPPCURENT Line number which LCD Controller is outputting to LCD Panel

Publication Release Date: September 19, 2006 - 305 - Revision B2

306 -

6.10.3.8 Palette SRAM Build In Self-Test

Lookup Table SRAM Build In Self Test Register (BIST) REGISTER ADDRESS R/W 0xFFF0_80D0 R/W Lookup Table SRAM Build In Self Test 0x0000_0000 Reserved Reserved Reserved Reserved FAIL FINISH BISTEN BITS DESCRIPTIONS [31:3] Reserved Reserved [2] FAIL BIST Fail indicator 0 = SRAM BIST not fail 1 = SRAM BIST fail [1] FINISH BIST Finish Status (Read Only) 0 = When BIST enabled, this value means BIST not finished 1 = When BIST enabled, this value means BIST finished, and FAIL can be referenced [0] BISTEN BIST Mode Enable 0 = SRAM is in normal operation. 1 = BIST enabled, SRAM is under BIST test

Publication Release Date: September 19, 2006 - 307 - Revision B2

6.11 Audio Controller

The audio controller consists of IIS/AC-link protocol to interface with external audio CODEC. One 8-level deep FIFO for read path and write path and each level has 32-bit width (16 bits for right channel and 16 bits for left channel). One DMA controller handles the data movement between FIFO and memory. The following are the property of the DMA. Always 8-beat incrementing burst Always bus lock when 8-beat incrementing burst When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically An AHB master port and an AHB slave port are offered in audio controller.

6.11.1 IIS Interface

The IIS interface signals are shown as figure 6.11.2.1 Figure 6.11.2.1 The interface signal of IIS The 16 bits IIS and MSB-justified format are support, the timing diagram is shown as Figure 6.11.2.2 Audio Controller Audio Codec MCLK BCLK LRCLK DOUT DIN

308 - L R C L K B C K D A T A L e ft R ig h t M S B B 2 L S B M S B I2 S b u s L R C L K B C K D A T A L e ft R ig h t B 2 B 3 M S B B 2 M S B – J u stifie d fo r m a t M S B L S B Figure 6.11.2.2 The format of IIS The sampling rate, bit shift clock frequency could be set by the control register ACTL_IISCON.

6.11.2 AC97 Interface

The AC97 interface, called AC-link is supported. For input and output direction, each frame contains a Tag slot and 12 data slots. However, in the 12 data slots, only 4 slots are used in W90P710, other 8 slots are not supported, and the control data and audio data are transferred in the 4 valid slots. Each slot contains 20 bits data. The interface signals are shown as Figure 6.11.2.1 Figure 6.11.2.1 The interface signal of AC-link Audio Controller Audio Codec SYNC BCLK DIN DOUT RESETB

Publication Release Date: September 19, 2006 - 309 - Revision B2 The signal format is shown as Figure 6.11.2.2 Figure 6.11.2.2 The signal format of AC-link The structure of output frame is shown as below: SLOT # CONTENT Tag CMD ADDR CMD DATA PCM LEFT PCM RIGHT Unused BITS 15-0 19-0 19-0 19-0 19-0 159 - 0 PHASE Tag phase Data phase The output frame data format is shown as following: SLOT # BIT Frame validity bit, 1 is valid, 0 is invalid. 14 - 3 Slot validity, but in W90P710, only bits 6-3 are used, bits 14-7 are unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot 2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared to 0. Tag (slot 0) 2 - 0 This field should be cleared to 0. 19 - 4 Control register write data. It should be cleared to 0 if current operation is read. CMD DATA (slot 2) 3 - 0 This field should be cleared to 0 SYNC BCLK DIN DOUT Tag phase Data phase Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 –12 Frame (48 KHz)

12.288 MHz

310 - Continued. SLOT # BIT

PCM playback data for left channel PCM LEFT (slot 3) 3 - 0 This field should be cleared to 0 19 - 4 PCM playback data for right channel PCM RIGHT (slot 4) 3 - 0 This field should be cleared to 0 The structure of input frame is shown as below: Slot # Content Tag status ADDR status DATA PCM LEFT PCM RIGHT Unused Bits 0-15 19-0 19-0 19-0 19-0 159 - 0 The input frame data format is shown as following: SLOT # BIT Frame validity bit, 1 is valid, 0 is invalid. 14 - 3 Slot validity, but in W90P710, only bits 6-3 are used, bits 14-7 are unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot 2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared to 0. Tag (slot 0) 2 - 0 This field should be cleared to 0. This bit should be cleared to 0 18-12 Control register address echo which previous frame requested PCM data for left channel request, it should be always 0 when VRA=0 (VRA: Variable Rate Audio mode). PCM data for right channel request (Same as Bit 11). Status ADDR (slot 1) 9 - 0 This field should be cleared to 0 19 - 4 Control register read data which previous frame requested. It should be cleared to 0 if this slot is invalid. Status DATA (slot 2) 3 - 0 This field should be cleared to 0 19 - 4 PCM record data for left channel PCM LEFT (slot 3) 3 - 0 This field should be cleared to 0 19 - 4 PCM record data for right channel PCM RIGHT (slot 4) 3 -0 This field should be cleared to 0

Publication Release Date: September 19, 2006 - 311 - Revision B2

6.11.3 Audio Controller Register Map

R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER ADDRESS R/W ACTL_CON 0xFFF0_9000 R/W Audio controller control register 0x0000_0000 ACTL_RESET 0xFFF0_9004 R/W Sub block reset control register 0x0000_0000 ACTL_RDSTB 0xFFF0_9008 R/W DMA destination base address register for record 0x0000_0000 ACTL_RDST_LENGTH 0xFFF0_900C R/W DMA destination length register for record 0x0000_0000 ACTL_RDSTC 0xFFF0_9010 R DMA destination current address register for record 0x0000_0000 ACTL_RSR 0xFFF0_9014 R/W Record status register 0x0000_0000 ACTL_PDSTB 0xFFF0_9018 R/W DMA destination base address register for play 0x0000_0000 ACTL_PDST_LENGTH 0xFFF0_901C R/W DMA destination length register for play 0x0000_0000 ACTL_PDSTC 0xFFF0_9020 R DMA destination current address register for play 0x0000_0000 ACTL_PSR 0xFFF0_9024 R/W Play status register 0x0000_0004 ACTL_IISCON 0xFFF0_9028 R/W IIS control register 0x0000_0000 ACTL_ACCON 0xFFF0_902C R/W AC-link control register 0x0000_0000 ACTL_ACOS0 0xFFF0_9030 R/W AC-link out slot 0 0x0000_0000 ACTL_ACOS1 0xFFF0_9034 R/W AC-link out slot 1 0x0000_0080 ACTL_ACOS2 0xFFF0_9038 R/W AC-link out slot 2 0x0000_0000 ACTL_ACIS0 0xFFF0_903C R AC-link in slot 0 0x0000_0000 ACTL_ACIS1 0xFFF0_9040 R AC-link in slot 1 0x0000_0000 ACTL_ACIS2 0xFFF0_9044 R AC-link in slot 2 0x0000_0000 Audio controller control registers (ACTL_CON) REGISTER ADDRESS R/W ACTL_CON 0xFFF0_9000 R/W Audio controller control register 0x0000_0000 The ACTL_CON register control the basic operation of audio controller.

312 - BITS DESCRIPTIONS [15] Reserved [14] Reserved [13] Reserved [12] R_DMA_IRQ When recording, when the DMA destination current address reach the DMA destination end address or middle address, the R_DMA_IRQ bit will be set to 1 automatically, and this bit could be cleared to 0 by CPU. The bit is hardwired to ARM as interrupt request signal with an inverter. The R_DMA_IRQ bit is read/write (write 1 to clear) [11] T_DMA_IRQ Transmit DMA interrupt request bit. When DMA current address reach the middle address (((ACTL_DESE – ACTL_DESB)-1)/2 + ACTL_DESB) or reach the end address ACTL_DESB, the bit T_DMA_IRQ will be set to 1, and this bit could be clear to 0 by write “1” by CPU. And the bit is hardwired to ARM as interrupt request signal with an inverter. The T_DMA_IRQ bit is read/write (write 1 to clear). [8] IIS_AC_PIN_SEL IIS or AC-link pin selection
If IIS_AC_PIN_SEL = 0, the pins select IIS
If IIS_AC_PIN_SEL = 1, the pins select AC-link The IIS_AC_PIN_SEL bis is read/write [7] FIFO_TH FIFO threshold control bit
If FIFO_TH=0, the FIFO threshold is 8 level
If FIFO_TH=1, the FIFO threshold is 4 level The FIFO_TH bit is read/write [6] Reserved Reserved Reserved Reserved R_DMA_IRQ T_DMA_IRQ Reserved IIS_AC_PIN_ SEL FIFO_TH Reserved Reserved BLOCK_EN[1:0] Reserved

Publication Release Date: September 19, 2006 - 313 - Revision B2 Continued. BITS DESCRIPTIONS [2:1] BLOCK_EN[1:0] Audio interface type selection

If BLOCK_EN[0]=0/1, IIS interface is disable/enable
If BLOCK_EN[1]=0/1, AC-link interface is disable/enable The BLOCK_EN[1:0] bits are read/write [0] Reserved Sub-block reset control register (ACTL_RESET) REGISTER ADDRESS R/W

ACTL_RESET 0xFFF0_9004 R/W Sub block reset control 0x0000_0000 The value in ACTL_RESET register control the reset operation in each sub block. BITS DESCRIPTIONS [31:17] Reserved [16] ACTL_RESET Audio controller reset control bit 1 = the whole audio controller is reset 0 = the audio controller is normal operation The ACTL_RESET bit is read/write [15:14] RECORD_SINGLE [1:0] record single/dual channel select bits 2’b11= the record is dual channel 2’b01= the record only select left channel 2’b10= the record only select right channel 2’b00 is reserved Note that, when ADC is selected as record path, it only support left channel record. The PLAY_SINGLE[1:0] bits are read/write ACTL_RESET RECORD_SINGLE[1:0] PLAY_SINGLE[1:0] Reserved AC_RECORD AC_PLAY IIS_RECORD IIS_PLAY Reserved AC_RESET IIS_RESET

314 - Continued. BITS DESCRIPTIONS [13:12] PLAY_SINGLE [1:0] Playback single/dual channel select bits PLAY_SINGLE[1:0]=11, the playback is in stereo mode PLAY_SINGLE[1:0]=10, the playback is in mono mode PLAY_SINGLE[1:0]= 00 & 01 is reserved The PLAY_SINGLE[1:0] bits are read/write [8] AC_RECORD AC link record control bit AC_RECORD=0, the record path of AC link is disable AC_RECORD=1, the record path of AC link is enable The AC_RECORD bit is read/write [7] AC_PLAY AC link playback control bit AC_PLAY=0, the playback path of AC link is disable AC_PLAY=1, the playback path of AC link is enable The AC_PLAY bit is read/write [6] IIS_RECORD IIS record control bit IIS_RECORD=0, the record path of IIS is disable IIS_RECORD=1, the record path of IIS is enable The IIS_RECORD bit is read/write [5] IIS_PLAY IIS playback control bit IIS_PLAY=0, the playback path of IIS is disable IIS_PLAY=1, the playback path of IIS is enable The IIS_PLAY bit is read/write [1] AC_RESET AC link sub block RESET control bit AC_RESET=0, release the AC link function block from reset mode AC_RESET=1, force the AC link function block to reset mode The AC_RESET bit is read/write [0] IIS_RESET IIS sub block RESET control bit IIS_RESET=0, release the IIS function block from reset mode IIS_RESET=1, force the IIS function block to reset mode The IIS_RESET bit is read/write DMA record destination base address (ACTL_RDSTB) REGISTER ADDRESS R/W

ACTL_RDSTB 0xFFF0_9008 R/W DMA record destination base address 0x0000_0000 The value in ACTL_RDSTB register is the record destination base address of DMA, and only could be changed by CPU.

Publication Release Date: September 19, 2006 - 315 - Revision B2 BITS DESCRIPTIONS [31:0] AUDIO_RDSTB[31:0] 32-bit record destination base address The AUDIO_RDSTB[31:0] bits is read/write. DMA destination end address (ACTL_RDST_LENGTH) REGISTER ADDRESS R/W ACTL_RDST_LENGTH 0xFFF0_900C R/W DMA record destination address length 0x0000_0000 The value in ACTL_RDST_LENGTH register is the record destination address length of DMA, and the register could only be changed by CPU. AUDIO_RDSTB[31:24] AUDIO_RDSTB[23:16] AUDIO_RDSTB[15:8] AUDIO_RDSTB[7:0] AUDIO_RDST_L[31:24] AUDIO_RDST_L[23:16] AUDIO_RDST_L[15:8] AUDIO_RDST_L[7:0]

316 - BITS DESCRIPTIONS [31:0] AUDIO_RDST_L[31:0] 32-bit record destination address length The AUDIO_RDST_L[31:0] bits is read/write. DMA destination current address (ACTL_RDSTC) REGISTER ADDRESS R/W

ACTL_RDSTC 0xFFF0_9010 RO DMA record destination current address 0x0000_0000 The value in ACTL_RDSTC is the DMA record destination current address, this register could only be read by CPU. BITS DESCRIPTIONS [31:0] AUDIO_RDSTC[31:0] 32-bit record destination current address The AUDIO_RDSTC[31:0] bits is read only. Audio controller record status register (ACTL_RSR) REGISTER ADDRESS R/W ACTL_RSR 0xFFF0_9014 R/W Audio controller FIFO and DMA status register for record 0x0000_0000 AUDIO_RDSTC[31:24] AUDIO_RDSTC[23:16] AUDIO_RDSTC[15:8] AUDIO_RDSTC[7:0]

Publication Release Date: September 19, 2006 - 317 - Revision B2 BITS DESCRIPTIONS [31:3] Reserved [2] R_FIFO_FULL Record FIFO full indicator bit R_FIFO_FULL=0, the record FIFO not full R_FIFO_FULL=1, the record FIFO is full The R_FIFO_READY bit is read only [1] R_DMA_END_IRQ DMA end address interrupt request bit for record R_DMA_END_IRQ=0, means record DMA address does not reach the end address R_DMA_END_IRQ=1, means record DMA address reach the end address The R_DMA_END_IRQ bit is readable, and only can be clear by write “1” to this bit [0] R_DMA_MIDDLE _IRQ DMA address interrupt request bit for record R_DMA_MIDDLE_IRQ=0, means record DMA address does not reach the middle address R_DMA_MIDDLE_IRQ=1, means record DMA address reach the middle address The R_DMA_MIDDLE_IRQ bit is readable, and only can be clear by write “1” to this bit DMA play destination base address (ACTL_PDSTB) REGISTER ADDRESS R/W ACTL_PDSTB 0xFFF0_9018 R/W DMA play destination base address 0x0000_0000 The value in ACTL_PDSTB register is the play destination base address of DMA, and only could be changed by CPU. Reserved Reserved Reserved Reserved R_FIFO_FULL R_DMA_END_IRQ R_DMA_MIDDLE_IRQ

318 - BITS DESCRIPTIONS [31:0] AUDIO_PDSTB[31:0] 32-bit play destination base address The AUDIO_PDSTB[31:0] bits is read/write. DMA destination end address (ACTL_PDST_LENGTH) REGISTER ADDRESS R/W

ACTL_PDST_LENGTH 0xFFF0_901C R/W DMA play destination address length 0x0000_0000 The value in ACTL_PDST_LENGTH register is the play destination address length of DMA, and the register could only be changed by CPU. AUDIO_PDSTB[31:24] AUDIO_PDSTB[23:16] AUDIO_PDSTB[15:8] AUDIO_PDSTB[7:0] AUDIO_PDST_L[31:24] AUDIO_PDST_L[23:16] AUDIO_PDST_L[15:8] AUDIO_PDST_L[7:0]

Publication Release Date: September 19, 2006 - 319 - Revision B2 BITS DESCRIPTIONS [31:0] AUDIO_PDST_L[31:0] 32-bit play destination address length The AUDIO_PDST_L[31:0] bits is read/write. DMA destination current address (ACTL_PDSTC) REGISTER ADDRESS R/W ACTL_PDSTC 0xFFF0_9020 RO DMA play destination current address 0x0000_0000 The value in ACTL_PDSTC is the DMA play destination current address, this register could only be read by CPU. BITS DESCRIPTIONS [31:0] AUDIO_PDSTC[31:0] 32-bit play destination current address The AUDIO_PDSTC[31:0] bits is read/write. Audio controller playback status register (ACTL_PSR) REGISTER ADDRESS R/W ACTL_PSR 0xFFF0_9024 R/W Audio controller FIFO and DMA status register for playback 0x0000_0004 AUDIO_PDSTC[31:24] AUDIO_PDSTC[23:16] AUDIO_PDSTC[15:8] AUDIO_PDSTC[7:0]

320 - BITS DESCRIPTIONS [31:3] Reserved [2] P_FIFO_EMPTY Playback FIFO empty indicator bit P_FIFO_EMPTY=0, the playback FIFO is not empty P_FIFO_EMPTY=1, the playback FIFO is empty The P_FIFO_EMPTY bit is read only [1] P_DMA_END_IRQ DMA end address interrupt request bit for playback P_DMA_END_IRQ=0, means playback DMA address does not reach the end address P_DMA_END_IRQ=1, means playback DMA address reach the end address The P_DMA_END_IRQ bit is readable, and only can be clear by write “1” to this bit [0] P_DMA_MIDDLE _IRQ DMA address interrupt request bit for playback P_DMA_MIDDLE_IRQ=0, means playback DMA address does not reach the middle address P_DMA_MIDDLE_IRQ=1, means playback DMA address reach the middle address The P_DMA_MIDDLE_IRQ bit is readable, and only can be clear by write “1” to this bit IIS control register (ACTL_IISCON) REGISTER ADDRESS R/W

ACTL_IISCON 0xFFF0_9028 R/W IIS control register 0x0000_0000 Reserved Reserved Reserved Reserved P_FIFO_EMPTY P_DMA_END_IRQ P_DMA_MIDDLE _IRQ

Publication Release Date: September 19, 2006 - 321 - Revision B2 The ACTL_IISCON is the IIS basic operation control register. BITS DESCRIPTIONS [31:20] Reserved [19:16] PRS[3:0] IIS frequency pre-scaler selection bits. (FPLL is the input PLL frequency, MCLK is the output main clock) PSR[3:0]=0000, MCLK=FPLL/1 PSR[3:0]=0001, MCLK=FPLL/2 PSR[3:0]=0010, MCLK=FPLL/3 PSR[3:0]=0011, MCLK=FPLL/4 PSR[3:0]=0100, MCLK=FPLL/5 PSR[3:0]=0101, MCLK=FPLL/6 PSR[3:0]=0110, MCLK=FPLL/7 PSR[3:0]=0111, MCLK=FPLL/8 PSR[3:0]=1000, reserved PSR[3:0]=1001, MCLK=FPLL/10 PSR[3:0]=1010, reserved PSR[3:0]=1011, MCLK=FPLL/12 PSR[3:0]=1100, reserved PSR[3:0]=1101, MCLK=FPLL/14 PSR[3:0]=1110, reserved PSR[3:0]=1111, MCLK=FPLL/16 (when the division factor is 3/5/7, the duty cycle of MCLK is not 50%, the high duration is 0.5*FPLL) The PSR[3:0] bits are read/write Reserved Reserved PRS[3:0] Reserved BCLK_SEL[1:0] FS_SEL MCLK_SEL FORMAT Reserved

322 - Continued BITS DESCRIPTIONS [7:6] BCLK_SEL [1:0] IIS serial data clock frequency selection bit BCLK_SEL[1:0]=00, 32fs is selected (fs is sampling rate), when FS_SEL=0, the frequency of bit clock is MCLK/8, when FS_SEL=1, the frequency of bit clock is MCLK/12. BCLK_SEL[1:0]=01, 48fs is selected (only when FS_SEL=1, this term could be selection), when FS_SEL=1, the frequency of bit clock is MCLK/8. The BCLK_SEL[1:0] bits are read/write [5] FS_SEL IIS sampling frequency selection bit FS_SEL=0, FMCLK/256 is selected (FMCLK is the frequency of signal MCLK) FS_SEL=1, FMCLK/384 is selected The FS_SEL bit is read/write [4] MCLK_SEL IIS MCLK output selection bit MCLK_SEL=0, IIS MCLK output will follow the PRS[3:0] setting. MCLK_SEL=1, IIS MCLK output will be the same with FPLL. The MCLK_SEL bit is read/write [3] FORMAT IIS format selection bits FORMAT=0, IIS compatible format is selected FORMAT=1, MSB-justified format is selected The FORMAT bit is read/write [2:0] Reserved AC-link Control Register (ACTL_ACCON) REGISTER ADDRESS R/W

ACTL_ACCON 0xFFF0_902C R/W AC-link control register 0x0000_0000 The ACTL_ACCON register is the AC-link basic operation control register.

Publication Release Date: September 19, 2006 - 323 - Revision B2 BITS DESCRIPTIONS [6] Reserved [5] AC_BCLK_PU_EN This bit controls the AC_BCLK pin pull-high resister. AC_BCLK_PU_EN=0, the AC_BCLK pin pull-high resister will be disabled AC_BCLK_PU_EN=1, the AC_BCLK pin pull-high resister will be enabled The AC_BCLK_PU_EN bit is read/write. [4] AC_R_FINISH AC-link read data ready bit. When read data indexed by previous frame is shifted into ACTL_ACIS2, the AC_R_FINISH bit will be set to 1 automatically. After CPU read out the read data, AC_R_FINISH bit will be cleared to 0. AC_R_FINISH=0, read data buffer has been read by CPU AC_R_FINISH=1, read data buffer is ready for CPU read The AC_R_FINISH bit is read only [3] AC_W_FINISH AC-link write frame finish bit. When writing data to register ACTL_ACOS0, the AC_W_FINISH bit will be set to 1 automatically. After AC-link interface shift out the register ACTL_ACOS0, the AC_W_FINISH bit will be cleared to 0. AC_W_FINISH=0, AC-link control data out buffer has been shifted out to codec by CPU and data out buffer is empty. AC_W_FINISH=1, AC-link control data out buffer is ready to be shifted out(After users have wrote data into register ACTL_ACOS0) The AC_W_FINISH bit is read only Reserved Reserved Reserved Reserved AC_BCLK_ PU_EN AC_R_FINI SH AC_W_FINI SH AC_W_RE S AC_C_RES Reserved

324 - Continued. BITS DESCRIPTIONS [2] AC_W_RES AC-link warm reset control bit, when this bit is set to 1, (AC-link begin warn reset procedure, after warn reset procedure finished, this bit will be cleared automatically) the interface signal AC_SYNC is high, when this bit is set to 0, the interface signal AC_SYNC is controlled by AC_BCLK input when this bit is set to 1. Note the AC-link spec. shows it need at least 10 us high duration of AC_SYNC to warn reset AC97. AC_W_RES=0, AC_SYNC pin is controlled by AC_BCLK input pin AC_W_RES=1, AC_SYNC pin is forced to high The AC_W_RES bit is read/write [1] AC_C_RES AC-link cold reset control bit, when this bit is set to 1, the interface signal AC_RESETB is low, when this bit is set to 0, the signal AC_RESETB is high. Note the AC-link spec. shows it need at least 10 us low duration of AC_RESETB to cold reset AC97. AC_C_RES=0, AC_RESETB pin is set to 1 AC_C_RES=1, AC_RESETB pin is set to 0 The AC_C_RES bit is read/write [0] Reserved AC-link output slot 0 (ACTL_ACOS0) REGISTER ADDRESS R/W

ACTL_ACOS0 0xFFF0_9030 R/W AC-link out slot 0 0x0000_0000 The ACTL_ACOS0 register store the slot 0 value to be shift out by AC-link. Note that write data to ACTL_ACOS0 register when AC_W_FINISH bit (ACTL_ACCON[3]) is set is invalid. Therefore, check AC_W_FINISH bit status before write data into ACTL_ACOS0 register. Reserved Reserved Reserved Reserved VALID_ FRAME SLOT_VALID[3:0]

Publication Release Date: September 19, 2006 - 325 - Revision B2 BITS DESCRIPTIONS [31:5] Reserved [4] VALID_FRAME Frame valid indicated bits VALID_FRAME=1, any one of slot is valid VALID_FRAME=0, no any slot is valid The VALID_FRAME bits are read/write [3:0] SLOT_VALID [3:0] Slot valid indicated bits SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid The SLOT_VALID[3:0] bits are read/write The AC-link output slot 1 (ACTL_ACOS1) REGISTER ADDRESS R/W ACTL_ACOS1 0xFFF0_9034 R/W AC-link out slot 1 0x0000_0080 The ACTL_ACOS1 register store the slot 1 value to be shift out by AC-link. Reserved Reserved Reserved R_WB R_INDEX[6:0]

326 - BITS DESCRIPTIONS [31:8] Reserved [7] R_WB Read/Write select bit R_WB=1, a read specified by R_INDEX[6:0] will occur, and the data will appear in next frame R_WB=0, a write specified by R_INDEX[6:0] will occur, and the write data is put at out slot 2 The R_WB bit is read/write [6:0] R_INDEX[6:0] External AC97 CODEC control register index (address) bits The R_INDEX[6:0] bits are read/write AC-link output slot 2 (ACTL_ACOS2) REGISTER ADDRESS R/W

ACTL_ACOS2 0xFFF0_9038 R/W AC-link out slot 2 0x0000_0000 The ACTL_ACOS2 register store the slot 2 value to be shift out by AC-link. BITS DESCRIPTIONS [31:0] Reserved [15:0] WD[15:0] AC-link write data The WD[15:0] bits are read/write Reserved Reserved WD[15:8] WD[7:0]

Publication Release Date: September 19, 2006 - 327 - Revision B2 AC-link input slot 0 (ACTL_ACIS0) REGISTER ADDRESS R/W ACTL_ACIS0 0xFFF0_903C R AC-link in slot 0 0x0000_0000 The ACTL_ACIS0 store the shift in slot 0 data of AC-link. BITS DESCRIPTIONS [31:5] Reserved [4] CODEC_READY External AC97 audio CODEC ready bit CODEC_READY=0, indicate external AC97 audio CODEC is not ready CODEC_READY=1, indicate external AC97 audio CODEC is ready The CODEC_READY bit is read only [3:0] SLOT_VALID[3:0] Slot valid indicated bits SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid The SLOT_VALID[3:0] bits are read Reserved Reserved Reserved Reserved CODEC_READY SLOT_VALID[3:0]

328 - AC-link input slot 1 (ACTL_ACIS1) REGISTER ADDRESS R/W

ACTL_ACIS1 0xFFF0_9040 R AC-link in slot 1 0x0000_0000 The ACTL_ACIS1 stores the shift in slot 1 data of AC-link. BITS DESCRIPTIONS [31:9] Reserved [8:2] R_INDEX[6:0] Register index. The R_INDEX[6:0] echo the register index (address) when a register read has been requested in the previous frame. The R_INDEX[6:0] bits are read only [1:0] SLOT_REQ[1:0] Slot request. The bits indicate if the external codec need new PCM data that will transfer in next frame. Any bit in SLOT_REQ[1:0] is set to 1, indicate external codec does not need a new sample in the corresponding slot[3:4] of the next frame Any SLOT_REQ[1:0] is clear to 0, indicate external codec need a new sample in the corresponding slot[3:4] of the next frame The SLOT_REQ[1:0] bits are read only Reserved Reserved Reserved R_INDEX[6] R_INDEX[5:0] SLOT_REQ[1:0]

Publication Release Date: September 19, 2006 - 329 - Revision B2 AC-link input slot 2 (ACTL_ACIS2) REGISTER ADDRESS R/W ACTL_ACIS2 0xFFF0_9044 R AC-link in slot 2 0x0000_0000 The ACTL_ACIS2 stores the shift in slot 2 data of AC-link. BITS DESCRIPTIONS [31:16] Reserved [15:0] RD[15:0] AC-link read data. The RD[15:0] bits are read only Reserved Reserved RD[15:8] RD[7:0]

330 -

6.12 Universal Asynchronous Receiver/Transmitter Controller

Asynchronous serial communication block include 4 UART blocks and accessory logic. They can be described as follow: UART0 It is merely a general purpose UART. It does not include any accessory function. Clock Source : 15MHz UART Type : general UART, FIFO Number : 16-byte receiving FIFO and 16 byte transmitting FIFO Modem Function : N/A Accessory Function : N/A UART1 It is designed for general purpose UART or Bluetooth transceiver. It includes a high speed UART block with 64-byte receiving FIFO and 64-byte transmitting FIFO. It includes 3 clock sources: 15M, 30M, and 43.6M. Programmer can feel free to choose the clock source and divisor number for suitable baud rate. Clock Source : 15MHz from external crystal 30M, 43.6M, 48M, 60M (optional function for Bluetooth HCI transport layer) UAR Type : high speed UART, FIFO Number : 64-byte receiving FIFO and 64 byte transmitting FIFO Modem Function : CTS and RTS (optional for Bluetooth. If they were enabled, TX & RX in UART2 will be cut off) Accessory Function : Bluetooth (optional) Baud Rate (max) : 1.875MHz I/O pin : TXD1, RXD1, RTS, CTS (optional) UART2 It is designed for general purpose UART or IrDA SIR. The part of UART includes 16-byte receiving FIFO and 16-byte transmitting FIFO. The UART has not modem function. The U3 block has merely 2 I/O. TXD2/RXD2 of UART2 occupy the same pins with RTS and CTS of UART1. Once the Bluetooth function has been enabled, UART2 should be disabled. Clock Source : 15MHz UART Type : general UART, FIFO Number : 16-byte receiving FIFO and 16 byte transmitting FIFO Modem Function : N/A

Publication Release Date: September 19, 2006 - 331 - Revision B2 Accessory Function : IrDA SIR (optional) I/O Pin : TXD2, RXD2. I/O Pin Share with : UART1 (Bluetooth function) UART3 It is also merely a general purpose UART. It does not include any accessory function. It share four I/O pins with AC97/I2S. Clock Source : 15MHz UART Type : general UART, FIFO Number : 16-byte receiving FIFO and 16 byte transmitting FIFO Modem Function : DTR, DSR Accessory Function : N/A I/O Pin : TXD3, RXD3, DTR, DSR I/O Pin Share with : AC97_DATAO, AC97_DATAI, AC97_SYNC, AC97_BITCLK Table 6.12.1 W90P710 UART features list BLOCK NUMBER UART TYPE CLOCK SOURCE MODEM FUNCTION SIGNALS IO PINS DESIGN TARGET General UART 15M N/A TxD0, RXD0 General UART High speed UART 15M, 30M, 43.6M, 48M, 60M CTS, RTS TXD1, RXD1, CTS1, RTS1 General UART/ Bluetooth General UART 15M N/A TX2, RX2 General UART/IrDA SIR General UART 15M DTR, DSR TXD3, RXD3, DRT3, DSR3 General UART

332 -

6.12.1 UART0

UART0 is a general UART block. It has not Modem I/O signals. More detail function description, please refer to section 7.12.5 General UARTcontroller description Table 6.12.1.1 UART0 Register Map REGISTER ADDRESS R/W OTHER CONDITION RESET VALUE UART0_RBR 0xFFF8_0000 R DLAB=0 Undefined UART0_THR 0xFFF8_0000 W DLAB=0 Undefined UART0_IER 0xFFF8_0004 R/W DLAB=0 0x0000_0000 UART0_DLL 0xFFF8_0000 R/W DLAB=1 0x0000_0000 UART0_DLM 0xFFF8_0004 R/W DLAB=1 0x0000_0000 UART0_IIR 0xFFF8_0008 R 0x8181_8181 UART0_FCR 0xFFF8_0008 W Undefined UART0_LCR 0xFFF8_000c R/W 0x0000_0000 Reserved 0xFFF8_0010 UART0_LSR 0xFFF8_0014 R 0x6060_6060 Reserved 0xFFF8_0018 UART0_TOR 0xFFF8_001c R/W 0x0000_0000

6.12.2 UART1

The UART1 is designed for general purpose UART or Bluetooth HCI transport layer. It is a high speed UART with 64-byte receive FIFO and 64-byte transmit FIFO. To perform 1.875MHz maximum baud rate, UART1 has 5 clock sources, 15M, 30M, 43.6M, 48M, and 60M. The first one is from external 15M crystal clock and the other are divided from system PLL 480MHz output. More detail about high speed UART, please refer to next section 7.12.6 High Speed UART controller function description. The block UART1 offer 4 I/O signals, TX, RX, CTS, and RTS. CTS and RTS are used as flow control for Bluetooth. CTS and RTS share the same I/O pins with TX and RX in block UART2.

Publication Release Date: September 19, 2006 - 333 - Revision B2 Table 6.12.2.1 UART1 Register Map REGISTER ADDRESS R/W OTHER CONDITION RESET VALUE UART1_RBR 0xFFF8_0100 R DLAB=0 Undefined UART1_THR 0xFFF8_0100 W DLAB=0 Undefined UART1_IER 0xFFF8_0104 R/W DLAB=0 0x0000_0000 UART1_DLL 0xFFF8_0100 R/W DLAB=1 0x0000_0000 UART1_DLM 0xFFF8_0104 R/W DLAB=1 0x0000_0000 UART1_IIR 0xFFF8_0108 R 0x8181_8181 UART1_FCR 0xFFF8_0108 W Undefined UART1_LCR 0xFFF8_010c R/W 0x0000_0000 UART1_MCR 0xFFF8_0110 R/W 0x0000_0000 UART1_LSR 0xFFF8_0114 R 0x6060_6060 UART1_MSR 0xFFF8_0118 R 0x0000_0000 UART1_TOR 0xFFF8_011c R/W 0x0000_0000 UART1_UBCR 0xFFF8_0120 R/W 0x0000_0000 UART1 Bluetooth Control Register (UART1_UBCR) REGISTER ADDRESS R/W UART1_UBCR 0xFFF8_0120 R/W UART 1 Bluetooth Control Register 0x0000_0000 Reserved Reserved Reserved Reserved UBCR[2:0]

334 - BITS DESCRIPTIONS [31:3] Reserved [2:0] UBCR UBCR is a 3 bits register which is used to select clock source to generate suitable baud rate: 000: 15Mhz from external crystal 100: 30Mhz divided from PLL 480Mhz 101: 43.6Mhz divided from PLL 480Mhz 110: 48Mhz divided from PLL 480Mhz 111: 60Mhz divided from PLL 480Mhz

6.12.3 UART2

UART2 contains 2 features: general UART and IrDA SIR decoder/encoder. UART has not modem function. Please read the spec of section 7.12.5 General UART controller function description. The IrDA SIR is described as follow: Table 6.12.3.1 UART2 Register Map Register Address R/W Other condition Reset value UART2_RBR 0xFFF8_0200 R DLAB=0 Undefined UART2_THR 0xFFF8_0200 W DLAB=0 Undefined UART2_IER 0xFFF8_0204 R/W DLAB=0 0x0000_0000 UART2_DLL 0xFFF8_0200 R/W DLAB=1 0x0000_0000 UART2_DLM 0xFFF8_0204 R/W DLAB=1 0x0000_0000 UART2_IIR 0xFFF8_0208 R 0x8181_8181 UART2_FCR 0xFFF8_0208 W Undefined UART2_LCR 0xFFF8_020c R/W 0x0000_0000 Reserved 0xFFF8_0210 Undefined UART2_LSR 0xFFF8_0214 R 0x6060_6060 Reserved 0xFFF8_0218 Undefined UART2_TOR 0xFFF8_021c R/W 0x0000_0000 UART2_IRCR 0xFFF8_0220 R/W 0x0000_0040 UART2 IrDA Control Register (UART2_IRCR) REGISTER ADDRESS R/W UART2_IRCR 0xFFF8_0220 R/W UART 2 IrDA Control Register 0x0000_0040

Publication Release Date: September 19, 2006 - 335 - Revision B2 Reserved Reserved Reserved Reserved INV_RX INV_TX Reserved Reserved LB TX_SELECT IrDA_EN BITS DESCRIPTIONS [31:7] Reserved Reserved [6] INV_RX 1: Inverse RX input signal 0: No inversion [5] INV_TX 1: Inverse TX output signal 0: No inversion [4:3] Reserved Reserved [2] LB IrDA loop back mode for self test. 1: enable IrDA loop back mode 0: disable IrDA loop back mode [1] TX_SELECT 1: enable IrDA transmitter 0: enable IrDA receiver [0] IrDA_EN 1: enable IrDA block 0: disable IrDA block

336 -

6.12.4 UART3

UART3 is a general UART block. It has not Modem I/O signals. More detail general UART function description, please refer to next section 7.12.5 General UART controller. Table 6.12.4.1 UART3 register map REGISTER ADDRESS R/W OTHER CONDITION RESET VALUE UART3_RBR 0xFFF8_0300 R DLAB=0 Undefined UART3_THR 0xFFF8_0300 W DLAB=0 Undefined UART3_IER 0xFFF8_0304 R/W DLAB=0 0x0000_0000 UART3_DLL 0xFFF8_0300 R/W DLAB=1 0x0000_0000 UART3_DLM 0xFFF8_0304 R/W DLAB=1 0x0000_0000 UART3_IIR 0xFFF8_0308 R 0x8181_8181 UART3_FCR 0xFFF8_0308 W Undefined UART3_LCR 0xFFF8_030c R/W 0x0000_0000 UART3_MCR 0xFFF8_0310 R/W 0x0000_0000 UART3_LSR 0xFFF8_0314 R 0x6060_6060 UART3_MSR 0xFFF8_0318 R 0x0000_0000 UART3_TOR 0xFFF8_031c R/W 0x0000_0000 UART3 Modem Control Register (UART3_MCR) REGISTER ADDRESS R/W UART3_MCR 0xFFF8_0310 R/W UART 3 Modem Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved LBME Reserved Reserved Reserved DTR#

Publication Release Date: September 19, 2006 - 337 - Revision B2 UART3 Modem Status Register (UART3_MSR) REGISTER ADDRESS R/W UART3_MSR 0xFFF8_0318 R UART 3 Modem Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved DSR# Reserved Reserved Reserved DDSR Reserved

6.12.5 General UART Controller

The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data characters received from the peripheral such as MODEM, and a parallel-to-serial conversion on data characters received from the CPU. There are five types of interrupts, i.e., line status interrupt, transmitter FIFO empty interrupt, receiver threshold level reaching interrupt, time out interrupt, and MODEM status interrupt. One 16-byte transmitter FIFO (TX_FIFO) and one 16-byte (plus 3-bit of error data per byte) receiver FIFO (RX_FIFO) has been built in to reduce the number of interrupts presented to the CPU. The CPU can completely read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt) found. The UART includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver needed. The equation is BaudOut = crystal clock / 16 * [Divisor + 2]. The UART includes the following features: y Transmitter and receiver are buffered with a 16-byte FIFO each to reduce the number of interrupts presented to the CPU. y Subset of MODEM control functions (DSR, DTR, by IP selection) y Fully programmable serial-interface characteristics: 5-, 6-, 7-, or 8-bit character Even, odd, or no-parity bit generation and detection 1-, 1&1/2, or 2-stop bit generation Baud rate generation

338 - y Line break generation and detection y False start bit detection y Full prioritized interrupt system controls y Loop back mode for internal diagnostic testing

6.12.5.1 UART Control Registers Map

R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER OFFSET R/W UART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined UART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined UART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART_DLL 0x00 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 UART_DLM 0x04 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 UART_IIR 0x08 R Interrupt Identification Register 0x8181_8181 UART_FCR 0x08 W FIFO Control Register Undefined UART_LCR 0x0C R/W Line Control Register 0x0000_0000 UART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 UART_LSR 0x14 R Line Status Register 0x6060_6060 UART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000 UART_TOR 0x1C R/W Time Out Register 0x0000_0000 Note: Real register address = 0xFFF8_0000+ (UART number – 1) * (0x0100) + offset Note: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times before send to APB bus. For example, when ARM CPU read register UARTn_BRR, ARM CPU will get UART0_RBR = {RBR[7:0], RBR[7:0], RBR[7:0], RBR[7:0]}. UART Receive Buffer Register (UART_RBR) REGISTER OFFSET R/W UART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined

Publication Release Date: September 19, 2006 - 339 - Revision B2 Reserved Reserved Reserved 8-bit Received Data BITS DESCRIPTIONS [7:0] 8-bit Received Data By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first). UART Transmit Holding Register (UART_THR) REGISTER OFFSET R/W UART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined Reserved Reserved Reserved 8-bit Transmitted Data BITS DESCRIPTIONS [7:0] 8-bit Transmitted Data By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first).

340 - UART Interrupt Enable Register (UART_IER) REGISTER OFFSET R/W

UART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 Reserved Reserved Reserved RESERVED nDBGACK_EN MSIE RLSIE THREIE RDAIE BITS DESCRIPTIONS [31:5] Reserved [4] nDBGACK_EN ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held 1 = No matter what DBGACK is high or not, the UART receiver timer-out clock will not be held [3] MSIE MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS [2] RLSIE Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS [1] THREIE Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable 0 = Mask off Irpt_THRE 1 = Enable Irpt_THRE [0] RDAIE Receive Data Available Interrupt (Irpt_RDA) Enable and Time-out Interrupt (Irpt_TOUT) Enable 0 = Mask off Irpt_RDA and Irpt_TOUT 1 = Enable Irpt_RDA and Irpt_TOUT

Publication Release Date: September 19, 2006 - 341 - Revision B2 UART Divider Latch (Low Byte) Register (UART_DLL) REGISTER OFFSET R/W UART_DLL 0x00 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 Reserved Reserved Reserved Baud Rate Divider (Low Byte) BITS DESCRIPTIONS [7:0] Baud Rate Divider (Low Byte) The low byte of the baud rate divider UART Divisor Latch (High Byte) Register (UART_DLM) REGISTER OFFSET R/W UART_DLM 0x04 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 Reserved Reserved Reserved Baud Rate Divider (High Byte) BITS DESCRIPTIONS [7:0] Baud Rate Divider (High Byte) The high byte of the baud rate divider

342 - This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} Note: This definition is different from 16550 UART Interrupt Identification Register (UART_IIR) REGISTER OFFSET R/W

UART_IIR 0x08 R Interrupt Identification Register 0x8181_8181 Reserved Reserved Reserved FMES RFTLS DMS IID NIP BITS DESCRIPTIONS [7] FMES FIFO Mode Enable Status This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enabling, this bit always shows the logical 1 when CPU is reading this register. [6:5] RFTLS RX FIFO Threshold Level Status These bits show the current setting of receiver FIFO threshold level (RTHO). The meaning of RTHO is defined in the following FCR description. [4] DMS DMA Mode Select The DMA function is not implemented in this version. When reading IIR, the DMS is always returned 0. [3:1] IID Interrupt Identification The IID together with NIP indicates the current interrupt request from UART [0] NIP No Interrupt Pending There is no pending interrupt.

Publication Release Date: September 19, 2006 - 343 - Revision B2 Table 6.12.5.1 Interrupt Control Functions IIR [3:0] PRIORITY INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL - - - 1 None None 0110 Highest Receiver Line Status (Irpt_RLS) Overrun error, parity error, framing error, or break interrupt Reading the LSR 0100 Second Received Data Available (Irpt_RDA) Receiver FIFO threshold level is reached Receiver FIFO drops below the threshold level 1100 Second Receiver FIFO Time-out (Irpt_TOUT) Receiver FIFO is non-empty and no activities are occurred in the receiver FIFO during the TOR defined time duration Reading the RBR 0010 Third Transmitter Holing Register Empty (Irpt_THRE) Transmitter holding register empty Reading the IIR (if source of interrupt is Irpt_THRE) or writing into the THR 0000 Fourth MODEM Status (Irpt_MOS) The CTS, DSR, or DCD bits are changing state or the RI bit is changing from high to low. Reading the MSR (optional) Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550 UART FIFO Control Register (UART_FCR) REGISTER OFFSET R/W UART_FCR 0x08 W FIFO Control Register Undefined Reserved Reserved Reserved RFITL RESERVED DMS TFR RFR FME

344 - BITS DESCRIPTIONS [7:6] RFITL RX FIFO Interrupt (Irpt_RDA) Trigger Level RFITL [7:6] Irpt_RDA Trigger Level (Bytes) [3] DMS DMA Mode Select The DMA function is not implemented in this version. [2] TFR TX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. [1] RFR RX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. [0] FME FIFO Mode Enable Because UART is always operating in the FIFO mode, writing this bit has no effect while reading always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not be programmed. UART Line Control Register (UART_LCR) REGISTER OFFSET R/W

UART_LCR 0x0C R/W Line Control Register 0x0000_0000 Reserved Reserved Reserved DLAB BCB SPE EPE PBE NSB WLS

Publication Release Date: September 19, 2006 - 345 - Revision B2 BITS DESCRIPTIONS [7] DLAB Divider Latch Access Bit 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM} [6] BCB Break Control Bit When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic. [5] SPE Stick Parity Enable 0 = Disable stick parity 1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit enable) is set. [4] EPE Even Parity Enable 0 = Odd number of logic 1’s are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1’s are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set. [3] PBE Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. [2] NSB Number of “STOP bit” 0= One “ STOP bit” is generated in the transmitted data 1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word length is selected; Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected. [1:0] WLS Word Length Select WLS[1:0] Character length 5 bits 6 bits 7 bits 8 bits

346 - UART Modem Control Register (UART_MCR) REGISTER OFFSET R/W

UART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 Reserved Reserved Reserved Reserved LBME Reserve Reserve Reserved DTR# BITS DESCRIPTIONS [31:5] Reserved [4] LBME Loop-back Mode Enable 0 = Disable 1 = When the loop-back mode is enabled, the following signals are connected internally SOUT connected to SIN and SOUT pin fixed at logic 1 DTR# connected to DSR# and DTR# pin fixed at logic 1 [3:1] Reserved [0] DTR Complement version of DTR# (Data-Terminal-Ready) signal Writing 0x00 to MCR, the DTR# bit are set to logic 1’s; Writing 0x0f to MCR, the DTR# bit are reset to logic 0’s. UART Line Status Control Register (UART_LSR) REGISTER OFFSET R/W UART_LSR 0x14 R Line Status Register 0x6060_6060

Publication Release Date: September 19, 2006 - 347 - Revision B2 Reserved Reserved Reserved ERR_RX TE THRE BII FEI PEI OEI RFDR BITS DESCRIPTIONS [31:8] Reserved [7] ERR_RX RX FIFO Error 0 = RX FIFO works normally 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO. [6] TE Transmitter Empty 0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not empty. 1 = Both THR and TSR are empty. [5] THRE Transmitter Holding Register Empty 0 = THR is not empty. 1 = THR is empty. THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER [1]=1. [4] BII Break Interrupt Indicator This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU reads the contents of the LSR. [3] FEI Framing Error Indicator This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads the contents of the LSR.

348 - Continued. BITS DESCRIPTIONS [2] PEI Parity Error Indicator This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. [1] OEI Overrun Error Indicator An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads the contents of the LSR. [0] RFDR RX FIFO Data Ready 0 = RX FIFO is empty 1 = RX FIFO contains at least 1 received data word. LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR. LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt" (Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not suggested) UART Modem Status Register (UART_MSR) REGISTER OFFSET R/W

UART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000 Reserved Reserved Reserved Reserved Reserved DSR# Reserved Reserved Reserved DDSR Reserved

Publication Release Date: September 19, 2006 - 349 - Revision B2 BITS DESCRIPTIONS [31:6] Reserved [5] DSR# Complement version of data set ready (DSR#) input (This bit is selected by IP) [4:2] Reserved [1] DDSR DSR# State Change (This bit is selected by IP) This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR. [0] Reserved Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing MSR is a null operation (not suggested). UART Time Out Register (UART_TOR) REGISTER OFFSET R/W UART_TOR 0x1C R/W Time Out Register 0x0000_0000 Reserved Reserved Reserved TOIE TOIC BITS DESCRIPTIONS [31:8] Reserved [7] TOIE Time Out Interrupt Enable The feature of receiver time out interrupt is enabled when TOR [7] = IER[0] = [6:0] TOIC Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears Irpt_TOUT.

350 -

6.12.6 High speed UART Controller

The High Speed Universal Asynchronous Receiver/Transmitter (HS_UART) performs a serial-to- parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from the CPU. There are five types of interrupts, they are, transmitter FIFO empty interrupt, receiver threshold level reaching interrupt, line status interrupt (overrun error or parity error or framing error or break interrupt) ,time out interrupt, and Modem status interrupt . One 64-byte transmitter FIFO (TX_FIFO) and one 64-byte (plus 3-bit of error data per byte) receiver FIFO (RX_FIFO) has been built in to reduce the number of interrupts presented to the CPU. The CPU can completely read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt) found. The UART includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver needed. The equation is Baud Out = crystal clock / 16 * [Divisor + 2]. The UART includes the following features: y Transmitter and receiver are buffered with a 64-byte FIFO each to reduce the number of interrupts presented to the CPU. y Subset of MODEM control function(selected by IP) y Fully programmable serial-interface characteristics: 5-, 6-, 7-, or 8-bit character Even, odd, or no-parity bit generation and detection 1-, 1&1/2, or 2-stop bit generation Baud rate generation y False start bit detection y Full-prioritized interrupt system controls y Not support Loop back mode

6.12.6.1 High Speed UART Control Registers Map

R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER OFFSET R/W HSUART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined HSUART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined HSUART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 HSUART_DLL 0x00 R/W Divisor Latch Register (LS)(DLAB = 1) 0x0000_0000 HSUART_DLM 0x04 R/W Divisor Latch Register (MS)(DLAB = 1) 0x0000_0000

Publication Release Date: September 19, 2006 - 351 - Revision B2 Continued. REGISTER OFFSET R/W HSUART_IIR 0x08 R Interrupt Identification Register 0x8181_8181 HSUART_FCR 0x08 W FIFO Control Register Undefined HSUART_LCR 0x0C R/W Line Control Register 0x0000_0000 HSUART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 HSUART_LSR 0x14 R Line Status Register 0x6060_6060 HSUART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000 HSUART_TOR 0x1C R/W Time Out Register 0x0000_0000 Note: Real register address = 0xFFF8_0000+ (UART number – 1) * (0x0100) + offset NOTE: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times before send to APB bus. For example, when ARM CPU read register UART1_BRR, ARM CPU will get UART1_RBR = {RBR[7:0], _RBR[7:0], RBR[7:0], RBR[7:0]}. HSUART Receive Buffer Register (HSUART_RBR) REGISTER OFFSET R/W HSUART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined Reserved Reserved Reserved 8-bit Received Data BITS DESCRIPTIONS [7:0] 8-bit Received Data By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first).

352 - HSUART Transmit Holding Register (HSUART_THR) REGISTER OFFSET R/W

HSUART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined Reserved Reserved Reserved 8-bit Transmitted Data BITS DESCRIPTIONS [7:0] 8-bit Transmitted Data By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first). HSUART Interrupt Enable Register (HSUART_IER) REGISTER OFFSET R/W HSUART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 Reserved Reserved Reserved RESERVED nDBGACK_EN MSIE RLSIE THREIE RDAIE

Publication Release Date: September 19, 2006 - 353 - Revision B2 BITS DESCRIPTIONS [31:5] Reserved [4] nDBGACK_EN ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held 1 = No matter what DBGACK is high or not, the UART receiver timer- out clock will not be held [3] MSIE MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS [2] RLSIE Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS [1] THREIE Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable 0 = Mask off Irpt_THRE 1 = Enable Irpt_THRE [0] RDAIE Receive Data Available Interrupt (Irpt_RDA) Enable and Time-out Interrupt (Irpt_TOUT) Enable 0 = Mask off Irpt_RDA and Irpt_TOUT 1 = Enable Irpt_RDA and Irpt_TOUT HSUART Divider Latch (Low Byte) Register (HSUART_DLL) REGISTER OFFSET R/W HSUART_DLL 0x00 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 Reserved Reserved Reserved Baud Rate Divider (Low Byte)

354 - BITS DESCRIPTIONS [31:8] Reserved [7:0] Baud Rate Divisor (Low Byte) The low byte of the baud rate divider HSUART Divisor Latch (High Byte) Register (HSUART_DLM) REGISTER OFFSET R/W

HSUART_DLM 0x04 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 Reserved Reserved Reserved Baud Rate Divider (High Byte) BITS DESCRIPTIONS [31:8] Reserved [7:0] Baud Rate Divisor (High Byte) The high byte of the baud rate divider This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} HSUART Interrupt Identification Register (HSUART_IIR) REGISTER OFFSET R/W HSUART_IIR 0x08 R Interrupt Identification Register 0x8181_8181

Publication Release Date: September 19, 2006 - 355 - Revision B2 Reserved Reserved Reserved FMES RFTLS DMS IID NIP BITS DESCRIPTIONS [31:8] Reserved [7] FMES FIFO Mode Enable Status This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable, this bit always shows the logical 1 when CPU is reading this register. [6:5] RFTLS RX FIFO Threshold Level Status These bits show the current setting of receiver FIFO threshold level (RTHO). The meaning of RTHO is defined in the following FCR description. [4] DMS DMA Mode Select The DMA function is not implemented in this version. When reading IIR, the DMS is always returned 0. [3:1] IID Interrupt Identification The IID together with NIP indicates the current interrupt request from UART. [0] NIP No Interrupt Pending There is no pending interrupt.

356 - Interrupt Control Functions IIR [3:0] PRIORITY INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL - - - 1 None None 0110 Highest Receiver Line Status (Irpt_RLS) Overrun error, parity error, framing error, or break interrupt Reading the LSR 0100 Second Received Data Available (Irpt_RDA) Receiver FIFO threshold level is reached Receiver FIFO drops below the threshold level 1100 Second Receiver FIFO Time- out (Irpt_TOUT) Receiver FIFO is non- empty and no activities are occurred in the receiver FIFO during the TOR defined time duration Reading the RBR 0010 Third Transmitter Holing Register Empty (Irpt_THRE) Transmitter holding register empty Reading the IIR (if source of interrupt is Irpt_THRE) or writing into the THR 0000 Fourth MODEM Status (Irpt_MOS) The CTS bits are changing state . Reading the MSR (optional) Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550. HSUART FIFO Control Register (HSUART_FCR) REGISTER OFFSET R/W

HSUART_FCR 0x08 W FIFO Control Register Undefined Reserved Reserved Reserved RFITL DMS TFR RFR FME

Publication Release Date: September 19, 2006 - 357 - Revision B2 BITS DESCRIPTIONS [31:8] Reserved [7:4] RFITL RX FIFO Interrupt (Irpt_RDA) Trigger Level RFITL Irpt_RDA Trigger Level (Bytes) 0000 0001 0010 0011 0100 0101 0110 others [3] DMS DMA Mode Select The DMA function is not implemented in this version. [2] TFR TX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. [1] RFR RX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated. [0] FME FIFO Mode Enable Because UART is always operating in the FIFO mode, writing this bit has no effect while reading always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not be programmed.

358 - HSUART Line Control Register (HSUART_LCR) REGISTER OFFSET R/W

HSUART_LCR 0x0C R/W Line Control Register 0x0000_0000 BITS DESCRIPTIONS [31:8] Reserved [7] DLAB Divider Latch Access Bit 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM}. [6] BCB Break Control Bit When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic. [5] SPE Stick Parity Enable 0 = Disable stick parity 1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit enable) is set. [4] EPE Even Parity Enable 0 = Odd number of logic 1’s are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1’s are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set. [3] PBE Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. [2] NSB Number of “STOP bit” 0= One “ STOP bit” is generated in the transmitted data 1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word length is selected; Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected. [1:0] WLS Word Length Select WLS[1:0] Character length 5 bits 6 bits 7 bits 8 bits

Publication Release Date: September 19, 2006 - 359 - Revision B2 Reserved Reserved Reserved DLAB BCB SPE EPE PBE NSB WLS HSUART Modem Control Register (HSUART_MCR) REGISTER OFFSET R/W HSUART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 Reserved Reserved Reserved Reserved LBME Reserved RTS Reserved BITS DESCRIPTIONS [31:5] Reserved [4] LBME Loop-back Mode Enable 0 = Disable 1 = When the loop-back mode is enabled, the following signals are connected internally: SOUT connected to SIN and SOUT pin fixed at logic 1 RTS# connected to CTS# and RTS# pin fixed at logic 1

360 - Continued. BITS DESCRIPTIONS [3:2] Reserved [1] RTS# Complement version of RTS# (Request-To-Send) signal Writing 0x00 to MCR, RTS# bit are set to logic 1’s; Writing 0x0f to MCR, RTS# bit are reset to logic 0’s. [0] Reserved HSUART Line Status Control Register (HSUART_LSR) REGISTER OFFSET R/W

HSUART_LSR 0x14 R Line Status Register 0x6060_6060 Reserved Reserved Reserved ERR_RX TE THRE BII FEI PEI OEI RFDR BITS DESCRIPTIONS [31:8] Reserved [7] ERR_RX RX FIFO Error 0 = RX FIFO works normally 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO. [6] TE Transmitter Empty 0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register (TSR) are not empty. 1 = Both THR and TSR are empty.

Publication Release Date: September 19, 2006 - 361 - Revision B2 Continued. BITS DESCRIPTIONS [5] THRE Transmitter Holding Register Empty 0 = THR is not empty. 1 = THR is empty. THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER [1]=1. [4] BII Break Interrupt Indicator This bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU reads the contents of the LSR. [3] FEI Framing Error Indicator This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads the contents of the LSR. [2] PEI Parity Error Indicator This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. [1] OEI Overrun Error Indicator An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads the contents of the LSR. [0] RFDR RX FIFO Data Ready 0 = RX FIFO is empty 1 = RX FIFO contains at least 1 received data word. LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR. LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt" (Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not suggested).

362 - HSUART Modem Status Register (HSUART_MSR) REGISTER OFFSET R/W

HSUART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000 Reserved Reserved Reserved Reserved CTS# Reserved DCTS BITS DESCRIPTIONS [31:5] Reserved [4] CTS# Complement version of clear to send (CTS#) input (This bit is selected by IP) [3:1] Reserved [0] DCTS CTS# State Change (This bit is selected by IP) This bit is set whenever CTS# input has changed state, and it will be reset if the CPU reads the MSR. Whenever any of MSR [0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing MSR is a null operation (not suggested). HSUART Time Out Register (HSUART_TOR) REGISTER OFFSET R/W HSUART_TOR 0x1C R/W Time Out Register 0x0000_0000

Publication Release Date: September 19, 2006 - 363 - Revision B2 Reserved Reserved Reserved TOIE TOIC BITS DESCRIPTIONS [31:8] Reserved [7] TOIE Time Out Interrupt Enable The feature of receiver time out interrupt is enabled only when TOR [7] = IER[0] = 1. [6:0] TOIC Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears Irpt_TOUT.

364 -

6.13 Timer/Watchdog Controller

6.13.1 General Timer Controller

The timer module includes two channels, TIMER0 and TIMER1, which allow you to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information. The timer can generate an interrupt signal upon timeout, or provide the current value of count during operation. The general TIMER Controller includes the following features y AMBA APB interface compatible y Two channels with a 8-bit presale counter/24-bit down counter and an interrupt request each y Independent clock source for each channel y Maximum uninterrupted time = (1 / 25 MHz) * (256) * (2^24), if TCLK = 25 MHz

6.13.2 Watchdog Timer

6.13.3 Timer Control Registers Map

R: read only, W: write only, R/W: both read and write REGISTER ADDRESS R/W/C 0xFFF8_1000 R/W Timer Control and Status Register 0 0x0000_0005 TCSR1 0xFFF8_1004 R/W Timer Control and Status Register 1 0x0000_0005 TICR0 0xFFF8_1008 R/W Timer Initial Control Register 0 0x0000_0000 TICR1 0xFFF8_100C R/W Timer Initial Control Register 1 0x0000_0000 TDR0 0xFFF8_1010 R Timer Data Register 0 0x0000_0000 TDR1 0xFFF8_1014 R Timer Data Register 1 0x0000_0000 TISR 0xFFF8_1018 R/W Timer Interrupt Status Register 0x0000_0000 WTCR 0xFFF8_101C R/W Watchdog Timer Control Register 0x0000_0400 Timer Control Register 0/1 (TCSR 0/1) REGISTER ADDRESS R/W 0xFFF8_1000 R/W Timer Control and Status Register 0 0x0000_0005 TCSR1 0xFFF8_1004 R/W Timer Control and Status Register 1 0x0000_0005

Publication Release Date: September 19, 2006 - 365 - Revision B2 nDBGACK_EN CEN IE MODE[1:0] CRST CACT Reserved Reserved Reserved PRESCALE[7:0] BITS DESCRIPTIONS [31] nDBGACK_EN ICE debug mode acknowledge enable 0 = When DBGACK is high, the TIMER counter will be held 1 = No matter DBGACK is high or not, the TIMER counter will not be held [30] CEN Counter Enable 0 = Stops/Suspends counting 1 = Starts counting [29] IE Interrupt Enable 0 = Disable TIMER Interrupt. 1 = Enable TIMER Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter decrements to zero. [28:27] MODE Timer Operating Mode MODE Timer Operating Mode The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared then. The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. Reserved.

366 - Continued BITS DESCRIPTIONS [26] CRST Counter Reset Set this bit will reset the TIMER counter, and also force CEN to 0. 0 = No effect. 1 = Reset Timer’s prescale counter, internal 24-bit counter and CEN. [25] CACT Timer is in Active This bit indicates the counter status of timer. 0 = Timer is not active. 1 = Timer is in active. [24:8] Reserved Reserved [7:0] PRESCALE Prescale Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling. Timer Initial Count Register 0/1 (TICR0/1) REGISTER ADDRESS R/W

0xFFF8_1008 R/W Timer Initial Control Register 0 0x0000_0000 TICR1 0xFFF8_100C R/W Timer Initial Control Register 1 0x0000_0000 Reserved TIC [23:16] TIC [15:8] TIC [7:0]

Publication Release Date: September 19, 2006 - 367 - Revision B2 BITS DESCRIPTIONS [31:24] Reserved Reserved [23:0] TIC Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. NOTE1: Never write 0x0 in TIC, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. Timer Data Register 0/1 (TDR0/1) REGISTER ADDRESS R/W 0xFFF8_10010 R Timer Data Register 0 0x0000_0000 TDR1 0xFFF8_10014 R Timer Data Register 1 0x0000_0000 Reserved TDR [23:16] TDR [15:8] TDR [7:0] BITS DESCRIPTIONS [31:24] Reserved Reserved [23:0] TDR Timer Data Register The current count is registered in this 24-bit value. NOTE: Software can read a correct current value on this register only when CEN = 0, or the value represents here could not be a correct one.

368 - Timer Interrupt Status Register (TISR) REGISTER ADDRESS R/W

0xFFF8_1018 R/W Timer Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TIF1 TIF0 BITS DESCRIPTIONS [1] TIF1 Timer Interrupt Flag 1 This bit indicates the interrupt status of Timer channel 1. 0 = It indicates that the Timer 1 dose not countdown to zero yet. 1 = It indicates that the counter of Timer 1 has decremented to zero. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. [0] TIF0 Timer Interrupt Flag 0 This bit indicates the interrupt status of Timer channel 0. 0 = It indicates that the Timer 0 dose not countdown to zero yet. 1 = It indicates that the counter of Timer 0 has decremented to zero. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. Watchdog Timer Control Register (WTCR) REGISTER ADDRESS R/W 0xFFF8_101C R/W Watchdog Timer Control Register 0x0000_0400

Publication Release Date: September 19, 2006 - 369 - Revision B2 Reserved Reserved Reserved WTCLK nDBGACK_EN WTTME WTE WTIE WTIS WTIF WTRF WTRE WTR BITS DESCRIPTIONS [31:11] Reserved Reserved [10] WTCLK Watchdog Timer Clock This bit is used for deciding whether the Watchdog timer clock input is divided by 256 or not. Clock source of Watchdog timer is Crystal input. 0 = Using original clock input 1 = The clock input will be divided by 256 NOTE: When WTTME = 1, set this bit has no effect on WDT clock (using original clock input). [9] nDBGACK_EN ICE debug mode acknowledge enable 0 = When DBGACK is high, the Watchdog timer counter will be held 1 = No matter DBGACK is high or not, the Watchdog timer counter will not be held [8] WTTME Watchdog Timer Test Mode Enable For reasons of efficiency, the 26-bit counter within the Watchdog timer is considered as two independent 13-bit counters in the test mode. They are operated concurrently and separately during the test. This approach can save a lot of time spent in the test. When the 13- bit counter overflows, a Watchdog timer interrupt is generated. 0 = Put the Watchdog timer in normal operating mode 1 = Put the Watchdog timer in test mode [7] WTE Watchdog Timer Enable 0 = Disable the Watchdog timer (This action will reset the internal counter) 1 = Enable the Watchdog timer

370 - Continued BITS DESCRIPTIONS [6] WTIE Watchdog Timer Interrupt Enable 0 = Disable the Watchdog timer interrupt 1 = Enable the Watchdog timer interrupt [5:4] WTIS Watchdog Timer Interval Select These two bits select the interval for the Watchdog timer. No matter which interval is chosen, the reset timeout is always occurred 512 WDT clock cycles later than the interrupt timeout. WTIS Interrupt Timeout Reset Timeout Real Time Interval (CLK=15MHz/256) 214 clocks 214 + 1024 clocks 0.28 sec. 216 clocks 216 + 1024 clocks 1.12 sec. 218 clocks 218 + 1024 clocks 4.47 sec. 220 clocks 220 + 1024 clocks 17.9 sec. [3] WTIF Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. 0 = Watchdog timer interrupt does not occur 1 = Watchdog timer interrupt occurs NOTE: This bit is read only, but can be cleared by writing 1 to this bit. [2] WTRF Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it up manually. If WTRE is disabled, then the Watchdog timer has no effect on this bit. 0 = Watchdog timer reset does not occur 1 = Watchdog timer reset occurs NOTE: This bit is read only, but can be cleared by writing 1 to this bit.

Publication Release Date: September 19, 2006 - 371 - Revision B2 Continued BITS DESCRIPTIONS [1] WTRE Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function. 0 = Disable Watchdog timer reset function 1 = Enable Watchdog timer reset function [0] WTR Watchdog Timer Reset This bit brings the Watchdog timer into a known state. It helps reset the Watchdog timer before a timeout situation occurring. Failing to set WTR before timeout will initiates an interrupt if WTIE is set. If the WTRE bit is set, Watchdog timer reset will be occurred 512 WDT clock cycles after timeout. This bit is self-clearing. 0 = No operation 1 = Reset the contents of the Watchdog timer

372 -

6.14 Advanced Interrupt Controller

An interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception is occurred when the nIRQ input is asserted. Similarly, the FIQ exception is occurred when the nFIQ input is asserted. The FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible to ignore the FIQ and the IRQ by setting the F and I bits in the current program status register (CPSR). The W90P710 incorporates the advanced interrupt controller (AIC) that is capable of dealing with the interrupt requests from a total of 32 different sources. Currently, 31 interrupt sources are defined. Each interrupt source is uniquely assigned to an interrupt channel. For example, the watchdog timer interrupt is assigned to channel 1. The AIC implements a proprietary eight-level priority scheme that differentiates the available 31 interrupt sources into eight priority levels. Interrupt sources within the priority level 0 have the highest priority and the priority level 7 has the lowest. To work this scheme properly, you must specify a certain priority level to each interrupt source during power-on initialization; otherwise, the system shall behave unexpectedly. Within each priority level, interrupt source that is positioned in a lower channel has a higher priority. Interrupt source that is active, enabled, and positioned in the lowest channel within the priority level 0 is promoted to the FIQ. Interrupt sources within the priority levels other than 0 can petition for the IRQ. The IRQ can be preempted by the occurrence of the FIQ. Interrupt nesting is performed automatically by the AIC. Though interrupt sources originated from the W90P710 itself are intrinsically high-level sensitive, the AIC can be configured as either low-level sensitive, high-level sensitive, negative-edge triggered, or positive-edge triggered to each interrupt source. When the W90P710 is put in the test mode, all interrupt sources must be configured as positive-edge triggered. The advanced interrupt controller includes the following features: y AMBA APB bus interface y External interrupts can be programmed as either edge-triggered or level-sensitive y External interrupts can be programmed as either low-active or high-active y Has flags to reflect the status of each interrupt source y Individual mask for each interrupt source y Proprietary 8-level interrupt scheme to ease the burden from the interrupt y Priority methodology is adopted to allow for interrupt daisy-chaining y Automatically masking out the lower priority interrupt during interrupt nesting y Automatically clearing the interrupt flag when the external interrupt source is programmed to be edge-triggered

Publication Release Date: September 19, 2006 - 373 - Revision B2

6.14.1 Interrupt Sources

Table 6.14.1 W90P710 Interrupt Sources PRIORITY NAME MODE SOURCE 1 (Highest) WDT_INT Positive Level Watch Dog Timer Interrupt nIRQ0 Programmable External Interrupt 0 nIRQ1 Programmable External Interrupt 1 nIRQ2 Programmable External Interrupt 2 nIRQ3 Programmable External Interrupt 3 AC97_INT Positive Level AC97 Interrupt LCD_INT Positive Level LCD Controller Interrupt RTC_INT Positive Level RTC Interrupt UART_INT0 Positive Level UART Interrupt0 UART_INT1 Positive Level UART Interrupt1 UART_INT2 Positive Level UART Interrupt2 UART_INT3 Positive Level UART Interrupt3 T_INT0 Positive Level Timer Interrupt 0 T_INT1 Positive Level Timer Interrupt 1 USBH_INT0 Positive Level USB Host Interrupt 0 USBH_INT1 Positive Level USB Host Interrupt 1 EMCTX_INT Positive Level EMC TX Interrupt EMCRX_INT Positive Level EMC RX Interrupt GDMA_INT0 Positive Level GDMA Channel Interrupt 0 GDMA_INT1 Positive Level GDMA Channel Interrupt 1 SD_INT Positive Level SD Interrupt USBD_INT Positive Level USB Device Interrupt SC_INT0 Positive Level Smart Card Interrupt 0 SC_INT1 Positive Level Smart Card Interrupt 1 I2C_INT0 Positive Level I2C Interrupt0 I2C_INT1 Positive Level I2C Interrupt1 SSP_INT Positive Level SSP Interrupt PWM _INT Positive Level PWM Timer interrupt KPI_INT Positive Level Keypad Interrupt PS2_INT Positive Level PS2 Interrupt IRQ45_INT Positive Level GPIO0 & GPIO70 Interrupt

374 - AIC Functional Description Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used, priority determination must be carried out by software. When the Interrupt Priority Encoding Register (AIC_IPER) is read, it will return an integer representing the channel that is active and having the highest priority. This integer is equivalent to multiplied by 4 (shifted left two bits to word-align it) such that it may be used directly to index into a branch table to select the appropriate interrupt service routine vector. Priority Controller An 8-level priority encoder controls the NIRQ line. Each interrupt source belongs to priority group between of 0 to 7. Group 0 has the highest priority and group 7 the lowest. When more than one unmasked interrupt channels are active at a time, the interrupt with the highest priority is serviced first. If all active interrupts have equal priority, the interrupt with the lowest interrupt source number is serviced first. The current priority level is defined as the priority level of the interrupt with the highest priority at the time the register AIC_IPER is read. In the case when a higher priority unmasked interrupt occurs while an interrupt already exits, there are two possible outcomes depending on whether the AIC_IPER has been read. If the processor has already read the AIC_IPER and caused the NIRQ line to be de-asserted, then the NIRQ line is reasserted. When the processor has enabled nested interrupts and reads the AIC_IPER again, it reads the new, higher priority interrupt vector. At the same time, the current priority level is updated to the higher priority. If the AIC_IPER has not been read after the NIRQ line has been asserted, then the processor will read the new higher priority interrupt vector in the AIC_IPER register and the current priority level is updated. When the End of Service Command Register (AIC_EOSCR) is written, the current interrupt level is updated with the last stored interrupt level from the stack (if any). Therefore, at the end of a higher priority interrupt, the AIC returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted. Interrupt Handling When the IRQ line is asserted, the interrupt handler must read the AIC_IPER as soon as possible. This can de-assert the NIRQ request to the processor and clears the interrupt if it is programmed to be edge triggered. This allows the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. The AIC_EOSCR (End of Service Command Register) must be written at the end of the interrupt service routine. This permits pending interrupts to be serviced.

Publication Release Date: September 19, 2006 - 375 - Revision B2 Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled individually by using the command registers AIC_MECR and AIC_MDCR. The status of interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt doesn’t affect the servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources (including FIQ) can be individually set or clear by respectively writing to the registers AIC_SSCR and AIC_SCCR when they are programmed to be edge triggered. This feature of the AIC is useful in auto-testing or software debugging. Fake Interrupt When the AIC asserts the NIRQ line, the processor enters interrupt mode and the interrupt handler reads the AIC_IPER, it may happen that AIC de-asserts the NIRQ line after the processor has taken into account the NIRQ assertion and before the read of the AIC_IPER. This behavior is called a fake interrupt. The AIC is able to detect these fake interrupts and returns all zero when AIC_IPER is read. The same mechanism of fake interrupt occurs if the processor reads the AIC_IPER (application software or ICE) when there is no interrupt pending. The current priority level is not updated in this situation. Hence, the AIC_EOSCR shouldn’t be written. ICE/Debug Mode This mode allows reading of the AIC_IPER without performing the associated automatic operations. This is necessary when working with a debug system. When an ICE or debug monitor reads the AIC user interface, the AIC_IPER can be read. This has the following consequences in normal mode: y If there is no enabled pending interrupt, the fake vector will be returned. y If an enabled interrupt with a higher priority than the current one is pending, it will be stacked. In the second case, an End-of-Service command would be necessary to restore the state of the AIC. This operation is generally not performed by the debug system. Therefore, the debug system would become strongly intrusive, and could cause the application to enter an undesired state. This can be avoided by using ICE/Debug Mode. When this mode is enabled. The AIC performs interrupt stacking only when a write access is performed on the AIC_IPER. Hence, the interrupt service routine must write to the AIC_IPER (any value) just after reading it. When AIC_IPER is written, the new status of AIC, including the value of interrupt source number register (AIC_ISNR), is updated with the value that is kept at previous reading of AIC_IPER The debug system must not write to the AIC_IPER as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are performed according to the mode:

376 - ACTION NORMAL MODE ICE/DEBUG MODE Calculate active interrupt Read AIC_IPER Read AIC_IPER Determine and return the vector of the active interrupt Read AIC_IPER Read AIC_IPER Push on internal stack the current priority level Read AIC_IPER Write AIC_IPER Acknowledge the interrupt (Note 1) Read AIC_IPER Write AIC_IPER No effect (Note 2) Read AIC_IPER Notes: y NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive. y Note that software which has been written and debugged using this mode will run correctly in normal mode without modification. However, in normal mode writing to AIC_IPER has no effect and can be removed to optimize the code

6.14.2 AIC Registers Map

AIC_SCR1 0xFFF8_2004 R/W Source Control Register 1 0x0000_0047 AIC_SCR2 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 AIC_SCR3 0xFFF8_200C R/W Source Control Register 3 0x0000_0047 AIC_SCR4 0xFFF8_2010 R/W Source Control Register 4 0x0000_0047 AIC_SCR5 0xFFF8_2014 R/W Source Control Register 5 0x0000_0047 AIC_SCR6 0xFFF8_2018 R/W Source Control Register 6 0x0000_0047 AIC_SCR7 0xFFF8_201C R/W Source Control Register 7 0x0000_0047 AIC_SCR8 0xFFF8_2020 R/W Source Control Register 8 0x0000_0047 AIC_SCR9 0xFFF8_2024 R/W Source Control Register 9 0x0000_0047 AIC_SCR10 0xFFF8_2028 R/W Source Control Register 10 0x0000_0047 AIC_SCR11 0xFFF8_202C R/W Source Control Register 11 0x0000_0047 AIC_SCR12 0xFFF8_2030 R/W Source Control Register 12 0x0000_0047 AIC_SCR13 0xFFF8_2034 R/W Source Control Register 13 0x0000_0047 AIC_SCR14 0xFFF8_2038 R/W Source Control Register 14 0x0000_0047 AIC_SCR15 0xFFF8_203C R/W Source Control Register 15 0x0000_0047

Publication Release Date: September 19, 2006 - 377 - Revision B2 AIC Registers Map, continued REGISTER ADDRESS R/W AIC_SCR16 0xFFF8_2040 R/W Source Control Register 16 0x0000_0047 AIC_SCR17 0xFFF8_2044 R/W Source Control Register 17 0x0000_0047 AIC_SCR18 0xFFF8_2048 R/W Source Control Register 18 0x0000_0047 AIC_SCR19 0xFFF8_204C R/W Source Control Register 19 0x0000_0047 AIC_SCR20 0xFFF8_2050 R/W Source Control Register 20 0x0000_0047 AIC_SCR21 0xFFF8_2054 R/W Source Control Register 21 0x0000_0047 AIC_SCR22 0xFFF8_2058 R/W Source Control Register 22 0x0000_0047 AIC_SCR23 0xFFF8_205C R/W Source Control Register 23 0x0000_0047 AIC_SCR24 0xFFF8_2060 R/W Source Control Register 24 0x0000_0047 AIC_SCR25 0xFFF8_2064 R/W Source Control Register 25 0x0000_0047 AIC_SCR26 0xFFF8_2068 R/W Source Control Register 26 0x0000_0047 AIC_SCR27 0xFFF8_206C R/W Source Control Register 27 0x0000_0047 AIC_SCR28 0xFFF8_2070 R/W Source Control Register 28 0x0000_0047 AIC_SCR29 0xFFF8_2074 R/W Source Control Register 29 0x0000_0047 AIC_SCR30 0xFFF8_2078 R/W Source Control Register 30 0x0000_0047 AIC_SCR31 0xFFF8_207C R/W Source Control Register 31 0x0000_0047 AIC_IRSR 0xFFF8_2100 R Interrupt Raw Status Register 0x0000_0000 AIC_IASR 0xFFF8_2104 R Interrupt Active Status Register 0x0000_0000 AIC_ISR 0xFFF8_2108 R Interrupt Status Register 0x0000_0000 AIC_IPER 0xFFF8_210C R Interrupt Priority Encoding Register 0x0000_0000 AIC_ISNR 0xFFF8_2110 R Interrupt Source Number Register 0x0000_0000 AIC_IMR 0xFFF8_2114 R Interrupt Mask Register 0x0000_0000 AIC_OISR 0xFFF8_2118 R Output Interrupt Status Register 0x0000_0000 AIC_MECR 0xFFF8_2120 W Mask Enable Command Register Undefined AIC_MDCR 0xFFF8_2124 W Mask Disable Command Register Undefined AIC_SSCR 0xFFF8_2128 W Source Set Command Register Undefined AIC_SCCR 0xFFF8_212C W Source Clear Command Register Undefined AIC_EOSCR 0xFFF8_2130 W End of Service Command Register Undefined AIC_TEST 0xFFF8_2200 W ICE/Debug mode Register Undefined

378 - AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR31) REGISTER ADDRESS R/W

AIC_SCR1 0xFFF8_2004 R/W Source Control Register 1 0x0000_0047 AIC_SCR2 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 y y y y y y y y y y y y y y y AIC_SCR28 0xFFF8_2070 R/W Source Control Register 28 0x0000_0047 AIC_SCR29 0xFFF8_2074 R/W Source Control Register 29 0x0000_0047 AIC_SCR30 0xFFF8_2078 R/W Source Control Register 30 0x0000_0047 AIC_SCR31 0xFFF8_207C R/W Source Control Register 31 0x0000_0047 RESERVED RESERVED RESERVED SRCTYPE RESERVED PRIORITY BITS DESCRIPTIONS [31:8] Reserved Reserved [7:6] SRCTYPE Interrupt Source Type Whether an interrupt source is considered active or not by the AIC is subject to the settings of this field. Interrupt sources other than nIRQ0, nIRQ1, nIRQ2, nIRQ3, should be configured as level sensitive during normal operation unless in the testing situation. SRCTYPE [7:6] Interrupt Source Type Low-level Sensitive High-level Sensitive Negative-edge Triggered Positive-edge Triggered

Publication Release Date: September 19, 2006 - 379 - Revision B2 Continued BITS DESCRIPTIONS [5:3] Reserved Reserved [2:0] PRIORITY Priority Level Every interrupt source must be assigned a priority level during initiation. Among them, priority level 0 has the highest priority and priority level 7 the lowest. Interrupt sources with priority level 0 are promoted to FIQ. Interrupt sources with priority level other than 0 belong to IRQ. For interrupt sources of the same priority level that located in the lower channel number has higher priority. AIC Interrupt Raw Status Register (AIC_IRSR) REGISTER ADDRESS R/W AIC_IRSR 0xFFF8_2100 R Interrupt Raw Status Register 0x0000_0000 IRS31 IRS30 IRS29 IRS28 IRS27 IRS26 IRS25 IRS24 IRS23 IRS22 IRS21 IRS20 IRS19 IRS18 IRS17 IRS16 IRS15 IRS14 IRS13 IRS12 IRS11 IRS10 IRS9 IRS8 IRS7 IRS6 IRS5 IRS4 IRS3 IRS2 IRS1 RESERVED BITS DESCRIPTIONS [31:1] IRSx This register records the intrinsic state within each interrupt channel. IRS x: Interrupt Status Indicate the intrinsic status of the corresponding interrupt source 0 = Interrupt channel is in the voltage level 0 1 = Interrupt channel is in the voltage level 1 [0] Reserved Reserved

380 - AIC Interrupt Active Status Register (AIC_IASR) REGISTER ADDRESS R/W

AIC_IASR 0xFFF8_2104 R Interrupt Active Status Register 0x0000_0000 IAS31 IAS30 IAS29 IAS28 IAS27 IAS26 IAS25 IAS24 IAS23 IAS22 IAS21 IAS20 IAS19 IAS18 IAS17 IAS16 IAS15 IAS14 IAS13 IAS12 IAS11 IAS10 IAS9 IAS8 IAS7 IAS6 IAS5 IAS4 IAS3 IAS2 IAS1 RESERVED BITS DESCRIPTIONS [31:1] IASx This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting. IAS x: Interrupt Active Status Indicate the status of the corresponding interrupt source 0 = Corresponding interrupt channel is inactive 1 = Corresponding interrupt channel is active [0] Reserved Reserved AIC Interrupt Status Register (AIC_ISR) REGISTER ADDRESS R/W AIC_ISR 0xFFF8_2108 R Interrupt Status Register 0x0000_0000

Publication Release Date: September 19, 2006 - 381 - Revision B2 IS31 IS30 IS29 IS28 IS27 IS26 IS25 IS24 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 IS7 IS6 IS5 IS4 IS3 IS2 IS1 RESERVED BITS DESCRIPTIONS [31:1] ISx This register identifies those interrupt channels whose are both active and enabled. ISx: Interrupt Status Indicates the status of corresponding interrupt channel 0 = Two possibilities: (1) The corresponding interrupt channel is inactive no matter whether it is enabled or disabled; (2) It is active but not enabled 1 = Corresponding interrupt channel is both active and enabled (can assert an interrupt) [0] Reserved Reserved AIC IRQ Priority Encoding Register (AIC_IPER) REGISTER ADDRESS R/W AIC_IPER 0xFFF8_210C R Interrupt Priority Encoding Register 0x0000_0000 VECTOR

382 - BITS DESCRIPTIONS [6:2] Vector When the AIC generates the interrupt, VECTOR represents the interrupt channel number that is active, enabled, and has the highest priority. If the representing interrupt channel possesses a priority level 0, then the interrupt asserted is FIQ; otherwise, it is IRQ. The value of VECTOR is copied to the register AIC_ISNR thereafter by the AIC. This register was restored a value 0 after it was read by the interrupt handler. This register can help indexing into a branch table to quickly jump to the corresponding interrupt service routine. VECTOR [6:2]: Interrupt Vector 0 = no interrupt occurs 1 ~ 31 = representing the interrupt channel that is active, enabled, and having the highest priority [0] Reserved Reserved AIC Interrupt Source Number Register (AIC_ISNR) REGISTER ADDRESS R/W

AIC_ISNR 0xFFF8_2110 R Interrupt Source Number Register 0x0000_0000 IRQID BITS DESCRIPTIONS [31:5] Reserved Reserved [4:0] IRQID The purpose of this register is to record the interrupt channel number that is active, enabled, and has the highest priority. IRQID [4:0]: IRQ Identification Stands for the interrupt channel number

Publication Release Date: September 19, 2006 - 383 - Revision B2 AIC Interrupt Mask Register (AIC_IMR) REGISTER ADDRESS R/W AIC_IMR 0xFFF8_2114 R Interrupt Mask Register 0x0000_0000 IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 RESERVED BITS DESCRIPTIONS [31:1] IM x IM x: Interrupt Mask This bit determines whether the corresponding interrupt channel is enabled or disabled. Every interrupt channel can be active no matter whether it is enabled or disabled. If an interrupt channel is enabled, it does not definitely mean it is active. Every interrupt channel can be authorized by the AIC only when it is both active and enabled. 0 = Corresponding interrupt channel is disabled 1 = Corresponding interrupt channel is enabled [0] Reserved Reserved AIC Output Interrupt Status Register (AIC_OISR) REGISTER ADDRESS R/W AIC_OISR 0xFFF8_2118 R Output Interrupt Status Register 0x0000_0000 RESERVED RESERVED RESERVED RESERVED IRQ FIQ

384 - The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred. BITS DESCRIPTIONS [31:2] Reserved Reserved [1] IRQ IRQ [1]: Interrupt Request 0 = nIRQ line is inactive. 1 = nIRQ line is active. [0] FIQ FIQ [0]: Fast Interrupt Request 0 = nFIQ line is inactive. 1 = nFIQ line is active AIC Mask Enable Command Register (AIC_MECR) REGISTER ADDRESS R/W

AIC_MECR 0xFFF8_2120 W Mask Enable Command Register Undefined MEC31 MEC30 MEC29 MEC28 MEC27 MEC26 MEC25 MEC24 MEC23 MEC22 MEC21 MEC20 MEC19 MEC18 MEC17 MEC16 MEC15 MEC14 MEC13 MEC12 MEC11 MEC10 MEC9 MEC8 MEC7 MEC6 MEC5 MEC4 MEC3 MEC2 MEC1 RESERVED BITS DESCRIPTIONS [31:1] MEC x MEC x: Mask Enable Command 0 = No effect 1 = Enables the corresponding interrupt channel [0] Reserved Reserved

Publication Release Date: September 19, 2006 - 385 - Revision B2 AIC Mask Disable Command Register (AIC_MDCR) REGISTER ADDRESS R/W AIC_MDCR 0xFFF8_2124 W Mask Disable Command Register Undefined MDC31 MDC30 MDC29 MDC28 MDC27 MDC26 MDC25 MDC24 MDC23 MDC22 MDC21 MDC20 MDC19 MDC18 MDC17 MDC16 MDC15 MDC14 MDC13 MDC12 MDC11 MDC10 MDC9 MDC8 MDC7 MDC6 MDC5 MDC4 MDC3 MDC2 MDC1 RESERVED BITS DESCRIPTIONS [31:1] MDCx MDC x: Mask Disable Command 0 = No effect 1 = Disables the corresponding interrupt channel [0] Reserved Reserved AIC Source Set Command Register (AIC_SSCR) REGISTER ADDRESS R/W AIC_SSCR 0xFFF8_2128 W Source Set Command Register Undefined SSC31 SSC30 SSC29 SSC28 SSC27 SSC26 SSC25 SSC24 SSC23 SSC22 SSC21 SSC20 SSC19 SSC18 SSC17 SSC16 SSC15 SSC14 SSC13 SSC12 SSC11 SSC10 SSC9 SSC8 SSC7 SSC6 SSC5 SSC4 SSC3 SSC2 SSC1 RESERVED

386 - BITS DESCRIPTIONS [31:1] SSCx When the W90P710 is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SSCx: Source Set Command 0 = No effect. 1 = Activates the corresponding interrupt channel [0] Reserved Reserved AIC Source Clear Command Register (AIC_SCCR) REGISTER ADDRESS R/W

AIC_SCCR 0xFFF8_212C W Source Clear Command Register Undefined SCC31 SCC30 SCC29 SCC28 SCC27 SCC26 SCC25 SCC24 SCC23 SCC22 SCC21 SCC20 SCC19 SCC18 SCC17 SCC16 SCC15 SCC14 SCC13 SCC12 SCC11 SCC10 SCC9 SCC8 SCC7 SCC6 SCC5 SCC4 SCC3 SCC2 SCC1 RESERVED BITS DESCRIPTIONS [31:1] SCCx When the W90P710 is under debugging or verification, software can deactivate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SCCx: Source Clear Command 0 = No effect. 1 = Deactivates the corresponding interrupt channels [0] Reserved Reserved

Publication Release Date: September 19, 2006 - 387 - Revision B2 AIC End of Service Command Register (AIC_EOSCR) REGISTER ADDRESS R/W AIC_EOSCR 0xFFF8_2130 W End of Service Command Register Undefined --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- BITS DESCRIPTIONS [31:0] EOSCR This register is used by the interrupt service routine to indicate that it is completely served. Thus, the interrupt handler can write any value to this register to indicate the end of its interrupt service. AIC ICE/Debug Register (AIC_TEST) REGISTER ADDRESS R/W AIC_TEST 0xFFF8_2200 W ICE/Debug mode Register Undefined RESERVED RESERVED RESERVED RESERVED TEST

388 - BITS DESCRIPTIONS [31:1] Reserved Reserved [0] TEST This register indicates whether AIC_IPER will be cleared or not after been read. If bit0 of AIC_TEST has been set, ICE or debug monitor can read AIC_IPER for verification and the AIC_IPER will not be cleared automatically. Write access to the AIC_IPER will perform the interrupt stacking in this mode. TEST: ICE/Debug mode 0 = normal mode. 1 = ICE/Debug mode.

Publication Release Date: September 19, 2006 - 389 - Revision B2

6.15 General-Purpose Input/Output

The General-Purpose Input/Output (GPIO) module possesses 71 pins and serves multiple function purposes. Each port can be configured by software to meet various system configurations and design requirements. Software must configure each pin before starting the main program. If a pin is not used for multiplexed functions, the pin can be configured as I/O port Two extended interrupts nIRQ4 (GPIO0 pin) and nIRQ5 (nWAIT pin) are used the same interrupt request (channel #31) of AIC. It can be programmed as low/high sensitive or positive/negative edge triggered. When interrupt #31 assert in AIC, software can poll XISTATUS status register to identify which interrupt occur. These 71 IO pins are divided into 7 groups according to its peripheral interface definition. y Port0: 5-pin input/output port y Port1: 10-pin input/output port y Port2: 10-pin input/output port y Port3: 8-pin input/output port y Port4: 11-pin input/output port y Port5: 15-pin input/output port y Port6: 12-pin input/output port Table 6.16.1 GPIO multiplexed functions table PORT0 Configurable Pin Functions GPIO0 AC97_nRESET (I2S_MCLK) nIRQ4 USBPWREN GPIO1 AC97_DATAI (I2S_DATAI) PWM0 DTR3 GPIO2 AC97_DATAO (I2S_DATAO) PWM1 DSR3 GPIO3 AC97_SYNC (I2S_LRCLK) PWM2 TXD3 GPIO4 AC97_BITCLK (I2S_BITCLK) PWM3 RXD3 PORT1 Configuration Pin Functions GPIO20 SC1_PWR nXDACK VD8 GPIO21 SC1_PRES nXDREQ VD9 GPIO22 SC1_RST SD_CD VD10 GPIO23 SC1_CLK VD11 GPIO24 SC1_DAT SD_DAT3 VD12 GPIO25 SC0_PWR SD_DAT2 VD13

390 - Table 6.16.1 GPIO multiplexed functions table, continued GPIO26 SC0_PRES SD_DAT1 VD14 GPIO27 SC0_RST SD_DAT0 VD15 GPIO28 SC0_CLK SD_CLK VD16 GPIO29 SC0_DAT SD_CMD VD17 PORT2 Configuration Pin Functions GPIO42 PHY_RXERR KPCOL0 GPIO43 PHY_CRSDV KPCOL1 GPIO44 PHY_RXD[0] KPCOL2 GPIO45 PHY_RXD[1] KPCOL3 GPIO46 PHY_REFCLK KPCOL4 GPIO47 PHY_TXEN KPCOL5 GPIO48 PHY_TXD[0] KPCOL6 GPIO49 PHY_TXD[1] KPCOL7 GPIO50 PHY_MDIO KPROW0 GPIO51 PHY_MDC KPROW1 PORT3 Configuration Pin Functions GPIO60 D24 VD16 GPIO61 D25 VD17 GPIO62 D26 VD18 GPIO63 D27 VD19 GPIO64 D28 VD20 GPIO65 D29 VD21 GPIO66 D30 VD22 GPIO67 D31 VD23 PORT4 Configuration Pin Functions GPIO52 D16 VD8 GPIO53 D17 VD9 GPIO54 D18 VD10 GPIO55 D19 VD11 GPIO56 D20 VD12 GPIO57 D21 VD13 GPIO58 D22 VD14

Publication Release Date: September 19, 2006 - 391 - Revision B2 Table 6.16.1 GPIO multiplexed functions table, continued GPIO59 D23 VD15 GPIO68 nWBE2/SDQM2 GPIO69 nWBE3/SDQM3 GPIO70 nWAIT nIRQ5 PORT5 Configuration Pin Functions GPIO5 TXD0 GPIO6 RXD0 GPIO7 TXD1 GPIO8 RXD1 GPIO9 TXD2 CTS1 PS2CLK GPIO10 RXD2 RTS1 PS2DATA GPIO11 SCL0 SFRM TIMER0 GPIO12 SDA0 SSPTXD TIMER1 GPIO13 SCL1 SCLK KPROW3 GPIO14 SDA1 SSPRXD KPROW2 GPIO15 nWDOG USBPWREN GPIO16 nIRQ0 GP1O17 nIRQ1 USBOVRCUR GPIO18 nIRQ2 GPIO19 nIRQ3 PORT6 Configuration Pin Function GPIO30 VCLK KPROW0 GPIO31 VDEN KPROW1 GPIO32 VSYNC KPROW2 GPIO33 HSYNC KPROW3 GPIO34 VD0 KPCOL0 GPIO35 VD1 KPCOL1 GPIO36 VD2 KPCOL2 GPIO37 VD3 KPCOL3 GPIO38 VD4 KPCOL4 GPIO39 VD5 KPCOL5 GPIO40 VD6 KPCOL6 GPIO41 VD7 KPCOL7

392 -

6.15.1 GPIO Control Registers Map

Publication Release Date: September 19, 2006 - 393 - Revision B2 GPIO Control Registers Map, continued REGISTER ADDRESS R/W GPIO_CFG5 0xFFF8_3050 R/W GPIO port5 configuration register 0x0000_0000 GPIO_DIR5 0xFFF8_3054 R/W GPIO port5 direction control register 0x0000_0000 GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO port5 data output register 0x0000_0000 GPIO_DATAIN5 0xFFF8_305C R GPIO port5 data input register 0xXXXX_XXXX GPIO_CFG6 0xFFF8_3060 R/W GPIO port6 configuration register 0x0000_0000 GPIO_DIR6 0xFFF8_3064 R/W GPIO port6 direction control register 0x0000_0000 GPIO_DATAOUT6 0xFFF8_3068 R/W GPIO port6 data output register 0x0000_0000 GPIO_DATAIN6 0xFFF8_306C R GPIO port6 data input register 0xXXXX_XXXX GPIO_DBNCECON 0xFFF8_3070 R/W GPIO input debounce control register 0x0000_0000 GPIO_XICFG 0xFFF8_3074 R/W Extend Interrupt Configure Register 0xXXXX_XXX0 GPIO_XISTATUS 0xFFF8_3078 R/W Extend Interrupt Status Register 0xXXXX_XXX0

6.15.2 GPIO Register Description

GPIO Port0 Configuration Register (GPIO_CFG0) REGISTER ADDRESS R/W GPIO_CFG0 0xFFF8_3000 R/W GPIO port0 configuration register 0x0000_0000 RESERVED RESERVED RESERVED PT0CFG4 PT0CFG3 PT0CFG2 PT0CFG1 PT0CFG0

394 - PT0CFG0 Name Type Name Type Name Type Name Type PORT00 USB_PWREN O nIRQ4 AC97RESET or I2SMCLK O GPIO0 I/O PT0CFG1 Name Type Name Type Name Type Name Type PORT0_1 DTR3 O PWM0 O AC97DATAI or I2SDATAI O GPIO1 I/O PT0CFG2 Name Type Name Type Name Type Name Type PORT0_2 DSR3 I PWM1 O AC97DATAO or I2SDATAO O GPIO2 I/O PT0CFG3 Name Type Name Type Name Type Name Type PORT0_3 TXD3 O PWM2 O AC97SYNC or I2SLRCLK O GPIO3 I/O PT0CFG4 Name Type Name Type Name Type Name Type PORT0_4 RXD3 I PWM3 O AC97BITCLK or I2SBITCLK I O GPIO4 I/O GPIO Port0 Direction Register (GPIO_DIR0) REGISTER ADDRESS R/W

GPIO_DIR0 0xFFF8_3004 R/W GPIO port0 in/out direction control and pull-up enable register 0x0000_0000

Publication Release Date: September 19, 2006 - 395 - Revision B2 RESERVED RESERVED PUPEN0[3:0] RESERVED RESERVED OMDEN0[4:0] Bits [31:20] RESERVED [19:16] PUPEN0 GPIO3 -GPIO0 port pin internal pull-up resister enable There are 4 bits for this register, the corresponding bit is set to “1” will enable pull-up resister on IO pin. 1 = enable 0 = disable After power on the pull-up resisters are disabled. NOTE: GPIO4 is used as AC97 BITCLK input, an IO pad with Schmitt trigger input buffer PDB04SDGZ is implemented for this pin. Due to TSMC IO library without pull-up register, an external pull-up resister is necessary. [15:5] RESERVED [4:0] OMDEN0 GPIO4 ~GPIO0 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT0CFG4-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port0 Data Output Register (GPIO_DATAOUT0) REGISTER ADDRESS R/W GPIO_DATAOUT0 0xFFF8_3008 R/W GPIO port0 data output register 0x0000_0000

396 - RESERVED RESERVED RESERVED RESERVED DATAOUT0 BITS

[31:5] RESERVED [4:0] DATAOUT0 PORT0 data output value Writing data to this register will reflect the data value on the corresponding pin when it is configured as general output pin. And writing data to reserved bits is not effective. GPIO Port0 Data Input Register (GPIO_DATAIN0) REGISTER ADDRESS R/W GPIO_DATAIN0 0xFFF8_300C R/W GPIO port0 data input register 0xXXXX_XXXX RESERVED RESERVED RESERVED RESERVED DATAIN0 BITS [31:5] RESERVED [4:0] DATAIN0 PORT0 data input value The DATAIN0 indicates the status of each GPIO0~GPIO4 port pin regardless of its operation mode. The reserved bits will be read as “0”.

Publication Release Date: September 19, 2006 - 397 - Revision B2 GPIO Port1 Configuration Register (GPIO_CFG1) REGISTER ADDRESS R/W GPIO_CFG1 0xFFF8_3010 R/W GPIO port1 configuration register 0x0000_0000 RESERVED RESERVED PT1CFG9 PT1CFG8 PT1CFG7 PT1CFG6 PT1CFG5 PT1CFG4 PT1CFG3 PT1CFG2 PT1CFG1 PT1CFG0 *In the following pin definition, mark with shading is default function. PT1CFG0 Name Type Name Type Name Type Name Type PORT1_0 VD8 SC1_PWR O nXDACK O GPIO20 I/O PT1CFG1 Name Type Name Type Name Type Name Type PORT1_1 VD9 SC1_PRES I nXDREQ I GPIO21 I/O PT1CFG2 Name Type Name Type Name Type Name Type PORT1_2 VD10 SC1_RST O SD_CD I GPIO22 I/O PT1CFG3 Name Type Name Type Name Type Name Type PORT1_3 VD11 SC1_CLK O RESERVED GPIO23 I/O PT1CFG4 Name Type Name Type Name Type Name Type PORT1_4 VD12 SC1_DAT O SD_DAT3 I/O GPIO24 I/O

398 - PT1CFG5 Name Type Name Type Name Type Name Type PORT1_5 VD13 SC0_PWR O SD_DAT2 I/O GPIO25 I/O PT1CFG6 Name Type Name Type Name Type Name Type PORT1_6 VD14 SC0_PRES O SD_DAT1 I/O GPIO26 I/O PT1CFG7 Name Type Name Type Name Type Name Type PORT1_7 VD15 SC0_RST O SD_DAT0 I/O GPIO27 I/O PT1CFG8 Name Type Name Type Name Type Name Type PORT1_8 VD16 SC0_CLK O SD_CLK O GPIO28 I/O PT1CFG9 Name Type Name Type Name Type Name Type PORT1_9 VD17 SC0_DAT O SD_CMD I/O GPIO29 I/O GPIO Port1 Direction Register (GPIO_DIR1) REGISTER ADDRESS R/W

GPIO_DIR1 0xFFF8_3014 R/W GPIO port0 in/out direction control and pull-up enable register 0x0000_0000 RESERVED PUPEN1[9:8] PUPEN1[7:0] RESERVED OMDEN1[9:8] OMDEN1[7:0]

Publication Release Date: September 19, 2006 - 399 - Revision B2 BITS [31:26] RESERVED [25:16] PUPEN1 GPIO51 ~ GPIO42 port pins internal pull-up resister enable This is a 10-bit registers, set corresponding bit to “1” will enable pull up resister in IO pin. 1 = enable 0 = disable After power on the resisters are disabled. [15:10] RESERVED [9:0] OMDEN1 PIO51 ~ GPIO42 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT1CFG9-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port1 Data Output Register (GPIO_DATAOUT1) REGISTER ADDRESS R/W GPIO_DATAOUT1 0xFFF8_3018 R/W GPIO port1 data output register 0x0000_0000 RESERVED RESERVED RESERVED DATAOUT1[9:8] DATAOUT1[7:0] BITS [31:10] RESERVED [9:0] DATAOUT1 PORT1 data output value Writing data to this register will reflect the data value on the corresponding port1 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective.

400 - GPIO Port1 Data Input Register (GPIO_DATAIN1) REGISTER ADDRESS R/W

GPIO_DATAIN1 0xFFF8_301C R/W GPIO port1 data input register 0xXXXX_XXXX RESERVED RESERVED RESERVED DATAIN1[9:8] DATAIN1[7:0] BITS [31:10] RESERVED [9:0] DATAIN1 Port1 input data register The DATAIN1 indicates the status of each GPIO29~GPIO20 pin regardless of its operation mode. The reserved bits are read as 0s. GPIO Port2 Configuration Register (GPIO_CFG2) REGISTER ADDRESS R/W GPIO_CFG2 0xFFF8_3020 R/W GPIO port2 configuration register 0x0000_0000 RESERVED RESERVED PT2CFG9 PT2CFG8 PT2CFG7 PT2CFG6 PT2CFG5 PT2CFG4 PT2CFG3 PT2CFG2 PT2CFG1 PT2CFG0

Publication Release Date: September 19, 2006 - 401 - Revision B2 *In the following pin definition, mark with shading is default function. PT2CFG0 Name Type Name Type Name Type Name Type PORT2_0 VD8 O KPCOL0 I PHY_RXERR I GPIO42 I/O PT2CFG1 Name Type Name Type Name Type Name Type PORT2_1 VD9 O KPCOL1 I PHY_CRSDV I GPIO43 I/O PT2CFG2 Name Type Name Type Name Type Name Type PORT2_2 VD10 O KPCOL2 I PHY_RXD[0] I GPIO44 I/O PT2CFG3 Name Type Name Type Name Type Name Type PORT2_3 VD11 O KPCOL3 I PHY_RXD[1] I GPIO45 I/O PT2CFG4 Name Type Name Type Name Type Name Type PORT2_4 VD12 O KPCOL4 I PHY_REFCLK I GPIO46 I/O PT2CFG5 Name Type Name Type Name Type Name Type PORT2_5 VD13 O KPCOL5 I PHY_TXEN O GPIO47 I/O PT2CFG6 Name Type Name Type Name Type Name Type PORT2_6 VD14 O KPCOL6 I PHY_TXD[0] O GPIO48 I/O PT2CFG7 Name Type Name Type Name Type Name Type PORT2_7 VD15 O KPCOL7 I PHY_TXD[1] O GPIO49 I/O PT2CFG8 Name Type Name Type Name Type Name Type PORT2_8 VD16 O KPROW0 O PHY_MDIO I/O GPIO50 I/O

402 - PT2CFG9 Name Type Name Type Name Type Name Type PORT2_9 VD17 O KPROW1 O PHY_MDC O GPIO51 I/O GPIO Port2 Direction Register (GPIO_DIR2) REGISTER ADDRESS R/W

GPIO_DIR2 0xFFF8_3024 R/W GPIO port2 in/out direction control and pull-up enable register 0x0000_0000 RESERVED PUPEN2[9:8] PUPEN2[7:0] RESERVED OMDEN2[9:8] OMDEN2[7:0] BITS [31:26] RESERVED [25:16] PUPEN2 GPIO51 ~ GPIO42 port pin internal pull-up resister enable This is a 10-bit register, write corresponding bit “1” will enable pull –up resister in the IO pin. 1 = enable 0 = disable After power on, the registers are disabled. [15:10] RESERVED [9:0] OMDEN2 GPIO51 ~ GPIO42 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT2CFG7-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit.

Publication Release Date: September 19, 2006 - 403 - Revision B2 PGPIO Port2 Data Output Register (GPIO_DATAOUT2) REGISTER ADDRESS R/W GPIO_DATAOUT2 0xFFF8_3028 R/W GPIO port2 data output register 0x0000_0000 RESERVED RESERVED RESERVED DATAOUT2[9:8] DATAOUT2[7:0] BITS [31:10] RESERVED [9:0] DATAOUT2 PORT2 data output value Writing data to this register will reflect the data value on the corresponding port2 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. GPIO Port2 Data Input Register (GPIO_DATAIN2) REGISTER ADDRESS R/W GPIO_DATAIN2 0xFFF8_302C R/W GPIO port2 data input register 0xXXXX_XXXX RESERVED RESERVED RESERVED DATAIN2[9:8] DATAIN2[7:0]

404 - BITS

[31:10] RESERVED [9:0] DATAIN2 Port2 input data register The DATAIN2 indicates the status of each GPIO42~GPIO51 pin regardless of its operation mode. The reserved bits will be read as 0s. GPIO Port3 Configuration Register (GPIO_CFG3) REGISTER ADDRESS R/W GPIO_CFG3 0xFFF8_3030 R/W GPIO port3 configuration register 0x0000_5555 RESERVED RESERVED PT3CFG7 PT3CFG6 PT3CFG5 PT3CFG4 PT3CFG3 PT3CFG2 PT3CFG1 PT3CFG0 *In the following pin definition, mark with shading is default function. PT3CFG0 Name Type Name Type Name Type Name Type PORT3_0 RESERVED VD16 O D24 I/O GPIO60 I/O PT3CFG1 Name Type Name Type Name Type Name Type PORT3_1 RESERVED VD17 O D25 I/O GPIO61 I/O PT3CFG2 Name Type Name Type Name Type Name Type PORT3_2 RESERVED VD18 O D26 I/O GPIO62 I/O

Publication Release Date: September 19, 2006 - 405 - Revision B2 PT3CFG3 Name Type Name Type Name Type Name Type PORT3_3 RESERVED VD19 O D27 I/O GPIO63 I/O PT3CFG4 Name Type Name Type Name Type Name Type PORT3_4 RESERVED VD20 O D28 I/O GPIO64 I/O PT3CFG5 Name Type Name Type Name Type Name Type PORT3_5 RESERVED VD21 O D29 I/O GPIO65 I/O PT3CFG6 Name Type Name Type Name Type Name Type PORT3_6 RESERVED VD22 O D30 I/O GPIO66 I/O PT3CFG7 Name Type Name Type Name Type Name Type PORT3_7 RESERVED VD23 O D31 I/O GPIO67 I/O GPIO Port3 Direction Register (GPIO_DIR3) REGISTER ADDRESS R/W GPIO_DIR3 0xFFF8_3034 R/W GPIO port3 in/out direction control and pull-up enable register 0x0000_0000 RESERVED PUPEN3[7:0] RESERVED OMDEN3[7:0]

406 - BITS

[31:24] RESERVED [23:16] PUPEN2 After power on, the registers are disabled. [15:8] RESERVED GPIO67 ~ GPIO60 port pin internal pull-up resister enable 1 = enable 0 = disable After power on the pull-up registers are disabled [7:0] OMDEN2 GPIO67 ~ GPIO60 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT3CFG7-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port3 Data Output Register (GPIO_DATAOUT3) REGISTER ADDRESS R/W GPIO_DATAOUT3 0xFFF8_3038 R/W GPIO port3 data output register 0x0000_0000 RESERVED RESERVED RESERVED DATAOUT3[7:0] BITS [31:8] RESERVED [7:0] DATAOUT3 PORT3 data output value Writing data to this register will reflect the data value on the corresponding port3 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective.

Publication Release Date: September 19, 2006 - 407 - Revision B2 GPIO Port3 Data Input Register (GPIO_DATAIN3) REGISTER ADDRESS R/W GPIO_DATAIN3 0xFFF8_303C R/W GPIO port3 data input register 0xXXXX_XXXX RESERVED RESERVED RESERVED DATAIN3[7:0] BITS [31:8] RESERVED [7:0] DATAIN3 Port3 input data register The DATAIN3 indicates the status of each GPIO67~GPIO60 pin regardless of its operation mode. The reserved bits will be read as 0s. GPIO Port4 Configuration Register (GPIO_CFG4) REGISTER ADDRESS R/W GPIO_CFG4 0xFFF8_3040 R/W GPIO port4 configuration register 0x0015_5555 RESERVED RESERVED PT4CFG10 PT4CFG9 PT4CFG8 PT4CFG7 PT4CFG6 PT4CFG5 PT4CFG4 PT4CFG3 PT4CFG2 PT4CFG1 PT4CFG0

408 - *In the following pin definition, mark with shading is default function. PT4CFG0 Name Type Name Type Name Type Name Type PORT4_0 RESERVED VD8 O D16 I/O GPIO52 I/O PT4CFG1 Name Type Name Type Name Type Name Type PORT4_1 RESERVED VD9 O D17 I/O GPIO53 I/O PT4CFG2 Name Type Name Type Name Type Name Type PORT4_2 RESERVED VD10 O D18 I/O GPIO54 I/O PT4CFG3 Name Type Name Type Name Type Name Type PORT4_3 RESERVED VD11 O D19 I/O GPIO55 I/O PT4CFG4 Name Type Name Type Name Type Name Type PORT4_4 RESERVED VD12 O D20 I/O GPIO56 I/O PT4CFG5 Name Type Name Type Name Type Name Type PORT4_5 RESERVED VD13 O D21 I/O GPIO57 I/O PT4CFG6 Name Type Name Type Name Type Name Type PORT4_6 RESERVED VD14 O D22 I/O GPIO58 I/O PT4CFG7 Name Type Name Type Name Type Name Type PORT4_7 RESERVED VD15 O D23 I/O GPIO59 I/O

Publication Release Date: September 19, 2006 - 409 - Revision B2 PT4CFG8 Name Type Name Type Name Type Name Type PORT4_8 RESERVED RESERVED nWBE2/SDQM2 I/O GPIO68 I/O PT4CFG9 Name Type Name Type Name Type Name Type PORT4_9 RESERVED RESERVED nWBE3/SDQM3 I/O GPIO69 I/O PT4CFG10 Name Type Name Type Name Type Name Type PORT4_10 RESERVED nIRQ5 nWAIT I GPIO70 I/O GPIO Port4 Direction Register (GPIO_DIR4) REGISTER ADDRESS R/W GPIO_DIR4 0xFFF8_3044 R/W GPIO port4 in/out direction control and pull-up enable register 0x0000_0000 RESERVED PUPEN4[10:8] PUPEN4[7:0] RESERVED OMDEN4[10:8] OMDEN4[7:0] BITS [31:27] RESERVED [26:16] PUPEN4 GPIO70~GPIO68 and GPIO59~GPIO52 pin internal pull-up resister enable 1 = enable 0 = disable [15:11] RESERVED

410 - Continued BITS

[10:0] OMDEN4 GPIO70~GPIO68 and GPIO59~GPIO52 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT4CFG10-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port4 Data Output Register (GPIO_DATAOUT4) REGISTER ADDRESS R/W GPIO_DATAOUT4 0xFFF8_3048 R/W GPIO port4 data output register 0x0000_0000 RESERVED RESERVED RESERVED DATAOUT4[10:8] DATAOUT4[7:0] BITS [31:11] RESERVED [10:0] DATAOUT4 PORT4 data output value Writing data to this register will reflect the data value on the corresponding port4 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. GPIO Port4 Data Input Register (GPIO_DATAIN4) REGISTER ADDRESS R/W GPIO_DATAIN4 0xFFF8_304C R/W GPIO port4 data input register 0xXXXX_XXXX

Publication Release Date: September 19, 2006 - 411 - Revision B2 RESERVED RESERVED RESERVED DATAIN4[10:8] DATAIN3[7:0] BITS [31:11] RESERVED [10:0] DATAIN4 Port4 input data register The DATAIN4 indicates the status of each GPIO52~GPIO59, GPIO68 and GPIO69 pin regardless of its operation mode. The reserved bits will be read as 0s GPIO Port5 Configuration Register (GPIO_CFG5) REGISTER ADDRESS R/W GPIO_CFG5 0xFFF8_3050 R/W GPIO port5 configuration register 0x0000_0000 RESERVED PT5CFG14 PT5CFG13 PT5CFG12 PT5CFG11 PT5CFG10 PT5CFG9 PT5CFG8 PT5CFG7 PT5CFG6 PT5CFG5 PT5CFG4 PT5CFG3 PT5CFG2 PT5CFG1 PT5CFG0 *In the following pin definition, mark with shading is default function. PT5CFG0 Name Type Name Type Name Type Name Type PORT5_0 RESERVED RESERVED TXD0 O GPIO5 I/O

412 - PT5CFG1 Name Type Name Type Name Type Name Type PORT5_1 RESERVED RESERVED RXD0 I GPIO6 I/O PT5CFG2 Name Type Name Type Name Type Name Type PORT5_2 RESERVED RESERVED TXD1 O GPIO7 I/O PT5CFG3 Name Type Name Type Name Type Name Type PORT5_3 RESERVED RESERVED RXD1 I GPIO8 I/O PT5CFG4 Name Type Name Type Name Type Name Type PORT5_4 PS2CLK O CTS1 I TXD2 O GPIO9 I/O PT5CFG5 Name Type Name Type Name Type Name Type PORT5_5 PS2DATA I/O RTS1 O RXD2 I GPIO10 I/O PT5CFG6 Name Type Name Type Name Type Name Type PORT5_6 TIMER0 O SFRM O SCL0 I/O GPIO11 I/O PT5CFG7 Name Type Name Type Name Type Name Type PORT5_7 TIMER1 O SSPTX D O SDA0 I/O GPIO12 I/O PT5CFG8 Name Type Name Type Name Type Name Type PORT5_8 KPROW3 O SSPSCLK O SCL1 I/O GPIO13 I/O

Publication Release Date: September 19, 2006 - 413 - Revision B2 PT5CFG9 Name Type Name Type Name Type Name Type PORT5_9 KPROW2 O SSPRXD I/O SDA1 I/O GPIO14 I/O PT5CFG10 Name Type Name Type Name Type Name Type PORT5_10 RESERVED USBPWREN O nWDOG O GPIO15 I/O PT5CFG11 Name Type Name Type Name Type Name Type PORT5_11 RESERVED RESERVED nIRQ0 I GPIO16 I/O PT5CFG12 Name Type Name Type Name Type Name Type PORT5_12 RESERVED USBOVCUR I nIRQ1 I GPIO17 I/O PT5CFG13 Name Type Name Type Name Type Name Type PORT5_13 RESERVED RESERVED nIRQ2 I GPIO18 I/O PT5CFG14 Name Type Name Type Name Type Name Type PORT5_14 RESERVED RESERVED nIRQ3 I GPIO19 I/O GPIO Port5 Direction Register (GPIO_DIR5) REGISTER ADDRESS R/W GPIO_DIR5 0xFFF8_3054 R/W GPIO port5 in/out direction control and pull-up enable register 0x0000_0000

414 - RESERVED PUPEN5[14:8] PUPEN5[7:0] RESERVED OMDEN5[14:8] OMDEN5[7:0] BITS

[31] RESERVED [30:16] PUPEN5 GPIO19 ~ GPIO5 port pin internal pull-up resister enable 1 = enable 0 = disable [15] RESERVED [14:0] OUTEN5 GPIO19 ~ GPIO5 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT5CFG9-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port5 Data Output Register (GPIO_DATAOUT5) REGISTER ADDRESS R/W GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO port5 data output register 0x0000_0000 RESERVED RESERVED RESERVED DATAOUT5[14:8] DATAOUT5[7:0]

Publication Release Date: September 19, 2006 - 415 - Revision B2 BITS [31:15] RESERVED [14:0] DATAOUT5 PORT5 data output value Writing data to this register will reflect the data value on the corresponding port5 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective. GPIO Port5 Data Input Register (GPIO_DATAIN5) REGISTER ADDRESS R/W GPIO_DATAIN5 0xFFF8_305C R/W GPIO port4 data input register 0xXXXX_XXXX RESERVED RESERVED RESERVED DATAIN5[14:8] DATAIN5[7:0] BITS [31:15] RESERVED [14:0] DATAIN5 Port5 input data register The DATAIN5 indicates the status of each GPIO19~GPIO5 pin regardless of its operation mode. The reserved bits will be read as 0s. GPIO Port6 Configuration Register (GPIO_CFG6) REGISTER ADDRESS R/W GPIO_CFG6 0xFFF8_3060 R/W GPIO port6 configuration register 0x0000_0000

416 - RESERVED PT6CFG11 PT6CFG10 PT6CFG9 PT6CFG8 PT6CFG7 PT6CFG6 PT6CFG5 PT6CFG4 PT6CFG3 PT6CFG2 PT6CFG1 PT6CFG0 *In the following pin definition, mark with shading is default function. PT6CFG0 Name Type Name Type Name Type Name Type PORT6_0 RESERVED KPROW0 O VCLK O GPIO30 I/O PT6CFG1 Name Type Name Type Name Type Name Type PORT6_1 RESERVED KPROW1 O VDEN O GPIO31 I/O PT6CFG2 Name Type Name Type Name Type Name Type PORT6_2 RESERVED KPROW2 O VSYNC O GPIO32 I/O PT6CFG3 Name Type Name Type Name Type Name Type PORT6_3 RESERVED KPROW3 O HSYNC O GPIO33 I/O PT6CFG4 Name Type Name Type Name Type Name Type PORT6_4 RESERVED KPCOL0 I VD0 O GPIO34 I/O

Publication Release Date: September 19, 2006 - 417 - Revision B2 PT6CFG5 Name Type Name Type Name Type Name Type PORT6_5 RESERVED KPCOL1 I VD1 O GPIO35 I/O PT6CFG6 Name Type Name Type Name Type Name Type PORT6_6 RESERVED KPCOL2 I VD2 O GPIO36 I/O PT6CFG7 Name Type Name Type Name Type Name Type PORT6_7 RESERVED KPCOL3 I VD3 O GPIO37 I/O PT6CFG8 Name Type Name Type Name Type Name Type PORT6_8 RESERVED KPCOL4 I VD4 O GPIO38 I/O PT6CFG9 Name Type Name Type Name Type Name Type PORT6_9 RESERVED KPCOL5 I VD5 O GPIO39 I/O PT6CFG10 Name Type Name Type Name Type Name Type PORT6_10 RESERVED KPCOL6 I VD6 O GPIO40 I/O PT6CFG11 Name Type Name Type Name Type Name Type PORT6_11 RESERVED KPCOL7 I VD7 O GPIO41 I/O GPIO Port6 Direction Register (GPIO_DIR6) REGISTER ADDRESS R/W GPIO_DIR6 0xFFF8_3064 R/W GPIO port5 in/out direction control and pull-up enable register 0x0000_0000

418 - RESERVED PUPEN6[11:8] PUPEN6[7:0] RESERVED OMDEN6[11:8] OMDEN6[7:0] BITS

[31:27] RESERVED [26:16] PUPEN6 GPIO30 ~GPIO41 port pin internal pull-up resister enable 1 = enable 0 = disable [15:13] RESERVED [12:0] OMDEN6 GPIO41 ~ GPIO30 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT6CFG11-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit. GPIO Port6 Data Output Register (GPIO_DATAOUT6) REGISTER ADDRESS R/W GPIO_DATAOUT6 0xFFF8_3068 R/W GPIO port6 data output register 0x0000_0000 RESERVED RESERVED RESERVED DATAOUT6[11:8] DATAOUT6[7:0]

Publication Release Date: September 19, 2006 - 419 - Revision B2 BITS [31:12] RESERVED [11:0] DATAOUT6 PORT6 data output value Writing data to this register will reflect the data value on the corresponding port6 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective GPIO Port6 Data Input Register (GPIO_DATAIN6) REGISTER ADDRESS R/W GPIO_DATAIN6 0xFFF8_306C R/W GPIO port6 data input register 0xXXXX_XXXX RESERVED RESERVED RESERVED DATAIN6[11:8] DATAIN6[7:0] BITS [31:12] RESERVED [11:0] DATAIN6 Port6 input data register The DATAIN6 indicates the status of each GPIO18~GPIO5 pin regardless of its operation mode. The reserved bits will be read as 0s. GPIO Debounce Control Register (GPIO_DBNCECON) REGISTER ADDRESS R/W GPIO_DBNCECON 0xFFF8_3070 R/W GPIO debounce control register 0xXXXX_XX00

420 - RESERVED RESERVED RESERVED RESERVED DBCLKSEL DBEN3 DBEN2 DBEN1 DBEN0 BITS

[31:7] RESERVED [6:4] DBCLKSEL Debounce Clock Selection These 3 bits are used to select the clock rate for de-bouncer circuit. The relationship between the system clock HCLK and the de-bounce clock TCLK_BUN is as follows: TCLK_BUN = HCLK / 2DBCLKSEL [3] DBEN3 Debounce circuit enable for GPIO19 (nIRQ3) 1 = enable 0 = disable [2] DBEN2 Debounce circuit enable for GPIO18 (nIRQ2) 1 = enable 0 = disable [1] DBEN1 Debounce circuit enable for GPIO17 (nIRQ1) 1 = enable 0 = disable [0] DBEN0 Debounce circuit enable for GPIO16 (nIRQ0) 1 = enable 0 = disable GPIO Interrupt Configuration Register (GPIO_XICFG) REGISTER ADDRESS R/W GPIO_XICFG 0xFFF8_3074 R/W Extend Interrupt Configure Register 0xXXXX_XX00

Publication Release Date: September 19, 2006 - 421 - Revision B2 RESERVED RESERVED RESERVED EnINT5 DBE5 ISTYPE5 EnINT4 DBE4 ISTYPE4 BITS [31:8] RESERVED [7] EnINT5 Enable INT5 Setting this bit 1 to enable extend interrupt 5. 1 = Enable interrupt 5 0 = Disable interrupt 5 The AIC interrupt channel 31 is reserved for interrupt 5 and 4 (wired-OR), if this bit is set and interrupt 5 occur, then it will send an interrupt request signal into AIC module. [6] DBE5 Debounce circuit enable for INT5 (alternative function of nWAIT pin) Extend interrupt 5 shares the same debounce circuit with nIRQ[3:0], software can configure debounce sampling time in GPIO_DEBNCE control register. DBE5 function is the same as DBE0 in GPIO_DBENCE register. 1 = Enable debounce 0 = Disable debounce [5:4] STYPE5 Interrupt 5 source type ISTYPE5 Interrupt Source Type 2’b00 LOW level sensitive 2’b01 HIGH level sensitive 2’b10 Negative edge triggered 2’b11 Positive edge triggered

422 - Continued BITS

[3] EnINT4 Enable INT4 Setting this bit 1 to enable extend interrupt 4 1 = Enable interrupt 4 0 = Disable interrupt 4 The AIC interrupt channel 31 is reserved for interrupt 5 and 4 (wire-OR), if this bit is set and interrupt 4 occur, then it will send an interrupt request signal into AIC module. [2] DBE4 Debounce circuit enable for INT4 (alternative function of GPIO0 pin) 1 = Enable debounce 0 = Disable debounce Extend interrupt 4 shares the same debounce circuit with nIRQ[3:0], software can configure debounce sampling time in GPIO_DEBNCE control register. DBE5 function is the same as DBE0 in GPIO_DBENCE register. [1:0] ISTYPE4 Interrupt 4 source type ISTYPE5 Interrupt Source Type 2’b00 LOW level sensitive 2’b01 HIGH level sensitive 2’b10 Negative edge triggered 2’b11 Positive edge triggered GPIO Interrupt Status Register (GPIO_XISTATUS) REGISTER ADDRESS R/W GPIO_XISTATUS 0xFFF8_3078 R/W Extend interrupt status (flag) register 0xXXXX_XX00 RESERVED RESERVED RESERVED RESERVED INT5 INT4

Publication Release Date: September 19, 2006 - 423 - Revision B2 BITS [31:2] RESERVED [1] INT5 Interrupt 5 status When interrupt input is detected with ISTYPE5 triggered condition, this flag will be set. It must be cleared by software. 1 = interrupt detected. 0 = No interrupt [0] INT4 Interrupt 4 status When interrupt input is detected with ISTYPE4 triggered condition, this flag will be set. It must be cleared by software. 1 = interrupt 4 is detected. 0 = no interrupt

424 -

6.16 Real Time Clock

Real Time Clock (RTC) block can be operated by independent power supply while the system power is off. The RTC block utilizes an external crystal to generate 32.768 KHz clock. The RTC can transmit data to CPU as BCD values. The data include the time by second, minute, hour and the date by day, month, and year. In addition, to reach better frequency accuracy, the RTC counter can be adjusted by software. RTC features are shown as below: y Time counter (second, minute, hour) and calendar counter (day, month, year). y Alarm register (second, minute, hour, day, month, year). y 12/24 hour mode selectable. y Recognize leap year automatically. y Day of the week counter. y Frequency compensate register (RTC_FCR). y Beside RTC_FCR, all clock and alarm data expressed in BCD code. y Support tick time interrupt RTC Initiation: When RTC block is power on, programmer has to write a number (0xa5eb1357) to RTC_INIR to reset all logic. RTC_INIR act as hardware reset circuit. Once RTC_INIR has been set as 0xa5eb1357, user cannot reload any other value. RTC write enable: Register RTC_AER bit 15~0 is RTC read /write password. It is used to avoid signal interference from system during system power off. RTC_AER bit 15~0 has to be set as 0xa965 before user want to write new data into all registers besides RTC_INIR. If user set RTC_AER as 0xa965, RTC_WRITE_EN will be raised high. Then user can feel free to write data into register. RTC_WRITE_EN will keep high for a short period (about 24ms) and it will be pull low by internal state machine automatically. Frequency Compensation: The RTC_FCR allows software control digital compensation of a 32.768 KHz crystal oscillator. User can utilize a frequency counter to measure RTC clock in one of GPIO pin during manufacture, and store the value in Flash memory for retrieval when the product is first power on. Time and Calendar counter: RTC_TLR and RTC_CLR are used to load the time and calendar. RTC_TAR and RTC_CAR are used as alarm. They are all BCD counters. 12/24 hour Time scale selection: The 12/24 hour time scale selection depend on RTC_TSSR bit 0. Day of the week counter: Count from Sunday to Saturday

Publication Release Date: September 19, 2006 - 425 - Revision B2 Tick Time interrupt: RTC block use a counter to calibrate the tick time count value. When the value in counter reaches zero, RTC will issue an interrupt. RTC register property: When system power is off but RTC power is on, data stored in RTC registers will not be lost except RTC_TSSR, RTC_RIER and RTC_RIIR. Because of difference between RTC clock and system clock, every time user write new data to any one register, the register will be updated until 2 RTC clock later (60us). In addition, user must be aware that RTC block does not check whether loaded data is out of bounds. RTC does not check rationality between RTC_DWR and RTC_CLR either.

426 -

6.16.1 RTC Register Map

RTC_INIR 0xFFF8_4000 R/W RTC Initiation Register RTC_AER 0xFFF8_4004 R/W RTC Access Enable Register 0x0000_0000 RTC_FCR 0xFFF8_4008 R/W RTC Frequency Compensation Register 0x0000_0700 RTC_TLR 0xFFF8_400C R/W Time Loading Register 0x0000_0000 RTC_CLR 0xFFF8_4010 R/W Calendar Loading Register 0x0005_0101 RTC_TSSR 0xFFF8_4014 R/W Time Scale Selection Register 0x0000_0001 RTC_DWR 0xFFF8_4018 R/W Day of the Week Register 0x0000_0006 RTC_TAR 0xFFF8_401C R/W Time Alarm Register 0x0000_0000 RTC_CAR 0xFFF8_4020 R/W Calendar Alarm Register 0x0000_0000 RTC_LIR 0xFFF8_4024 R Leap year Indicator Register 0x0000_0000 RTC_RIER 0xFFF8_4028 R/W RTC Interrupt Enable Register 0x0000_0000 RTC_RIIR 0xFFF8_402C R/C RTC Interrupt Indicator Register 0x0000_0000 RTC_TTR 0xFFF8_4030 R/W RTC Tick Time Register 0x0000_0000 RTC Initiation Register (RTC_INIR) REGISTER ADDRESS R/W RTC_INIR 0xFFF8_4000 R/W RTC Initiation Register INIR[31:24] INIR[23:16] INIR[15:8] INIR[7:0]

Publication Release Date: September 19, 2006 - 427 - Revision B2 BITS DESCRIPTIONS [31:0] INIR INIR [31:0]: The INIR register is used to replace hardware reset circuit. User must write INIR as “0xa5eb_1357” after RTC is power on. INIR [0]: R/W. Once RTC INIR has been written, user can access this bit to find out whether RTC reset signal is pulled high. RTC Access Enable Register (RTC_AER) REGISTER ADDRESS R/W RTC_AER 0xFFF8_4004 R/W RTC Access Enable Register 0X0000_0000 Reserved Reserved AER[16] AER[15:8] AER[7:0] BITS DESCRIPTIONS [31:17] Reserved [16:0] AER AER [16]: Read only 1 = RTC register write enable 0 = RTC register write disable AER[15:0]: Write only RTC register write enable/disable password 0xa965 = write enable 0x0000 = write disable

428 - RTC Frequency Compensation Register (RTC_FCR) REGISTER ADDRESS R/W

RTC_FCR 0xFFF8_4008 R/W RTC Frequency Compensation Register 0X0000_0700 Reserved Reserved Reserved FCR_int Reserved FCR_fra BITS DESCRIPTIONS [31:12] Reserved [11:8] FCR_int FCR [11:8]: Integer part Integer part of detected value FCR[11:8] Integer part of detected value FCR[11:8] 32776 1111 32768 0111 32775 1110 32767 0110 32774 1101 32766 0101 32773 1100 32765 0100 32772 1011 32764 0011 32771 1010 32763 0010 32770 1001 32762 0001 32769 1000 32761 0000 [5:0] FCR_fra Fraction part Formula: FCR_int = (fraction part of detected value) X 60 Note: Digit in FCR must be expressed as hexadecimal number.

Publication Release Date: September 19, 2006 - 429 - Revision B2 Continued BITS DESCRIPTIONS Example 1 Frequency counter measurement: 32773.65Hz Integer part: 32773 => FCR [11:8] = 0xc Fraction part: 0.65 X 60 = 39(0x27) => FCR[5:0]=0x27 FCR Calibration Example 2 Frequency counter measurement: 32765.27Hz Integer part: 32765=> FCR [11:8] = 0x4 Fraction part: 0.27 X 60 = 16.2(0x10) => FCR [5:0] = 0x10 RTC Time Loading Register (RTC_TLR) REGISTER ADDRESS R/W RTC_TLR 0xFFF8_400C R/W RTC Time Loading Register 0X0000_0000 Reserved Reserved Hi_hr Lo_hr Reserved Hi_min Lo_min Reserved Hi_sec Lo_sec Note: TLR is a BCD digit counter and RTC will not check loaded data. BITS DESCRIPTIONS [21:20] Hi_hr 10 hour time digit [19:16] Lo_hr 1 hour time digit [14:12] Hi_min 10 min time digit [11:8] Lo_min 1 min time digit [6:4] Hi_sec 10 sec time digit [3:0] Lo_sec 1 sec time digit

430 - RTC Calendar Loading Register (RTC_CLR) REGISTER ADDRESS R/W

RTC_CLR 0xFFF8_4010 R/W RTC Calendar Loading Register 0X0005_0101 Reserved Hi_year Lo_year Reserved Hi_mon Lo_mon Reserved Hi_day Lo_day Note: CLR is a BCD digit counter and RTC will not check loaded data. BITS DESCRIPTIONS [23:20] Hi_year 10-year calendar digit [19:16] Lo_year 1-year calendar digit [12] Hi_mon 10-month calendar digit [11:8] Lo_mon 1-month calendar digit [5:4] Hi_day 10-day calendar digit [3:0] Lo_day 1-day calendar digit RTC Time Scale Selection Register (RTC_TSSR) REGISTER ADDRESS R/W RTC_TSSR 0xFFF8_40014 R/W Time Scale Selection Register 0X0000_0001

Publication Release Date: September 19, 2006 - 431 - Revision B2 Reserved Reserved Reserved Reserved 24Hr/12Hr BITS DESCRIPTIONS [31:1] Reserved [0] 24Hr/12Hr 24Hr/12Hr : 24hour / 12 hour mode selection It indicate that TLR and TAR are in 24-hour mode or 12-hour mode 1 = select 24-hour time scale 0 = select 12-hour time scale with am and pm indication 24-hour time scale 12-hour time scale 24-hour time scale 12-hour time scale 12(AM12) 32(PM12) 01(AM01) 21(PM01) 02(AM02) 22(PM02) 03(AM03) 23(PM03) 04(AM04) 24(PM04) 05(AM05) 25(PM05) 06(AM06) 26(PM06) 07(AM07) 27(PM07) 08(AM08) 28(PM08) 09(AM09) 29(PM09) 10(AM10) 30(PM10) 11(AM11) 31(PM11)

432 - RTC Day of the Week Register (RTC_DWR) REGISTER ADDRESS R/W

RTC_DWR 0xFFF8_4018 R/W Day of the Week Register 0X0000_0006 Reserved Reserved Reserved Reserved DWR[2:0] BITS DESCRIPTIONS [31:3] Reserved [2:0] DWR DWR[2:0] : Day of the Week Register Sunday Monday Tuesday Wednesday Thursday Friday Saturday RTC Time Alarm Register (RTC_TAR) REGISTER ADDRESS R/W RTC_TAR 0xFFF8_401C R/W RTC Time Alarm Register 0X0000_0000

Publication Release Date: September 19, 2006 - 433 - Revision B2 Reserved Reserved Hi_hr_alarm Hi_hr_alarm Reserved Hi_min_alarm Lo_min_alarm Reserved Hi_sec_alarm Lo_sec_alarm TAR is a BCD digit register and RTC will not check loaded data. BITS DESCRIPTIONS [31:22] Reserved [21:20] Hi_hr_alarm 10 hour time digit [19:16] Lo_hr_alarm 1 hour time digit [15] Reserved [14:12] Hi_min_alarm 10 min time digit [11:8] Lo_min_alarm 1 min time digit [7] Reserved [6:4] Hi_sec_alarm 10 sec time digit [3:0] Lo_sec_alarm 1 sec time digit RTC Calendar Alarm Register (RTC_CAR) REGISTER ADDRESS R/W RTC_CAR 0xFFF8_4020 R/W RTC Calendar Alarm Register 0X0000_0000

434 - Reserved Hi_year_alarm Lo_year_alarm Reserved Hi_mon_ alarm Lo_mon_alarm Reserved Hi_day_alarm Lo_day_alarm CAR is a BCD digit register and RTC will not check loaded data. BITS DESCRIPTIONS [31:24] Reserved [23:20] Hi_year 10-year calendar digit [19:16] Lo_year 1-year calendar digit [15:13] Reserved [12] Hi_mon 10-month calendar digit [11:8] Lo_mon 1-month calendar digit [5:4] Hi_day 10-day calendar digit [3:0] Lo_day 1-day calendar digit RTC Leap year Indication Register (RTC_LIR) REGISTER ADDRESS R/W

RTC_LIR 0xFFF8_4024 R RTC Leap year Indication Register 0X0000_0000

Publication Release Date: September 19, 2006 - 435 - Revision B2 Reserved Reserved Reserved Reserved LIR[0] BITS DESCRIPTIONS [31:1] Reserved [0] LIR LIR [0]: Real only. Leap year Indication REGISTER 1 = It indicate that this year is leap year 0 = It indicate that this year is not a leap year RTC Interrupt Enable Register (RTC_RIER) REGISTER ADDRESS R/W RTC_RIER 0xFFF8_4028 R/W RTC Interrupt Enable Register 0X0000_0000 Reserved Reserved Reserved Reserved Tick_int_en Alarm_int_en

436 - BITS DESCRIPTIONS [31:2] Reserved [1] Tick_int_en 1 = RTC Time Tick Interrupt and counter enable 0 = RTC Time Tick Interrupt and counter disable [0] Alarm_int_en 1 = RTC Alarm Interrupt enable 0 = RTC Alarm Interrupt disable RTC Interrupt Indication Register (RTC_RIIR) REGISTER ADDRESS R/W

RTC_RIIR 0xFFF8_402C R/C RTC Interrupt Indication Register 0X0000_0000 Reserved Reserved Reserved Reserved Tick_int_st Alarm_int_st BITS DESCRIPTIONS [31:2] Reserved [1] Tick_int_st RTC Time Tick Interrupt Indication REGISTER 1 = It indicates that time tick interrupt has been activated. 0 = It indicates that time tick interrupt has never occurred. Software Can also clear this bit after RTC interrupt has occur.

Publication Release Date: September 19, 2006 - 437 - Revision B2 Continued BITS DESCRIPTIONS [0] Alarm_int_st RTC Alarm Interrupt Indication REGISTER 1 = It indicates that time counter and calendar counter have counted to a specified time recorded in TAR and CAR. RTC alarm interrupt has been activated. 0 = It indicates that alarm interrupt has never occurred. Software can Also clear this bit after RTC interrupt has occurred. Note : User can clear these two bits by writing 0x0 to RIIR RTC Tick Time Register (RTC_TTR) REGISTER ADDRESS R/W RTC_TTR 0xFFF8_4030 R/W RTC Tick Time Register 0X0000_0000 Reserved Reserved Reserved Reserved TTI

438 - BITS DESCRIPTIONS [31:3] Reserved [2:0] TTI RTC Tick Time Interrupt request Interval The TTR [2:0] is used to select tick time interrupt request interval. The period of tick time interrupt is as follow: TTR[2:0] Tick Time interrupt interval 1 sec 1/2 sec 1/4 sec 1/8 sec 1/16 sec 1/32 sec 1/64 sec 1/128 sec

Publication Release Date: September 19, 2006 - 439 - Revision B2

6.16.2 RTC Application Note

Step1. Configure GPIO register GPIOCFG5[21:20] as “2’b11” Step2. Making use of frequency counter (for example: Agilent 53131A) to detect W90P710 IO Pin “GPIO15/nWDOG/USBPWREN”. Note: Because the parasitic capacitance would slow crystal oscillation, do not connect the probe with 32K crystal directly. RTC application circuit The recommended RTC appliction circuit is ad following: EXTAL32 XTAL32 RTCVDD1.8V C1 and C2 can not be connected to ground for improving noise issue. Do not connect any register in the circuit. Redundant register may stop crystal oscillation. To avoid parastic capacitance and resistance, user had better to place all components as close as possible. The C1 and C2 vaule would be changed by different crystal because different crystal requires different oscillation condition. In general, capacitance value of C1/C2 is between 10pF and 30pF.

440 -

6.17 Smart Card Host Interface

The Smart Card resides in APB bus. The whole chip of W90P710 operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode. y ISO-7816 compliant y PC/SC T=0, T=1 compliant y 16-byte transmitter FIFO and 16-byte receiver FIFO y FIFO threshold interrupt to optimize system performance y Programmable transmission clock frequency y Versatile baud rate configuration y UART-like register file structure y Versatile 8-bit, 16-bit, 24-bit time-out counter for Answer-To-Reset (ATR) and waiting times processing. y Parity error counter in reception mode and in transmission mode with automatic re-transmission. y Automatic activation and deactivation sequence through an independence sequencer

6.17.1 Register Mapping

R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written. Table 6.12.2.1 Smart Card Host Interface 0 Register Map REGISTER ADDRESS R/W Smartcard Host Interface 0 SCHI_RBR0 0xFFF8_5000 (BDLAB=0) R Receiver Buffer Register Undefined SCHI_TBR0 0xFFF8_5000 (BDLAB=0) W Transmitter Buffer Register Undefined SCHI_IER0 0xFFF8_5004 (BDLAB=0) R/W Interrupt Enable Register 0x0000_0080 SCHI_ISR0 0xFFF8_5008 (BDLAB=0) R Interrupt Status Register 0X0000_00C1 SCHI_SCFR0 0xFFF8_5008 (BDLAB=0) W Smart card FIFO Control Register 0x0000_0000 SCHI_SCCR0 0xFFF8_500C R/W Smart card Control Register 0x0000_0018 SCHI_CBR0 0xFFF8_5010 R/W Clock Base Register 0x0000_000C SCHI_SCSR0 0xFFF8_5014 R Smart Card Status Register 0x0000_0060 SCHI_GTR0 0xFFF8_5018 R/W Guard Rime Register 0x0000_0001 SCHI_ECR0 0xFFF8_501C R/W Extended Control Register 0x0000_0052 SCHI_TMR0 0xFFF8_5020 R/W Test Mode Register 0x0000_0000 SCHI_TOC0 0xFFF8_5028 R/W Time out Configuration Register 0x0000_0000 SCHI_TOIR0_0 0xFFF8_502C R/W Time out Initial Register 0 0x0000_0000

Publication Release Date: September 19, 2006 - 441 - Revision B2 Table 6.12.2.1 Smart Card Host Interface 0 Register Map, continued REGISTER ADDRESS R/W SCHI_TOIR1_0 0xFFF8_5030 R/W Time out Initial Register 1 0x0000_0000 SCHI_TOIR2_0 0xFFF8_5034 R/W Time out Initial Register 2 0x0000_0000 SCHI_TOD0_0 0xFFF8_5038 R Time out Data Register 0 0x0000_00FF SCHI_TOD1_0 0xFFF8_503C R Time out Data Register 1 0x0000_00FF SCHI_TOD2_0 0xFFF8_5040 R Time out Data Register 2 0x0000_00FF SCHI_BTOR_0 0xFFF8_5044 R/W Buffer Time out Data Register 0x0000_0000 SCHI_BLL_0 0xFFF8_5000 (BDLAB=1) R/W Baud Rate Divisor Latch Lower Byte Register 0x0000_001F SCHI_BLH_0 0xFFF8_5004 (BDLAB=1) R/W Baud Rate Divisor Latch Higher Byte Register 0x0000_0000 SCHI_ID_0 0xFFF8_5008 (BDLAB=1) R Smart Card ID Number Register 0x0000_0070 Smartcard Host Interface 1 SCHI_RBR1 0xFFF8_5800 (BDLAB=0) R Receiver Buffer Register Undefined SCHI_TBR1 0xFFF8_5800 (BDLAB=0) W Transmitter Buffer Register Undefined SCHI_IER1 0xFFF8_5804 (BDLAB=0) R/W Interrupt Enable Register 0x0000_0080 SCHI_ISR1 0xFFF8_5808 (BDLAB=0) R Interrupt Status Register 0X0000_00C1 SCHI_SCFR1 0xFFF8_5808 (BDLAB=0) W Smart card FIFO Control Register 0x0000_0000 SCHI_SCCR1 0xFFF8_580C R/W Smart card Control Register 0x0000_0018 SCHI_CBR1 0xFFF8_5810 R/W Clock Base Register 0x0000_000C SCHI_SCSR1 0xFFF8_5814 R Smart Card Status Register 0x0000_0060 SCHI_GTR1 0xFFF8_5818 R/W Guard Rime Register 0x0000_0001 SCHI_ECR1 0xFFF8_581C R/W Extended Control Register 0x0000_0052 SCHI_TMR1 0xFFF8_5820 R/W Test Mode Register 0x0000_0000 SCHI_TOC1 0xFFF8_5828 R/W Time out Configuration Register 0x0000_0000 SCHI_TOIR0_1 0xFFF8_582C R/W Time out Initial Register 0 0x0000_0000 SCHI_TOIR1_1 0xFFF8_5830 R/W Time out Initial Register 1 0x0000_0000 SCHI_TOIR2_1 0xFFF8_5834 R/W Time out Initial Register 2 0x0000_0000 SCHI_TOD0_1 0xFFF8_5838 R Time out Data Register 0 0x0000_00FF SCHI_TOD1_1 0xFFF8_583C R Time out Data Register 1 0x0000_00FF SCHI_TOD2_1 0xFFF8_5840 R Time out Data Register 2 0x0000_00FF SCHI_BTOR1 0xFFF8_5844 R/W Buffer Time out Data Register 0x0000_0000 SCHI_BLL1 0xFFF8_5800 (BDLAB=1) R/W Baud Rate Divisor Latch Lower Byte Register 0x0000_001F SCHI_BLH1 0xFFF8_5804 (BDLAB=1) R/W Baud Rate Divisor Latch Higher Byte Register 0x0000_0000 SCHI_ID1 0xFFF8_5808 (BDLAB=1) R Smart Card ID Number Register 0x0000_0070

442 -

6.17.2 Register Description

Receive Buffer Register (SCHI_RBR) REGISTER ADDRESS R/W SCHI_RBR0 0XFFF8_5000 (DLAB = 0) R Receiver Buffer Register 0 Undefined SCHI_RBR1 0xFFF8_5800 (DLAB = 0) R Receiver Buffer Register 1 Undefined RESERVED RESERVED RESERVED RxBDATA[7:0] BITS DESCRIPTIONS [31:8] RESERVED [7:0] RxBDATA 8-bit Received Data By reading this register, the SCHI will return an 8-bit data received from SCx_DAT pin. This register is the access port for receiver FIFO. The depth of receiver FIFO is 16 bytes. Transmit Buffer Register (SCHI_TBR) REGISTER ADDRESS R/W SCHI_TBR0 0xFFF8_5000(DLAB = 0) W Transmit Buffer Register 0 Undefined SCHI_TBR1 0xFFF8_5800(DLAB = 0) W Transmit Buffer Register 1 Undefined

Publication Release Date: September 19, 2006 - 443 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED [7:0] TxBDATA 8-bit Transmit Buffer Data By writing to this register, the SCHI will send out an 8-bit data through the SCx_DAT pin. This register is the access port for transmitter FIFO. The depth of transmitter FIFO is 16 bytes. Interrupt Enable register (SCHI_IER) REGISTER ADDRESS R/W SCHI_IER0 0xFFF8_5004 (DLAB = 0) R/W Interrupt Enable Register 0 0x0000_0080 SCHI_IER1 0xFFF8_5804 (DLAB = 0) R/W Interrupt Enable Register 1 0x0000_0080 RESERVED RESERVED RESERVED TxBDATA[7:0] RESERVED RESERVED RESERVED ETOR2 ETOR1 ETOR0 PWRDN Interface RESERVED ESCPTI ESCSRI ETBREI ERDRI

444 - BITS DESCRIPTIONS [31:11] RESERVED [10] ETOR2 TOR2 interrupt enable bit When 24 bit time-out counter decrease to zero, it will set TO2 flag to high. If we set ETOR2 to high, then the 24 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. [9] ETOR1 TOR1 interrupt enable bit When 16 bit time-out counter decrease to zero, it will set TO1 flag to high. If we set ETOR1 to high, then the 16 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. [8] ETOR0 TOR0 interrupt enable bit When 8 bit time-out counter decrease to zero, it will set TO0 flag to high. If we set ETOR0 to high, then the 8 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. [7] PWRDN Smart card POWER DOWN bit PWRDN is used when the Smartcard controller needs to be powered down. Powering down must be done whenever the controller needs to switch between class A and B. When this bit is a ‘1’, it will deactivate all contacts to the Smartcard except for SCRST_L which will be discussed later. When the Smartcard is removed, the H/W will also set the POWER DOWN bit. [6] Interface Smart card different interface bit Interface is used for controlling the different power control device signals. When ‘1’, the controller will direct a power control pin is active high. When ‘0’, a power control pin is active low to meet different power control interface. [5:4] RESERVED Reserved for future [3] ESCPTI Smart card present toggle interrupt enable bit A rising/falling edge of SCPSNT signal triggers an interrupt if this bit is set to "1". 0 = SCPSNT toggle interrupt is disabled. 1 = SCPSNT toggle interrupt is enabled. [2] ESCSRI Enable SCSR interrupt bit An ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error, no stop bit error, parity bit error or overrun error. Any SCSR-related event as described above will trigger an interrupt if this bit is set to "1". 0 = SCSR-related event interrupt is disabled. 1 = SCSR-related event interrupt is enabled.

Publication Release Date: September 19, 2006 - 445 - Revision B2 Continued BITS DESCRIPTIONS [1] ETBREI Enable Transmit Buffer Empty interrupt bit An ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An interrupt is issued when TBR is empty and this bit is set to "1". 0 = TBR empty interrupt is disabled. 1 = TBR empty interrupt is enabled. [0] ERDRI Enable Receive Data Ready interrupt bit The active FIFO threshold level for this kind of interrupt when FIFO is enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of SCFR at base address + 8. Refer to description of SCFR for details). An interrupt is issued if a data byte is ready for host to read when FIFO is disabled or incoming data from card reaches active FIFO threshold level when FIFO is enabled. Interrupt Status Register (SCHI_ISR) REGISTER ADDRESS R/W SCHI_ISR0 0xFFF8_5008 (DLAB = 0) R Interrupt Status Register 0 0x0000_00C1 SCHI_ISR1 0xFFF8_5808 (DLAB = 0) R Interrupt Status Register 1 0x0000_00C1 This register contains mainly interrupt status including transmission-related interrupts and SCPSNT toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 8 when BDLAB = 0) and SCPSNT line status. RESERVED RESERVED RESERVED RESERVED SCPSNT SCPTI INTS2 INTS1 INTS0 Interrupt pending

446 - BITS DESCRIPTIONS [31:6] RESERVED [5] SCPSNT Smart card present line status. User may poll this bit to see SCPSNT pin's voltage level 0 = Smart card has been remove from the reader 1 = Smart card IC is contact with the reader [4] SCPTI SCPSNT toggle interrupt status. A rising/falling edge of SCPSNT signal triggers an interrupt and set this status bit if ESCPTI (IER bit 3) is set to "1" to enable SCPSNT toggle interrupt. 0= No SCPSNT toggle interrupt. 1 = SCPSNT toggle interrupt occurs. [3:1] INTS2 INTS0 Interrupt Status bit 2 ~0 The combination indicates which kind of transmission-related interrupt has occurred. Refer to the following table for details. ISR bit Interrupt set and function 3 2 1 Priority Interrupt type Interrupt source Clear interrupt condition 0 0 0 No interrupt pending 1 0 1 first Card insert or remove SCPTI =1 Read ISR 1 1 1 second TIME- OUT interrupt 1. TO2 =1 2. TO1 =1 3. TO0 =1 Read SCSR 0 1 1 third Data receiving status 1. OER = 1 2. PBER = 1 3. NSER = 1 4. SBD = 1 Read SCSR 0 1 0 fourth RBR data ready 1. RBR data ready 2. FIFO interrupt active level reached 1. Read RBR 2. Read RBR until FIFO is under active level 1 1 0 fifth FIFO data time out Receiver FIFO is non- empty and no activities are occurred in the receiver FIFO during the TOR defined time duration Read RBR 0 0 1 sixth TBR empty TBR empty 1. Write data to TBR 2. Read ISR (if priority is sixth) [0] Interrupt pending Interrupt pending status bit. This bit is a logical "1" if there is no interrupt pending. If one of the interrupt sources occurs, this bit will be set to a logical "0". 0 = Interrupt pending. 1 = No interrupt occurs.

Publication Release Date: September 19, 2006 - 447 - Revision B2 Smart Card FIFO control Register (SCHI_SCFR) REGISTER ADDRESS R/W SCHI_SCFR0 0xFFF8_5008 (DLAB = 0) W Interrupt Status Register 0 0x0000_0000 SCHI_SCFR1 0xFFF8_5808 (DLAB = 0) W Interrupt Status Register 1 0x0000_0000 BITS DESCRIPTIONS [31:8] RESERVED [7:6] RxTL1, RxTL0 Receiver FIFO active Threshold Level control bits. These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an interrupt is activated to notify host to read data from FIFO. Default to be 00b. RxTL1 RxTL0 Rx FIFO Interrupt Active Level (Bytes) RESERVED RESERVED RESERVED RxTL1 RxTL0 PEC2 PEC1 PEC0 TxFRST RxFRST Reserved

448 - Continued BITS DESCRIPTIONS [5:3] PEC2, PEC1, PEC0 Parity Error Count. Bits PEC2, PEC1 and PEC0 determine the number of allowed repetitions in reception or in transmission before setting bit PBER in SCSR. The value 000 indicates that, if only one parity error has occurred, bit PE is set; the value 111 indicate that bit PE will be set after 8 parity errors. In protocol T =0: If a correct character is received before the programmed error number is reached, the error counter will be reset If the programmed number of allowed parity errors is reached, bit PBER in register SCSR will be set as long as register SCSR has not been read. If a transmitted character has been NAK by the card, then our smart card host interface will automatically re-transmit it a number of times equal to the value programmed in bits PEC2, PEC1 and PEC0 by generating interrupt to inform CPU to flush the transmit buffer. In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then the automatic re-transmission is invalided. The retransmitted character will start after the gardtime. So if you set guardtime =2 and the card pull 2 etu low, then there will be no guardtime. Set guardtime =3 when T=0 in case of 2 etu pull down NAK by card. In protocol T= 1: The error counter has no action; bit PE is set at the first incorrectly received character. [2] TxFRST Transmitter FIFO Reset control bit. Setting this bit to a logical "1" resets the transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". [1] RxFRST Receiver FIFO Reset control bit. Setting this bit to a logical "1" resets the receiver FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". [0] RESERVED Smart Card Control Register (SCHI_SCCR) REGISTER ADDRESS R/W

SCHI_SCCR0 0xFFF8_500C R/W Smart Card Control Register 0 0x0000_0018 SCHI_SCCR1 0xFFF8_580C R/W Smart Card Control Register 1 0x0000_0018

Publication Release Date: September 19, 2006 - 449 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED [7] BDLAB Baud rate Divisor Latch Access Bit. When this bit is set to a logical "1", users may access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of baudrate generator during a read/write operation. A special Smart Card ID can also be read at base address + 8 when BDLAB is "1". When this bit is set to "0", accesses to base address + 0, 4 or 8 refer to RBR/TBR, IER or ISR/SCFR respectively. [6] DIR DIRect convention When set as a ‘0’ or ‘1’ will receive data in the direct convention or indirect convention manner respectively. In other words, the controller will need to have this bit set to a ‘1’ if the first byte of the ATR process is 3F (i.e. Indirect convention) and a ‘0’ if the first byte is 3B (i.e. Direct convention). [5] NSBE Silent Byte Enable. Receiver detect the data byte, parity bit and stop bit are all zero [4] EPE Even Parity Enable. This bit is only available when bit 3 of SCCR is programmed to "1". It prescribes number of logical 1s in a data word including parity bit. When this bit is set to "1", even parity is required for transmission and reception. Odd parity is demanded when this bit is set to "0". In contrast to its UART counterpart, Smart Card Control Register only controls parity bit setting because data length is fixed at 8-bit long for Smart Card interface protocol. [3] Protocol Protocol. Bit PROT is set if the protocol is T = 1 (asynchronous) and bit PROT = 0 if the protocol is T = 0. RESERVED RESERVED RESERVED BDLAB DIR NSBE EPE PROT CDP Reserved Reserved

450 - Contiuned BITS DESCRIPTIONS [2] CDP Card Detect Polarity. We can use the CDP bit to choose the card present input polarity for different socket application. 0 : the input high means card is present. 1 : the input low means card is present. [1:0] RESERVED Smart Card Host Clock Base Register (SCHI_CBR) REGISTER ADDRESS R/W

SCHI_CBR0 0xFFF8_5010 R/W Clock base Register 0 0x0000_000C SCHI_CBR1 0xFFF8_5810 R/W Clock base Register 1 0x0000_00OC BITS DESCRIPTIONS [31:8] RESERVED [7:0] CBR Clock Base value. It specifies number of internal sampling clock pulses for a data bit. Default to be 0Ch. This register combining with BLH and BLL (baud rate latches) determine internal sampling clock frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh which mean SCCLK clock frequency is 372 (12 x 31) times of internal sampling clock frequency. The default values of CBR, BLH and BLL are corresponding to default values of transmission factors F and D specified in ISO/IEC 7816-3. The value of 0Ch of CBR means there're 12 sampling clock pulses to detect a 1-etu (elementary time unit) data bit on SCIO signal. It is recommended that user sets CBR to be around 16 to maintain better data integrity and transmission stability. RESERVED RESERVED RESERVED 8-bit clock base Data

Publication Release Date: September 19, 2006 - 451 - Revision B2 Smart Card Host Status Register (SCHI_SCSR) REGISTER ADDRESS R/W SCHI_SCSR0 0xFFF8_5014 R Smart card Status Register 0 0x0000_0060 SCHI_SCSR1 0xFFF8_5814 R Smart card Status Register 1 0x0000_0060 BITS DESCRIPTIONS [31:11] RESERVED RESERVED [10:8] TOF2, TOF1, TOF0 TOF2 is Time-Out Flag of Timer2. When Timer 2 time out, it will set the FLAG (TOF2) When host reads SCSR, it clears this bit to "0". TOF1 is Time-Out Flag of Timer1. When Timer 1 time out, it will set the FLAG (TOF1) When host reads SCSR, it clears this bit to "0". TOF0 is Time-Out Flag of Timer0. When Timer 0 time out, it will set the FLAG (TOF0) When host reads SCSR, it clears this bit to "0". [7] SC_RESET SC_RESET pin status This bit reflects the RESET pin high or low. [6] TSRE Transmitter Shift Register Empty This bit is set to "1" when transmitter shift register is empty. RESERVED RESERVED RESERVED TOF2 TOF1 TOF0 SC_RESET TSRE TBRE SBD NSER PBER OER RDR

452 - Contiuned BITS DESCRIPTIONS [5] TBRE Transmitter Buffer Register Empty In non-FIFO mode, this bit will be set to a logical 1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or FIFO. [4] SBD Silent Byte Detected This bit is set to "1" to indicate that received data byte are kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". [3] NSER No Stop bit Error This bit is set to "1" to indicate that received data has no stop bit. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". [2] PBER Parity Bit Error This bit is set to "1" to indicate that parity bit of received data is wrong. In FIFO mode, it indicates the same condition for the data on top of the FIFO. When host reads SCSR, it clears this bit to "0". [1] OER Overrun Error This bit is set to "1" to indicate previously received data is overwritten by the next received data before it is read by host. In FIFO mode, it indicates the same condition instead of FIFO full. When host reads SCSR, it clears this bit to "0". [0] RDR Receiver Data Ready This bit is set to "1" to indicate received data is ready to be read by host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is cleared to "0". Smart Card Host Guard Time Register (SCHI_GTR) REGISTER ADDRESS R/W

SCHI_GTR0 0xFFF8_5018 R/W Guard time Register 0 0x0000_0001 SCHI_GTR1 0xFFF8_5818 R/W Guard time Register 1 0x0000_0001

Publication Release Date: September 19, 2006 - 453 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED [7:0] GTR Guard Time Register value. This register specifies number of stop bits appended in the end of data byte. Bit 7 ~ 0: Guard time values. Default to be 01h. Smart Card Host Extended Control Register (SCHI_ECR) REGISTER ADDRESS R/W SCHI_ECR0 0xFFF8_501C R/W Extended Control Register 0 0x0000_0052 SCHI_ECR1 0xFFF8_581C R/W Extended Control Register 1 0x0000_0052 RESERVED RESERVED RESERVED GTR[7:0] RESERVED RESERVED RESERVED PSCKFS2 PSCKF PSCKFS Reserved SCKFS2 SCKFS1 SCKFS0 CLKSTP CLKSTPL Reserved

454 - BITS DESCRIPTIONS [31:11] RESERVED [10:8] PSCKFS2, PSCKFS1, PSCKFS0 PSCK Frequency Selection bit 2, 1 and 0. This selection can adjust power-on /power-offf sequence interval. They select working clock frequency as following table. Default values are 05h. SCKFS0, SCKFS1, SCKFS2 SCCLK frequency 000 80MHz 001

40 MHz

20 MHz

10 MHz

5 MHz

2.5 MHz

1.25 MHz

[6:4] SCKFS2, SCKFS1, SCKFS0 SCCLK Frequency Selection bit 2, 1 and 0. They select working clock frequency as following table. Default values are 05h. SCKFS0, SCKFS1, SCKFS2 SCCLK frequency 000 80MHz 001 [3] CLKSTPL Clock Stop voltage Level 0 = SCCLK stops at low if CLKSTP is also set to "0". 1 = SCCLK stops at high if CLKSTP is also set to "1". [2] CLKSTP Clock Stop control bit Setting "1" to this bit stops SCCLK at a voltage level specified by CLKSTPL (bit 3 of ECR). [1:0] RESERVED

Publication Release Date: September 19, 2006 - 455 - Revision B2 Smart Card Host Test Mode Register (SCHI_TMR) REGISTER ADDRESS R/W SCHI_TMR0 0xFFF8_5020 R/W Test mode Register 0 0x0000_0000 SCHI_TMR1 0XFFF8_5820 R/W Test mode Register 1 0x0000_0000 This 8 bit register is added in order to allow better testability of the Smart Card host. Currently only bit 1 is utilized. In the future, other bits can be used to program the host to improve testability on the testing platform. RESERVED RESERVED RESERVED RESERVED SCRST_L POWER_SEQ _SKIP

456 - BITS DESCRIPTIONS [31:2] RESERVED [1] SCRST_L Smart card Reset pin control bit Software driver controls this bit directly which in turn determines the SCRST_L signal to the Smart Card. ‘0’ or ‘1’ in this bit drives ‘0’ or ‘1’ respectively on the SCRST_L signal. This feature was first added to allow the SCRST_L to be pulled high at a quicker rate during the reset phase to improve testability. However, upon the attempt to further improve the capability of the Smart Card host, it was found that this bit holds the key in solving one of the major problems of this design. Originally, the SCRST_L signal is pulled high automatically after a fixed period of time (via the use of a hardware counter) when the card is inserted. However, there have been many cases where this signal is pulled high even before power is supplied to the card, which is a clear violation to the ISO 7816 specification. This as a result causes non valid ATR to be read by the host during the initial insertion of the card. Earlier versions of this IP rectified this problem by having the software ignore the invalid ATR during the initial insertion and do either a warm or cold setup to capture the true ATR on its second try. This bit allows a lot of flexibility to fix the problem mentioned above. Software driver now has the ability to determine when the SCRST_L is to be pulled either high or low, avoiding this problem which has plagued earlier versions. With this modification, software ensures that the SCRST_L signal is pulled high only after the power is supplied to the card, thus allowing the true ATR to be always read during the initial insertion of the card. [0] POWER_SE Q_SKIP When the bit is low, it is normal case When the bit is high, it will skip the power_on/off_seq so it can speed up the S/W simulation Smart Card Host Time-out configuration Register (SCHI_TOC) REGISTER ADDRESS R/W

SCHI_TOC0 0xFFF8_5028 R/W Time out Configuration Register 0 0x0000_0000 SCHI_TOC1 0xFFF8_5828 R/W Time out Configuration Register 1 0x0000_0000

Publication Release Date: September 19, 2006 - 457 - Revision B2 BITS DESCRIPTIONS [31:12] RESERVED [11] nDBGACK_EN2 ICE Debug mode Acknowledge enable for time-out counter 2 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held. RESERVED RESERVED RESERVED nDBGACK_EN2 TOC8 TOC7 TOC6 nDBGACK_EN1 TOC5 TOC4 TOC3 nDBGACK_EN0 TOC2 TOC1 TOC0

458 - Continued BITS DESCRIPTIONS [10:8] TOC8, TOC7, TOC6 TOC8, TOC7, TOC6 (Time Out Configuration) control 24 bit time- out counter 2 configuration. TOC8, TOC7, TOC6 value OPERATION MODE 000 24 bit counter 2 is stopped 001 Counting the value stored in register TOIR 2 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO2 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. 010 Counter 2 starts counting the content of register TOIR2 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 2 reaches its terminal count, an interrupt is given if enable. Bit TO2 in register SCSR is set. The counter is reloaded with TOIR2 and starts counting on each subsequent START bit. It is possible to change the content of TOIR2 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, 011 Counter 2 starts counting the content of register TOIR2 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 2 reaches its terminal count, an interrupt is given if enable. Bit TO2 in register SCSR is set. The count is stopped by writing 000b in register TOC, 100 Same as value 000b, except that counter 2 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC [7] nDBGACK_EN1 ICE Debug mode Acknowledge enable for time-out counter 1 0 = When DBGACK is high, the timer clock will be held 1= No matter what DBGACK is high or not, the timer clock will not be held

Publication Release Date: September 19, 2006 - 459 - Revision B2 Continued BITS DESCRIPTIONS [6:4] TOC5, TOC4, TOC3 TOC5, TOC4, TOC3 (Time Out Configuration) control 16 bit time- out counter 1 configuration. TOC5, TOC4, TOC3 value OPERATION MODE 000 16 bit counter 1 is stopped 001 Counting the value stored in register TOIR 1 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO1 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. 010 Counter 1 starts counting the content of register TOIR1 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 1 reaches its terminal count, an interrupt is given if enable. Bit TO1 in register SCSR is set. The counter is reloaded with TOIR1 and starts counting on each subsequent START bit. It is possible to change the content of TOIR1 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, 011 Counter 1 starts counting the content of register TOIR1 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 1 reaches its terminal count, an interrupt is given if enable. Bit TO1 in register SCSR is set. The count is stopped by writing 000b in register TOC, 100 Same as value 000b, except that counter 1 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC [3] nDBGACK_EN0 ICE Debug mode Acknowledge enable for time-out counter 0 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held

460 - Continued BITS DESCRIPTIONS [2:0] TOC2, TOC1, TOC0 TOC5, TOC4, TOC3 (Time Out Configuration) control 8 bit time-out counter 0 configuration. TOC2, TOC1, TOC0 value OPERATION MODE 000 8 bit counter 0 is stopped 001 Counting the value stored in register TOIR 0 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO0 is set within register SCSR when the terminal count is reached. The counter is stopped by writing 000b in register TOC, and should be stopped before reloading new values in register TOC. 010 Counter 0 starts counting the content of register TOIR0 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 0 reaches its terminal count, an interrupt is given if enable. Bit TO0 in register SCSR is set. The counter is reloaded with TOIR0 and starts counting on each subsequent START bit. It is possible to change the content of TOIR0 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The count is stopped by writing 000b in register TOC, 011 Counter 0 starts counting the content of register TOIR0 on the first START bit (reception or transmission) detected on the pin I/O after 010b is written in register TOC. When counter 0 reaches its terminal count, an interrupt is given if enable. Bit TO0 in register SCSR is set. The count is stopped by writing 000b in register TOC, 100 Same as value 000b, except that counter 0 will be stopped at the end of the 12th ETU following the first START bit detected after 100b has been written in register TOC

Publication Release Date: September 19, 2006 - 461 - Revision B2 Smart Card Host Time-out Initial Register 0 (SCHI_TOIR 0) REGISTER ADDRESS R/W SCHI_TOIR0_0 0xFFF8_502C R/W 8 bit Time out initial Register 0 0x0000_0000 SCHI_TOIR0_1 0xFFF8_582C R/W 8 bit Time out initial Register 1 0x0000_0000 BITS DESCRIPTIONS [31:8] RESERVED [7:0] TOIR0 8 bit Time Out Initial Register 0 The value to load in register TOIR 0 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 8 bit time-out initial register used to initial loading value when every start counting. Smart Card Host Time-out Initial Register 1 (SCHI_TOIR 1) REGISTER ADDRESS R/W SCHI_TOIR1_0 0xFFF8_5030 R/W 16 bit Time out initial Register 0 0x0000_0000 SCHI_TOIR1_1 0xFFF8_5830 R/W 16 bit Time out initial Register 1 0x0000_0000 RESERVED RESERVED RESERVED TOIR0[7:0]

462 - BITS DESCRIPTIONS [31:16] RESERVED [15:0] TOIR1 16 bit Time Out Initial Register 1 The value to load in register TOIR 1 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 16 bit time-out initial register used to initial loading value when every start counting. Smart Card Host Time-out Initial Register 2 (SCHI_TOIR 2) REGISTER ADDRESS R/W

SCHI_TOIR2_0 0xFFF8_5034 R/W 24 bit Time out initial Register 0 0x0000_0000 SCHI_TOIR2_1 0xFFF8_5834 R/W 24 bit Time out initial Register 1 0x0000_0000 BITS DESCRIPTIONS [31:24] RESERVED [23:0] TOIR2 24 bit Time Out Initial Register 2 The value to load in register TOIR 2 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 24 bit time-out initial register used to initial loading value when every start counting. RESERVED RESERVED TOIR1[15:8] TOIR1[7:0] RESERVED TOIR2[23:16] TOIR2[15:8] TOIR2[7:0]

Publication Release Date: September 19, 2006 - 463 - Revision B2 Smart Card Host Time-Out Data Register 0 (SCHI_TODR0) REGISTER ADDRESS R/W SCHI_TOD0_0 0xFFF8_5038 R 8 bit Time out data Register 0 0x0000_00FF SCHI_TOD0_1 0xFFF8_5838 R 8 bit Time out data Register 1 0x0000_00FF BITS DESCRIPTIONS [31:8] RESERVED [7:0] TOD0 8 bit Time Out Data count Register 0 The value showing in register TOD 0 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 8 bit time-out data register used to show the current counting value. Smart Card Host Time-Out Data Register 1 (SCHI_TODR1) REGISTER ADDRESS R/W SCHI_TOD1_0 0xFFF8_503C R 16 bit Time out Data Register 0 0x0000_00FF SCHI_TOD1_1 0xFFF8_583C R 16 bit Time out Data Register 1 0x0000_00FF RESERVED RESERVED RESERVED TOD0[7:0] RESERVED RESERVED TOD1[15:8] TDO1[7:0]

464 - BITS DESCRIPTIONS [31:16] RESERVED [15:0] TOD1 16 bit Time Out Data count Register 1 The value showing in register TOD 1 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 16 bit time-out data register used to show the current counting value. Smart Card Host Time-Out Data Register 2 (SCHI_TODR2) REGISTER ADDRESS R/W

SCHI_TOD2_0 0xFFF8_5040 R 24 bit Time out Data Register 0 0x0000_00FF SCHI_TOD2_1 0xFFF8_5840 R 24 bit Time out Data Register 1 0x0000_00FF BITS DESCRIPTIONS [31:24] RESERVED [23:0] TOR2 24 bit Time Out Data count Register 2 The value to load in register TOD 2 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock. This is 24 bit time-out data register used to show the current counting value. RESERVED TOD2[23:16] TOD2[15:8] TDO2[7:0]

Publication Release Date: September 19, 2006 - 465 - Revision B2 Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR) REGISTER ADDRESS R/W SCHI_BTOR0 0XFFF8_5044 R/W Buffer Time out Data Register 0 0x0000_0000 SCHI_BTOR1 0XFFF8_5844 R/W Buffer Time out Data Register 1 0x0000_0000 BITS DESCRIPTIONS [31:8] RESERVED [7] BTOIE Buffer Time Out Interrupt Enable The feature of receiver buffer time out interrupt is enabled only when BTOIE[7] = ERDRI =1 . [6:0] BTOIC Buffer Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = ETU) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR[7] = ERDRI =1. A new incoming data word or BRX FIFO empty clear Irpt_TOUT. Smart Card Host Baud Rate Divider Latch Lower Byte (SCHI_BLL) REGISTER ADDRESS R/W SCHI_BLL0 0XFFF8_5000 (DLAB = 1) R/W Baud rate divisor Latch Lower byte Register 0 0x0000_001F SCHI_BLL1 0XFFF8_5800 (DLAB = 1) R/W Baud rate divisor Latch Lower byte Register 1 0x0000_001F RESERVED RESERVED RESERVED BTOIE BTOIC_6 BTOIC_5 BTOIC_4 BTOIC_3 BTOIC_2 BTOIC_1 BTOIC_0

466 - BITS DESCRIPTIONS [31:8] RESERVED [7:0] BLL 8 bit Baud rate divider Latch Low byte register This register combining with BLH and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh. Baud Rate Divider Latch Higher Byte (SCHI_BLH) REGISTER ADDRESS R/W

SCHI_BLH0 0XFFF8_5004 (DLAB = 1) R/W Baud rate divisor Latch Higher byte Register 0 0x0000_0000 SCHI_BLH1 0XFFF8_5804 (DLAB = 1) R/W Baud rate divisor Latch Higher byte Register 1 0x0000_0000 RESERVED RESERVED RESERVED BLL[7:0] RESERVED RESERVED RESERVED BLH[7:0]

Publication Release Date: September 19, 2006 - 467 - Revision B2 BITS DESCRIPTIONS [31:8] RESERVED [7:0] BLH 8 bit Baud rate divider Latch High byte register This register combining with BLL and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h. SMART CARD ID NUMBER (SCHI_ID) Register Address R/W SCHI_ID0 0xFFF8_5008 (DLAB = 1) R Smart card ID number Register 0 0x0000_0070 SCHI_ID1 0XFFF8_5808 (DLAB = 1) R Smart card ID number Register 1 0x0000_0070 BITS DESCRIPTIONS [31:8] RESERVED [7:0] ID 8 bit smart card ID number register This register contains a specific value of 70h for driver to identify Smart Card interface. RESERVED RESERVED RESERVED ID[7:0]

468 -

6.17.3 Functional description

The following description uses abbreviations to refer to control/status registers and their contents of Smart Card interface as seen in section 7.12.2 z Initialization User needs to program control registers so that ATR (Answer To Reset) data streams can be properly decoded after card insertion. Initialization settings include the following steps where sequential order is irrelevant. 1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3. 2. GTR is programmed with 01h for one stop bit. 3. Set SCFR bit 1 to "1" to reset receiver FIFO. 4. Set EPE bit in SCCR bit 4 to be “1” for EVEN parity, set EPE bit to be “0” for odd parity. 5. Set SCKFS1 and SCKFS0 to "05" to select 2.5 MHz for SCCLK on 80MHz system clock. Most default values of above control bits are designed as specified in initialization step but it is recommended that user performs all the initialization sequence to avoid any ambiguity. The relationship between transmission factors and settings of BLH, BLL and CBR is best described in the following example. f D F etu (f means SCCLK frequency) Therefore, CBR BLL BLH 372 Dd Fd z Activation Card insertion pulls up SCPSNT (assuming SCPSNT in ISR bit 5 is active high) and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually applied. SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3). To meet another timing requirement, tc of ISO/IEC 7816-3, a counter based on SCCLK is implemented to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR (Answer To Reset) is detected after 65536 clock cycles from the rising edge of SCRST#. z Answer-to-Reset Answer-to-Reset (ATR) is the data streams sent by the card to the interface as an answer to a reset on SCRST# signal. Refer to ISO/IEC 7816-3 for detailed description of ATR. There're two kinds of cards specified in ISO/IEC 7816-3, inverse convention card and direct convention card. Although these two conventions treat logical meanings (0 or 1) of voltage levels (low or high) differently, Winbond's implementation of Smart Card interface decodes a high voltage level data bit as "1" and low voltage level data bit "0" nevertheless and resorts to software to interpret incoming data. Software driver needs to interpret initial character of ATR first to determine which

Publication Release Date: September 19, 2006 - 469 - Revision B2 convention is for inserted card and chooses a conversion procedure for it. Subsequent incoming data bytes must be passed through a conversion procedure before actually transfers these data bytes to host. Similar conversion procedure must be applied to outgoing data byte before writing to TBR too. For example, the raw data byte for initial character of inverse-convention ATR would be 3Fh. Software driver therefore needs a conversion procedure to reverse bit-significance and polarity to process subsequent raw data bytes. On the other hand, initial character of direct-convention ATR is 3Bh which needs no conversion procedure to process data byte. z Data transfer Software driver might need to configure control registers again based on information contained in ATR before process subsequent data transfer. The following guidelines are provided for programming reference. 1. EPE should be set to "1" for direct-convention card and otherwise for inverse-convention card. 2. BLH, BLL and CBR should be set to comply with Fi and Di. 3. GTR is used for various stop bit requirement of different transmission protocols. 4. Use interrupt resources to control communication sequence. 5. Monitor SCSR for transmission integrity. z Cold reset and warm reset Cold reset is achieved by writing a "1" to PWRDN (bit 7 of IER). It deactivates SCPWR# to high. Consequentially, SCRST# is pulled down and SCCLK is stopped. User must write a "0" to PWRDN (bit 7 of IER) to resume Smart Card interface to a normal activation state assuming card is still present. The activation sequence and deactivation sequence are done by internal F.S.M When in a normal activation state, writing a "0" SCRST_L (bit 1 of TMR) will force SC_RST pin to low that will triggers a warm reset. Its effect is similar to cold reset except SCPWR# is kept activated and therefore power supply to card stays on. z Power states SCHI employs a sophisticated algorithm to partition Smart Card interface's internal circuits to achieve optimal power utilization. However, users must pay extra care in the design of application circuits following guidelines stated below to prevent potential signal conflict and unnecessary power consumption. There're three power states: disabled state, active state, and power down state. Disabled state is the default state when power is first applied to the IC. SCPWD (Smart Card Power Down) controls whether in active state (SCPWD = 0) or in power down state (SCPWD = 1). z Disabled state Smart Card interface is in disabled state initially. Clock is stopped in this state and therefore it is the least power-consuming state. To prevent current leakage from floating connections, it is designed to output a predetermined voltage level on all the I/O pins of Smart Card interface as follows: SCPWR# outputs high to disable power supply to socket; SCRST#, SCCLK, and SCIO output low; SCPSNT is tri-stated.

470 - These I/O conditions also apply to socket in power down state (SCPWD = 1) or deselected socket in idle state. Designers of application circuits must take extra care so that no contention occurs when Smart Card interface is in those power-saving states. z Active state Active state is when Smart Card interface is actually performing all its functions: configuration of control and interrupt registers, detection of card insertion/extraction, reception of ATR (Answer To Reset) packet and communication of information between host and card. Refer to section 7.12.3 for detailed function description. This is the most power-consuming state and actual power consumption is dependent on traffic of interface. z Power down state Transition from active state to power down state is accomplished by setting SCPWD to "1". Clock is stopped for most internal core circuits except detection circuit for SCPSNT toggle (card insertion/extraction). SCPSNT toggle can interrupt CPU and through this feature Smart Card interface in power down state can be waken up by card insertion/extraction. User may also directly write a "0" to SCPWD to wake up Smart Card interface. Smart Card interface spends a little bit more power to maintain SCPSNT toggle detection circuit in power down state than in disabled state while spares even more power than in active state by stopping clock to core circuit. Users must make sure that all on-going transactions are concluded before putting Smart Card interface into power down state to prevent potential disoperation of internal state machine.

Publication Release Date: September 19, 2006 - 471 - Revision B2

6.18 I2C Interface

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and 400kbps modes are supported directly. For High-speed mode special IOs are needed. If these IOs are available and used, then High-speed mode is also supported. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte- by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). The I2C Master Core includes the following features:

AMBA APB interface compatible
Compatible with Philips I2C standard, support master mode
Multi Master Operation
Clock stretching and wait state generation
Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
Software programmable acknowledge bit
Arbitration lost interrupt, with automatic transfer cancellation
Start/Stop/Repeated Start/Acknowledge generation
Start/Stop/Repeated Start detection
Bus busy detection
Supports 7 bit addressing mode
Fully static synchronous design with one clock domain
Software mode I2C

472 -

6.18.1 I2C Protocol

Normally, a standard communication consists of four parts: 1) START or Repeated START signal generation 2) Slave address transfer 3) Data transfer 4) STOP signal generation SCL SDA S or Sr MSB ACK P or Sr P Sr LSB MSB LSB 3 - 7 A4 - A1 R/W D5 - D1 NACK ACK Fig. 6.18.1.1 Data transfer on the I2C-bus S SLAVE ADDRESS R/W A DATA A DATA A/A P '0'(write) data transfer (n bytes + acknowledge) from master to slave from slave to master A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition P = STOP condition A master-transmitter addressing a slave receiver with a 7-bit address The transfer direction is not changed '1'(read) data transfer (n bytes + acknowledge) S SLAVE ADDRESS R/W A DATA A DATA A P A master reads a slave immediately after the first byte (address)

Publication Release Date: September 19, 2006 - 473 - Revision B2 START or Repeated START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer. A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus. The I2C core generates a START signal when the START bit in the Command Register (CMDR) is set and the READ or WRITE bits are also set. Depending on the current status of the SCL line, a START or Repeated START is generated. STOP signal The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. START condition STOP condition SCL SDA START and STOP conditions Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle. The core treats a Slave Address Transfer as any other write action. Store the slave device’s address in the Transmit Register (TxR) and set the WRITE bit. The core will then transfer the slave address on the bus. MSB LSB R/W slave address The first byte after the START procedure

474 - Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by- byte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle. If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. To write data to a slave, store the data to be transmitted in the Transmit Register (TxR) and set the WRITE bit. To read data from a slave, set the READ bit. During a transfer the core set the I2C_TIP flag, indicating that a Transfer is In Progress. When the transfer is done the I2C_TIP flag is cleared, the IF flag set if enabled, then an interrupt generated. The Receive Register (RxR) contains valid data after the IF flag has been set. The software may issue a new write or read command when the I2C_TIP flag is cleared. data line stable; data valid change of data allowed SCL SDA Bit transfer on the I2C-bus SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER S START condition clock pulse for acknowledgement not acknowledge acknowledge Acknowledge on the I2C-bus

Publication Release Date: September 19, 2006 - 475 - Revision B2

6.18.2 I2C Serial Interface Control Registers Map

R: read only, W: write only, R/W: both read and write NOTE1: The reset value of I2C_WR0/1 is 0x3F only when SCR, SDR and SER are connected to pull high resistor. REGISTER ADDRESS R/W I2C_CSR0 0xFFF8_6000 R/W I2C0 Control and Status Register 0x0000_0000 I2C_DIVIDER0 0xFFF8_6004 R/W I2C0 Clock Prescale Register 0x0000_0000 I2C_CMDR0 0xFFF8_6008 R/W I2C0 Command Register 0x0000_0000 I2C_SWR0 0xFFF8_600C R/W I2C0 Software Mode Control Register 0x0000_003F I2C_RxR0 0xFFF8_6010 R I2C0 Data Receive Register 0x0000_0000 I2C_TxR0 0xFFF8_6014 R/W I2C0 Data Transmit Register 0x0000_0000 I2C Interface 1 I2C_CSR1 0xFFF8_6100 R/W I2C1 Control and Status Register 0x0000_0000 I2C_DIVIDER1 0xFFF8_6104 R/W I2C1 Clock Prescale Register 0x0000_0000 I2C_CMDR1 0xFFF8_6108 R/W I2C1 Command Register 0x0000_0000 I2C_SWR1 0xFFF8_610C R/W I2C1 Software Mode Control Register 0x0000_003F I2C_RxR1 0xFFF8_6110 R I2C1 Data Receive Register 0x0000_0000 I2C_TxR1 0xFFF8_6114 R/W I2C1 Data Transmit Register 0x0000_0000 I2C Control and Status Register 0/1 (I2C_CSR0/1) REGISTER ADDRESS R/W I2C_CSR0 0xFFF8_6000 R/W I2C Control and Status Register 0 0x0000_0000 I2C_CSR1 0xFFF8_6100 R/W I2C Control and Status Register 1 0x0000_0000 Reserved Reserved Reserved I2C_RxACK I2C_BUSY I2C_AL I2C_TIP Reserved Tx_NUM Reserved IF IE I2C_EN

476 - BITS DESCRIPTIONS [31:12] Reserved Reserved [11] I2C_RxACK Received Acknowledge From Slave (Read only) This flag represents acknowledge from the addressed slave. 0 = Acknowledge received (ACK). 1 = Not acknowledge received (NACK). [10] I2C_BUSY I2C Bus Busy (Read only) 0 = After STOP signal detected. 1 = After START signal detected. [9] I2C_AL Arbitration Lost (Read only) This bit is set when the I2C core lost arbitration. Arbitration is lost when: A STOP signal is detected, but no requested. The master drives SDA high, but SDA is low. [8] I2C_TIP Transfer In Progress (Read only) 0 = Transfer complete. 1 = Transferring data. NOTE: When a transfer is in progress, you will not allow writing to any register of the I2C master core except SWR. [5:4] Tx_NUM Transmit Byte Counts These two bits represent how many bytes are remained to transmit. When a byte has been transmitted, the Tx_NUM will decrease 1 until all bytes are transmitted (Tx_NUM = 0x0) or NACK received from slave. Then the interrupt signal will assert if IE was set. 0x0 = Only one byte is left for transmission. 0x1 = Two bytes are left to for transmission. 0x2 = Three bytes are left for transmission. 0x3 = Four bytes are left for transmission. [3] Reserved Reserved [2] IF Interrupt Flag The Interrupt Flag is set when: Transfer has been completed. Transfer has not been completed, but slave responded NACK (in multi- byte transmit mode). Arbitration is lost. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. [1] IE Interrupt Enable 0 = Disable I2C Interrupt. 1 = Enable I2C Interrupt. [0] I2C_EN I2C Core Enable 0 = Disable I2C core, serial bus outputs are controlled by SDW/SCW. 1 = Enable I2C core, serial bus outputs are controlled by I2C core.

Publication Release Date: September 19, 2006 - 477 - Revision B2 I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1) REGISTER ADDRESS R/W I2C_DIVIDER0 0xFFF8_6004 R/W I2C Clock Prescale Register 0 0x0000_0000 I2C_DIVIDER1 0xFFF8_6104 R/W I2C Clock Prescale Register 1 0x0000_0000 Reserved Reserved DIVIDER[15:8] DIVIDER[7:0] BITS DESCRIPTIONS [15:0] DIVIDER Clock Prescale Register It is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when the “I2C_EN” bit is cleared. Example: pclk = 32MHz, desired SCL = 100KHz 100 hex F dec KHz MHz prescale I2C Command Register 0/1 (I2C_CMDR 0/1) REGISTER ADDRESS R/W I2C_CMDR0 0xFFF8_6008 R/W I2C Command Register 0 0x0000_0000 I2C_CMDR1 0xFFF8_6108 R/W I2C Command Register 1 0x0000_0000

478 - Reserved Reserved Reserved Reserved START STOP READ WRITE ACK NOTE: Software can write this register only when I2C_EN = 1. BITS DESCRIPTIONS [31:5] Reserved Reserved [4] START Generate Start Condition Generate (repeated) start condition on I2C bus. [3] STOP Generate Stop Condition Generate stop condition on I2C bus. [2] READ Read Data From Slave Retrieve data from slave. [1] WRITE Write Data To Slave Transmit data to slave. [0] ACK Send Acknowledge To Slave When I2C behaves as a receiver, sent ACK (ACK = ‘0’) or NACK (ACK = ‘1’) to slave. NOTE: The START, STOP, READ and WRITE bits are cleared automatically while transfer finished. READ and WRITE cannot be set concurrently. I2C Software Mode Register 0/1(I2C_SWR 0/1) REGISTER ADDRESS R/W

I2C_SWR0 0xFFF8_600C R/W I2C Software Mode Control Register 0 0x0000_003F I2C_SWR1 0xFFF8_610C R/W I2C Software Mode Control Register 1 0x0000_003F

Publication Release Date: September 19, 2006 - 479 - Revision B2 Reserved Reserved Reserved Reserved Reserved SDR SCR Reserved SDW SCW Note: This register is used as software mode of I2C. Software can read/write this register no matter I2C_EN is 0 or 1. But SCL and SDA are controlled by software only when I2C_EN = 0. BITS DESCRIPTIONS [31:6] Reserved Reserved [5] Reserved Reserved [4] SDR Serial Interface SDA Status (Read only) 0 = SDA is Low. 1 = SDA is High. [3] SCR Serial Interface SCK Status (Read only) 0 = SCL is Low. 1 = SCL is High. [2] Reserved Reserved [1] SDW Serial Interface SDA Output Control 0 = SDA pin is driven Low. 1 = SDA pin is tri-state. [0] SCW Serial Interface SCK Output Control 0 = SCL pin is driven Low. 1 = SCL pin is tri-state. I2C Data Receive Register 0/1 (I2C_RxR 0/1) REGISTER OFFSET R/W I2C_RXR0 0xFFF8_6010 R I2C Data Receive Register 0 0x0000_0000 I2C_RXR1 0xFFF8_6110 R I2C Data Receive Register 1 0x0000_0000

Publication Release Date: September 19, 2006 - 481 - Revision B2 Reserved Reserved Reserved Rx [7:0] BITS DESCRIPTIONS [31:8] Reserved Reserved [7:0] Rx Data Receive Register The last byte received via I2C bus will put on this register. The I2C core only used 8-bit receive buffer. I2C Data Transmit Register 0/1 (I2C_TxR 0/1) REGISTER ADDRESS R/W I2C_TXR0 0xFFF8_6014 R/W I2C Data Transmit Register 0x0000_0000 I2C_TXR1 0xFFF8_6114 R/W I2C Data Transmit Register 0x0000_0000 Tx [31:24] Tx [23:16] Tx [15:8] Tx [7:0]

482 - BITS DESCRIPTIONS [31:0] Tx Data Transmit Register The I2C core used 32-bit transmit buffer and provide multi-byte transmit function. Set CSR[Tx_NUM] to a value that you want to transmit. I2C core will always issue a transfer from the highest byte first. For example, if CSR[Tx_NUM] = 0x3, Tx[31:24] will be transmitted first, then Tx[23:16], and so on. In case of a data transfer, all bits will be treated as data. In case of a slave address transfer, the first 7 bits will be treated as 7- bit address and the LSB represent the R/W bit. In this case, LSB = 1, reading from slave LSB = 0, writing to slave

Publication Release Date: September 19, 2006 - 483 - Revision B2

6.19 Universal Serial Interface

The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. This interface can drive one external peripherals and is seen as the master. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to low active or high active, which depends on the peripheral it’s connected. Writing a divisor into DIVIDER register can program the frequency of serial clock output. This master core contains four 32-bit transmit/receive buffers, and can provide burst mode operation. The maximum bits can be transmitted/received is 32 bits, and can transmit/receive data up to four times successive. The USI (Microwire/SPI) Master Core includes the following features:

AMBA APB interface compatible
Support USI (Microwire/SPI) master mode
Full duplex synchronous serial data transfer
Variable length of transfer word up to 32 bits
Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
1 slave/device select lines
Fully static synchronous design with one clock domain

6.19.1 USI Timing Diagram

The timing diagram of USI is shown as following. MSB (Tx[7]) LSB (Tx[0]) MSB (Rx[7]) LSB (Rx[0]) mw_ss_o mw_sclk_o mw_so_o mw_si_i CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0 Tx[6] Tx[5] Tx[4] Tx[3] Tx[2] Tx[1] Rx[6] Rx[5] Rx[4] Rx[3] Rx[2] Rx[1] Fig. 6.19.1.1 USI Timing

484 - mw_ss_o mw_sclk_o mw_so_o mw_si_i CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0 MSB (Tx[7]) LSB (Tx[0]) MSB (Rx[7]) LSB (Rx[0]) Tx[1] Tx[2] Tx[3] Tx[4] Tx[5] Tx[6] Rx[1] Rx[2] Rx[3] Rx[4] Rx[5] Rx[6] Fig. 6.19.1.2 Alternate Phase SCLK Clock Timing

6.19.2 USI Registers Map

R: read only, W: write only, R/W: both read and write REGISTER ADDRESS R/W USI_CNTRL 0xFFF8_6200 R/W Control and Status Register 0x0000_0004 USI_DIVIDER 0xFFF8_6204 R/W Clock Divider Register 0x0000_0000 USI_SSR 0xFFF8_6208 R/W Slave Select Register 0x0000_0000 Reserved 0xFFF8_620C N/A Reserved N/A USI_Rx0 0xFFF8_6210 R Data Receive Register 0 0x0000_0000 USI_Rx1 0xFFF8_6214 R Data Receive Register 1 0x0000_0000 USI_Rx2 0xFFF8_6218 R Data Receive Register 2 0x0000_0000 USI_Rx3 0xFFF8_621C R Data Receive Register 3 0x0000_0000 USI_Tx0 0xFFF8_6210 W Data Transmit Register 0 0x0000_0000 USI_Tx1 0xFFF8_6214 W Data Transmit Register 1 0x0000_0000 USI_Tx2 0xFFF8_6218 W Data Transmit Register 2 0x0000_0000 USI_Tx3 0xFFF8_621C W Data Transmit Register 3 0x0000_0000 NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last.

Publication Release Date: September 19, 2006 - 485 - Revision B2 USI_Control and Status Register (USI_CNTRL) REGISTER ADDRESS R/W USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register 0x0000_0004 Reserved Reserved IE IF SLEEP Reserved LSB Tx_NUM Tx_BIT_LEN Tx_NEG Rx_NEG GO_BUSY BITS DESCRIPTIONS [31:18] Reserved Reserved [17] IE Interrupt Enable 0 = Disable USI Interrupt. 1 = Enable USI Interrupt. [16] IF Interrupt Flag 0 = It indicates that the transfer dose not finish yet. 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. NOTE: This bit is read only, but can be cleared by writing 1 to this bit. [15:12] SLEEP Suspend Interval These four bits provide the configuration of suspend interval between two successive transmit/receive in a transfer. The default value is 0x0. When CNTRL [Tx_NUM] = 00, setting this field has no effect on transfer. The desired interval is obtained according to the following equation (from the last falling edge of current sclk to the first rising edge of next sclk): (CNTRL[SLEEP] + 2)*period of SCLK SLEEP = 0x0 … 2 SCLK clock cycle SLEEP = 0x1 … 3 SCLK clock cycle SLEEP = 0xe … 16 SCLK clock cycle SLEEP = 0xf … 17 SCLK clock cycle

486 - Continued BITS DESCRIPTIONS [11] Reserved Reserved [10] LSB Send LSB First 0 = The MSB is transmitted/received first (which bit in TxX/RxX register that is depends on the Tx_BIT_LEN field in the CNTRL register). 1 = The LSB is sent first on the line (bit TxX[0]), and the first bit received from the line will be put in the LSB position in the Rx register (bit RxX[0]). [9:8] Tx_NUM Transmit/Receive Numbers This field specifies how many transmit/receive numbers should be executed in one transfer. 00 = Only one transmit/receive will be executed in one transfer. 01 = Two successive transmit/receive will be executed in one transfer. 10 = Three successive transmit/receive will be executed in one transfer. 11 = Four successive transmit/receive will be executed in one transfer. [7:3] Tx_BIT_LEN Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. Tx_BIT_LEN = 0x01 … 1 bit Tx_BIT_LEN = 0x02 … 2 bits Tx_BIT_LEN = 0x1f … 31 bits Tx_BIT_LEN = 0x00 … 32 bits [2] Tx_NEG Transmit On Negative Edge 0 = The mw_so_o signal is changed on the rising edge of mw_sclk_o. 1 = The mw_so_o signal is changed on the falling edge of mw_sclk_o. [1] Rx_NEG Receive On Negative Edge 0 = The mw_si_i signal is latched on the rising edge of mw_sclk_o. 1 = The mw_si_i signal is latched on the falling edge of mw_sclk_o. [0] GO_BUSY Go and Busy Status 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished. NOTE: All registers should be set before writing 1 to the GO_BUSY bit in the CNTRL register. When a transfer is in progress, writing to any register of the USI(Microwire/SPI) master core has no effect.

Publication Release Date: September 19, 2006 - 487 - Revision B2 USI Divider Register (USI_DIVIDER) REGISTER ADDRESS R/W USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register 0x0000_0000 Reserved Reserved DIVIDER[15:8] DIVIDER[7:0] BITS DESCRIPTIONS [15:0] DIVIDER Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output usi_sclk_o. The desired frequency is obtained according to the following equation: ) 2 = DIVIDER f f pclk sclk NOTE: Suggest DIVIDER should be at least 1. USI Slave Select Register (USI_SSR) REGISTER ADDRESS R/W USI_SSR 0xFFF8_6208 R/W USI Slave Select Register 0x0000_0000

488 - Reserved Reserved Reserved Reserved ASS SS_LVL SSR[1:0] BITS DESCRIPTIONS [3] ASS Automatic Slave Select 0 = If this bit is cleared, slave select signals are asserted and de- asserted by setting and clearing related bits in SSR register. 1 = If this bit is set, usi_ss_o signals are generated automatically. It means that device/slave select signal, which is set in SSR register is asserted by the USI controller when transmit/receive is started by setting CNTRL[GO_BUSY], and is de-asserted after every transmit/receive is finished. [2] SS_LVL Slave Select Active Level It defines the active level of device/slave select signal (usi_ss_o). 0 = The usi_ss_o slave select signal is active Low. 1 = The usi_ss_o slave select signal is active High. [1:0] SSR Slave Select Register If SSR[ASS] bit is cleared, writing 1 to any bit location of this field sets the proper sui_ss_o line to an active state and writing 0 sets the line back to inactive state. If SSR[ASS] bit is set, writing 1 to any bit location of this field will select appropriate sui_ss_o line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of usi_ss_o is specified in SSR[SS_LVL]). NOTE: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer.

Publication Release Date: September 19, 2006 - 489 - Revision B2 USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3) REGISTER ADDRESS R/W USI_RX0 0xFFF8_6210 R USI Data Receive Register 0 0x0000_0000 USI_RX1 0xFFF8_6214 R USI Data Receive Register 1 0x0000_0000 USI_RX2 0xFFF8_6218 R USI Data Receive Register 2 0x0000_0000 USI_RX3 0xFFF8_621C R USI Data Receive Register 3 0x0000_0000 Rx [31:24] Rx [23:16] Rx [15:8] Rx [7:0] BITS DESCRIPTIONS [31:0] Rx Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and CNTRL[Tx_NUM] is set to 0x0, bit Rx0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same FFs. Data Transmit Register 0/1/2/3 (Tx0/1/2/3) REGISTER ADDRESS R/W USI_TX0 0xFFF8_6210 W USI Data Transmit Register 0 0x0000_0000 USI_TX1 0xFFF8_6214 W USI Data Transmit Register 1 0x0000_0000 USI_TX2 0xFFF8_6218 W USI Data Transmit Register 2 0x0000_0000 USI_TX3 0xFFF8_621C W USI Data Transmit Register 3 0x0000_0000

490 - Tx [31:24] Tx [23:16] Tx [15:8] Tx [7:0] BITS DESCRIPTIONS [31:0] Tx Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if CNTRL[Tx_BIT_LEN] is set to 0x08 and the CNTRL[Tx_NUM] is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If CNTRL[Tx_BIT_LEN] is set to 0x00 and CNTRL[Tx_NUM] is set to 0x3, the core will perform four 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0], Tx2[31:0], Tx3[31:0]). NOTE: The RxX and TxX registers share the same flip-flops, which means that what is received from the input data line in one transfer will be transmitted on the output data line in the next transfer if no write access to the TxX register is executed between the transfers.

Publication Release Date: September 19, 2006 - 491 - Revision B2

6.20 PWM

The W90P710 have 4 channels PWM timers. They can be divided into two groups. Each group has 1 Prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 Dead-Zone generator. They are all driven by PCLK (80 MHz). Each channel can be used as a timer and issue interrupt independently. Two channels PWM timers in one group share the same prescaler. Clock divider provides each channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock signal from clock divider which receives clock from 8-bit prescaler. The 16-bit counter in each channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-bit comparator compares number in counter with threshold number in register loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is enabled, output of two PWM timer in one group is blocked. Two output pin are all used as Dead-Zone generator output signal to control off-chip power device. To prevent PWM driving output pin with unsteady waveform, 16-bit counter and 16-bit comparator are implemented with double buffering feature. User can feel free to write data to counter buffer register and comparator buffer register without generating glitch. When 16-bit down counter reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches zero, if counter is set as toggle mode, it is reloaded automatically and start to generate next cycle. User can set counter as one-shot mode instead of toggle mode. If counter is set as one-shot mode, counter will stop and generate one interrupt request when it reaches zero. The value of comparator is used for pulse width modulation. The counter control logic changes the output level when down-counter value matches the value of compare register. The PWM timer features are shown as below: z Two 8-bit prescalers and two clock dividers z Four clock selectors z Four 16-bit counters and four 16-bit comparators z Two Dead-Zone generator

6.20.1 PWM double buffering and reload automatically

W90P710 PWM Timers have a double buffering function, enabling the reload value changed for next timer operation without stopping current timer operation. Although new timer value is set, current timer operation still operate successfully. The counter value can be written into PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 and current counter value can be read from PWM_PDR0, PWM_PDR1, PWM_PDR2, PWM_PDR3.

492 - The auto-reload operation copies from PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 to down-counter when down-counter reaches zero. If PWM_CNR0~3 are set as zero, counter will be halt when counter count to zero. If auto-reload bit is set as zero, counter will be stopped immediately.

6.20.2 Modulate Duty Ratio

The double buffering function allows PWM_CMR written at any point in current cycle. The loaded value will take effect from next cycle.

6.20.3 Dead Zone Generator

W90P710 PWM is implemented with Dead Zone generator. They are built for power device protection. This function enables generation of a programmable time gap at the rising of PWM output waveform. User can program PWM_PPR [31:24] and PWM_PPR [23:16] to determine the Dead Zone interval.

Publication Release Date: September 19, 2006 - 493 - Revision B2 Dead zone generator operation PWM_out1 PWM_out1_n PWM_out1_DZ PWM_out1_n_DZ Dead zone interval

6.20.4 PWM Timer Start procedure

Setup clock selector (PWM_CSR) 2. Setup prescaler & dead zone interval (PWM_PPR) 3. Setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and PWM timer off. (PWM_PCR) 4. Setup comparator register (PWM_CMR) 5. Setup counter register (PWM_CNR) 6. Setup interrupt enable register (PWM_PIER) 7. Enable PWM timer (PWM_PCR)

6.20.5 PWM Timer Stop procedure

Method 1 : Set 16-bit down counter(PWM_CNR) as 0, and monitor PWM_PDR. When PWM_PDR reaches to 0, disable PWM timer (PWM_PCR). (Recommended) Method 2 : Set 16-bit down counter(PWM_CNR) as 0. When interrupt request happen, disable PWM timer (PWM_PCR). (Recommended) Method 3 : Disable PWM timer directly (PWM_PCR). (Not recommended)

494 -

6.20.6 PWM Register Map

Publication Release Date: September 19, 2006 - 495 - Revision B2 BITS DESCRIPTIONS [31:24] DZI1 DZI1: Dead zone interval register 1, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 2. [23:16] DZI0 DZI0: Dead zone interval register 0, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 0. [15:8] CP1 CP1 : Clock prescaler 1 for PWM Timer channel 2 & 3 Clock input is divided by (CP1 + 1) before it is fed to the counter. 2 & 3 If CP1=0, then the prescaler 1 output clock will be stopped. [7:0] CP0 CP0 : Clock prescaler 0 for PWM Timer channel 0 & 1 Clock input is divided by (CP0 + 1) before it is fed to the counter. 0 & 1 If CP0=0, then the prescaler 0 output clock will be stopped. PWM Clock Select Register (PWM_CSR) REGISTER ADDRESS R/W PWM_CSR 0xFFF8_7004 R/W PWM Clock Select Register 0x0000_0000 Reserved Reserved Reserved CSR3 Reserved CSR2 Reserved CSR1 Reserved CSR0 BITS DESCRIPTIONS [14:12] CSR3 Select clock input for channel 3 [10:8] CSR2 Select clock input for channel 2. [6:4] CSR1 Select clock input for channel 1 [2:0] CSR0 Select clock input for channel 0

496 - CSR3 INPUT CLOCK DIVIDED BY 000 001 010 011 100 PWM Control Register (PWM_PCR) REGISTER ADDRESS R/W

PWM_PCR 0xFFF8_7008 R/W PWM Control Register 0x0000_0000 Reserved Reserved PCR19 PCR18 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 PCR09 PCR08 PCR07 PCR06 PCR05 PCR04 PCR03 PCR02 PCR01 PCR00 BITS DESCRIPTIONS [19] PCR 19 Channel 3 toggle/one shot mode 1 = toggle mode 0 = one shot mode [18] PCR 18 Channel 3 Inverter on/off 1 = inverter on 0 = inverter off [17] PCR 17 Reserved [16] PCR 16 Channel 3 enable/disable 1 = enable 0 = disable

Publication Release Date: September 19, 2006 - 497 - Revision B2 Continued BITS DESCRIPTIONS [15] PCR 15 Channel 2 toggle/one shot mode 1 = toggle mode 0 = one shot mode [14] PCR 14 Channel 2 Inverter on/off 1 = inverter on 0 = inverter off [13] PCR 13 Reserved [12] PCR 12 Channel 2 enable/disable 1 = enable 0 = disable [11] PCR 11 Channel 1 toggle/one shot mode 1 = toggle mode 0 = one shot mode [10] PCR 10 Channel 1 Inverter on/off 1 = inverter on 0 = inverter off [09] PCR 09 Reserved [08] PCR 08 Channel 1 enable/disable 1 = enable 0 = disable [07] PCR 07 Reserved [06] PCR 06 Reserved [05] PCR 05 Dead-Zone generator 1 enable/disable 1 = enable dead-zone generator 0 = disable dead-zone generator [04] PCR 04 Dead-Zone generator 0 enable/disable 1 = enable dead-zone generator 0 = disable dead-zone generator

498 - Continued BITS DESCRIPTIONS [03] PCR 03 Channel 0 toggle/one shot mode 1 = toggle mode 0 = one shot mode [02] PCR 02 Channel 0 Inverter on/off 1 = inverter on 0 = inverter off [01] PCR 01 Reserved [00] PCR 00 Channel 0 enable/disable 1 = enable 0 = disable PWM Counter Register 0/1/2/3 (PWM_CNR0/1/2/3) REGISTER ADDRESS R/W

PWM_CNR0 0xFFF8_700C R/W PWM Counter Register 0 0x0000_0000 PWM_CNR1 0xFFF8_7018 R/W PWM Counter Register 1 0x0000_0000 PWM_CNR2 0xFFF8_7024 R/W PWM Counter Register 2 0x0000_0000 PWM_CNR3 0xFFF8_7030 R/W PWM Counter Register 3 0x0000_0000 Reserved Reserved CNRx[15:8] CNRx[7:0]

Publication Release Date: September 19, 2006 - 499 - Revision B2 BITS DESCRIPTIONS [31:16] Reserved [15:0] CNRx CNR: PWM counter/timer buffer. Inserted data range: 65535~0. Unit:

1 PWM clock cycle

Note 1: One PWM counter countdown interval = CNR + 1.If CNR is loaded as zero, PWM counter will be stopped. Note 2: Programmer can feel free to write data to CNR at any time, and it will be reloaded when PWM counter reaches zero. PWM Comparator Register 0/1/2/3 (PWM_CMR0/1/2/3) REGISTER ADDRESS R/W PWM_CMR0 0xFFF8_7010 R/W PWM Comparator Register 0 0x0000_0000 PWM_CMR1 0xFFF8_701C R/W PWM Comparator Register 1 0x0000_0000 PWM_CMR2 0xFFF8_7028 R/W PWM Comparator Register 2 0x0000_0000 PWM_CMR3 0xFFF8_7034 R/W PWM Comparator Register 3 0x0000_0000 Reserved Reserved CMRx[15:8] CMRx[7:0] BITS DESCRIPTIONS [31:16] Reserved [15:0] CMRx CMR: PWM comparator register Inserted data range: 65535~0. CMR is used to determine PWM output duty ratio. Note 1: PWM duty = CMR + 1.If CMR is loaded as zero, PWM duty = Note 2: Programmer can feel free to write data to CMR at any time, and it will be reloaded when PWM counter reaches zero.

500 - PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3) REGISTER ADDRESS R/W

PWM_PDR0 0xFFF8_7014 R PWM Data Register 0 0x0000_0000 PWM_PDR1 0xFFF8_7020 R PWM Data Register 1 0x0000_0000 PWM_PDR2 0xFFF8_702C R PWM Data Register 2 0x0000_0000 PWM_PDR3 0xFFF8_7038 R PWM Data Register 3 0x0000_0000 Reserved Reserved PDRx[15:8] PDRx[7:0] BITS DESCRIPTIONS [31:16] Reserved [15:0] PDRx PDR: PWM Data register. User can monitor PDR to get current value in 16-bit down counter. PWM Interrupt Enable Register (PWM_PIER) REGISTER ADDRESS R/W PWM_PIER 0xFFF8_703C R/W PWM Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved PIER3 PIER2 PIER1 PIER0

Publication Release Date: September 19, 2006 - 501 - Revision B2 BITS DESCRIPTIONS [31:4] Reserved [3] PIER3 Enable/Disable PWM counter channel 3 interrupt request 1 = enable 0 = disable [2] PIER2 Enable/Disable PWM counter channel 2 interrupt request 1 = enable 0 = disable [1] PIER1 Enable/Disable PWM counter channel 1 interrupt request 1 = enable 0 = disable [0] PIER0 Enable/Disable PWM counter channel 0 interrupt request 1 = enable 0 = disable PWM Interrupt Indication Register (PWM_PIIR) REGISTER ADDRESS R/W/C PWM_PIIR 0xFFF8_7040 R/C PWM Interrupt Indication Register 0x0000_0000 Reserved Reserved Reserved Reserved PIIR3 PIIR2 PIIR1 PIIR0 BITS DESCRIPTIONS [3] PIIR3 PWM counter channel 3 interrupt flag [2] PIIR2 PWM counter channel 2 interrupt flag [1] PIIR1 PWM counter channel 1 interrupt flag [0] PIIR0 PWM counter channel 0 interrupt flag Note: User can clear each interrupt flag by writing a zero to corresponding bit in PIIR

502 -

6.21 Keypad Interface

W90P710 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input. KPI scans an array up to 16x8 with an external 4 to 16 decoder. It can also be programmed to scan 8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the scan signals are dived by W90P710 itself. For minimum pin counts application, an auxiliary priority encoder (TTL 74148) can be used to encode 8 columns input to 3 binary code and one indicator flag. Total 8 pins are required to implement 16x8 key scan. Any 1 or 2 keys in the array that pressed are debounced and encoded. The keypad controller scan key matrix from ROW0 COL 0 Æ 1 Æ 2 …. Æ 7, ROW1 COL 0 Æ 1 Æ 2 … Æ 7 till to ROW 16 (or ROW 8 or ROW 4) COL 0 Æ 0 Æ 1 …. Æ 7. If more than 2 keys are pressed, only the keys or apparent keys in the array with the lowest address will be decoded. KPI also supports 2-keys scan interrupt and specified 3-keys interrupt or chip reset. If the 3 pressed keys matches with the 3 keys defined in KPI3KCONF, it will generate an interrupt or chip reset to nWDOG reset output depend on the ENRST setting. The interrupt is generated whenever the scanner detects a key is pressed. The interrupt conditions are 1 key, 2 keys and 3keys. W90P710 provides two keypad connecting interface. One is allocated in LCD (GPIO30-41) interface, the other is in Ethernet RMII PHY interface and I2C interface 2 SDA1, SCL1 (GPIO42-51). Software should set KPSEL bit in KPICONF register to decide which interface is used as keypad connection port. The keypad interface has the following features: z maximum 16x8 array z programmable debounce time z low-power wakeup mode z programmable three-key reset

Publication Release Date: September 19, 2006 - 503 - Revision B2 W90P710 4 :16 DECODER ROW[[16:0] KPIC[7:0] KPIR[3:0] COL[7:0] 16x8 key pad matrix Fig. 6.21.1 W90P710 Keypad Interface

6.21.1 KeyPad Interface Register Map

0xFFF8_8000 R/W Keypad controller configuration Register 0x0000_0000 KPI3KCONF 0xFFF8_8004 R/W Keypad controller 3-keys configuration register 0x0000_0000 KPILPCONF 0xFFF8_8008 R/W Keypad controller low power configuration register 0x0000_0000 KPISTATUS 0xFFF8_800C R/O Keypad controller status register 0x0000_0000

504 -

6.21.2 Register Description

Keypad Controller Configuration Register (KPI_CONF) REGISTER ADDRESS R/W 0xFFF8_8000 R/O key pad configuration register 0x0000_0000 RESERVED RESERVED ENCODE ODEN KPSEL ENKP KSIZE DBTC PRESCALE BITS [31:22] RESERVED [21] ENCODE Enable Encode Function If an auxiliary 8 to 3 encoder is used to minimize keypad interface pin counts, user can connect encoder data to KPCOL[2:0] and indicator flag (low active) to KPCOL[3]. 1 = enable encoder function 0 = default. (8 column inputs) [20] ODEN Open Drain Enable If there are more than one key are pressed in the same column, then “short-circuit” will appear between active scan and inactive scan row. Software can set this bit HIGH to enable scan output KPROW[3:0] pins work as “open-drain” to avoid the “short-circuit”. 1 = Open drain 0 = push-pull driver [19] KPSEL Key pad select W90P710 provide two interfaces for keypad function. Software should set this bit to select which interface is used to connect keypad matrix. 1 = pin#23 ~#34 is used as keypad interface 0 = pin #81~88 and #19,#20 are used as keypad interface

Publication Release Date: September 19, 2006 - 505 - Revision B2 Continued BITS [18] ENKP Key pad scan enable Setting this bit high enable the key scan function. 1 = enable key pad scan 0 = disable key pad scan [17:16] KSIZE Key array size KSIZE Key array size 2’b00 4x8, 3x8, 2x8, 1x8 2’b01 8x8, 7x8, 6x8, 5x8 2’b1x 16x8, 15x8, 14x8, 13x8, 12x8, 11x8, 10x8, 9x8 [15:8] DBTC Debounce terminal count Debounce counter counts the number of consecutive scans that decoded the same keys. When de-bounce counter counter is equal to terminal count it will generate a key scan interrupt. [7:0] PRESCALE Row scan cycle pre-scale value This value is used to prescale row scan cycle. The prescale counter is clocked by 0.9375MHz clock. Key array scan time = 1.067us x PRESCALE x16 ROWS The following example is the scan time for PRESCALE = 0xFA Tscan_time = 1.067us x 250 x16 = 4.268ms If debounce terminal count = 0x05, key detection interrupt is fired in approximately 21.34ms. The array scan time can range from 17.07us to 1.118 sec.

506 - COL[0] COL[1] COL[2] COL[3] GS 16x8 keys matrix ROW[15:0] COL[7:0] IN[7:0] 74148 ENCODER 74138 ROW[3:0] W90P710 keypad I/F with 8:3 encoder Fig. 6.21.1 Keypad Interface with row decoder and column encoder Keypad Controller 3-keys Configuration Register (KPI3KCONF) REGISTER ADDRESS R/W

0xFFF8_8004 W/R three-key configuration register 0x0000_0000 RESERVED EN3KY ENRST RESERVED K32R K32C RESERVED K31R K31C RESERVED K30R K30C

Publication Release Date: September 19, 2006 - 507 - Revision B2 BITS [31:26] RESERVED [25] EN3KY Enable three-keys detection Setting this bit enables hardware to detect 3 keys specified by software [24] ENRST Enable three-key reset Setting this bit enable hardware reset when three-key is detected. EN3KY ENRST Function X three-key function is disable generate three-key interrupt hardware reset by three-key-reset [23] RESERVED [22:19] K32R The #2 key row address The #2 means the row address and the column address is the highest of the specified 3-kyes. [18:16] K32C The #2 key column address [15] RESERVED [14:11] K31R The #1 key row address The #1 means the row address and the column address is the 2nd of the specified 3-kyes. [10:8] K31C The #1 key column address [7] RESERVED [6:3] K30R The #0 key row address The #0 means the row address and the column address is the lowest of the specified 3-kyes. [2:0] K30C The #0 key column address Application Note: Due to hardware scan from {row[0], col[0]}, {row[0], col[1]}, …, to {row[15], col[7]} the {K30R,K30C} should be filled the lowest address of the three-keys. For example, if {2,0} {4,6}, {1,3} keys are defined as three-keys. Software should set {K30R, K30C} = {1, 3}, {K31R, K31C} = {2,

508 - KeyPad Interface Low Power Mode Configuration Register (KPILPCONF) REGISTER ADDRESS R/W

0xFFF8_8008 W/R Low power configuration register 0x0000_0000 RESERVED WAKE LPWCEN RESERVED LPWR BITS [31:17] RESERVED [16] WAKE Lower power wakeup enable Setting this bit enables low power wakeup 1 = wakeup enable 0 = not enable [15:8] LPWCEN Low power wakeup column enable Specify columns for low power wakeup. For example, if user wants to use keys in row N and column 0, 2, 5 to wake up W90P710, then the LPWCEN should be fill 8’b00100101. Application restriction: when ENCODE=1 case, LPWCEN should be set as 0xFF ie, all columns in specified row are used as wake up input. In this case, user can not specify special cloumn(s) to wake up W90P710. [7:4] RESERVED [3:0] LPWR Low power wakeup row address Define the row address keys used to wakeup. For 16x8 or 8x8 (with 4:16 or 3:8 decoder) keypad key configuration, LPWR means “Hex” code but for 4x8 (without decoder), LPWR means “binary” code. For example, if user wants to use all keys on row 3 of 16x8 keypad to wakeup W90P710, then 0x3 should be fill into this register but for 4x8 keypad it should be filled as 4’b1000.

Publication Release Date: September 19, 2006 - 509 - Revision B2 Key Pad Interface Status Register (KPISTATUS) REGISTER ADDRESS R/W 0xFFF8_800C R/O key pad status register 0x0000_0000 RESERVED RESERVED INT

3 K R S T

[31:22] RESERVED [21] INT Key interrupt This bit indicates the key scan interrupt is active and that one or two keys have changed status. The interrupt also occur when the three specified keys are detected if ENRST bit in KPI3KFCON is cleared. It will be cleared by hardware automatically when software read KPISTATUS register. [20] 3KRST 3-Keys reset flag This bit is a record flag for software reference, it will be set after 3- keys reset occur. 1 = 3 keys reset 0 = not reset. This bit is cleared while it is read. [19] PDWAKE Power Down Wakeup flag This flag indicates the chip is wakeup from power down by keypad 1 =wakeup up by keypad 0 = not wakeup [18] 3KEY Specified three-key is detected. This flag indicates specified-three-keys was detected. Software can read this bit to know the keypad interrupt is 3 key or not.

510 - Continued BITS

[17] 2KEY Double-key press This bit indicates that 2 keys have been detected. Software can read {KEY1R, KEY1C} and {KEY0R, KEY0C} to know which two keys are pressed. [16] 1KEY Single-key press This bit indicates that 1 key has been detected. Software can read {KEY0R, KEY0C} to know which key is pressed. [15] RESERVED [14:11] KEY1R KEY1 row address This value indicates key1 row address. The keypad controller scan keypad matrix from row 0, column0 Æ1 Æ2 …. Æ 7 and then row1 column 0 Æ 1 Æ 2 Æ7 so the lowest key address will be stored in {KEY0R, KEY0C}. This register stores the 2nd address, if more than one key is pressed. [10:8] KEY1C KEY1 column address This value indicates key1 column address.. [7] RESERVED [6:3] KEY0R KEY1 row address This value indicates key0 row address. This value indicates key0 row address. This value indicates key1 row address. The keypad controller scan keypad matrix from row 0, column0 Æ1 Æ2 …. Æ 7 and then row1 col 0 Æ 1 Æ 2 Æ …Æ 7 still to row16 (or 8, or 4) column 0 Æ 1 Æ 2 ….. Æ 7 so the lowest key address will be stored in {KEY0R, KEY0C}. [2:0] KEY0C KEY1 column address This value indicates key0 row address.

Publication Release Date: September 19, 2006 - 511 - Revision B2

6.22 PS2 Host Interface Controller

W90P710 PS2 host controller interface is an APB slave consisted of PS2 protocol. It is used to connect to your IBM keyboard or other device through PS2 interface. For example, the IBM keyboard will sends scan codes to the host controller, and the scan codes will tell your Keyboard Bios what keys you have pressed or released. Besides Scan codes, commands can also be sent to the keyboard from host. The most common commands would be the setting/resetting of the status indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs). The PS2 interface implements a bi-directional protocol. The keyboard can send data to the Host and the Host can send data to the Keyboard using two PS2 Clock and PS2 Data lines. Both the PS2 Clock and Data lines are Open Collector bi-directional I/O lines. The Host has the ultimate priority over direction. The keyboard is free to send data to the host when both the PS2 Data and PS2 Clock lines are high (Idle). If the host takes the PS2 Clock line low, the keyboard will buffer any data until the PS2 Clock is released, ie goes high. The transmission of data in the forward direction, ie Keyboard to Host is done with a frame of 11 bits. The first bit is a Start Bit (Logic 0) followed by 8 data bits (LSB First), one Parity Bit (Odd Parity) and a Stop Bit (Logic 1). Each bit should be read on the falling edge of the clock. The Keyboard will generate the clock. The frequency of the clock signal typically ranges from 20 to 30 KHz. The Host to Keyboard Protocol is initiated by taking the PS2 data line low. It is common to take the PS2 Clock line low for more than 60us and then the KBD data line is taken low, while the KBD clock line is released. After that, the keyboard will start generating a clock signal on its PS2 clock line. After the first falling edge has been detected, host will load the first data bit on the PS2 Data line. This bit will be read into the keyboard on the next falling edge, after which host place the next bit of data. This process is repeated for the 8 data bits. It will follow an Odd Parity Bit after the data byte.

512 -

6.22.1 PS2 Host Controller Interface Register Map

0xFFF8_9000 R/W PS2 Host Controller Command Register 0x0000_0000 PS2STS 0xFFF8_9004 R/W PS2 Host Controller Status Register 0x0000_0000 PS2SCANCODE 0xFFF8_9008 RO PS2 Host Controller RX Scan Code Register 0x0000_0000 PS2ASCII 0xFFF8_900C RO PS2 Host Controller RX ASCII Code Register 0x0000_0000

6.22.2 Register Description

PS2 Host Controller Command Register (PS2_CMD) REGISTER ADDRESS R/W 0xFFF8_9000 R/W Command register 0x0000_0000 RESERVED RESERVED RESERVED TRAP_SHIFT EnCMD PS2CMD BITS DESCRIPTIONS [31:10] RESERVED [9] TRAP_SHIFT Trap Shift Key Output to Scan Code Register If the shift key scan code (0x12 0r 0x59) is received by host, software can indicate host whether to update to scan code register or not. No ASCII or SCAN codes will be reported for the shift keys if this bit is set. In this condition, host will only report the shift keys at the RX_shift_key bit of Status register and no interrupt will occur for the shift keys. This is useful for those who wish to use the ASCII data stream and don’t want to “manually” filter out the shift key codes. This bit is clear by default.

Publication Release Date: September 19, 2006 - 513 - Revision B2 Continued BITS DESCRIPTIONS [8] EnCMD Enable write PS2 Host Controller Commands This bit enables the write function of Host controller command to device. Set this bit will start the write process of PS2CMD content and hardware will automatically clear this bit while write process is finished. [7:0] PS2CMD PS2 Host Controller Commands This command filed is sent by the Host to the Keyboard. The most common command would be the setting/resetting of the Status Indicators (i.e. the Num lock, Caps Lock & Scroll Lock LEDs). PS2 Host Controller Status Register (PS2_STS) REGISTER ADDRESS R/W 0xFFF8_9004 R/W Status register 0x0000_0000 RESERVED RESERVED RESERVED RESERVED TX_err TX_IRQ RESERVED RX_IRQ BITS DESCRIPTIONS [31:6] RESERVED [5] TX_err This Transmit Error Status bit indicates software that device doesn’t response ACK after Host wrote a command to it. This bit is valid when TX_IRQ is asserted. It will automatically reset after software starts next command writing process. This bit is read only. [4] TX_IRQ This Transmit Complete Interrupt bit indicates software that the process of Host controller writing command to device is finished. Software needs to write one to this bit to clear this interrupt.

514 - Continued BITS DESCRIPTIONS [3:1] Reserved [0] RX_IRQ This Receive Interrupt bit indicates software that Host controller receives one byte data from device. This data is stored at PS2_SCANCODE register. Software needs to write one to this bit to clear this interrupt after reading receiving data in RX_SCAN_CODE register. Note that the reception of the Extend (0xE0) and Release (0xF0) scan code will not cause an interrupt by host. The case of the shift key codes will be determined by the TRAP_SHIFT bit of PS2_CMD register. PS2 Host Controller RX Scan Code Register (PS2_SCANCODE) REGISTER ADDRESS R/W

0xFFFF_9008 R/W key pad c RX Scan Code Register 0x0000_0000 RESERVED RESERVED RESERVED RX_shift_key RX_release RX_extend RX_SCAN_CODE BITS DESCRIPTIONS [31:11] RESERVED [10] RX_shift_key This Receive Shift Key bit indicates that left or right shift key on the keyboard is hold. This bit is read only and will clear by host when the release shift key codes are received. [9] RX_release Receive Released Byte When one key has been released, the keyboard will send F0 (hex) to inform Host controller. This bit indicates software that Host controller receives release byte (F0). This bit is read only and will update when host has received next data byte.

Publication Release Date: September 19, 2006 - 515 - Revision B2 Continued BITS DESCRIPTIONS [8] RX_extend Receive Extend Byte A handful of the keys on keyboard are extended keys and thus require two more scan code. These keys are preceded by an E0 (hex). This bit indicates software that Host controller receives extended byte (E0). This bit is read only and will update when host has received next data byte. [7:0] RX_SCAN_CODE PS2 Host Controller Received Data Field This field stores the original data content transmitted from device. This filed is valid when RX_IRQ is asserted. Note that host will not report “Extend” or “Release” scan code to this field and not generate interrupt if they are received by host, i.e. 0xE0 and 0xF0. The case of the shift key codes will be determined by the TRAP_SHIFT bit of PS2_CMD register. PS2 Host Controller RX ASCII Code Register (PS2_ASCII) REGISTER ADDRESS R/W 0xFFF8_900C R/W key pad c RX ASCII Code Register 0x0000_0000 RESERVED RESERVED RESERVED RX_ASCII_CODE BITS DESCRIPTIONS [31:8] RESERVED [7:0] RX_ASCII_CODE PS2 Host Controller Received Data Filed This field stores the ASCII data content transmitted from device. Therefore, this part translates the scan code into an ASCII value. It will be read as 0x2E when there is no ASCII code mapped to the scan code stored in RX_SCAN_CODE register. This filed is valid when RX_IRQ is asserted.

516 - 7. ELECTRICAL SPECIFICATIONS

7.1 Absolute Maximum Ratings

-40 °C ~ +125°C -0.5V ~ 6V -0.5V ~ 1.92V -0.5V ~ 3.6V 100mA 4MHz ~ 30MHz

7.2 DC Specifications

7.2.1 Digital DC Characteristics (Normal test conditions: VDD33/USBVDD = 3.3V+/- 0.3V, VDD18/DVDD18/AVDD18 = 1.8V+/- 0.18V TA = -40 °C ~ +85 °C unless otherwise specified) SYMBOL PARAMETER CONDITION MIN. MAX. UNIT VDD33/ USB1VDD USB2VDD Power Supply 3.00 3.60 V VDD18/ DVDD18/ AVDD18/ RTCVDD18 Power Supply 1.62 1.98 V VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2.0 5.5 V VT+ Schmitt Trigger positive-going threshold 1.47 1.5 V VT- Schmitt trigger negative-going threshold 0.89 0.95 V VOL Output Low Voltage Depend on driving 0.4 V VOH Output High Voltage Depend on driving 2.4 V ICC1 1.8V Supply Current FCPU = 80MHz 150 mA ICC2 3.3V Supply Current FCPU = 80MHz mA ICCRTC RTC 1.8V Supply Current FRTC = 32.768KHZ uA IIH Input High Current VIN = 2.4 V µA IIL Input Low Current VIN = 0.4 V µA IIHP Input High Current (pull-up) VIN = 2.4 V -15 -10 µA IILP Input Low Current (pull-up) VIN = 0.4 V -55 -25 µA IIHD Input High Current (pull-down) VIN = 2.4 V µA IILD Input Low Current (pull-down) VIN = 0.4 V µA

Publication Release Date: September 19, 2006 - 517 - Revision B2 Table 7.2.1TSMC IO DC Characteristics PARAMETER MIN. TYP. MAX. VIL Input Low Voltage -0.3V 0.8V VIIHH Input High Voltage 5.5V VT Threshold point 1.46V 1.59V 1.75V VT+ Schmitt trig low to high threshold point 1.47V 1.50V 1.50V VT- Schmitt trig, high to low threshold point 0.90V 0.94V 0.96V II Input leakage current @VI= 3.3V or 0V +/- 10uA Ioz Tri-state output leakage current @Vo =3.3V or 0V +/- 10UA RPU Pull-up resister 44KΩ 66KΩ 110KΩ RPD Pull-down resister 25KΩ 50KΩ 110KΩ VOL Output low voltage @IOL(min) 0.4V VOH Output high voltage @IOH (min) 2.4V Low level output current @VOL = 0.4V 4mA 4.9mA 7.4mA 9.8mA Low level output current @VOL = 0.4V 8mA 9.7mA 14.9mA 19.5mA IOL Low level output current @VOL = 0.4V 12mA 14.6mA 22.3mA 29.3mA High level output current @VOH = 2.4V 4mA 6.3mA 12.8mA 21.2mA High level output current @VOH = 2.4V 8mA 12.7mA 25.6mA 42.4mA IOH High level output current @VOH = 2.4V 12mA 19.0mA 38.4mA 63.6mA NOTE: The values in this table are copied from TSMC 1P5M IO library tpz937g_240b silicon report. This table is just for reference. More precision DC vaule should refer to Alpha-Test result.

518 - 7.2.2 USB Transceiver DC Characteristics SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDI Differential Input Sensitivity DP − DM 0.2 V VCM Differential Common Mode Range Includes VDI range 0.8 2.5 V VSE Single Ended Receiver Threshold 0.8 2.0 V VOL Static Output Low Voltage RL of 1.5 KΩ to 3.6 V 0.3 V VOH Static Output High Voltage RL of 15 KΩ to VSS 2.8 3.6 V VCRS Output Signal Crossover Voltage 1.3 2.0 V ZDRV Driver Output Resistance Steady state drive Ω CIN Pin Capacitance pF

7.3 AC Specifications

7.3.1 EBI/SDRAM Interface AC Characteristics TDH TDSU 1.5V Output Valid Iutput Valid 1.5V 1.5V 1.5V MCLK MCLK D[31:0] D[31:0] SDRAM input to W90P710 W90P710 write to SDRAM TDO SYMBOL PARAMETER MIN. MAX. UNIT TDSU D [31:0] Setup Time ns TDH D [31:0] Hold Time ns TDO D [31:0], A [24:0], nSCS [1:0], SDQM [3:0], CKE, nSWE, nSRAS, nSCAS ns

Publication Release Date: September 19, 2006 - 519 - Revision B2 7.3.2 EBI/(ROM/SRAM/External I/O) AC Characteristics Address Valid R Data Write Data Vaild MCLK TDO nECS[3:0] A[21:0] nOE D[31:0] nWAIT nWBE[3:0] D[31:0] TNECSO TNECSO TADDO TNOEO TNOEO TDSU TDH TNWAH TNWBO TNWBO TNWASU SYMBOL ROM/SRAM/Flash or External I/O Chip Select Delay Time ns TNOEO ROM/SRAM or External I/O Bank Output Enable Delay ns TNWBO ROM/SRAM or External I/O Bank Write Byte Enable Delay ns TDH Read Data Hold Time ns TDSU Read Data Setup Time ns TDO Write Data Output Delay Time (SRAM or External I/O) ns TNWASU External Wait Setup Time ns TNWAH External Wait Hold Time ns

520 - 7.3.3 USB Transceiver AC Characteristics Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Full Speed: 4 to 20ns at CL = 50pF Differential Data Lines 10% Rise Time 90% Fall Time tF tR 10% 90% CL CL Data Signal Rise and Fall Time USB Transceiver AC Characteristics SYMBOL

CL = 50 pF ns TF Fall Time CL = 50 pF ns TRFM Rise/Fall Time Matching 110 TDRATE Full Speed Data Rate Average bit rate (12 Mb/s ± 0.25%) 11.97 12.03 Mbps

Publication Release Date: September 19, 2006 - 521 - Revision B2 7.3.4 EMC RMII AC Characteristics The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3. PHY_REFCLK PHY_TXEN PHY_TXD[1:0] TTXO valid data TTXH TFREQ TRXS TRXH PHY_RXERR PHY_RXD[1:0] PHY_CRSDV TDUTY valid data SYMBOL RMII reference clock frequency MHz TDUTY RMII clock duty 35% 50% 65% ns TTXO Transmit data output delay ns TTXH Transmit data hold time ns TRXS Receive data setup time ns TRXH Receive data hold time ns

522 - PHY_MDC PHY_MDIO (Write) TMDO valid data TMDH valid data TMDS TMDH PHY_MDIO (Read) SYMBOL

Publication Release Date: September 19, 2006 - 523 - Revision B2 7.3.5 LCD Interface AC Characteristics THOLD TDELAY VCLK VSYNC HSYNC VDEN VD[23:0] TPIXCLK valid data SYMBOLS VSYNC, HSYNC, VDEN and VD[23:0] output delay from VCLK rising edge ns THOLD VSYNC, HSYNC, VDEN and VD[23:0] output data hold time from VCLK rising edge ns

524 - 7.3.6 SD Interface AC Characteristics Twh Tpp Twl Tisu Tih Tod(max) Toh SD_CLK SD_CMD SD_DAT (Input) SD_CMD SD_DAT (Output) SYMBOLS

MIN. TYP. MAX. UNIT Tpp SD Clock Frequency MHz Twh SD Clock High Time ns Twl SD Clock Low Time ns Input CMD, DAT (reference to SD_CLK rising edge) Tisu Input Setup Time ns Tih Input Hold Time ns Output CMD, DAT (reference to SD_CLK falling edge) Tod Output Delay Time ns

Publication Release Date: September 19, 2006 - 525 - Revision B2 7.3.7 AC97/I2S Interface AC Characteristics TISU TOD TIHD TOH AC97_BCLK AC97_DATAO AC97_SYNC AC97_DATAI TCLK_PERIOD SYMBOLS TYP. MAX UNIT TCLK_PERIOD AC97 Bit Clock Frequency 12.288 MHz TOD AC97_DATAO and AC97_SYNC output delay from AC97_BCLK rising edge ns TOH AC97_DATAO and AC97_SYNC output hold time from AC97_BCLK rising edge ns TISU AC97_DATAI input setup time to AC97_BCLK falling edge ns TIHD AC97_DATAI input hold time from AC97_BCLK falling edge ns

526 - TDIS TDIH TDOH Tout_delay TBCLK_PERIOD I2S_BCLK I2S_DATAO I2S_RLCLK I2S_DATAI SYMBOLS

TBCLK_PERIOD IIS Bit Clock Frequency Note:depend on codec spec. and register setting MHz Tout_delay IIS_DATAO and IIS_RLCLK output delay from IIS_BCLK falling edge ns TDOH IIS_DATAO and IIS_RLCLK data output hold time from IIS_BCLK falling edge ns TDIS IIS_DATAI input setup time to IIS_BCLK rising edge ns TDIH IIS_DATAI input hold time from IIS_BCLK rising edge 100 ns

Publication Release Date: September 19, 2006 - 527 - Revision B2 7.3.8 Smart Card Interface AC Characteristics Tclk_dat Tclkh Tclkl FSC Tclk_rst SC_RST SC_CLK SC_DAT TR TF SYMBOL Rising and falling time of RST signal CL = 30pF (Max) 0.8 us TR and TF for CLK Rising and falling time of CLK signal CL = 30pF (Max) 8% of clock period TR and TF for DAT (Transmit) Rising and falling time of DAT signal in transmission mode CL = 30pF (Max) 0.8 us TR and TF for DAT (Receive) Rising and falling time of DAT siganl in receive mode 1.2 us FSC Smart card clock frequency 2.5 MHz Tclkh Smart card clock high time 40% 50% 60% clock Tclkl Smart card clock low time 40% 50% 60% clock Tclk_dat DAT output delay from SC_CLK falling edge ns Tclk_rst RST output delay from SC_CLK falling edge ns

528 - 7.3.9 I2C Interface AC Characteristics TSU:STO TSU:DAT2 TLOW THIGH Thd:DAT TSU:DAT Thd:STA SCL SDA SCL SDA TSU:SAT

Publication Release Date: September 19, 2006 - 529 - Revision B2 SYMBOL Thd:STA Start condition hold time us Receive data setup time 0.1 us TSU:DAT Transmit data output delay 0.5 us Receive data hold time us THD:DAT Transmit data hold time 0.9 us TSU:DAT2 SDA setup time (before STOP condition) 0.5 us TSU:STO Stop condition setup time us TSU:STA Restart condition setup time 1.5 us

7.3.10 USI Interface AC Characteristics

(TX_NEG =1) SSPTXD (TX_NEG =0)

530 - FUSI Tlead TCLKH TCLKL TISU TISU TIH TIH Tlag SFRM SCLK SSPRXD (RX_NEG =1) SSPRXD (RX_NEG =0) SYMBOL

12.5 ns TCLKL USI clock low time ns TISU Data input setup time ns TIH Data input hold time ns Tlead USI enable lead time 12.5 ns Tlag USI enable lag time 12.5 ns TOD USI output data valid time ns

Publication Release Date: September 19, 2006 - 531 - Revision B2

7.3.11 PS2 Interface AC Characteristics

PS2_CLK PS2_DATA Start Bit Bit 0 Parity Bit STOP Bit 1st CLK 2nd CLK 10th CLK 11th CLK Timing for data received from the auxiliary device 1st CLK 2nd CLK 9th CLK 10th CLK 11th CLK PS2_DATA PS2_CLK Parity Bit Timing for data send to the auxiliary device Bit 0 SYMBOL MIN. MAX. UNIT Time from DATA transition to falling edge of CLK us Time form rising edge of CLK to DATA transition T4-5 us Duration of CLK inactive us Duration of clock active us Time to auxiliary device inhibit after clock 11 to ensure the auxiliary device does not start another transmission us Duration of CLK inactive us Duration of CLK active us Time to fom inactive to active CLK transition, used to time when the auxiliary device samples DATA us

532 - 8. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90P710CD LQFP176 176 Leads, body 22 x 22 x 1.4 mm W90P710CDG LQFP176 176 Leads, body 22 x 22 x 1.4 mm, Lead free package

Publication Release Date: September 19, 2006 - 533 - Revision B2 9. PACKAGE SPECIFICATIONS 176L LQFP (20X20X1.4 mm footprint 2.0mm)

534 - 10. APPENDIX A: W90P710 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written System Manager Control Registers Map REGISTER ADDRESS R/W

0xFFF0_0000 R Product Identifier Register 0xX090.0710 ARBCON 0xFFF0_0004 R/W Arbitration Control Register 0x0000_0000 PLLCON 0xFFF0_0008 R/W PLL Control Register 0x0000_2F01 CLKSEL 0xFFF0_000C R/W Clock Select Register 0x1FFF_3FX8 PLLCON1 0xFFF0_0010 R/W PLL Control Register 2 0x0001_0000 I2SCKCON 0xFFF0_0014 R/W Audio IIS Clock Control Register 0x0000_0000 IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register 0x0000_0000 IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register 0x0000_0000 PMCON 0xFFF0_0028 R/W Power Manager Control Register 0x0000_0000 USBTxrCON 0xFFF0_0030 R/W USB Transceiver Control Register 0x0000_0000 External Bus Interface Control Registers Map REGISTER ADDRESS R/W 0xFFF0_1000 R/W EBI control register 0x0001_0000 ROMCON 0xFFF0_1004 R/W ROM/FLASH control register 0x0000_0XFC SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800 SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800 SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000 SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000 EXT0CON 0xFFF0_1018 R/W External I/O 0 control register 0x0000_0000 EXT1CON 0xFFF0_101C R/W External I/O 1 control register 0x0000_0000 EXT2CON 0xFFF0_1020 R/W External I/O 2 control register 0x0000_0000 EXT3CON 0xFFF0_1024 R/W External I/O 3 control register 0x0000_0000 CKSKEW 0xFFF0_1F00 R/W Clock skew control register (for testing) 0xXXXX_0038

Publication Release Date: September 19, 2006 - 535 - Revision B2 Cache Control Registers Map REGISTER ADDRESS R/W 0xFFF0_2000 R/W Cache configuration register 0x0000_0000 CAHCON 0xFFF0_2004 R/W Cache control register 0x0000_0000 CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000 EMC Registers Map REGISTER ADDRESS R/W 0xFFF0_3000 R/W CAM Command Register 0x0000_0000 CAMEN 0xFFF0_3004 R/W CAM Enable Register 0x0000_0000 CAM0M 0xFFF0_3008 R/W CAM0 Most Significant Word Register 0x0000_0000 CAM0L 0xFFF0_300C R/W CAM0 Least Significant Word Register 0x0000_0000 CAM1M 0xFFF0_3010 R/W CAM1 Most Significant Word Register 0x0000_0000 CAM1L 0xFFF0_3014 R/W CAM1 Least Significant Word Register 0x0000_0000 CAM2M 0xFFF0_3018 R/W CAM2 Most Significant Word Register 0x0000_0000 CAM2L 0xFFF0_301C R/W CAM2 Least Significant Word Register 0x0000_0000 CAM3M 0xFFF0_3020 R/W CAM3 Most Significant Word Register 0x0000_0000 CAM3L 0xFFF0_3024 R/W CAM3 Least Significant Word Register 0x0000_0000 CAM4M 0xFFF0_3028 R/W CAM4 Most Significant Word Register 0x0000_0000 CAM4L 0xFFF0_302C R/W CAM4 Least Significant Word Register 0x0000_0000 CAM5M 0xFFF0_3030 R/W CAM5 Most Significant Word Register 0x0000_0000 CAM5L 0xFFF0_3034 R/W CAM5 Least Significant Word Register 0x0000_0000 CAM6M 0xFFF0_3038 R/W CAM6 Most Significant Word Register 0x0000_0000 CAM6L 0xFFF0_303C R/W CAM6 Least Significant Word Register 0x0000_0000 CAM7M 0xFFF0_3040 R/W CAM7 Most Significant Word Register 0x0000_0000 CAM7L 0xFFF0_3044 R/W CAM7 Least Significant Word Register 0x0000_0000 CAM8M 0xFFF0_3048 R/W CAM8 Most Significant Word Register 0x0000_0000 CAM8L 0xFFF0_304C R/W CAM8 Least Significant Word Register 0x0000_0000 CAM9M 0xFFF0_3050 R/W CAM9 Most Significant Word Register 0x0000_0000 CAM9L 0xFFF0_3054 R/W CAM9 Least Significant Word Register 0x0000_0000 CAM10M 0xFFF0_3058 R/W CAM10 Most Significant Word Register 0x0000_0000 CAM10L 0xFFF0_305C R/W CAM10 Least Significant Word Register 0x0000_0000 CAM11M 0xFFF0_3060 R/W CAM11 Most Significant Word Register 0x0000_0000 CAM11L 0xFFF0_3064 R/W CAM11 Least Significant Word Register 0x0000_0000

536 - EMC Registers Map, continued REGISTER ADDRESS R/W

0xFFF0_3068 R/W CAM12 Most Significant Word Register 0x0000_0000 CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register 0x0000_0000 CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register 0x0000_0000 CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register 0x0000_0000 CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register 0x0000_0000 CAM14L 0xFFF0_307C R/W CAM14 Least Significant Word Register 0x0000_0000 CAM15M 0xFFF0_3080 R/W CAM15 Most Significant Word Register 0x0000_0000 CAM15L 0xFFF0_3084 R/W CAM15 Least Significant Word Register 0x0000_0000 TXDLSA 0xFFF0_3088 R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC RXDLSA 0xFFF0_308C R/W Receive Descriptor Link List Start Address Register 0xFFFF_FFFC MCMDR 0xFFF0_3090 R/W MAC Command Register 0x0000_0000 MIID 0xFFF0_3094 R/W MII Management Data Register 0x0000_0000 MIIDA 0xFFF0_3098 R/W MII Management Control and Address Register 0x0090_0000 FFTCR 0xFFF0_309C R/W FIFO Threshold Control Register 0x0000_0101 TSDR 0xFFF0_30A0 W Transmit Start Demand Register Undefined RSDR 0xFFF0_30A4 W Receive Start Demand Register Undefined DMARFC 0xFFF0_30A8 R/W Maximum Receive Frame Control Register 0x0000_0800 MIEN 0xFFF0_30AC R/W MAC Interrupt Enable Register 0x0000_0000 MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register 0x0000_0000 MGSTA 0xFFF0_30B4 R/W MAC General Status Register 0x0000_0000 MPCNT 0xFFF0_30B8 R/W Missed Packet Count Register 0x0000_7FFF MRPC 0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000 MRPCC 0xFFF0_30C0 R MAC Receive Pause Current Count Register 0x0000_0000 MREPC 0xFFF0_30C4 R MAC Remote Pause Count Register 0x0000_0000 DMARFS 0xFFF0_30C8 R/W DMA Receive Frame Status Register 0x0000_0000 CTXDSA 0xFFF0_30CC R Current Transmit Descriptor Start Address Register 0x0000_0000 CTXBSA 0xFFF0_30D0 R Current Transmit Buffer Start Address Register 0x0000_0000 CRXDSA 0xFFF0_30D4 R Current Receive Descriptor Start Address Register 0x0000_0000 CRXBSA 0xFFF0_30D8 R Current Receive Buffer Start Address Register 0x0000_0000

Publication Release Date: September 19, 2006 - 537 - Revision B2 EMC Registers Map, continued REGISTER ADDRESS R/W 0xFFF0_3200 R Receive Finite State Machine Register 0x0081_1101 TXFSM 0xFFF0_3204 R Transmit Finite State Machine Register 0x0101_1101 FSM0 0xFFF0_3208 R Finite State Machine Register 0 0x0001_0101 FSM1 0xFFF0_320C R Finite State Machine Register 1 0x1100_0100 DCR 0xFFF0_3210 R/W Debug Configuration Register 0x0000_003F DMMIR 0xFFF0_3214 R Debug Mode MAC Information Register 0x0000_0000 BISTR 0xFFF0_3300 R/W BIST Mode Register 0x0000_0000 GDMA Registers Map REGISTER ADDRESS R/W GDMA_CTL0 0xFFF0_4000 R/W Channel 0 Control Register 0x0000_0000 GDMA_SRCB0 0xFFF0_4004 R/W Channel 0 Source Base Address Register 0x0000_0000 GDMA_DSTB0 0xFFF0_4008 R/W Channel 0 Destination Base Address Register 0x0000_0000 GDMA_TCNT0 0xFFF0_400C R/W Channel 0 Transfer Count Register 0x0000_0000 GDMA_CSRC0 0xFFF0_4010 R Channel 0 Current Source Address Register 0x0000_0000 GDMA_CDST0 0xFFF0_4014 R Channel 0 Current Destination Address Register 0x0000_0000 GDMA_CTCNT 0xFFF0_4018 R Channel 0 Current Transfer Count Register 0x0000_0000 GDMA_CTL1 0xFFF0_4020 R/W Channel 1 Control Register 0x0000_0000 GDMA_SRCB1 0xFFF0_4024 R/W Channel 1 Source Base Address Register 0x0000_0000 GDMA_DSTB1 0xFFF0_4028 R/W Channel 1 Destination Base Address Register 0x0000_0000 GDMA_TCNT1 0xFFF0_402C R/W Channel 1 Transfer Count Register 0x0000_0000 GDMA_CSRC1 0xFFF0_4030 R Channel 1 Current Source Address Register 0x0000_0000 GDMA_CDST1 0xFFF0_4034 R Channel 1 Current Destination Address Register 0x0000_0000 GDMA_CTCNT 0xFFF0_4038 R Channel 1 Current Transfer Count Register 0x0000_0000

538 - USB Host Controller Registers Map REGISTER ADDRESS R/W

0xFFF0_5000 R Host Controller Revision Register 0x0000_0010 HcControl 0xFFF0_5004 R/W Host Controller Control Register 0x0000_0000 HcCommandStatus 0xFFF0_5008 R/W Host Controller Command Status Register 0x0000_0000 HcInterruptStatus 0xFFF0_500C R/W Host Controller Interrupt Status Register 0x0000_0000 HcInterruptEnbale 0xFFF0_5010 R/W Host Controller Interrupt Enable Register 0x0000_0000 HcInterruptDisbale 0xFFF0_5014 R/W Host Controller Interrupt Disable Register 0x0000_0000 HcHCCA 0xFFF0_5018 R/W Host Controller Communication Area Register 0x0000_0000 HcPeriodCurrentED 0xFFF0_501C R/W Host Controller Period Current ED Register 0x0000_0000 HcControlHeadED 0xFFF0_5020 R/W Host Controller Control Head ED Register 0x0000_0000 HcControlCurrentED 0xFFF0_5024 R/W Host Controller Control Current ED Register 0x0000_0000 HcBulkHeadEd 0xFFF0_5028 R/W Host Controller Bulk Head ED Register 0x0000_0000 HcBulkCurrentED 0xFFF0_502C R/W Host Controller Bulk Current ED Register 0x0000_0000 HcDoneHeadED 0xFFF0_5030 R/W Host Controller Done Head Register 0x0000_0000 HcFmInterval 0xFFF0_5034 R/W Host Controller Frame Interval Register 0x0000_2EDF HcFrameRemaining 0xFFF0_5038 R Host Controller Frame Remaining Register 0x0000_0000 HcFmNumber 0xFFF0_503C R Host Controller Frame Number Register 0x0000_0000 HcPeriodicStart 0xFFF0_5040 R/W Host Controller Periodic Start Register 0x0000_0000 HcLSThreshold 0xFFF0_5044 R/W Host Controller Low Speed Threshold Register 0x0000_0628 HcRhDescriptorA 0xFFF0_5048 R/W Host Controller Root Hub Descriptor A Register 0x0100_0002 HcRhDescriptorB 0xFFF0_504C R/W Host Controller Root Hub Descriptor B Register 0x0000_0000 HcRhStatus 0xFFF0_5050 R/W Host Controller Root Hub Status Register 0x0000_0000 HcRhPortStatus [1] 0xFFF0_5054 R/W Host Controller Root Hub Port Status [1] 0x0000_0000 HcRhPortStatus [2] 0xFFF0_5058 R/W Host Controller Root Hub Port Status [2] 0x0000_0000 USB Configuration Registers TestModeEnable 0xFFF0_5200 R/W USB Test Mode Enable Register 0x0XXX_XXXX OperationalModeEnable 0xFFF0_5204 R/W USB Operational Mode Enable Register 0x0000_0000

Publication Release Date: September 19, 2006 - 539 - Revision B2 USB Device Register Map REGISTER OFFSET R/W USB_CTL 0xFFF0_6000 R/W USB control register 0x0000_0000 VCMD 0xFFF0_6004 R/W USB class or vendor command register 0x0000_0000 USB_IE 0xFFF0_6008 R/W USB interrupt enable register 0x0000_0000 USB_IS 0xFFF0_600C R USB interrupt status register 0x0000_0000 USB_IC 0xFFF0_6010 R/W USB interrupt status clear register 0x0000_0000 USB_IFSTR 0xFFF0_6014 R/W USB interface and string register 0x0000_0000 USB_ODATA0 0xFFF0_6018 R USB control transfer-out port 0 register 0x0000_0000 USB_ODATA1 0xFFF0_601C R USB control transfer-out port 1 register 0x0000_0000 USB_ODATA2 0xFFF0_6020 R USB control transfer-out port 2 register 0x0000_0000 USB_ODATA3 0xFFF0_6024 R USB control transfer-out port 3 register 0x0000_0000 USB_IDATA0 0xFFF0_6028 R/W USB transfer-in data port0 register 0x0000_0000 USB_IDATA1 0xFFF0_602C R/W USB control transfer-in data port 1 0x0000_0000 USB_IDATA2 0xFFF0_6030 R/W USB control transfer-in data port 2 0x0000_0000 USB_IDATA3 0xFFF0_6034 R/W USB control transfer-in data port 3 0x0000_0000 USB_SIE 0xFFF0_6038 R USB SIE status Register 0x0000_0000 USB_ENG 0xFFF0_603C R/W USB Engine Register 0x0000_0000 USB_CTLS 0xFFF0_6040 R USB control transfer status register 0x0000_0000 USB_CONFD 0xFFF0_6044 R/W USB Configured Value register 0x0000_0000 EPA_INFO 0xFFF0_6048 R/W USB endpoint A information register 0x0000_0000 EPA_CTL 0xFFF0_604C R/W USB endpoint A control register 0x0000_0000 EPA_IE 0xFFF0_6050 R/W USB endpoint A Interrupt Enable register 0x0000_0000 EPA_IC 0xFFF0_6054 W USB endpoint A interrupt clear register 0x0000_0000 EPA_IS 0xFFF0_6058 R USB endpoint A interrupt status register 0x0000_0000 EPA_ADDR 0xFFF0_605C R/W USB endpoint A address register 0x0000_0000 EPA_LENTH 0xFFF0_6060 R/W USB endpoint A transfer length register 0x0000_0000 EPB_INFO 0xFFF0_6064 R/W USB endpoint B information register 0x0000_0000 EPB_CTL 0xFFF0_6068 R/W USB endpoint B control register 0x0000_0000 EPB_IE 0xFFF0_606C R/W USB endpoint B Interrupt Enable register 0x0000_0000 EPB_IC 0xFFF0_6070 W USB endpoint B interrupt clear register 0x0000_0000 EPB_IS 0xFFF0_6074 R USB endpoint B interrupt status register 0x0000_0000 EPB_ADDR 0xFFF0_6078 R/W USB endpoint B address register 0x0000_0000 EPB_LENTH 0xFFF0_607C R/W USB endpoint B transfer length register 0x0000_0000

540 - USB Device Register Map, continued REGISTER OFFSET R/W

EPC_INFO 0xFFF0_6080 R/W USB endpoint C information register 0x0000_0000 EPC_CTL 0xFFF0_6084 R/W USB endpoint C control register 0x0000_0000 EPC_IE 0xFFF0_6 088 R/W USB endpoint C Interrupt Enable register 0x0000_0000 EPC_IC 0xFFF0_608C W USB endpoint C interrupt clear register 0x0000_0000 EPC_IS 0xFFF0_6090 R USB endpoint C interrupt status register 0x0000_0000 EPC_ADDR 0xFFF0_6094 R/W USB endpoint C address register 0x0000_0000 EPC_LENTH 0xFFF0_6098 R/W USB endpoint C transfer length register 0x0000_0000 EPA_XFER 0xFFF0_609C R/W USB endpoint A remain transfer length register 0x0000_0000 EPA_PKT 0xFFF0_60A0 R/W USB endpoint A remain packet length register 0x0000_0000 EPB_XFER 0xFFF0_60A4 R/W USB endpoint B remain transfer length register 0x0000_0000 EPB_PKT 0xFFF0_60A8 R/W USB endpoint B remain packet length register 0x0000_0000 EPC_XFER 0xFFF0_60AC R/W USB endpoint C remain transfer length register 0x0000_0000 EPC_PKT 0xFFF0_60B0 R/W USB endpoint C remain packet length register 0x0000_0000 SD Control Register Map REGISTER OFFSET R/W 0xFFF0_7000 R/W SD Global Control Register 0x0000_0000 SDDSA 0xFFF0_7004 R/W SD DMA Transfer Starting Address Register 0x0000_0000 SDBCR 0xFFF0_7008 R/W SD DMA Byte Count Register 0x0000_0000 SDGIER 0xFFF0_700C R/W SD Global Interrupt Enable Register 0x0000_0000 SDGISR 0xFFF0_7010 R/W SD Global Interrupt Status Register 0x0000_0000 SDBIST 0xFFF0_7014 R/W SD BIST Register 0x0000_0000 SDCR 0xFFF0_7300 R/W SD Control Register 0x0000_0000 SDHINI 0xFFF0_7304 R/W SD Host Initial Register 0x0000_0018 SDIER 0xFFF0_7308 R/W SD Interrupt Enable Register 0x0000_0000 SDISR 0xFFF0_730C R/W SD Interrupt Status Register 0x0000_00XX SDAUG 0xFFF0_7310 R/W SD Command Argument Register 0x0000_0000 SDRSP0 0xFFF0_7314 R SD Receive Response Token Register 0 0xXXXX_XXXX SDRSP1 0xFFF0_7318 R SD Receive Response Token Register 1 0x0000_XXXX SDBLEN 0xFFF0_731C R/W SD Block Length Register 0x0000_0000

Publication Release Date: September 19, 2006 - 541 - Revision B2 SD Control Register Map, continued REGISTER OFFSET R/W FB0_0 ….. FB0_127 0xFFF0_7400 ….. 0xFFF0_75FC R/W Flash Buffer 0 Undefined FB1_0 ….. FB1_127 0xFFF0_7800 ... 0xFFF0_79FC R/W Flash Buffer 1 Undefined LCDC Control Register Map REGISTER ADDRESS R/W 0XFFF0_8000 R/W LCD Control 0x0000_0000 LCD Interrupt Control LCDINTENB 0xFFF0_8004 R/W LCD Interrupt Enable 0x0000_0000 LCDINTS 0xFFF0_8008 R LCD Interrupt Status 0x0000_0000 LCDINTC 0xFFF0_800C W LCD Interrupt Clear 0x0000_0000 LCD Pre-processing OSDUPSCF 0xFFF0_8010 R/W OSD Horizontal/Vertical up-scaling factor 0x0000_0000 VDUPSCF 0xFFF0_8014 R/W Video Horizontal/Vertical up-scaling factor 0x0000_0000 OSDDNSCF 0xFFF0_8018 R/W OSD Horizontal/Vertical down-scaling factor 0x0000_0000 VDDNSCF 0xFFF0_801C R/W Video Horizontal/Vertical down-scaling factor 0x0000_0000 LCD FIFO Control FIFOCON 0xFFF0_8020 R/W FIFOs control 0x0000_0000 FIFOSTATUS 0xFFF0_8024 R FIFOs status 0x0000_0000 FIFO1PRM 0xFFF0_8028 R/W FIFO1 parameters 0x0000_0000 FIFO2PRM 0xFFF0_802C R/W FIFO2 parameters 0x0000_0000 FIFO1SADDR 0xFFF0_8030 R/W FIFO1 start address 0x0000_0000 FIFO2SADDR 0xFFF0_8034 R/W FIFO2 start address 0x0000_0000 FIFO1DREQCNT 0xFFF0_8038 R/W FIFO1 data request count 0x0000_0000 FIFO2DREQCNT 0xFFF0_803C R/W FIFO2 data request count 0x0000_0000 FIFO1CURADR 0xFFF0_8040 R FIFO1 current access address 0x0000_0000 FIFO2CURADR 0xFFF0_8044 R FIFO2 current access address 0x0000_0000 FIFO1RELACOLCNT 0xFFF0_8048 R/W FIFO1 real column count 0x0000_0000 FIFO2RELACOLCNT 0xFFF0_804C R/W FIFO2 real column count 0x0000_0000

542 - LCDC Control Register Map, continued. REGISTER ADDRESS R/W

0xFFF0_8050 R/W Video lookup table entry index 1 0x0000_0000 VDLUTENTRY2 0xFFF0_8054 R/W Video lookup table entry index 2 0x0000_0000 VDLUTENTRY3 0xFFF0_8058 R/W Video lookup table entry index 3 0x0000_0000 VDLUTENTRY4 0xFFF0_805C R/W Video lookup table entry index 4 0x0000_0000 OSDLUTENTRY1 0xFFF0_8060 R/W OSD lookup table entry index 1 0x0000_0000 OSDLUTENTRY2 0xFFF0_8064 R/W OSD lookup table entry index 2 0x0000_0000 OSDLUTENTRY3 0xFFF0_8068 R/W OSD lookup table entry index 3 0x0000_0000 OSDLUTENTRY4 0xFFF0_806C R/W OSD lookup table entry index 4 0x0000_0000 DITHP1 0xFFF0_8070 R/W Gray level dithered data duty pattern 1 0x0101_0001 DITHP2 0xFFF0_8074 R/W Gray level dithered data duty pattern 2 0x1111_0841 DITHP3 0xFFF0_8078 R/W Gray level dithered data duty pattern 3 0x4949_2491 DITHP4 0xFFF0_807C R/W Gray level dithered data duty pattern 4 0x5555_52A5 DITHP5 0xFFF0_8080 R/W Gray level dithered data duty pattern 5 0xB6B6_B556 DITHP6 0xFFF0_8084 R/W Gray level dithered data duty pattern 6 0xEEEE_DB6E DITHP7 0xFFF0_8088 R/W Gray level dithered data duty pattern 7 0xEFEF_EFBE LCD Post-processing DDISPCP 0xFFF0_8090 R/W Dummy Display Color Pattern 0x0000_0000 VWINS 0xFFF0_8094 R/W Video Window Starting Coordinate 0x0000_0000 VWINE 0xFFF0_8098 R/W Video Window Ending Coordinate 0x0000_0000 OSDWINS 0xFFF0_809C R/W OSD Window Starting Coordinate 0x0000_0000 OSDWINE 0xFFF0_80A0 R/W OSD Window Ending Coordinate 0x0000_0000 OSDOVCN 0xFFF0_80A4 R/W OSD Overlay Control 0x0000_0000 OSDCKP 0xFFF0_80A8 R/W OSD Overlay Color-Key Pattern 0x0000_0000 OSDCKM 0xFFF0_80AC R/W OSD Overlay Color-Key Mask 0x0000_0000 LCD Timing Generation LCDTCON1 0xFFF0_80B0 R/W LCD Timing Control 1 0x0000_0000 LCDTCON2 0xFFF0_80B4 R/W LCD Timing Control 2 0x0000_0000 LCDTCON3 0xFFF0_80B8 R/W LCD Timing Control 3 0x0000_0000 LCDTCON4 0xFFF0_80BC R/W LCD Timing Control 4 0x0000_0000 LCDTCON5 0xFFF0_80C0 R/W LCD Timing Control 5 0x0000_0000 LCDTCON6 0xFFF0_80C4 R LCD Timing Control 6 0x0000_0000 Lookup Table SRAM Build In Self Test BIST 0xFFF0_80D0 R/W 0x0000_0000

Publication Release Date: September 19, 2006 - 543 - Revision B2 LCDC Control Register Map, continued. REGISTER ADDRESS R/W 0xFFF0_0100 0xFFF0_84FF R/W Look-Up Table RAM 0xXXXX_XXXX Audio Control Register Map REGISTER ADDRESS R/W ACTL_CON 0xFFF0_9000 R/W Audio controller control register 0x0000_0000 ACTL_RESET 0xFFF0_9004 R/W Sub block reset control register 0x0000_0000 ACTL_RDSTB 0xFFF0_9008 R/W DMA destination base address register for record 0x0000_0000 ACTL_RDST_LENGTH 0xFFF0_900C R/W DMA destination length register for record 0x0000_0000 ACTL_RDSTC 0xFFF0_9010 R DMA destination current address register for record 0x0000_0000 ACTL_RSR 0xFFF0_9014 R/W Record status register 0x0000_0000 ACTL_PDSTB 0xFFF0_9018 R/W DMA destination base address register for play 0x0000_0000 ACTL_PDST_LENGTH 0xFFF0_901C R/W DMA destination length register for play 0x0000_0000 ACTL_PDSTC 0xFFF0_9020 R DMA destination current address register for play 0x0000_0000 ACTL_PSR 0xFFF0_9024 R/W Play status register 0x0000_0004 ACTL_IISCON 0xFFF0_9028 R/W IIS control register 0x0000_0000 ACTL_ACCON 0xFFF0_902C R/W AC-link control register 0x0000_0000 ACTL_ACOS0 0xFFF0_9030 R/W AC-link out slot 0 0x0000_0000 ACTL_ACOS1 0xFFF0_9034 R/W AC-link out slot 1 0x0000_0080 ACTL_ACOS2 0xFFF0_9038 R/W AC-link out slot 2 0x0000_0000 ACTL_ACIS0 0xFFF0_903C R AC-link in slot 0 0x0000_0000 ACTL_ACIS1 0xFFF0_9040 R AC-link in slot 1 0x0000_0000 ACTL_ACIS2 0xFFF0_9044 R AC-link in slot 2 0x0000_0000 Cache Controller Test Registers Map REGISTER ADDRESS R/W 0xFFF6_0000 R/W Cache test register 0 0x0000_0000 CTEST1 0xFFF6_0004 R Cache test register 1 0x0000_0000

544 - UART0 Control Registers Map REGISTER ADDRESS R/W

UART0_RBR 0xFFF8_0000 R Receive Buffer Register (DLAB = 0) Undefined UART0_THR 0xFFF8_0000 W Transmit Holding Register (DLAB = 0) Undefined UART0_IER 0xFFF8_0004 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART0_DLL 0xFFF8_0000 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 UART0_DLM 0xFFF8_0004 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 UART0_IIR 0xFFF8_0008 R Interrupt Identification Register 0x8181_8181 UART0_FCR 0xFFF8_0008 W FIFO Control Register Undefined UART0_LCR 0xFFF8_000C R/W Line Control Register 0x0000_0000 UART0_LSR 0xFFF8_0014 R Line Status Register 0x6060_6060 UART0_TOR 0xFFF8_001C R Time Out Register 0x0000_0000 High Speed UART1 Control Registers Map REGISTER ADDRESS R/W UART1_RBR 0xFFF8_0100 R Receive Buffer Register (DLAB = 0) Undefined UART1_THR 0xFFF8_0100 W Transmit Holding Register (DLAB = 0) Undefined UART1_IER 0xFFF8_0104 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART1_DLL 0xFFF8_0100 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 UART1_DLM 0xFFF8_0104 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 UART1_IIR 0xFFF8_0108 R Interrupt Identification Register 0x8181_8181 UART1_FCR 0xFFF8_0108 W FIFO Control Register Undefined UART1_LCR 0xFFF8_010C R/W Line Control Register 0x0000_0000 UART1_MCR 0xFFF8_0110 R/W Modem Control Register 0x0000_0000 UART1_LSR 0xFFF8_0114 R Line Status Register 0x6060.6060 UART1_MSR 0xFFF8_0118 R MODEM Status Register 0x0000_0000 UART1_TOR 0xFFF8_011C R Time Out Register 0x0000_0000 UART1_UBCR 0xFFF8_0120 R/W UART1 Bluetooth Control Register 0x0000_0000

Publication Release Date: September 19, 2006 - 545 - Revision B2 UART2 Control Register Map REGISTER ADDRESS R/W UART2_RBR 0xFFF8_0200 R Receive Buffer Register (DLAB = 0) Undefined UART2_THR 0xFFF8_0200 W Transmit Holding Register (DLAB = 0) Undefined UART2_IER 0xFFF8_0204 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART2_DLL 0xFFF8_0200 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 UART2_DLM 0xFFF8_0204 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 UART2_IIR 0xFFF8_0208 R Interrupt Identification Register 0x8181_8181 UART2_FCR 0xFFF8_0208 W FIFO Control Register Undefined UART2_LCR 0xFFF8_020C R/W Line Control Register 0x0000_0000 UART2_MCR 0xFFF8_0210 R/W Modem Control Register 0x0000_0000 UART2_LSR 0xFFF8_0214 R Line Status Register 0x6060_6060 UART2_MSR 0xFFF8_0218 R MODEM Status Register 0x0000_0000 UART2_TOR 0xFFF8_021C R Time Out Register 0x0000_0000 UART2_IRCR 0xFFF8_0220 R/W IrDA Control Register 0x0000_0040 UART3 Control Register Map REGISTER ADDRESS R/W UART3_RBR 0xFFF8_0300 R Receive Buffer Register (DLAB = 0) Undefined UART3_THR 0xFFF8_0300 W Transmit Holding Register (DLAB = 0) Undefined UART3_IER 0xFFF8_0304 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART3_DLL 0xFFF8_0300 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000_0000 UART3_DLM 0xFFF8_0304 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 UART3_IIR 0xFFF8_0308 R Interrupt Identification Register 0x8181_8181 UART3_FCR 0xFFF8_0308 W FIFO Control Register Undefined UART3_LCR 0xFFF8_030C R/W Line Control Register 0x0000_0000 UART3_MCR 0xFFF8_0310 R/W Modem Control Register 0x0000_0000 UART3_LSR 0xFFF8_0314 R Line Status Register 0x6060_6060 UART3_MSR 0xFFF8_0318 R MODEM Status Register 0x0000_0000 UART3_TOR 0xFFF8_031C R Time Out Register 0x0000_0000

546 - Timer Control Registers Map REGISTER ADDRESS R/W

0xFFF8_1000 R/W Timer Control Register 0 0x0000_0005 TCR1 0xFFF8_1004 R/W Timer Control Register 1 0x0000_0005 TICR0 0xFFF8_1008 R/W Timer Initial Control Register 0 0x0000_00FF TICR1 0xFFF8_100C R/W Timer Initial Control Register 1 0x0000_00FF TDR0 0xFFF8_1010 R Timer Data Register 0 0x0000_0000 TDR1 0xFFF8_1014 R Timer Data Register 1 0x0000_0000 TISR 0xFFF8_1018 R/C Timer Interrupt Status Register 0x0000_0000 WTCR 0xFFF8_101C R/W Watchdog Timer Control Register 0x0000_0000 AIC Control Registers Map REGISTER ADDRESS R/W AIC_SCR1 0xFFF8_2004 R/W Source Control Register 1 0x0000_0047 AIC_SCR2 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 AIC_SCR3 0xFFF8_200C R/W Source Control Register 3 0x0000_0047 AIC_SCR4 0xFFF8_2010 R/W Source Control Register 4 0x0000_0047 AIC_SCR5 0xFFF8_2014 R/W Source Control Register 5 0x0000_0047 AIC_SCR6 0xFFF8_2018 R/W Source Control Register 6 0x0000_0047 AIC_SCR7 0xFFF8_201C R/W Source Control Register 7 0x0000_0047 AIC_SCR8 0xFFF8_2020 R/W Source Control Register 8 0x0000_0047 AIC_SCR9 0xFFF8_2024 R/W Source Control Register 9 0x0000_0047 AIC_SCR10 0xFFF8_2028 R/W Source Control Register 10 0x0000_0047 AIC_SCR11 0xFFF8_202C R/W Source Control Register 11 0x0000_0047 AIC_SCR12 0xFFF8_2030 R/W Source Control Register 12 0x0000_0047 AIC_SCR13 0xFFF8_2034 R/W Source Control Register 13 0x0000_0047 AIC_SCR14 0xFFF8_2038 R/W Source Control Register 14 0x0000_0047 AIC_SCR15 0xFFF8_203C R/W Source Control Register 15 0x0000_0047 AIC_SCR16 0xFFF8_2040 R/W Source Control Register 16 0x0000_0000 AIC_SCR17 0xFFF8_2044 R/W Source Control Register 17 0x0000_0000 AIC_SCR18 0xFFF8_2048 R/W Source Control Register 18 0x0000_0000 AIC_SCR19 0xFFF8_204C R/W Source Control Register 19 0x0000_0047 AIC_SCR20 0xFFF8_2050 R/W Source Control Register 20 0x0000_0047

Publication Release Date: September 19, 2006 - 547 - Revision B2 AIC Control Registers Map, continued REGISTER ADDRESS R/W AIC_SCR21 0xFFF8_2054 R/W Source Control Register 21 0x0000_0047 AIC_SCR22 0xFFF8_2058 R/W Source Control Register 22 0x0000_0047 AIC_SCR23 0xFFF8_205C R/W Source Control Register 23 0x0000_0047 AIC_SCR24 0xFFF8_2060 R/W Source Control Register 24 0x0000_0047 AIC_SCR25 0xFFF8_2064 R/W Source Control Register 25 0x0000_0047 AIC_SCR26 0xFFF8_2068 R/W Source Control Register 26 0x0000_0047 AIC_SCR27 0xFFF8_206C R/W Source Control Register 27 0x0000_0047 AIC_SCR28 0xFFF8_2070 R/W Source Control Register 28 0x0000_0047 AIC_SCR29 0xFFF8_2074 R/W Source Control Register 29 0x0000_0047 AIC_SCR30 0xFFF8_2078 R/W Source Control Register 30 0x0000_0047 AIC_SCR31 0xFFF8_207C R/W Source Control Register 31 0x0000_0047 AIC_IRSR 0xFFF8_2100 R Interrupt Raw Status Register 0x0000_0000 AIC_IASR 0xFFF8_2104 R Interrupt Active Status Register 0x0000_0000 AIC_ISR 0xFFF8_2108 R Interrupt Status Register 0x0000_0000 AIC_IPER 0xFFF8_210C R Interrupt Priority Encoding Register 0x0000_0000 AIC_ISNR 0xFFF8_2110 R Interrupt Source Number Register 0x0000_0000 AIC_IMR 0xFFF8_2114 R Interrupt Mask Register 0x0000_0000 AIC_OISR 0xFFF8_2118 R Output Interrupt Status Register 0x0000_0000 AIC_MECR 0xFFF8_2120 W Mask Enable Command Register Undefined AIC_MDCR 0xFFF8_2124 W Mask Disable Command Register Undefined AIC_SSCR 0xFFF8_2128 W Source Set Command Register Undefined AIC_SCCR 0xFFF8_212C W Source Clear Command Register Undefined AIC_EOSCR 0xFFF8_2130 W End of Service Command Register Undefined AIC_TEST 0xFFF8_2200 W ICE/Debug mode Register Undefined

548 - GPIO Control Register Map REGISTER ADDRESS R/W

GPIO_CFG0 0xFFF8_3000 R/W GPIO port0 configuration register 0x0000_0000 GPIO_DIR0 0xFFF8_3004 R/W GPIO port0 direction control register 0x0000_0000 GPIO_DATAOUT0 0xFFF8_3008 R/W GPIO port0 data output register 0x0000_0000 GPIO_DATAIN0 0xFFF8_300C R GPIO port0 data input register 0xXXXX_XXXX GPIO_CFG1 0xFFF8_3010 R/W GPIO port1 configuration register 0x0000_0000 GPIO_DIR1 0xFFF8_3014 R/W GPIO port1 direction control register 0x0000_0000 GPIO_DATAOUT1 0xFFF8_3018 R/W GPIO port1 data output register 0x0000_0000 GPIO_DATAIN1 0xFFF8_301C R GPIO port1 data input register 0xXXXX_XXXX GPIO_CFG2 0xFFF8_3020 R/W GPIO port2 configuration register 0x0000_0000 GPIO_DIR2 0xFFF8_3024 R/W GPIO port2 direction control register 0x0000_0000 GPIO_DATAOUT2 0xFFF8_3028 R/W GPIO port2 data output register 0x0000_0000 GPIO_DATAIN2 0xFFF8_302C R GPIO port2 data input register 0x0000_0000 GPIO_CFG3 0xFFF8_3030 R/W GPIO port3 configuration register 0x0000_5555 GPIO_DIR3 0xFFF8_3034 R/W GPIO port3 direction control register 0x0000_0000 GPIO_DATAOUT3 0xFFF8_3038 R/W GPIO port3 data output register 0x0000_0000 GPIO_DATAIN3 0xFFF8_303C R GPIO port3 data input register 0xXXXX_XXXX GPIO_CFG4 0xFFF8_3040 R/W GPIO port4 configuration register 0x0015_5555 GPIO_DIR4 0xFFF8_3044 R/W GPIO port4 direction control register 0x0000_0000 GPIO_DATAOUT4 0xFFF8_3048 R/W GPIO port4 data output register 0x0000_0000 GPIO_DATAIN4 0xFFF8_304C R GPIO port4 data input register 0xXXXX_XXXX GPIO_CFG5 0xFFF8_3050 R/W GPIO port5 configuration register 0x0000_0000 GPIO_DIR5 0xFFF8_3054 R/W GPIO port5 direction control register 0x0000_0000 GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO port5 data output register 0x0000_0000 GPIO_DATAIN5 0xFFF8_305C R GPIO port5 data input register 0xXXXX_XXXX GPIO_CFG6 0xFFF8_3060 R/W GPIO port6 configuration register 0x0000_0000 GPIO_DIR6 0xFFF8_3064 R/W GPIO port6 direction control register 0x0000_0000 GPIO_DATAOUT6 0xFFF8_3068 R/W GPIO port6 data output register 0x0000_0000 GPIO_DATAIN6 0xFFF8_306C R GPIO port6 data input register 0xXXXX_XXXX GPIO_DBNCECON 0xFFF8_3070 R/W GPIO input debounce control register 0x0000_0000 GPIO_XICFG 0xFFF8_3074 R/W Extend Interrupt Configure Register 0xXXXX_XXX0 GPIO_XISTATUS 0xFFF8_3078 R/W Extend Interrupt Status Register 0xXXXX_XXX0

Publication Release Date: September 19, 2006 - 549 - Revision B2 RTC Control Register Map REGISTER ADDRESS R/W RTC_INIR 0xFFF8_4000 R/W RTC Initiation Register RTC_AER 0xFFF8_4004 R/W RTC Access Enable Register 0x0000_0000 RTC_FCR 0xFFF8_4008 R/W RTC Frequency Compensation Register 0x0000_0700 RTC_TLR 0xFFF8_400C R/W Time Loading Register 0x0000_0000 RTC_CLR 0xFFF8_4010 R/W Calendar Loading Register 0x0005_0101 RTC_TSSR 0xFFF8_4014 R/W Time Scale Selection Register 0x0000_0001 RTC_DWR 0xFFF8_4018 R/W Day of the Week Register 0x0000_0006 RTC_TAR 0xFFF8_401C R/W Time Alarm Register 0x0000_0000 RTC_CAR 0xFFF8_4020 R/W Calendar Alarm Register 0x0000_0000 RTC_LIR 0xFFF8_4024 R Leap year Indicator Register 0x0000_0000 RTC_RIER 0xFFF8_4028 R/W RTC Interrupt Enable Register 0x0000_0000 RTC_RIIR 0xFFF8_402C R/C RTC Interrupt Indicator Register 0x0000_0000 RTC_TTR 0xFFF8_4030 R/W RTC Tick Time Register 0x0000_0000 Smart card Host Control Register Map REGISTER ADDRESS R/W Smartcard Host Interface 0 SCHI_RBR0 0xFFF8_5000(BDLAB=0) R Receiver Buffer Register Undefined SCHI_TBR0 0xFFF8_5000 (BDLAB=0) W Transmitter Buffer Register Undefined SCHI_IER0 0xFFF8_5004 (BDLAB=0) R/W Interrupt Enable Register 0x0000_0080 SCHI_ISR0 0xFFF8_5008 (BDLAB=0) R Interrupt Status Register 0x0000_00C1 SCHI_SCFR0 0xFFF8_5008 (BDLAB=0) W Smart card FIFO Control Register 0x0000_0000 SCHI_SCCR0 0xFFF8_500C R/W Smart card Control Register 0x0000_0010 SCHI_CBR0 0xFFF8_5010 R/W Clock Base Register 0x0000_000C SCHI_SCSR0 0xFFF8_5014 R Smart Card Status Register 0x0000_0060 SCHI_GTR0 0xFFF8_5018 R/W Guard Rime Register 0x0000_0001 SCHI_ECR0 0xFFF8_501C R/W Extended Control Register 0x0000_0052 SCHI_TMR0 0xFFF8_5020 R/W Test Mode Register 0x0000_0000 SCHI_TOC0 0xFFF8_5028 R/W Time out Configuration Register 0x0000_0000 SCHI_TOIR0_0 0xFFF8_502C R/W Time out Initial Register 0 0x0000_0000 SCHI_TOIR1_0 0xFFF8_5030 R/W Time out Initial Register 1 0x0000_0000 SCHI_TOIR2_0 0xFFF8_5034 R/W Time out Initial Register 2 0x0000_0000

550 - Smart card Host Control Register Map, continued. REGISTER ADDRESS R/W

Smartcard Host Interface 0 SCHI_TOD0_0 0xFFF8_5038 R Time out Data Register 0 0x0000_00FF SCHI_TOD1_0 0xFFF8_503C R Time out Data Register 1 0x0000_00FF SCHI_TOD2_0 0xFFF8_5040 R Time out Data Register 2 0x0000_00FF SCHI_BTOR_0 0xFFF8_5044 R/W Buffer Time out Data Register 0x0000_0000 SCHI_BLL_0 0xFFF8_5000 (BDLAB=1) R/W Baud Rate Divisor Latch Lower Byte Register 0x0000_001F SCHI_BLH_0 0xFFF8_5004 (BDLAB=1) R/W Baud Rate Divisor Latch Higher Byte Register 0x0000_0000 SCHI_ID_0 0xFFF8_5008 (BDLAB=1) R Smart Card ID Number Register 0x0000_0070 Smartcard Host Interface 1 SCHI_RBR1 0xFFF8_5800 (BDLAB=0) R Receiver Buffer Register Undefined SCHI_TBR1 0xFFF8_5800 (BDLAB=0) W Transmitter Buffer Register Undefined SCHI_IER1 0xFFF8_5804 (BDLAB=0) R/W Interrupt Enable Register 0x0000_0080 SCHI_ISR1 0xFFF8_5808 (BDLAB=0) R Interrupt Status Register 0x0000_00C1 SCHI_SCFR1 0xFFF8_5808 (BDLAB=0) W Smart card FIFO Control Register 0x0000_0000 SCHI_SCCR1 0xFFF8_580C R/W Smart card Control Register 0x0000_0010 SCHI_CBR1 0xFFF8_5810 R/W Clock Base Register 0x0000_000C SCHI_SCSR1 0xFFF8_5814 R Smart Card Status Register 0x0000_0060 SCHI_GTR1 0xFFF8_5818 R/W Guard Rime Register 0x0000_0001 SCHI_ECR1 0xFFF8_581C R/W Extended Control Register 0x0000_0052 SCHI_TMR1 0xFFF8_5820 R/W Test Mode Register 0x0000_0000 SCHI_TOC1 0xFFF8_5828 R/W Time out Configuration Register 0x0000_0000 SCHI_TOIR0_1 0xFFF8_582C R/W Time out Initial Register 0 0x0000_0000 SCHI_TOIR1_1 0xFFF8_5830 R/W Time out Initial Register 1 0x0000_0000 SCHI_TOIR2_1 0xFFF8_5834 R/W Time out Initial Register 2 0x0000_0000 SCHI_TOD0_1 0xFFF8_5838 R Time out Data Register 0 0x0000_00FF SCHI_TOD1_1 0xFFF8_583C R Time out Data Register 1 0x0000_00FF SCHI_TOD2_1 0xFFF8_5840 R Time out Data Register 2 0x0000_00FF SCHI_BTOR1 0xFFF8_5844 R/W Buffer Time out Data Register 0x0000_0000 SCHI_BLL1 0xFFF8_5800 (BDLAB=1) R/W Baud Rate Divisor Latch Lower Byte Register 0x0000_001F SCHI_BLH1 0xFFF8_5804 (BDLAB=1) R/W Baud Rate Divisor Latch Higher Byte Register 0x0000_0000 SCHI_ID1 0xFFF8_5808 (BDLAB=1) R Smart Card ID Number Register 0x0000_0070

Publication Release Date: September 19, 2006 - 551 - Revision B2 I2C Register Map REGISTER ADDRESS R/W I2C_CSR0 0xFFF8_6000 R/W I2C0 Control and Status Register 0x0000_0000 I2C_DIVIDER0 0xFFF8_6004 R/W I2C0 Clock Prescale Register 0x0000_0000 I2C_CMDR0 0xFFF8_6008 R/W I2C0 Command Register 0x0000_0000 I2C_SWR0 0xFFF8_600C R/W I2C0 Software Mode Control Register 0x0000_003F I2C_RxR0 0xFFF8_6010 R I2C0 Data Receive Register 0x0000_0000 I2C_TxR0 0xFFF8_6014 R/W I2C0 Data Transmit Register 0x0000_0000 I2C Interface 1 I2C_CSR1 0xFFF8_6000 R/W I2C1 Control and Status Register 0x0000_0000 I2C_DIVIDER1 0xFFF8_6004 R/W I2C1 Clock Prescale Register 0x0000_0000 I2C_CMDR1 0xFFF8_6008 R/W I2C1 Command Register 0x0000_0000 I2C_SWR1 0xFFF8_600C R/W I2C1 Software Mode Control Register 0x0000_003F I2C_RxR1 0xFFF8_6010 R I2C1 Data Receive Register 0x0000_0000 I2C_TxR1 0xFFF8_6014 R/W I2C1 Data Transmit Register 0x0000_0000 USI Register Map REGISTER ADDRESS R/W USI_CNTRL 0xFFF8_6200 R/W Control and Status Register 0x0000_0004 USI_DIVIDER 0xFFF8_6204 R/W Clock Divider Register 0x0000_0000 USI_SSR 0xFFF8_6208 R/W Slave Select Register 0x0000_0000 Reserved 0xFFF8_620C N/A Reserved N/A USI_Rx0 0xFFF8_6210 R Data Receive Register 0 0x0000_0000 USI_Rx1 0xFFF8_6214 R Data Receive Register 1 0x0000_0000 USI_Rx2 0xFFF8_6218 R Data Receive Register 2 0x0000_0000 USI_Rx3 0xFFF8_621C R Data Receive Register 3 0x0000_0000 USI_Tx0 0xFFF8_6210 W Data Transmit Register 0 0x0000_0000 USI_Tx1 0xFFF8_6214 W Data Transmit Register 1 0x0000_0000 USI_Tx2 0xFFF8_6218 W Data Transmit Register 2 0x0000_0000 USI_Tx3 0xFFF8_621C W Data Transmit Register 3 0x0000_0000

552 - PWM Control Registers Map REGISTER ADDRESS R/W

PWM_PPR 0xFFF8_7000 R/W PWM Prescaler Register 0x0000_0000 PWM_CSR 0xFFF8_7004 R/W PWM Clock Select Register 0x0000_0000 PWM_PCR 0xFFF8_7008 R/W PWM Control Register 0x0000_0000 PWM_CNR0 0xFFF8_700C R/W PWM Counter Register 0 0x0000_0000 PWM_CMR0 0xFFF8_7010 R/W PWM Comparator Register 0 0x0000_0000 PWM_PDR0 0xFFF8_7014 R PWM Data Register 0 0x0000_0000 PWM_CNR1 0xFFF8_7018 R/W PWM Counter Register 1 0x0000_0000 PWM_CMR1 0xFFF8_701C R/W PWM Comparator Register 1 0x0000_0000 PWM_PDR1 0xFFF8_7020 R PWM Data Register 1 0x0000_0000 PWM_CNR2 0xFFF8_7024 R/W PWM Counter Register 2 0x0000_0000 PWM_CMR2 0xFFF8_7028 R/W PWM Comparator 2 0x0000_0000 PWM_PDR2 0xFFF8_702C R PWM Data Register 2 0x0000_0000 PWM_CNR3 0xFFF8_7030 R/W PWM Counter Register 3 0x0000_0000 PWM_CMR3 0xFFF8_7034 R/W PWM Comparator Register 3 0x0000_0000 PWM_PDR3 0xFFF8_7038 R PWM Data Register 3 0x0000_0000 PWM_PIER 0xFFF8_703C R/W PWM Interrupt Enable Register 0x0000_0000 PWM_PIIR 0xFFF8_7040 R/C PWM Interrupt Indication Register 0x0000_0000 KPI Control Register Map REGISTER ADDRESS R/W 0xFFF8_8000 R/W Keypad controller configuration Register 0x0000_0000 KPI3KCONF 0xFFF8_8004 R/W Keypad controller 3-keys configuration register 0x0000_0000 KPILPCONF 0xFFF8_8008 R/W Keypad controller low power configuration register 0x0000_0000 KPISTATUS 0xFFF8_800C R/O Keypad controller status register 0x0000_0000 PS2 Control Register Map REGISTER ADDRESS R/W/C 0xFFF8_9000 R/W PS2 Host Controller Command Register 0x0000_0000 PS2STS 0xFFF8_9004 R/W PS2 Host Controller Status Register 0x0000_0000 PS2SCANCODE 0xFFF8_9008 RO PS2 Host Controller RX Scan Code Register 0x0000_0000 PS2ASCII 0xFFF8_900C RO PS2 Host Controller RX ASCII Code Register 0x0000_0000

Publication Release Date: September 19, 2006 - 553 - Revision B2 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Taipei Office TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (H.K.) Ltd. No. 378 Kwun Tong Rd., Kowloon, Hong Kong FAX: 852-27552064 Unit 9-15, 22F, Millennium City, TEL: 852-27513100 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998 27F, 2299 Yan An W. Rd. Shanghai, TEL: 86-21-62365999 Winbond Electronics Corporation Japan Shinyokohama Kohoku-ku, Yokohama, 222-0033 FAX: 81-45-4781800 7F Daini-ueno BLDG, 3-7-18 TEL: 81-45-4781881 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C.

Product Information

W90P710CD specifications and overview.

Summary

32-BIT ARM7TDMI-BASED MCU

Description

32-BIT ARM7TDMI-BASED MCU

Source title W90P710CD Datasheet(PDF) - Winbond

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