W320-04XT

W320-04 SPECTRALINEAR | Alldatasheet

Document overview

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• PDF pages: 16

Technical content

Features

• Compliant with Intel® CK-Titan clock synthesizer/driver specifications  Multiple output clocks at different frequencies — Three pairs of differential CPU outputs, up to

200 MHz

— Ten synchronous PCI cl ocks, three free-running — Six 3V66 clocks — Two 48 MHz clocks — One reference clock at 14.318 MHz — One VCH clock  Spread Spectrum clocking (down spread)  Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#)  Three Select inputs (Mode select and IC Frequency Select)  OE and Test Mode support  56-pin SSOP package and 56-pin TSSOP package Benefits  Supports next-generation Pentium® processors using differential clock drivers  Motherboard clock generator — Supports multiple CPUs and a chipset — Support for PCI slots and chipset — Supports AGP, DRCG reference, and Hub Link — Supports USB host contro ller and graphic controller — Supports ISA slots and I/O chip  Enables reduction of electromagnetic interference (EMI) and overall system cost  Enables ACPI-compliant designs  Supports up to four CPU clock frequencies  Enables ATE and “bed of nails” testing  Widely available standard package enables lower cost Logic Block Diagram SSOP and TSSOP Top View VDD_REF XTAL_IN XTAL_OUT GND_REF PCI0 PCI5 66BUFF2/3V66_4 GND_3V66 PCI_STOP# GND_CPU CPU_STOP# PCI_F2 GND_PCI GND_3V66 VDD_CORE VDD_ 48 MHz MULT0# VDD_CPU REF PCI_F0 PCI_F1 VDD_PCI GND_PCI PCI1 PCI2 PCI3 VDD_PCI PCI4 PCI6 VDD_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66IN/3V66_5 PWR_DWN# 3V66_0 VDD_3V66 3V66_1/VCH GND_ 48 MHz DOT USB GND_IREF IREF CPU#2 CPU2 VDD_CPU CPU#1 CPU1 CPU#0 CPU0 GND_CORE PWR_GD# SCLK SDATA W320-04 VDD_REF CPU0:2 CPU#0:2 PCI_F0:2 XTAL PLL Ref Freq X1 REF VDD_PCI USB (48MHz) VCH_CLK/ 3V66_1 OSC VDD_CPU CPU_STOP# SCLK PCI0:6 PCI_STOP# Stop Clock Control Stop Clock Control PLL 1 SMBus Logic DOT (48MHz) PWR_DWN# S0:2 VDD_48MHz SDATA VDD_3V66 3V66_0 3V66_2:4/ Divider Network 3V66_5/ 66IN PWR PWR PWR PWR PWRPLL 2 PWR 66BUFF0:2 Gate PWR_GD# Pin Configurations

Rev 1.0,November 25, 2006 Page 2 of 16 Pin Summary Name Pins Description REF 56 3.3V 14.318-MHz clock output. XTAL_IN 2 14.318-MHz crystal input. XTAL_OUT 3 14.318-MHz crystal input. CPU, CPU# [0:2] 44, 45, 48, 49, 51, 52 Differential CPU clock outputs. 3V66_0 33 3.3V 66-MHz clock output. 3V66_1/VCH 35 3.3V selectable through SMBus to be 66 MHz or 48 MHz. 66IN/3V66_5 24 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO. 66BUFF [2:0] /3V66 [4:2] 21, 22, 23 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO. PCI_F [0:2] 5, 6, 7, 33-MHz clocks divided down from 66Input or divided down from 3V66. PCI [0:6] 10, 11, 12, 13, 16, 17, 18 PCI clock outputs divided down from 66Input or divided down from 3V66. USB 39 Fixed 48-MHz clock output. DOT 38 Fixed 48-MHz clock output. S2 40 Special 3.3V 3-level input for Mode selection. S1, S0 54, 55 3.3V LVTTL inputs for CPU frequency selection. IREF 42 A precision resistor is attached to this pin, which is connected to the internal current reference. MULT0 43 3.3V LVTTL input for selecting the current multiplier for the CPU outputs. PWR_DWN# 25 3.3V LVTTL input for Power_Down# (active LOW). PCI_STOP# 34 3.3V LVTTL input for PCI_STOP# (active LOW). CPU_STOP# 53 3.3V LVTTL input for CPU_STOP# (active LOW). PWRGD# 28 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SDATA 29 SMBus compatible SDATA. SCLK 30 SMBus compatible SCLK. VDD_REF, VDD_PCI, VDD_3V66, VDD_CPU 1, 8, 14, 19, 32, 46, 50 3.3V power supply for outputs. VDD_48 MHz 37 3.3V power supply for 48 MHz. VDD_CORE 26 3.3V power supply for PLL. GND_REF, GND_PCI, GND_3V66, GND_IREF, VDD_CPU 4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs. GND_CORE 27 Ground for PLL.

Rev 1.0,November 25, 2006 Page 3 of 16 Function Table[1] S2 S1 S0 CPU (MHz) 3V66[0:1] (MHz) 66BUFF[0:2]/ 3V66[2:4] (MHz) 66IN/3V66_5 (MHz) PCI_F/PCI (MHz) REF0(MHz) USB/DOT (MHz) Notes 1 0 0 66 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 1 0 1 100 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 1 1 0 200 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 1 1 1 133 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 0 0 0 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 0 1 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 1 0 200 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 0 1 1 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 Mid 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1, 5 Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 5, 6, 7 Mid 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved – Mid 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved – Swing Select Functions Mult0 Board Target Trace/Term Z Reference R, IREF = VDD/(3*Rr) Output Current V OH @ Z 05 0 : Rr = 221 1%, IREF = 5.00 mA I OH = 4*IREF 1.0V @ 50 15 0 : Rr = 475 1%, IREF = 2.32 mA I OH = 6*IREF 0.7V @ 50 Clock Driver Impedances Impedance Buffer Name V DD Range Buffer Type Min. : Typ. : Max. : CPU, CPU# Type X1 50 REF 3.135–3.465 Type 5 12 30 55 PCI, 3V66, 66BUFF 3.135–3.465 Type 5 12 30 55 USB 3.135–3.465 Type 3A 12 30 60 DOT 3.135–3.465 Type 3B 12 30 60 Clock Enable Configuration PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC

0 X X IREF*2 FLOAT LOW LOW LOW LOW LOW OFF

1 0 0 ON FLOAT ON ON ON OFF ON ON 1 0 1 ON LOW ON ON ON ON ON ON 1 1 0 ON ON ON ON ON OFF ON ON

111 O N O N O N O N O N O N O N O N

Note: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. “Normal” mode of operation 4. Frequency accuracy of 48 MHz must be +167PPM to match USB default. 6. Required for DC output impedance verification. 7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock margining.

Rev 1.0,November 25, 2006 Page 5 of 16 Data Byte 1 Bit Pin# Name Description Type Power On Default Bit 7 – N/A CPU Mult0 Value R N/A Bit 6 52, 49, 45 CPU0:2 Three-State CPU0:2 during power down 0 = Normal; 1 = Three-stated R/W 0 Bit 5 44, 45 CPU2 CPU2# Allow Control of CPU2 with assertion of CPU_STOP# 0 = Not free running; 1 = Free running R/W 0 Bit 4 48, 49 CPU1 CPU1# Allow Control of CPU1 with assertion of CPU_STOP# 0 = Not free running;1 = Free running R/W 0 Bit 3 51, 52 CPU0 CPU0# Allow Control of CPU0 with assertion of CPU_STOP# 0= Not free running; 1 = Free running R/W 0 Bit 2 44, 45 CPU2 CPU2# CPU2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 48, 49 CPU1 CPU1# CPU1Output Enable 1 = Enabled; 0= Disabled R/W 1 Bit 0 51, 52 CPU0 CPU0# CPU0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 2 Bit Pin# Name Pin Description Type Power On Default Bit 7 – N/A N/A R 0 Bit 6 18 PCI6 PCI6 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 5 17 PCI5 PCI5 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 16 PCI4 PCI4 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 13 PCI3 PCI3 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 2 12 PCI2 PCI2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 11 PCI1 PCI1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 10 PCI0 PCI0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 3 Bit Pin# Name Pin Description Type Power On Default Bit 7 38 DOT DOT 48-MHz Output Enable R/W 1 Bit 6 39 USB USB 48-MHz Output Enable R/W 1 Bit 5 7 PCI_F2 Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 4 6 PCI_F1 Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 3 5 PCI_F0 Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 2 7 PCI_F2 PCI_F2 Output Enable R/W 1 Bit 1 6 PCI_F1 PCI_F1Output Enable R/W 1 Bit 0 5 PCI_F0 PCI_F0 Output Enable R/W 1

Rev 1.0,November 25, 2006 Page 6 of 16 Data Byte 4 Bit Pin# Name Pin Description Type Power On Default Bit 7 – TBD N/A R 0 Bit 6 – TBD N/A R 0 Bit 5 33 3V66_0 3V66_0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 35 3V66_1/VCH 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 24 66IN/3V66_5 3V66_5 Output Enable 1 = Enable; 0 = Disable NOTE: This bit should be used when pin 24 is configured as 3v66_5 output. Do not clear this bit when pin 24 is configured as 66in input. R/W 1 Bit 2 23 66BUFF2 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 22 66BUFF1 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 21 66BUFF0 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 5 Bit Pin# Name Pin Description Type Power On Default Bit 7 N/A N/A R 0 Bit 6 N/A N/A R 0 Bit 5 66BUFF [2:0] Tpd 66IN to 66BUFF propagation delay control R/W 0 Bit 4 66BUFF [2:0] R/W 0 Bit 3 DOT DOT edge rate control R/W 0 Bit 2 DOT R/W 0 Bit 1 USB USB edge rate control R/W 0 Bit 0 USB R/W 0 Byte 6: Vendor ID Bit Description Type Power On Default Bit 7 Revision Code Bit 3 R 0 Bit 6 Revision Code Bit 2 R 0 Bit 5 Revision Code Bit 1 R 0 Bit 4 Revision Code Bit 0 R 0 Bit 3 Vendor ID Bit 3 R 1 Bit 2 Vendor ID Bit 2 R 0 Bit 1 Vendor ID Bit 1 R 0 Bit 0 Vendor ID Bit 0 R 0

Rev 1.0,November 25, 2006 Page 7 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature (Non-Condensing) ....–65qC to +150qC Static Discharge Voltage Operating Conditions[8] Over which Electrical Parameters are Guaranteed Parameter Description Min. Max. Unit VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_CPU, 3.3V Supply Voltages 3.135 3.465 V VDD_48 MHz 48-MHz Supply Voltage 2.85 3.465 V TA Operating Temperature, Ambient 0 70 qC Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 pF f(REF) Reference Frequency, Oscillator Nominal Value 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage Except Crystal Pads. Threshold Voltage for Crystal Pads = V DD/2 2.0 V VIL Low-level Input Voltage Except Crystal Pads 0.8 V VOH High-level Output Voltage USB, REF, 3V66 I OH = –1 mA 2.4 V PCI I OH = –1 mA 2.4 V VOL Low-level Output Voltage USB, REF, 3V66 I OL = 1 mA 0.4 V PCI I OL = 1 mA 0.55 V IIH Input HIGH Current 0 < VIN < VDD –5 5 mA IIL Input LOW Current 0 < VIN < VDD –5 5 mA IOH High-level Output Current CPU For IOH =6*IRef Configuration Type X1, VOH = 0.65V 12.9 mA Type X1, VOH = 0.74V 14.9 REF, DOT, USB Type 3, V OH = 1.00V –29 Type 3, VOH = 3.135V –23 3V66, DOT, PCI, REF Type 5, V OH = 1.00V –33 Type 5, VOH = 3.135V –33 IOL Low-level Output Current REF, DOT, USB Type 3, V OL = 1.95V 29 mA Type 3, VOL = 0.4V 27 3V66, PCI, REF Type 5, V OL = 1.95 V 30 Type 5, VOL = 0.4V 38 IOZ Output Leakage Current Three-state 10 mA IDD3 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 360 mA IDDPD3 3.3V Shut-down Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA 25 mA IDDPD3 3.3V Shut-down Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA 45 mA Note: 8. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

Rev 1.0,November 25, 2006 Page 8 of 16 Switching Characteristics[9] Over the Operating Range Parameter Output Description Test Conditions Min. Max. Unit t1 All Output Duty Cycle[10] Measured at 1.5V 45 55 % t3 USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ns t3 PCI,3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t5 3V66[0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t5 66BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66, PCI 3V66-PCI Clock Jitter 3V66 leads. Measured at 1.5V 1.5 3.5 ns t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 USB, DOT Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps CPU 1.0V Switching Characteristics t2 CPU Rise Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t3 CPU Fall Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B 150 ps CPU Rise/Fall Matching Measured with test loads[11] 325 mV Voh CPU High-level Output Voltage including overshoot Measured with test loads[11] 0.92 1.45 V Vol CPU Low-level Output Voltage including undershoot Measured with test loads[11] –0.2 0.35 V Vcrossover CPU Crossover Voltage Measured with test loads[11] 0.51 0.76 V CPU 0.7V Switching Characteristics t2 CPU Rise Time Measured single ended waveform from 0.175V to 0.525V 175 700 ps t3 CPU Fall Time Measured single ended waveform from 0.175V to 0.525V 175 700 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 150 ps CPU Rise/Fall Matching Measured with test loads[12, 13] 20 % Voh CPU High-level Output Voltage Including Overshoot Measured with test loads[13] 0.85 V Vol CPU Low-level Output Voltage Including Undershoot Measured with test loads[13] –0.15 V Vcrossover CPU Crossover Voltage Measured with test loads[13] 0.28 0.43 V Notes: 9. All parameters specified with loaded outputs. 11. The 1.0V test load is shown on the test circuit page. 12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.

Rev 1.0,November 25, 2006 Page 9 of 16 Definition and Application of PWRGD# Signal CPU VRM8.5 3.3V PWRGD# NPN CLOCK GENERATOR 10K 10K 10K 10K GMCH 3.3V 3.3V PWRGD# BSEL0 BSEL1 Vtt

Rev 1.0,November 25, 2006 Page 10 of 16 Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time OUTPUT VDD CPU-CPU Clock Skew Host_b Host Host_b Host 3V66-3V66 Clock Skew 3V66 3V66 t PCI-PCI Clock Skew PCI PCI t

Rev 1.0,November 25, 2006 Page 11 of 16 Switching Waveforms (continued) 3V66 PCI 3V66-PCI Clock Skew t8A t8B CPU Clock Cycle-Cycle Jitter Host_b Host t9A t9B Cycle-Cycle Clock Jitter CLK PWRDWN# Assertion Power Down Rest of Generator UNDEF 66BUFF PCI_F (APIC) CPU CPU# 3V66 66IN USB REF PCI PWR_DWN# Note: PCI_STOP# asserted LOW

up. Will be gone in 0.2–0.3 mS delay. Figure 2. CPU Power Before Clock Power

Figure 3. CPU Power After Clock Power

Rev 1.0,November 25, 2006 Page 14 of 16 Layout Example G = VIA to GND plane layer. V = VIA to respective supply plane layer. Note: Each supply plane or strip should have a ferrite bead and capacitors. 3918 FB +3.3V Supply Ceramic Caps C1 = 10–22 µF 10 PF FB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S. 0.005PF G G VDDQ3 C5 = 0.1 PF C6 = 10 PF GV G V G V G V G V G V GV G G VDDQ3 C5 C6 W320-04 GV G G G G G G G G G G G G G G G G G G G G C2 = 0.005 PF

Rev 1.0,November 25, 2006 Page 15 of 16 Test Circuit Note: All capacitors must be placed as close to the pins as is physically possible. 4, 9, 15, 20, 27, 31, 36, 41 VDD_REF, VDD_PCI, OUTPUTS W320-04 Note: Each supply pin must have an individual decoupling capacitor. VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU Test Nodes Rs Rs Rp Rp CPURef,USB Outputs PCI,3V66 Outputs 30 pF 20 pF Test Node Test Node 8, 14, 19, 26, 32, 37, 46, 50 0.7V amplitude: RS = 33 ohm, RP = 50 ohm 0.7V Test Load 2 pF 2 pF

Ordering Information

Ordering Code Package Type Operating Range W320-04H 56-pin SSOP Commercial 0qC TO 70qC W320-04HT 56-pin SSOP - Tape and Reel Commercial 0qC TO 70qC W320-04X 56-pin TSSOP Commercial 0qC TO 70qC W320-04XT 56-pin TSSOP - Tape and Reel Commercial 0qC TO 70qC Lead-Free CYW320OXC-4 56-pin SSOP Commercial 0qC TO 70qC CYW320OXC-4T 56-pin SSOP - Tape and Reel Commercial 0qC TO 70qC CYW320ZXC-4 56-pin TSSOP Commercial 0qC TO 70qC CYW320ZXC-4T 56-pin TSSOP - Tape and Reel Commercial 0qC TO 70qC 4, 9, 15, 20, 27, 31, 36, 41 VDD_REF, VDD_PCI, OUTPUTS W320-04 VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU Test NodesCPURef,USB Outputs PCI,3V66 Outputs 30 pF 20 pF Test Node Test Node 8, 14, 19, 26, 32, 37, 46 ,50 1.0V Test Load 2 pF 2 pF 63.4 63.4 475 1.0V Amplitude

Rev 1.0, November 25, 2006 Page 16 of 16 W320-04 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Package Diagrams 0.095 0.025 0.008 SEATING PLANE 0.420 0.088 .020 0.292 0.299 0.395 0.092 BSC 0.110 0.016 0.720 0.008 0.0135 0.730 DIMENSIONS IN INCHES MIN. MAX. 0.040 0.024 0° -8° GAUGE PLANE .010 128 5629 0.110 0.005 0.010 56-Lead Shrunk Small Outline Package O56 SEATING PLANE BSC 0° -8° MAX. GAUGE PLANE 29 56 1.100[0.043] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] DIMENSIONS IN MM[INCHES] MIN. MAX. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56