SL2309

SL2309 SPECTRALINEAR | Alldatasheet

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Technical content

Rev 1.1, May 29, 2007 Page 1 of 12 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL2309 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features x 10 to 140 MHz operating frequency range x Low output clock skew: 50ps-typ x Low output clock jitter:  50 ps-typ cycle-to-cycle jitter x Low part-to-part output skew: 150 ps-typ x 3.3 V power supply range x Low power dissipation:  28 mA-max at 66 MHz  44 mA –max at 140 MHz x One input drives 9 outputs organized as 4+4+1 x Select mode to bypass PLL or tri-state outputs x SpreadThru™ PLL that allows use of SSCG x Standard and High-Drive options x Available in 16-pin SOIC and TSSOP packages x Available in Commercial and Industrial grades

Applications

x Routers, Switchers and Servers x Digital Embeded Systems

Description

The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri- stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V. Benefits x Up to nine (9) distribution of input clock x Standard and High-Dirive levels to control impedance level, frequency range and EMI x Low power dissipation, jitter and skew x Low cost Block Diagram Low Power and Low Jitter PLL MUX Input Selection Decoding Logic VDD GND CLKIN CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4

Rev 1.1, May 29, 2007 Page 2 of 12 SL2309 Pin Configuration 16-Pin SOIC and TSSOP Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (250k ȍ). 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250k ȍ). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250k ȍ). 4 VDD Power 3.3V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250k ȍ). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250k ȍ). 8 S2 Input Select Input, select pin S2. Weak pull-up (250k ȍ). 9 S1 Input Select Input, select pin S1. Weak pull-up (250k ȍ). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250k ȍ). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250k ȍ). 12 GND Power Power Ground. 13 VDD Power 3.3V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250k ȍ). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250k ȍ). 16 CLKOUT Output Buffered Clock Output, PLL In ternal Feedback Output. Weak pull-down (250kȍ).

for systems requiring clock distribution. Table 1. Input/Output Frequency Range product draws less than 12ȝA-max supply current. on drive levels and load specifications. the switching electrical tables for the details. and B clocks since CLKOUT is the feedback to the PLL. of skew, jitter and power dissipation. 1.8V power supply operations.

Figure 1. CLKIN Input to CLK A and B Delay Table 2. Select Input Decoding

Rev 1.1, May 29, 2007 Page 5 of 12 SL2309 Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 85 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C Soldering Temperature – 260 °C ESD Rating (Human Body Model) MIL-STD-883, Method 3015 2000 – V Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit VDD 3.3V Supply Voltage 3.3V+/-10% 3.0 3.6 V Commercial 0 85 °C TA Operating Temperature(Ambient) Industrial – 40 85 °C 10 to 140 MHz, -1H high drive All active PLL modes –1 5 p F CLOAD Load Capacitance 10 to 100 MHz, -1H high drive All active PLL modes –3 0 p F 10 to 100MHz, -1 standard drive All active PLL modes –1 5 p F 10 to 66MHz, -1 standard drive All active PLL modes –3 0 pF CIN Input Capacitance S1, S2 and CLKIN pins – 7 pF tpu Power-up Time Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). 0.05 100 ms CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz 3.3V, (typical), -1H high drive 22 ŸZOUT Output Impedance 3.3V, (typical), -1 standard drive 32 Ÿ

Rev 1.1, May 29, 2007 Page 6 of 12 SL2309 Symbol Description Condition Min Max Unit VDD Supply Voltage 3.0 3.6 V VIL Input LOW Voltage CLKIN, S2 and S1 Pins – 0.8 V VIH Input HIGH Voltage CLKIN, S2 and S1 pins 2.0 V DD+0.3 V IIL Input LOW Current CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V – 25 µA IIH Input HIGH Current CLKIN, S2 and S1 Pins, VIN = VDD – 50 µA IOL = 8 mA (standard drive) – 0.4 V VOL Output LOW Voltage (All outputs) IOL = 12 mA (high drive) – 0.4 V IOH = –8 mA (standard drive) 2.4 – V VOH Output HIGH Voltage (All outputs) IOH = –12 mA (high drive) 2.4 – V C-Grade – 12 µAIDDPD Power Down Supply Current CLKIN=0 to VDD or floating (input will be pulled-down by 250kŸ weak pull-down on-chip resistor) I-Grade – 25 µA IDD1 Power Supply Current All Outputs CL=0, 33MHz CLKIN S2=S1=1 (High) –2 0 m A IDD2 Power Supply Current All Outputs CL=0, 66MHz CLKIN S2=S1=1 (High) –2 8 m A IDD3 Power Supply Current All Outputs CL=0, 100MHz CLKIN S2=S1=1 (High) –3 6 m A IDD4 Power Supply Current All Outputs CL=0, 140MHz CLKIN S2=S1=1 (High) –4 4 m A RPU/D Pull-up and Pull-down Resistors Pins-1/2/3/6/7/8/9/10/11/14/15/16 250kŸ-typ 175 325 k Ÿ

Rev 1.1, May 29, 2007 Page 7 of 12 SL2309 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Typ Max Unit High drive (-1H). All outputs CL=15pF 10 – 140 MHz High drive (-1H), All outputs CL=30pF 10 – 100 MHz Standard drive, (-1), All outputs CL=15pf 10 – 100 MHz FMAX1 Maximum Frequency [1] (Input=Output ) All Active PLL Modes Standard drive, (-1), All outputs CL=30pf 10 – 66 MHz High drive (-1H). All outputs CL=15pF 0 – 140 Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. MHz High drive (-1H), All outputs CL=30pF 0 – 100 MHz Standard drive, (-1), All outputs CL=15pf 0 – 100 MHz FMAX2 Maximum Frequency [1] (Input=Output ) PLL Bypass Mode (S2=1 and S1=0) Standard drive, (-1), All outputs CL=30pf 0 – 66 MHz INDC Input Duty Cycle Measured at 1.4V, Fout=66MHz, CL=15pF 30 50 70 % OUTDC Output Duty Cycle [2] Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 % High drive (-1H), CL=15pF – – 1.5 ns High drive (-1H), CL=30pF – – 1.8 ns Standard drive (-1), CL=15pF – – 2.2 ns tr/f Rise, Fall Time (3.3V) [2] (Measured at: 0.8 to 2.0V) Standard drive (-1), CL=30pF – – 2.5 ns t1 Output-to-Output Skew [2] All outputs CL=0 or equally loaded, -1 or -1H drives – 50 120 ps(Measured at VDD/2) t2 Device-to-Device Skew [2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 150 400 ps PLL Bypass mode Only when S2=1 and S1=0 1.5 5 8.7 nst3 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge [2] (Measured at VDD/2) PLL enabled –150 – 150 psAll active PLL modes PLL Lock Time[2]tPLOCK Time from 90% of VDD to valid clocks on all the output clocks – – 1.0 ms Fin=Fout=66 MHz, <CL=15pF, -1H drive – 50 100 ps CCJ Cycle-to-cycle Jitter [2] Fin=Fout=66 MHz, <CL=15pF, -1 drive – 60 120 ps Fin=Fout=66 MHz, <CL=30pF, -1H drive – 65 130 ps Fin=Fout=66 MHz, <CL=30pF, -1 drive – 75 150 ps

Rev 1.1, May 29, 2007 Page 8 of 12 SL2309 External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1ȝF must be used between VDD and VSS pins. Place the capacitor s on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination resistors as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.

Rev 1.1, May 29, 2007 Page 10 of 12 SL2309 Package Drawing and Dimensions 16-Lead TSSOP (4.4mm) 0.190(0.007) 0.300(0.012) 0.090(0.003) 0.200(0.008) 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) 2.900(0.114) 3.100(0.122) 0.850(0.033) 0.950(0.037) 0.050(0.002) 0.150(0.006) 1.100(0.043) MAX 0.076(0.003) 0 to 8 ° 0.500(0.020) 0.700(0.027) 0.650(0.025) BSC Gauge Plane Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID Seating Plane 0.650(0.025) BSC Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit ș JA Still air - 80 - °C/W ș JA 1m/s air flow - 70 - °C/W Thermal Resistance Junction to Ambient ș JA 3m/s air flow - 68 - °C/W Thermal Resistance Junction to Case ș JC Independent of air flow - 36 - °C/W

Rev 1.1, May 29, 2007 Page 11 of 12 SL2309 Package Drawing and Dimensions (Cont.) 0.150(3.810) 0.157(3.987 0.230(5.842) 0.244(6.197) 0.189(4.800) 0.196(4.978) 0.050(1.270) BSC 0.004(0.102) Seating plane0.004(0.102) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0° to 8° 0.010(0.2540) 0.016(0.406) X 45° 0.016(0.406) 0.035(0.889) 0.0075(0.190) 0.0098(0.249) Pin-1 ID Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) 16-Lead SOIC (150 Mil) 916 0.0138(0.350) 0.0192(0.487) Thermal Characteristics Parameter Symbol Condition Min Typ Max Unit ș JA Still air - 120 - °C/W ș JA 1m/s air flow - 115 - °C/W Thermal Resistance Junction to Ambient ș JA 3m/s air flow - 105 - °C/W Thermal Resistance Junction to Case ș JC Independent of air flow - 60 - °C/W

Rev 1.1, May 29, 2007 Page 12 of 12 SL2309 Ordering Information[3] Ordering Number Marking Shipping Package Package Temperature SL2309ZC-1 SL2309ZC-1 Tube 16-pin TSSOP 0 to 70°C SL2309ZC-1T SL2309ZC-1 Tape and Reel 16-pin TSSOP 0 to 70°C SL2309ZC-1H SL2309ZC-1H Tube 16-pin TSSOP 0 to 70°C SL2309ZC-1HT SL2309ZC-1H Tape and Re el 16-pin TSSOP 0 to 70°C SL2309ZI-1 SL2309ZI-1 Tube 16-pin TSSOP -40 to 85°C SL2309ZI-1T SL2309ZI-1 Tape and Reel 16-pin TSSOP -40 to 85°C SL2309ZI-1H SL2309ZI-1H Tube 16-pin TSSOP -40 to 85°C SL2309ZI-1HT SL2309ZI-1H Tape and Reel 16-pin TSSOP -40 to 85°C SL2309SC-1 SL2309SC-1 Tube 16-pin SOIC 0 to 70°C SL2309SC-1T SL2309SC-1 Tape and Reel 16-pin SOIC 0 to 70°C SL2309SC-1H SL2309SC-1H Tube 16-pin SOIC 0 to 70°C SL2309SC-1HT SL2309SC-1H Tape and Reel 16-pin SOIC 0 to 70°C SL2309SI-1 SL2309SI-1 Tube 16-pin SOIC -40 to 85°C SL2309SI-1T SL2309SI-1 Tape and Reel 16-pin SOIC -40 to 85°C SL2309SI-1H SL2309SI-1H Tube 16-pin SOIC -40 to 85°C SL2309SI-1HT SL2309SI-1H Tape and Reel 16-pin SOIC -40 to 85°C Notes: 3. The SL2309 products are RoHS compliant. While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This produ ct is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. re serves the right to change any circuitry or specification without notice.