W40S11-02 SPECTRALINEAR | Alldatasheet
Document overview
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Technical content
Features
- Ten skew-controlled CMOS outputs (SDRAM0:9) Supports two SDRAM DIMMs Ideal for high-performance systems designed around Intel®’s latest mobile chip set SMBus serial configuration interface Skew between any two outputs is less than 250 ps 1 to 5 ns propagation delay DC to 133-MHz operation Single 3.3V supply voltage Low power CMOS design packaged in a 28-pin, 209-mil SSOP (Shrink Small Outline Package) Overview The Cypress W40S11-02 is a low-voltage, ten-output clock buffer. Output buffer impedance is approximately 15:, which is ideal for driving SDRAM DIMMs. Key Specifications DD + 0.5V
1.5 V/ns
Pin ConfigurationBlock Diagram Note: 1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE in- puts (should not be relied upon for pulling up to VDD). [1][1] SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM0 Serial PortSCLOCK SDATA Device Control BUF_IN OE VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN VDD SDRAM8 GND VDD SDATA VDD SDRAM7 SDRAM6 GND VDD SDRAM5 SDRAM4 GND OE VDD SDRAM9 GND GND SCLOCK [1]
Outputs three-stated when OE = 0, and toggle when OE = 1. each. Bytes are written in the order shown in Table 1. to within ±250 ps of each other. BUF_IN 9 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ). section of this data sheet. Internal 250-k: pull-up resistor. described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor. G Ground Connection: Connect all ground pins to the common system ground plane. OE 20 I Output Enable: Internal 250-k: pull-up resistor. Three-states outputs when LOW. Table 1. Byte Writing Sequence
1 Slave Address 11010010 Commands the W40S11-02 to accept the bits in Data Bytes 0–6 for
correct (or is for an alternate slave receiver).
2 Command
addressed slave receiver on the serial data bus.
3 Byte Count “Don’t Care” Unused by the W40S11-02, therefore bit values are ignored (“Don’t
addressed slave receiver on the serial data bus. functions, refer to Table 2, Data Byte Serial Configuration Map.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3 Don’t Care Refer to Cypress clock drivers.
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
Each bit in the data bytes control a particular device function. Bits are written most significant bit (MSB) first, which is bit 7.
- At power-up all SDRAM outputs are enabled and active. It is recommended to program Bits 4–7 of Byte0 and Bits 0–3 of Byte1 to a “0” to save power and reduce
Table 2. Data Bytes 0–2 Serial Configuration Map[2]
7 N/A Reserved (Reserved) -- --
6 N/A Reserved (Reserved) -- --
5 N/A Reserved (Reserved) -- --
4 N/A Reserved (Reserved) -- --
3 N/A Reserved (Reserved) -- --
2 N/A Reserved (Reserved) -- --
1 N/A Reserved (Reserved) -- --
0 N/A Reserved (Reserved) -- --
Rev 1.0,Dec. 01, 2006 Page 7 of 9 Parameter Description Test Condition/Comments Min Typ Max Unit IDD 3.3V Supply Current at 66 MHz 120 160 mA IDD 3.3V Supply Current at 100 MHz 185 220 mA IDD Tristate 3.3V Supply Current in Three-State 51 0 m A Logic Inputs VIL Input Low Voltage V SS – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.5 V IILEAK Input Leakage Current, BUF_IN –5 +5 µA IILEAK Input Leakage Current[3] –20 +5 µA Logic Outputs (SDRAM0:9)[4] VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 70 110 185 mA IOH Output High Current V OH = 1.5V 65 100 160 mA Pin Capacitance/Inductance CIN Input Pin Capacitance 5p F COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H Note: 3. OE, SDATA, and SCLOCK logic pins have a 250-k: internal pull-up resistor (VDD – 0.8V). 4. All SDRAM outputs loaded by 6" transmission lines with 22-pF capacitors on ends. Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency 0 133 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 4.0 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4.0 V/ns tSR Output Skew, Rising Edges 250 ps tSF Output Skew, Falling Edges 250 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 1.0 5.0 ns tPF Falling Edge Propagation Delay 1.0 5.0 ns tD Duty Cycle Measured at 1.5V 45 55 % Zo AC Output Impedance 15 :
Rev 1.0,Dec. 01, 2006 Page 8 of 9 Layout Example FB +3.3V Supply 10PF.005PF G G VDDQ3 W40S11-02 GV G = VIA to GND plane layer V = VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors Ceramic Caps C3 = 10–22 µF C4 = 0.005 µF FB = Dale ILB1206 - 300 (300:@ 100 MHz) All VDDs have –1 mF low ESR bypass at pin to ground GV GV G V G V G V G V All bypass caps = 0.1 PF ceramic
Rev 1.0, Dec. 01, 2006 Page 9 of 9 W40S11-02 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Ordering Information
Ordering Code Freq. Mask Code Package Name Package Type W40S11 -02 H X 28-pin SSOP (209-mil) 28-pin TSSOP (173-mil) Package Diagrams Freq. Mask Code Package Name Package Type W40S11 -02 H X 28-pin SSOP (209-mil) 28-pin TSSOP (173-mil) PIN 1 ID SEATING PLANE BSC. BSC 0° -8° PLANE GAUGE 9.60[0.378] 1.10[0.043] MAX. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 9.80[0.386] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.16 gms PART # Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG. 28-Lead Thin Shrunk Small Outline Package (4.40-mm Body)