W312-02HT

W312-02 SPECTRALINEAR | Alldatasheet

Document overview

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Technical content

Features

• Single chip FTG solution for VIA™ K7 Series chipsets  Programmable clock outpu t frequency with less than

1 MHz increment

 Integrated fail-safe Watc hdog timer for system recovery  Automatically switch to HW selected or SW programmed clock frequency when watchdog timer time-out  Capable of generate system RESET after a watchdog timer time-out occurs or a change in output frequency via SMBus interface  Support SMBus byte read/write and block read/ write operations to simplify system BIOS development  Vendor ID and Revision ID support  Programmable drive strength for PCI output clocks  Programmable output skew between CPU, AGP and PCI  Maximized EMI suppression using Cypress’s Spread Spectrum technology  Low jitter and tightly controlled clock skew  Two pairs of differential CPU clocks  Eleven copies of PCI clocks  Three copies of 66-MHz outputs  Two copies of 48-MHz outputs  Three copies of 14.31818-MHz reference clocks  One RESET output for system recovery  Power management control support Key Specifications 48-MHz, 3V66, PCI Outputs Block Diagram Pin Configuration Note: 1. Internal 100K pull-up resistors present on inputs marked with *. De- sign should not rely solely on internal pull-up resistor to set I/O pins HIGH. [1] VDD_REF VDD_CPU PCI1:8 XTAL PLL REF FREQ PLL 1 X1 REF2 24_48MHz/FS4* PLL2 OSC VDD_48MHz SMBusSDATA LogicSCLK AGP0:2 CPUT0,CPUC0 CPUT_CS,CPUC_CS Divider, Delay, and Phase Control Logic 3 VDD_PCI RST# PCI0/SEL24_48#* PCI9_E (FS0:4) 48MHz/FS3* VDD_REF GND_REF VDD_48MHz *FS2/48MHz *FS3/24_48MHz GND_48MHz *FS4/PCI_F *SEL24_48#/PCI0 PCI1 GND_PCI PCI2 PCI3 VDD_PCI PCI4 PCI5 PCI6 GND_PCI PCI7 PCI8 PCI9_E VDD_PCI RST# W312-02 REF0/FS0* REF1/FS1* REF2 REF_STOP#* AGP_STOP#* GND_CPU CPUT0 CPUC0 VDD_CPU CPUT_CS CPUC_CS GND_CPU CPU_STOP#* PCI_STOP#* PD#* VDD_CORE GND_CORE SDATA SCLK GND_AGP AGP2 AGP1 AGP0 VDD_AGP REF1/FS1* REF0/FS0* VDD_AGP SEL24_48#* PD# CPU_STOP# PCI_STOP# AGP_STOP# REF_STOP#

Rev 1.0,November 27, 2006 Page 2 of 19 I Pin Definitions Pin Name Pin No. Pin Type Pin Description REF0/FS0 48 I/O Reference Clock Output 0/Frequency Select 0: 3.3V 14.318-MHz clock output. REF0 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 5. REF1/FS1 47 I/O Reference Clock Output 0/Frequency Select 1: 3.3V 14.318-MHz clock output. REF1 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 5. REF2 46 I/O Reference Clock Output 2: 3.3V 14.318-MHz clock output. REF2 will be disabled when REF_STOP# is active. X1 3 I Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 4 I Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI_F/FS4 9 I Free-Running PCI Clock/Frequency Select 4: 3.3V 33-MHz free running PCI clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 5. PCI_0/SEL24_48# 10 I/O PCI Clock 0/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This output will be disabled when PCI_STOP# is active. This pin also serves as the select strap to determine device operating frequency of 24_48MHz output. PCI1:8 11, 13, 14, 16, 17, 18, 20, 21 O PCI Clock 1 through 8: 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled when PCI_STOP# is active. PCI9_E 22 O Early PCI Clock 9: 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled when PCI_STOP# is active. AGP0:2 26, 27, 28 O AGP Clock 0 through 2: 3.3V 66-MHz clock outputs. The operating frequency is controlled by FS0:4 (see Table 5). AGP0:2 will be disabled when AGP_STOP# is active. 48MHz/FS2 6 I/O 48-MHz Output/Frequency Selection 3: 3.3V 48-MHz non-spread spectrum output. 48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 5. 24_48MHz/FS3 7 I/O 24 or 48-MHz Output/Select 24 or 48 MHz: 3.3V 24 or 48-MHz non-spread spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 5. RST# 24 O (open-d rain) Reset#: Open-drain RESET# output. CPUT0, CPUC0 42, 41 O (open-d rain) CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs for the K7 processor. They are open-drain outputs. CPUT_CS, CPUC_CS 39, 38 O CPU Clock Output for Chipset: CPUT_CS and CPUC_CS are the differential CPU clock outputs for the chipset. They are push-pull outputs. These outputs will be disabled when CPU_STOP# is active. CPU_STOP# 36 I CPU STOP Input: This input will disable CPUT_CS and CPUC_CS when it is active. PCI_STOP# 35 I PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active. AGP_STOP# 44 I AGP STOP Input: This input will disable AGP0:2 when it is active. REF_STOP# 45 I REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz outputs when it is active.

Rev 1.0,November 27, 2006 Page 3 of 19 PD# 34 I Power-Down Input: This input will trigger the clock generator into Power Down mode when it is active. SDATA 31 I/O Data pin for SMBus circuitry. SCLK 30 I Clock pin for SMBus circuitry. VDD_CPU 40 P 2.5V Power Connection: Power supply for CPU output buffers. Connect to 2.5V. VDDQ_AGP 25 P 3.3V Power Connection: Power supply for AGP output buffers. Connect to 3.3V. VDDQ_PCI 15, 23 P 3.3V Power Connection: Power supply for PCI output buffers. Connect to 3.3V. VDDQ_48MHz 5 P 3.3V Power Connection: Power supply for 48 MHz output buffers. Connect to 3.3V. VDD_REF 1 P 3.3V Power Connection: Power supply for reference output buffers. Connect to 3.3V. VDD_Core 33 P 3.3V Power Connection: Power supply for PLL core. Connect to 3.3V. GND_REF, GND_48MHz, GND_PCI, GND_AGP , GND_Core, GND_CPU 2, 8, 29, 32, 37, G Ground Connections: Connect all ground pins to the common system ground plane. Pin Definitions (continued) Pin Name Pin No. Pin Type Pin Description

particular device functions. indexed byte is encoded in the command code. Table 1. Command Code Definitions need to be set at ‘0000000’. Table 2. Block Read and Block Write Protocol

10 Acknowledge from slave 10 Acknowledge from slave

19 Acknowledge from slave 19 Acknowledge from slave

28 Acknowledge from slave 21:27 Slave address – 7 bits

37 Acknowledge from slave 29 Acknowledge from slave

46 Acknowledge from slave 38 Acknowledge

Table 3. Word Read and Word Write Protocol

38 Stop 30:37 Data byte low from slave – 8 bits

38 Acknowledge

47 NOT acknowledge

48 Stop

Table 4. Byte Read and Byte Write Protocol

29 Stop 28 Read

29 Acknowledge from slave

38 Not Acknowledge

39 Stop

Rev 1.0,November 27, 2006 Page 6 of 19 W312-02 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 2. All unused register bits (reserved and N/A) should be written to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Byte 0: Control Register 0 Bit Pin# Name Default Description Bit 7 – Spread Enable 0 0 = Disabled 1 = Enabled Bit 6 – Spread Select2 0 ‘000’ = ±0.25% ‘001’ = –0.5% ‘010’ = ±0.5% ‘011’ = ±0.38% ‘100’ = Reserved ‘101’ = Reserved ‘110’ = Reserved ‘111’ = Reserved Bit 5 – Spread Select1 0 Bit 4 – Spread Select0 0 Bit 3 – SEL3 0 SW Frequency selection bits. See Table 5. Bit 2 – SEL2 0 Bit 1 – SEL1 0 Bit 0 – SEL0 0 Byte 1: Control Register 1 Bit Pin# Name Default Description Bit 7 42, 41 CPUT0, CPUC0 1 (Active/Inactive) Bit 6 39, 38 CPUT_CS, CPUC_CS 1 (Active/Inactive) Bit 5 6 48MHz 1 (Active/Inactive) Bit 4 7 24_48MHz 1 (Active/Inactive) Bit 3 – Reserved 0 Reserved Bit 2 28 AGP2 1 (Active/Inactive) Bit 1 27 AGP1 1 (Active/Inactive) Bit 0 26 AGP0 1 (Active/Inactive) Byte 2: Control Register 2 Bit Pin# Name Default Description Bit 7 20 PCI7 1 (Active/Inactive) Bit 6 18 PCI6 1 (Active/Inactive) Bit 5 17 PCI5 1 (Active/Inactive) Bit 4 16 PCI4 1 (Active/Inactive) Bit 3 14 PCI3 1 (Active/Inactive) Bit 2 13 PCI2 1 (Active/Inactive) Bit 1 11 PCI1 1 (Active/Inactive) Bit 0 10 PCI0 1 (Active/Inactive)

Rev 1.0,November 27, 2006 Page 7 of 19 Byte 3: Control Register Bit Pin# Name Default Description Bit 7 9 PCI_F 1 (Active/Inactive) Bit 6 22 PCI9_E 1 (Active/Inactive) Bit 5 – Reserved 0 Reserved Bit 4 21 PCI8 1 (Active/Inactive) Bit 3 46 REF2 1 (Active/Inactive) Bit 2 – Reserved 0 Reserved Bit 1 47 REF1 1 (Active/Inactive) Bit 0 48 REF0 1 (Active/Inactive) Byte 4: Watchdog Timer Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – FS_Override 0 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings Bit 5 – WD_TIMER4 1 These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. Bit 4 – WD_TIMER3 1 Bit 3 – WD_TIMER2 1 Bit 2 – WD_TIMER1 1 Bit 1 – WD_TIMER0 1 Bit 0 – WD_PRE_SCAL ER 0 0 = 150 ms 1 = 2.5 sec Byte 5: Control Register 5 Bit Pin# Name Default Description Bit 7 9 Latched FS4 input X Latched FS[4:0] inputs. These bits are read only. Bit 6 7 Latched FS3 input X Bit 5 6 Latched FS2 input X Bit 4 47 Latched FS1 input X Bit 3 48 Latched FS0 input X Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 0 Reserved Bit 0 – SEL4 0 SW Frequency selection bits. See Table 5.

Rev 1.0,November 27, 2006 Page 8 of 19 Byte 6: Reserved Register Bit Name Default Pin Description Bit 7 Reserved 1 Reserved Bit 6 Reserved 1 Reserved Bit 5 Reserved 1 Reserved Bit 4 Reserved 1 Reserved Bit 3 Reserved 1 Reserved Bit 2 Reserved 1 Reserved Bit 1 Reserved 1 Reserved Bit 0 Reserved 1 Reserved Byte 7: Reserved Register Bit Name Default Pin Description Bit 7 Reserved 1 Reserved Bit 6 Reserved 1 Reserved Bit 5 Reserved 1 Reserved Bit 4 Reserved 1 Reserved Bit 3 Reserved 1 Reserved Bit 2 Reserved 1 Reserved Bit 1 Reserved 1 Reserved Bit 0 Reserved 1 Reserved Byte 8: Vendor ID and Revision ID Register (Read Only) Bit Name Default Pin Description Bit 7 Revision_ID3 0 Revision ID bit[3] Bit 6 Revision_ID2 0 Revision ID bit[2] Bit 5 Revision_ID1 0 Revision ID bit[1] Bit 4 Revision_ID0 0 Revision ID bit[0] Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.

Rev 1.0,November 27, 2006 Page 9 of 19 Byte 9: System Reset and Watchdog Timer Register Bit Name Default Pin Description Bit 7 Reserved 0 Reserved Bit 6 PCI_DRV 0 PCI clock output drive strength 0 = Normal 1 = High Drive Bit 5 Reserved 0 Reserved Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Bit 2 WD_TO_STATUS 0 Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) Bit 1 WD_EN 0 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Bit 0 Reserved 0 Reserved Byte 10: Skew Control Register Bit Name Default Description Bit 7 CPU_Skew2 0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Bit 6 CPU_Skew1 0 Bit 5 CPU_Skew0 0 Bit 4 Reserved 0 Reserved Bit 3 PCI_Skew1 0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps Bit 2 PCI_Skew0 0 Bit 1 AGP_Skew1 0 AGP skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Bit 0 AGP_Skew0 0

Rev 1.0,November 27, 2006 Page 10 of 19 Byte 11: Recovery Frequency N - Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_N7 0 If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W312-02 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Bit 6 ROCV_FREQ_N6 0 Bit 5 ROCV_FREQ_N5 0 Bit 4 ROCV_FREQ_N4 0 Bit 3 ROCV_FREQ_N3 0 Bit 2 ROCV_FREQ_N2 0 Bit 1 ROCV_FREQ_N1 0 Bit 0 ROCV_FREQ_N0 0 Byte 12: Recovery Frequency M- Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_SEL 0 ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] Bit 6 ROCV_FREQ_M6 0 If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W312-02 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom- mended to use Word or Block write to update both registers within the same SMBus bus operation. Bit 5 ROCV_FREQ_M5 0 Bit 4 ROCV_FREQ_M4 0 Bit 3 ROCV_FREQ_M3 0 Bit 2 ROCV_FREQ_M2 0 Bit 1 ROCV_FREQ_M1 0 Bit 0 ROCV_FREQ_M0 0 Byte 13: Programmable Frequency Select N-Value Register Bit Name Default Pin Description Bit 7 CPU_FSEL_N7 0 If Prog_Freq_EN is set, W300 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 6 CPU_FSEL_N6 0 Bit 5 CPU_FSEL_N5 0 Bit 4 CPU_FSEL_N4 0 Bit 3 CPU_FSEL_N3 0 Bit 2 CPU_FSEL_N2 0 Bit 1 CPU_FSEL_N1 0 Bit 0 CPU_FSEL_N0 0

Rev 1.0,November 27, 2006 Page 11 of 19 Byte 14: Programmable Frequency Select N-Value Register Bit Name Default Description Bit 7 Pro_Freq_EN 0 Programmable output frequencies enabled 0 = disabled 1 = enabled Bit 6 CPU_FSEL_M6 0 If Prog_Freq_EN is set, W300 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 5 CPU_FSEL_M5 0 Bit 4 CPU_FSEL_M4 0 Bit 3 CPU_FSEL_M3 0 Bit 2 CPU_FSEL_M2 0 Bit 1 CPU_FSEL_M1 0 Bit 0 CPU_FSEL_M0 0 Byte 15: Reserved Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – Reserved 0 Reserved Bit 5 – Reserved 0 Reserved Bit 4 – Reserved 0 Reserved Bit 3 – Reserved 0 Reserved Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 1 Reserved. Write with ‘1’ Bit 0 – Reserved 1 Reserved. Write with ‘1’ Byte 16: Reserved Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – Reserved 0 Reserved Bit 5 – Reserved 0 Reserved Bit 4 – Reserved 0 Reserved Bit 3 – Reserved 0 Reserved Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 0 Reserved Byte 17: Reserved Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – Reserved 0 Reserved Bit 5 – Reserved 0 Reserved Bit 4 – Reserved 0 Reserved Bit 3 – Reserved 0 Reserved Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 0 Reserved

generated and a recovery frequency will be activated. All of the related registers are summarized inTable 7. Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Table 6. Register Summary will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. mended to use Word or Block write to update both registers within the same SMBus bus operation. FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. within the same SMBus bus operation. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.

value of the N-Value Register. RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. Table 6. Register Summary (continued) Table 7. Examples of N and M Value for Different CPU Frequency Range

Rev 1.0,November 27, 2006 Page 15 of 19 Absolute Maximum Ratings[2] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV Parameter Description Test Cond ition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPU =100 MHz Outputs Loaded[3] 260 mA IDD 2.5V Supply Current CPUCS =100 MHz Outputs Loaded[3] 25 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[4] –25 µA IIH Input High Current[4] 10 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V VOL Output Low Voltage CPUT_CS, CPUC_CS, CPUT0, CPUC0 Termination to V pull-up (external) 00 . 3 V VOH Output High Voltage CPUT_CS, CPUC_CS, CPUT0, CPUC0 Termination to V pull-up (external) 1.0 1.2 V IOL Output Low Current PCI, AGP V OL = 1.5V 70 110 135 mA REF V OL = 1.5V 50 70 100 mA 48 MHz V OL = 1.5V 50 70 100 mA 24_48 MHz V OL = 1.5V 50 70 100 mA IOH Output High Current PCI, AGP V OH = 1.5V 70 110 135 mA REF V OH = 1.5V 50 70 100 mA 48 MHz V OH = 1.5V 50 70 100 mA 24_48 MHz V OH = 1.5V 50 70 100 mA Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing i s NOT required. 3. All clock outputs loaded with 6" 60 : transmission lines with 20-pF capacitors. 4. X1 input threshold voltage (typical) is V DD/2.

Rev 1.0,November 27, 2006 Page 16 of 19 TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. Notes: 5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Tota l load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Refer to Figure 1 for K7 operation clock driver test circuit. Crystal Oscillator VTH X1 Input Threshold Voltage[4] VDD = 3.3V 1.65 V CLOAD Load Capacitance, Imposed on External Crystal[5] 18 pF CIN,X1 X1 Input Capacitance[6] Pin X2 unconnected TBD pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H Parameter Description Test Cond ition Min. Typ. Max. Unit CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[7] Parameter Description Test Condition/Comments CPU = 100 MHz CPU = 133 MHz tR Output Rise Edge Rate CPU_CS 1.0 4.0 1.0 4.0 V/ns tF Output Fall Edge Rate CPU_CS 1.0 4.0 1.0 4.0 V/ns tD Duty Cycle Measured at 50% point 45 55 45 55 % tJC Jitter, Cycle to Cycle 250 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance V O = VX 50 50 :

Rev 1.0,November 27, 2006 Page 17 of 19 PCI Clock Outputs (Lump Capacitance Test Load = 30 pF) Parameter Description Test Cond ition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabi- lization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 : REF Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 : 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz f D Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 :

for determining series termination value. Figure 1. K7 Open Drain Clock Driver Test Circuit

Rev 1.0, November 27, 2006 Page 19 of 19 W312-02 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Package Drawing and Dimension

Ordering Information

Ordering Code Package Type Product Flow W312-02H 48-pin SSOP Commercial, 0°C to 70°C W312-02HT 48-pin SSOP - Tape and Reel Commercial, 0°C to 70°C Lead-free CYW312OXC 48-pin SSOP Commercial, 0°C to 70°C CYW312OXCT 48-pin SSOP - Tape and Reel Commercial, 0°C to 70°C 4 8 - L e a dS h r u n kS m a l lO u t l i n eP a c k a g eO 4 8 51 85061 *C