W19B320BT

W19B320B WINBOND | Alldatasheet

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Technical content

Publication Release Date: Dec. 22, 2008 - 1 - Revision A5 Table of Contents-

Publication Release Date:Dec, 22, 2008 - 2 - Revisionv A5

Publication Release Date:Dec, 22, 2008 - 3 - Revisionv A5

Publication Release Date:Dec, 22, 2008 - 4 - Revisionv A5 1. GENERAL DESCRIPTION The W19B320BT/B is a 32Mbit, 2.7~3.6-volt single bank CMOS flash memory organized as 4M x 8 or 2M × 16 bits. The word-wide ( × 16) data appears on DQ15-DQ0, and byte-wi de (x 8) data appears on DQ7-DQ0. The device can be programmed and erased in-system with a standard 3.0-volt power supply. A 12-volt V PP is not required. The unique cell architecture of the W19B320BT/ B results in fast program/erase operations with extremely low current consumption (compared to other comparable 3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers. 2. FEATURES Performance

• 2.7~3.6-volt write (program and erase) operations
• Fast write operation − Sector erases time: 0.4 Sec (typical) − Chip erases time: 30Sec (typical) − Byte/Word programming time: 7/9 μs (typical)
• Read access time: 70 ns
• Typical program/erase cycles: 100K
• Twenty-year data retention
• Ultra low power consumption − Active current (Read): 10 mA (typical) − Active current (Read while Erase): 21 mA (typical) − Standby current: 0.2 μA (typical) Architecture
• Sector erase architecture − Eight 8KB, and sixty-three 64KB sectors − Top or bottom boot block configurations available − Supports full chip erase
• Security Sector Size: 256 Bytes − The Security Sector is an OTP; once the sector is programmed, it cannot be erased
• JEDEC standard byte-wide and word-wide pinouts
• Manufactured on WinStack 0.13μm process technology
• Available packages: 48-pin TSOP Software Features
• Compatible with common Flash Memory Interface (CFI) specification − Flash device parameters stored directly on the device − Allows software driver to identify and use a variety of different current and future Flash products
• End of program detection − Software method: Toggle bit/Data polling
• Unlock Bypass Program command − Reduces overall programming time when issuing multiple program command sequences Hardware Features
• Ready/#Busy output (RY/#BY) − Detect program or erase cycle completion
• Hardware reset pin (#RESET) − Reset the internal state machine to the read mode
• #WP/ACC input pin − Write protect (#WP) function allows protection of two outermost boot sectors, regardless of sector protection status Temperature range
• Extended temperature range (-20 to 85 )℃℃ •

Publication Release Date:Dec, 22, 2008 - 5 - Revisionv A5 3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM DECODER CONTROL OUTPUT BUFFER #CE #OE #WE A20 DQ0 DQ15/A-1 V V DD SS BANK DQ15/A-1 #WP/ACC #BYTE #RESET 5. PIN DESCRIPTION SYMBOL PIN NAME A0−A20 Address Inputs DQ0−DQ14 Data Inputs/Outputs Word mode DQ15 is Data Inputs/Outputs DQ15/A-1 Byte mode A-1 is Address input #CE Chip Enable #OE Output Enable #WE Write Enable #WP/ACC Hardware Write Protect/ Acceleration Pin #BYTE Byte Enable Input #RESET Hardware Reset RY/#BY Ready/Busy Status VDD Power Supply VSS Ground NC No Connection

Publication Release Date:Dec, 22, 2008 - 6 - Revisionv A5 6. FUNCTIONAL DESCRIPTION

6.1 Device Bus Operation

6.1.1 Word/Byte Configuration

The #BYTE pin controls the device data I/O pins operat e whether in the byte or word configuration. When the #BYTE pin is ‘1’, the device is in word configuration; DQ0 -DQ15 are active and controlled by #CE and #OE. When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 ar e tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

6.1.2 Reading Array Data

To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power control and used to select the device. #OE is the output control and gates a rray data to the output pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in words or bytes. The internal state machine is set for reading arra y data when device power-up, or after hardware reset. This ensures that no excess modification of the memo ry content occurs during the power transition. In this mode there is no command necessary to obtai n array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are changed.

6.1.3 Writing Commands/Command Sequences

In writhing a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH. For program operations, the #BYTE pin determines the device accepts program data whether in bytes or in words. Refer to “Word/Byte Configuration” for more information. The Unlock Bypass mode of device is to facilitat e a faster programming. When a bank enters the Unlock Bypass mode, only two write cycles are requir ed to program a word or byte. Please refer to "Word/Byte Configuration” section for details on programming data to the device using both standard and Unlock Bypass command sequences. The erase operation can erase a sector, multiple se ctors, even the entire devic e. The “sector address” is the address bits required to solely select a sector. Accelerated Program Operation The device provides accelerated program operations through the ACC function. This is one of two functions provided by the #WP/A CC pin. This function is primarily intended to allow a faster manufacturing throughput in the factory. If #WP/ACC pin is set at V HH, the device automatically enters in to the Unlock Bypass mode. Then the device will temporarily unprotect any protected sect ors, and uses the higher voltage on this pin to reduce the time required for program operations. The system would use a two-cycle program command sequence required by the Unlock Bypass mode. When V HH is removed from the #WP/ACC pin, the device is back to a normal operation.

Publication Release Date:Dec, 22, 2008 - 7 - Revisionv A5 Please note that the #WP/ ACC pin can not be at V HH for operations except accelerated programming; otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left floating; otherwise, an unconnected inconsistent behavior will occur. AUTOSELECT Functions When the system writes the AUTOSELECT comm and sequence, the device enters the AUTOSELECT mode. The system can then read AUTOSELECT codes fr om the internal register (which is separate from the memory array) on DQ0 –DQ7. The standar d read cycle timings are applied in this mode. Please refer to the AUTOSELECT Mode and AUTO SELECT Command Sequence sections for more information.

6.1.4 Standby Mode

When the system is not reading or writing to the device, the device will be in a standby mode. In this mode, current consumption is greatly reduced, and the outputs are in the high impedance state, independent from the #OE input. When the #CE and #RESET pins are both held at V DD ±0.3V, the device enters into the CMOS standby mode (note that this is a more restricted voltage range than V IH.) When #CE and #RESET are held at V IH, but not within VDD ±0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. When the device is deselected during erasing or progr amming, the device initiates active current until the operation is completed.

6.1.5 Automatic Sleep Mode

The automatic sleep mode minimizes device's energy consumption. When addresses remain stable for tACC + 30ns, the device will enable this mode automat ically. The automatic sleep mode is independent from the #CE, #WE, and #OE control signals. Standard address access timings provide new data when addresses are changed. In sleep mode, output data is latched and always available to the system. 6.1.6 #RESET: Hardware Reset Pin The #RESET pin provides a hardware method to re set the device to reading array data. When the #RESET pin is set to low for at least a period of t RP, the device will immediately terminate every operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data mode. To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. Current is reduced for the duration of t he #RESET pulse. When #RESET is held at V SS ±0.3V, the device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within VSS ±0.3V, the standby current will be greater. The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the device, enabling the system to read the boot-up firmware from the device. If #RESET is asserted during the progr am or erase operation, the RY/#BY pin will be at “0” (busy) until the internal reset operation is complete. If #RESET is asserted when a program or erase operation is not processing (RY/#BY pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH.

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6.1.7 Output Disable Mode

When the #OE input is at V IH, output from the device is disabled. The output pins are set in the high impedance state.

6.1.8 AUTOSELECT Mode

The AUTOSELECT mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on DQ0-DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the AUTOSELECT codes can also be accessed in-system through the command register. When using programming equipment, the AUTOSELECT mode requires VID (8.5V to 11.5V) on address pins A9. Address pins A6, A1, and A0 must be as s hown in table. In addition, when verifying sector protection, the sector address must appear on t he appropriate highest order address bits. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ0-DQ7.

6.1.9 Sector/Sector Block Protection and Unprotection

The hardware sector protection feature disables bot h program and erasure operations in any sectors. The hardware sector Unprotection feature re- enables both program and erasure operations in previously protected sectors. Sector Protection/Unprotection can be implemented through two methods. The primary method requires V ID on the #RESET pin, and can be implemented either in-system or through programming equipment. This method uses standard microprocessor bus cycle timing. The alternate method intended only for programming equipment requires V ID on address pin A9 and #OE. It is possible to determine whether a sector is protected or unprotected. See the Application Note for detail information.

6.1.10 Write Protect (#WP)

The Write Protect function provides a hardware method to protect the certain boot sectors without using VID. This function is one of two features provided by the #WP/ACC pin. When the #WP/ACC pin is set at V IL, the device disables program and erase functions in the two outermost 8 Kbytes boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection.” The two outermost 8 Kbytes boot sectors are the two sectors containi ng either the lowest addresses in a bottom-boot- configured device or the highest addresses in a top-boot-configured device. When the #WP/ACC pin is set at V IH, the device reverts to the two outermost 8 Kbytes boot sectors were last set either to be protect ed or unprotected. That is, sector Protection or Unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Please note that the #WP/ACC pin must not be left fl oating or unconnected; otherwise, the inconsistent behavior of the device may occur.

6.1.11 Temporary Sector Unprotect

This feature allows temporary U nprotection of previously protect ed sectors to change data in-system. When the #RESET pin is set to V ID, the Sector Unprotect mode is acti vated. During this mode, formerly

Publication Release Date:Dec, 22, 2008 - 9 - Revisionv A5 protected sectors can be programmed or erased by selecting the sector addresses. What if V ID is removed from the #RESET pin, all the previously protected sectors are protected again.

6.1.12 Security Sector Flash Memory Region

The Security Sector feature provides an OT P memory region that enables permanent device identification through an Electronic Serial Number (ESN ). The Security Sector uses a Security Sector Indicator Bit (DQ7) to indicate whether the Securi ty Sector is locked or not when shipped from the factory. The DQ7 is permanently set when it is in the factory and cannot be changed, which prevents copying of a factory locked part. This ensures the security of the ESN when the product is shipped to the field. This issue should be considered during system design. Winbond offe rs the device with the Security Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Security Sector Indicator Bit permanently set to “1” The customer-lockable version is shipped with the Security Sector unprotected, which allowing customers to utilize the sector in any ways they choose. The customer-lockable version has the Security Sector Indicator Bit permanently set to “0.” Thus, the Security Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Security Sector through a command sequence (see “Enter Security Sector/Exit Security Sector Command Sequence”). A fter the system has written the Enter Security Sector command sequence, it may read the Security Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system i ssues the Exit Security Sector command sequence, or until power is removed from t he device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Factory Locked: Security Sector Programmed and Protected At the Factory The device Security Sector is protected when it is shipped from the factory, and it cannot be modified in any way. The device is available to be preprogrammed by one of the following:

• A random, secure ESN only
• Customer code through the supplier's service
• Both a random, secure ESN and customer code through supplier's service. In devices with an ESN, the Bottom Boot device will be with the 16-byte ESN in the lowest addressable memory area at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot device the starting addr ess of the ESN will be at the bottom of the highest 8 Kbytes boot sector at addresses 1FF000h–1FF007h in word mode (or addresses 3FE000h–3FE00Fh in byte mode). Customers may choose have their code programmed by Winbond. Winbond can program the customer’s code, with or without the random ESN . The devices are then shipped with the Security Sector permanently locked. Customer Lockable: Security Sector NOT Programmed or Protected At the Factory If the security feature is not nec essary, the Security Sector can be seen as an additional OTP memory space. When in system design, this issue should be considered. The Security Sector can be read, programmed; but cannot be erased. Please note t hat when programming the Security Sector, the accelerated programming (ACC) and unlock bypass functi ons are not available. The Security Sector area can be protected using one of the following procedures:
• Write the three-cycle Enter Security Sector Region command sequence, and then follow the in- system sector protect algorithm, except that #RESET may be at either V IH or VID. This allows in-system protection of the Security Sector without raising any device pin to a high voltage. Please note that this method is only suitable for the Security Sector.

Publication Release Date:Dec, 22, 2008 - 10 - Revisionv A5

• To verify the protect/unprotect status of the Security Sector; follow the algorithm show in Security Sector Protect Verify. The Security Sector protection must be used with caution, since there is no procedure available for unprotect the Security Sector area and none of the bits in the Security Sector memory space can be modified in any ways.

6.1.13 Hardware Data Protection

The command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes. In addition, the following hardware data protection measures prevent inadvertent erasure or pr ogramming, which might be caused by spurious system level signals during VDD power-up and power-down transitions, or from system noise. Write Pulse “Glitch” Protection Noise pulses, which is less than 5 ns (typical) on #OE, #CE or #WE, do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of #OE = V IL, #CE = V IH or #WE = V IH. #CE and #WE must be a logical zero while #OE is a logical one to initiate a write cycle. Power-Up Write Inhibit During power up, if #WE = #CE = V IL and #OE = V IH, the device does not accept commands on the rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.

6.2 Command Definitions

The device operation can be initiated by writing specific address and data commands or sequences into the command register. The device will be reset to reading array data when writing incorrect address and data values or writing them in the improper sequence. The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing waveforms.

6.2.1 Reading Array Data

After device power-up, it is automatically set to reading array data. There is no commands are required to retrieve data. After completing an Embedded Pr ogram or Embedded Erase algorithm, each bank is ready to read array data. The system must initiate the reset command to re turn a bank to read mode if DQ5 goes high during an active program or erase operation, or the bank is in the AUTOSELECT mode. See Reset Command section and Requirements for Reading Array Data in the Device Bus Operations section for more information.

6.2.2 Reset Command

The banks will be to the read mode when writing t he reset command. For this command, the address bits are Don’t Care.

Publication Release Date:Dec, 22, 2008 - 11 - Revisionv A5 The reset command may be written between the sequential cycles in an erase command sequence before erasing begins. This resets the bank to whic h the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank, to wh ich the system was writ ing to the read mode. When programming begins, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an AUTOSELECT command sequence. When in the AUTOSELECT mode, the reset command must be written to return to the read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode.

6.2.3 AUTOSELECT Command Sequence

The AUTOSELECT command sequence provides the host system to access the manufacturer and device codes, and determine whether a sector is protec ted or not. This is an alternative method, which is intended for PROM programmers and requires V ID on address pin A9. The AUTOSELECT command sequence may be written to an address within a bank t hat is either in the read mode. When the device is actively programming or erasing in the other bank, the AUTOSELECT command may not be written. The first writing two unlock cycles initiate the AUTOSELECT command sequence. This is followed by a third write cycle that contains the bank address and the AUTOSELECT command. The bank then enters into the AUTOSELECT mode. The system may read at any address within the same bank without initiating another AUTOSELECT command sequence:

• A read cycle at address (BA) XX00h (where BA is the bank address) returns the manufacturer code.
• A read cycle at address (BA) XX01h in word mode (or (BA) XX02h in byte mode) returns the device code.
• A read cycle to an address containing a sector address (SA) within the same bank, and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected or 00h if it is unprotected. To return to read mode, the system must write the reset command. Enter Security Sector/Exit Security Sector Command Sequence The Security Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Se curity Sector region by issuing the three-cycle Enter Security Sector command sequence. The device continues to access the Security Sector region until the system issues the four-c ycle Exit Security Sector co mmand sequence. The Exit Security Sector command sequence returns the device to normal operation. See “Security Sector Flash Memory Region” for further information.

6.2.4 Byte/Word Program Command Sequence

The device can be programmed either by word or byte, which depending on the state of the #BYTE pin. Programming is a four-bus-cycle operation. The pr ogram command sequence is initiated by writing two unlock write cycles, followed by the program setup command. The program address and data are written next, which in turn initiate the Embedded Progr am algorithm. The device automatically provides internally generated program pulses and verifies the programmed cell margin.

Publication Release Date:Dec, 22, 2008 - 12 - Revisionv A5 Once the Embedded Program algorithm is complete, the bank then returns to the read mode and addresses are no longer latched. The system can det ermine the status of t he program operation by using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information. Any commands written to the device during the Embedded Program Algorithm are ignored. Please note that a hardware reset will immediately stop the pr ogram operation. The program command sequence should be reinitiated when the bank has returned to the read mode, in order to ensure data integrity. Programming is allowed in any sequence and acro ss sector boundaries. A bit cannot be programmed from “0” back to “1.” If trying to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate that the operation is su ccessful. However, a succeeding read will show that the data is still “0.” Only erase operations can change “0” to “1.”

6.2.5 Unlock Bypass Command Sequence

The unlock bypass feature provides the system to program bytes or words to a bank which is faster than using the standard program command sequenc e. The unlock bypass command sequence is initiated by first writing two unlock cycles. A nd a third write cycle c ontaining the unlock bypass command, 20h, is followed. Then, the bank enters into the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. In the same manner, additional data is programmed. This mode dispenses with the initial two unlock cycles which required in the st andard program command sequence, resulting in faster total programming time. All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The system must issue the two-cycle unlock bypass reset command sequence to exit the unlock bypass mode. T he first cycle must contain t he bank address and the data 90h. The second cycle needs to contain the data 00h. Then, the bank returns to the read mode. The device offers accelerated program oper ations by the #WP/ ACC pin. When the V HH is set at the #WP/ACC pin, the device automatic ally enters into the Unlock By pass mode. Then, the two-cycle Unlock Bypass program command sequence may be writt en. To accelerate the operation, the device must use the higher voltage on the #WP/ACC pin. Pl ease note that the #WP/A CC pin must not be at VHH in any operation other than accelerated progr amming; otherwise the device may be damaged. In addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent behavior may occur.

6.2.6 Chip Erase Command Sequence

Chip erase is a six-bus cycle operation. Writing tw o unlock cycles initiate the chip erase command sequence, which is followed by a set-up command. After chip erase command, two additional unlock write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system preprogram is not required prior to erase. Befo re electrical erase, the Embedded Erase algorithm automatically preprograms and verifies the entire memo ry for an all zero data pattern. Any controls or timings during these operations is not required in system. As the Embedded Erase algorithm is complete, the bank returns to the read mode and addresses are no longer latched. The system can determine the status of the eras e operation by using DQ7, DQ6, DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status bits.

Publication Release Date:Dec, 22, 2008 - 13 - Revisionv A5 Any commands written during the chip erase operation will be ignored. However, a hardware reset shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip erase command sequence should be reinitiated when that bank has returned to reading array data.

6.2.7 Sector Erase Command Sequence

Sector erase is a six-bus cycle operation. Writing tw o unlock cycles initiate the sector erase command sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The device does not require the system to preprogram before erase. Before electrical erase, the Embedded Erase algorithm automatically programs and ve rifies the entire memory for an all zero data pattern. Any controls or timings during these operations are not required in system. A sector erase time-out of 50 μs occurs after the command sequence is written. Additional sector addresses and sector erase commands may be written during the time-out period. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these addi tional cycles must be less than 50 μs; otherwise, erasure may begin. Any sector erase address and command follo wing the exceeded time-out may or may not be accepted. To ensure all commands are accepted, proc essor interrupts be disabled during this time is recommended. The interrupts can be re-enabled after t he last Sector Erase command is written. Any command other than Sector Erase during the time -out period resets the bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time -out begins from the rising edge of the final #WE pulse in the command sequence. As the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Please note that when the Embedded Erase operation is in progress, the system can read data from the non-erasing bank at the same time. By reading DQ7, DQ6, DQ2, or RY/#BY in the erasing bank, the system can det ermine the status of the erase oper ation. Please refer to the Write Operation Status section for information on these status bits. When the sector erase operation begins, no command is valid. All commands are ignored. However, a hardware reset shall terminate the erase operation imm ediately. If this occurs, to ensure data integrity, the sector erase command sequence should be reinitia ted once the bank has returned to reading array data.

6.3 Write Operation Status

The device provides several bits to determine the st atus of a program or er ase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. T he device also offers a hardware-based output signal, RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been completed.

6.3.1 DQ7: #Data Polling

The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence.

Publication Release Date:Dec, 22, 2008 - 14 - Revisionv A5 During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program al gorithm has completed that the device outputs the data programmed to DQ7. The system must pr ovide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1μs, and then that bank returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase algorithm has completed, #Data Polling produces “1 ” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. After an erase command sequence is written, if all se ctors selected for erasi ng are protected, #Data Polling on DQ7 is active for about 100 μs, and then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just before the completion of an Embedded Pr ogram or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data output s on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will appear on successive read cycles.

6.3.2 RY/#BY: Ready/#Busy

The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode or the standby mode.

6.3.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operati on, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the operation has completed, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for about 100 μs, and then returns to reading array dat a. If not all selected sectors are protected, the Embedded Erase algorithm erases t he unprotected sectors, and ignores the selected sectors which are protected. If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program command sequence is written, and then returns to reading array data.

6.3.4 Reading Toggle Bits DQ6/DQ2

Whenever the system initially starts to read toggle bit status, it must read DQ0-DQ7 at least twice in a row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the toggle bit after the first read. While after the second read, the system would compare the new value of the

Publication Release Date:Dec, 22, 2008 - 15 - Revisionv A5 toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erasure operation. The system can read array data on DQ0-DQ7 on the following read cycle. However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erasure operation. If it is still toggling, the device did not complete the operation, and the system must write the reset command to return to reading array data. Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation.

6.3.5 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indica tes that the program or erase cycle was not successfully completed. The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.” Under both these conditions, the system must write the reset command to return to the read mode.

6.3.6 DQ3: Sector Erase Timer

After writing a sector erasure command sequence, the system may read DQ3 to determine whether erasure has begun or not. (The sector erase timer does not apply to the chip erase command.) The entire time-out applies after each additional sector erasure command if additional sectors are selected for erasure. Once the timeout period has completed, DQ3 switches from “0” to “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 μs, the system need not monitor, DQ3 does not need to be monitored. Please also refer to Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 ( #Data Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all further commands are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. The system software should check the status of DQ3 before and following each subsequent sector erase command to ensure the command has been accepted. If DQ3 is high on the second status check, the last command might not have been accepted.

Publication Release Date:Dec, 22, 2008 - 16 - Revisionv A5 7. TABLE OF OPERATION MODES

7.1 Device Bus Operations

MODE #CE #OE #WE #RESET #WP/ACC ADDRESSES DQ0-DQ7 #BYTE=VIH #BYTE =VIL Read L L H H L/H A IN D OUT D OUT Write L H L H (Note2) A IN D IN D IN DQ8-DQ14 =High-Z, DQ15=A-1 Standby VDD ±0.3V X X VDD ±0.3V H X High-Z High-Z High-Z Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H X High-Z High-Z High-Z Sector Protect L H L V ID L/H SA, A6=L, A1=H, A0=L DIN X X Sector Unprotect L H L V ID (Note2) SA, A6=H, A1=H, A0=L D IN X X Temporary Sector Unprotect X X X V ID (Note2) A IN D IN D IN High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 ~ 11.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out. Notes: 1. Addresses are A20:A0 in word mode (#BYTE = V IH), A20: A-1 in byte mode (#BYTE = VIL). 2. If #WP/ACC = V IL, the two outermost boot sectors remain protected. If #WP/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotect ion”. If #WP/ACC = VHH, all sectors will be unprotected.

Publication Release Date:Dec, 22, 2008 - 17 - Revisionv A5

7.2 AUTOSELECT Codes (High Voltage Method)

#CE #OE #WE A20 TO A12 A11 TO A10 TO TO A1 A0 #BYTE = VIH #BYTE = VIL DQ7 TO DQ0 Manufacturer ID: Winbond VIL VIL VIH X X V ID X VIL XV IL VIL X X DAh Device ID: W19B320BT (Top Boot Block) V IL VIL VIH X X V ID X VIL XV IL VIH 22h X BAh Device ID: W19B320BB (Bottom Boot Block) V IL V IL V IH X X V ID XV IL XV IL VIH 22h X 2Ah Sector Protection Verification VIL VIL VIH SA X V ID X VIL XV IH VIL X X X X 01h (protected) 00h (unprotected) Security Indicator Bit (DQ7) VIL VIL VIH X X V ID X VIL XV IH VIH X X 82h (factory locked) 02h (not factory locked) Legend: SA= Sector Address, X= Don't Care.

Publication Release Date:Dec, 22, 2008 - 18 - Revisionv A5

7.3 Sector Address Table (Top Boot Block)

(Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 000000XXX 64/32 000000h-00FFFFh 000000h-07FFFh SA1 000001XXX 64/32 010000h-01FFFFh 008000h-0FFFFh SA2 000010XXX 64/32 020000h-02FFFFh 010000h-17FFFh SA3 000011XXX 64/32 030000h-03FFFFh 018000h-01FFFFh SA4 000100XXX 64/32 040000h-04FFFFh 020000h-027FFFh SA5 000101XXX 64/32 050000h-05FFFFh 028000h-02FFFFh SA6 000110XXX 64/32 060000h-06FFFFh 030000h-037FFFh SA7 000111XXX 64/32 070000h-07FFFFh 038000h-03FFFFh SA8 001000XXX 64/32 080000h-08FFFFh 040000h-047FFFh SA9 001001XXX 64/32 090000h-09FFFFh 048000h-04FFFFh SA10 001010XXX 64/32 0A0000h-0AFFFFh 050000h-057FFFh SA11 001011XXX 64/32 0B0000h-0BFFFFh 058000h-05FFFFh SA12 001100XXX 64/32 0C0000h-0CFFFFh 060000h-067FFFh SA13 001101XXX 64/32 0D0000h-0DFFFFh 068000h-06FFFFh SA14 001110XXX 64/32 0E0000h-0EFFFFh 070000h-077FFFh SA15 001111XXX 64/32 0F0000h-0FFFFFh 078000h-07FFFFh SA16 010000XXX 64/32 100000h-10FFFFh 080000h-087FFFh SA17 010001XXX 64/32 110000h-11FFFFh 088000h-08FFFFh SA18 010010XXX 64/32 120000h-12FFFFh 090000h-097FFFh SA19 010011XXX 64/32 130000h-13FFFFh 098000h-09FFFFh SA20 010100XXX 64/32 140000h-14FFFFh 0A0000h-0A7FFFh SA21 010101XXX 64/32 150000h-15FFFFh 0A8000h-0AFFFFh SA22 010110XXX 64/32 160000h-16FFFFh 0B0000h-0B7FFFh SA23 010111XXX 64/32 170000h-17FFFFh 0B8000h-0BFFFFh SA24 011000XXX 64/32 180000h-18FFFFh 0C0000h-0C7FFFh SA25 011001XXX 64/32 190000h-19FFFFh 0C8000h-0CFFFFh SA26 011010XXX 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh SA27 011011XXX 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh SA28 011100XXX 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh SA29 011101XXX 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh SA30 011110XXX 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh SA31 011111XXX 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh SA32 100000XXX 64/32 200000h-20FFFFh 100000h-107FFFh SA33 100001XXX 64/32 210000h-21FFFFh 108000h-10FFFFh SA34 100010XXX 64/32 220000h-22FFFFh 110000h-117FFFh

Publication Release Date:Dec, 22, 2008 - 19 - Revisionv A5 Sector Address Table (Top Boot Block), continued SECTOR SECTOR ADDRESS A20-A12 SECTOR SIZE (Kbytes/Kwords) (X8) ADDRESS RANGE (X16) ADDRESS RANGE SA35 100011XXX 64/32 230000h-23FFFFh 118000h-11FFFFh SA36 100100XXX 64/32 240000h-24FFFFh 120000h-127FFFh SA37 100101XXX 64/32 250000h-25FFFFh 128000h-12FFFFh SA38 100110XXX 64/32 260000h-26FFFFh 130000h-137FFFh SA39 100111XXX 64/32 270000h-27FFFFh 138000h-13FFFFh SA40 101000XXX 64/32 280000h-28FFFFh 140000h-147FFFh SA42 101010XXX 64/32 2A0000h-2AFFFFh 150000h-157FFFh SA43 101011XXX 64/32 2B0000h-2BFFFFh 158000h-15FFFFh SA44 101100XXX 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA45 101101XXX 64/32 2D0000h-2DFFFFh 168000h-16FFFFh SA46 101110XXX 64/32 2E0000h-2EFFFFh 170000h-177FFFh SA47 101111XXX 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA48 110000XXX 64/32 300000h-30FFFFh 180000h-187FFFh SA49 110001XXX 64/32 310000h-31FFFFh 188000h-18FFFFh SA50 110010XXX 64/32 320000h-32FFFFh 190000h-197FFFh SA51 110011XXX 64/32 330000h-33FFFFh 198000h-19FFFFh SA52 110100XXX 64/32 340000h-34FFFFh 1A0000h-1A7FFFh SA53 110101XXX 64/32 350000h-35FFFFh 1A8000h-1AFFFFh SA54 110110XXX 64/32 360000h-36FFFFh 1B0000h-1B7FFFh SA55 110111XXX 64/32 370000h-37FFFFh 1B8000h-1BFFFFh SA56 111000XXX 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA57 111001XXX 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA58 111010XXX 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh SA59 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA60 111100XXX 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh SA61 111101XXX 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh SA62 111110XXX 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh SA63 111111000 8/4 3F0000h-3F1FFFh 1F8000h-1F8FFFh SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h-1F9FFFh SA65 111111010 8/4 3F4000h-3F5FFFh 1FA000h-1FAFFFh SA66 111111011 8/4 3F6000h-3F7FFFh 1FB000h-1FBFFFh SA67 111111100 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh SA68 111111101 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h-1FEFFFh SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h-1FFFFFh Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE = VIH).

Publication Release Date:Dec, 22, 2008 - 20 - Revisionv A5 Security Sector Addresses for Top Boot Devices DEVICE Sector Address A20-A12 SECTOR SIZE (bytes/words) (X 8) ADDRESS RANGE (X 16) ADDRESS RANGE W19B320BT/ B 111111XXX 256/128 3FE000h-3FE0FFh 1FF000h-1FF07Fh

7.4 Sector Address Table (Bottom Boot Block)

(Kbytes/Kwords) (X8) ADDRESS RANGE (X16) ADDRESS RANGE SA0 000000000 8/4 000000h-001FFFh 000000h-000FFFh SA1 000000001 8/4 002000h-003FFFh 001000h-001FFFh SA2 000000010 8/4 004000h-005FFFh 002000h-002FFFh SA3 000000011 8/4 006000h-007FFFh 003000h-003FFFh SA4 000000100 8/4 008000h-009FFFh 004000h-004FFFh SA5 000000101 8/4 00A000h-00BFFFh 005000h-005FFFh SA6 000000110 8/4 00C000h-00DFFFh 006000h-006FFFh SA7 000000111 8/4 00E000h-00FFFFh 007000h-007FFFh SA8 000001XXX 64/32 010000h-01FFFFh 008000h-00FFFFh SA9 000010XXX 64/32 020000h-02FFFFh 010000h-017FFFh SA10 000011XXX 64/32 030000h-03FFFFh 018000h-01FFFFh SA11 000100XXX 64/32 040000h-04FFFFh 020000h-027FFFh SA12 000101XXX 64/32 050000h-05FFFFh 028000h-02FFFFh SA13 000110XXX 64/32 060000h-06FFFFh 030000h-037FFFh SA14 000111XXX 64/32 070000h-07FFFFh 038000h-03FFFFh SA15 001000XXX 64/32 080000h-08FFFFh 040000h-047FFFh SA16 001001XXX 64/32 090000h-09FFFFh 048000h-04FFFFh SA17 001010XXX 64/32 0A0000h-0AFFFFh 050000h-057FFFh SA18 001011XXX 64/32 0B0000h-0BFFFFh 058000h-05FFFFh SA19 001100XXX 64/32 0C0000h-0CFFFFh 060000h-067FFFh SA20 001101XXX 64/32 0D0000h-0DFFFFh 068000h-06FFFFh SA21 001110XXX 64/32 0E0000h-0EFFFFh 070000h-077FFFh SA22 001111XXX 64/32 0F0000h-0FFFFFh 078000h-07FFFFh SA23 010000XXX 64/32 100000h-10FFFFh 080000h-087FFFh SA24 010001XXX 64/32 110000h-11FFFFh 088000h-08FFFFh SA25 010010XXX 64/32 120000h-12FFFFh 090000h-097FFFh SA26 010011XXX 64/32 130000h-13FFFFh 098000h-09FFFFh SA27 010100XXX 64/32 140000h-14FFFFh 0A0000h-0A7FFFh SA28 010101XXX 64/32 150000h-15FFFFh 0A8000h-0AFFFFh SA29 010110XXX 64/32 160000h-16FFFFh 0B0000h-0B7FFFh SA30 010111XXX 64/32 170000h-17FFFFh 0B8000h-0BFFFFh SA31 011000XXX 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

Publication Release Date:Dec, 22, 2008 - 21 - Revisionv A5 Sector Address Table (Bottom Boot Block), continued SECTOR SECTOR ADDRESS A20-A12 SECTOR SIZE (Kbytes/Kwords) (X8) ADDRESS RANGE (X16) ADDRESS RANGE SA32 011001XXX 64/32 190000h-19FFFFh 0C8000h-0CFFFFh SA33 011010XXX 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh SA34 011011XXX 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh SA35 011100XXX 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh SA36 011101XXX 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh SA37 011110XXX 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh SA38 011111XXX 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh SA39 100000XXX 64/32 200000h-20FFFFh 100000h-107FFFh SA40 100001XXX 64/32 210000h-21FFFFh 108000h-10FFFFh SA41 100010XXX 64/32 220000h-22FFFFh 110000h-117FFFh SA42 100011XXX 64/32 230000h-23FFFFh 118000h-11FFFFh SA43 100100XXX 64/32 240000h-24FFFFh 120000h-127FFFh SA44 100101XXX 64/32 250000h-25FFFFh 128000h-12FFFFh SA45 100110XXX 64/32 260000h-26FFFFh 130000h-137FFFh SA46 100111XXX 64/32 270000h-27FFFFh 138000h-13FFFFh SA47 101000XXX 64/32 280000h-28FFFFh 140000h-147FFFh SA48 101001XXX 64/32 290000h-29FFFFh 148000h-14FFFFh SA49 101010XXX 64/32 2A0000h-2AFFFFh 150000h-157FFFh SA50 101011XXX 64/32 2B0000h-2BFFFFh 158000h-15FFFFh SA51 101100XXX 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA52 101101XXX 64/32 2D0000h-2DFFFFh 168000h-16FFFFh SA53 101110XXX 64/32 2E0000h-2EFFFFh 170000h-177FFFh SA54 101111XXX 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA55 111000XXX 64/32 300000h-30FFFFh 180000h-187FFFh SA56 110001XXX 64/32 310000h-31FFFFh 188000h-18FFFFh SA57 110010XXX 64/32 320000h-32FFFFh 190000h-197FFFh SA58 110011XXX 64/32 330000h-33FFFFh 198000h-19FFFFh SA59 110100XXX 64/32 340000h-34FFFFh 1A0000h-1A7FFFh SA60 110101XXX 64/32 350000h-35FFFFh 1A8000h-1AFFFFh SA61 110110XXX 64/32 360000h-36FFFFh 1B0000h-1B7FFFh SA62 110111XXX 64/32 370000h-37FFFFh 1B8000h-1BFFFFh SA63 111000XXX 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA64 111001XXX 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA65 111010XXX 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh SA65 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA67 111100XXX 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh SA68 111101XXX 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh SA69 111110XXX 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh SA70 111111XXX 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE =VIH).

Publication Release Date:Dec, 22, 2008 - 22 - Revisionv A5 Security Sector Addresses for Bottom Boot Devices DEVICE SECTOR ADDRESS A20-A12 SECTOR SIZE (bytes/words) (X8) ADDRESS RANGE (X16) ADDRESS RANGE W19B320BT/ B 000000XXX 256/128 000000h-0000FFh 000000h-00007Fh

Publication Release Date:Dec, 22, 2008 - 23 - Revisionv A5 Top Boot Sector/Sector Block Address for Protection/Unprotection) SECTOR A20-A12 SECTOR/ SECTOR BLOCK SIZE SA0-SA3 000000XXX 000001XXX 000010XXX 000011XXX 256(4x64) K bytes SA4-SA7 0001XXXXX 256(4x64) K bytes SA8-SA11 0010XXXXX 256(4x64) K bytes SA12-SA15 0011XXXXX 256(4x64) K bytes SA16-SA19 0100XXXXX 256(4x64) K bytes SA20-SA23 0101XXXXX 256(4x64) K bytes SA24-SA27 0110XXXXX 256(4x64) K bytes SA28-SA31 0111XXXXX 256(4x64) K bytes SA32-SA35 1000XXXXX 256(4x64) K bytes SA36-SA39 1001XXXXX 256(4x64) K bytes SA40-SA43 1010XXXXX 256(4x64) K bytes SA44-SA47 1011XXXXX 256(4x64) K bytes SA48-SA51 1100XXXXX 256(4x64) K bytes SA52-SA55 1101XXXXX 256(4x64) K bytes SA56-SA59 1110XXXXX 256(4x64) K bytes SA60-SA62 111100XXX 111101XXX 111110XXX 192(3x64) K bytes SA63 111111000 8 K bytes SA64 111111001 8 K bytes SA65 111111010 8 K bytes SA66 111111011 8 K bytes SA67 111111100 8 K bytes SA68 111111101 8 K bytes SA69 111111110 8 K bytes SA70 111111111 8 K bytes

Publication Release Date:Dec, 22, 2008 - 24 - Revisionv A5 Bottom Boot Sector/Sector Block Address for Protection/Unprotection) SECTOR A20-A12 SECTOR/ SECTOR BLOCK SIZE SA70-SA67 111111XXX 111110XXX 111101XXX 111100XXX 256(4x64) K bytes SA66-SA63 1110XXXXX 256(4x64) K bytes SA62-SA59 1101XXXXX 256(4x64) K bytes SA58-SA55 1100XXXXX 256(4x64) K bytes SA54-SA51 1011XXXXX 256(4x64) K bytes SA50-SA47 1010XXXXX 256(4x64) K bytes SA46-SA43 1001XXXXX 256(4x64) K bytes SA42-SA39 1000XXXXX 256(4x64) K bytes SA38-SA35 0111XXXXX 256(4x64) K bytes SA34-SA31 0110XXXXX 256(4x64) K bytes SA30-SA27 0101XXXXX 256(4x64) K bytes SA26-SA23 0100XXXXX 256(4x64) K bytes SA22-SA19 0011XXXXX 256(4x64) K bytes SA18-SA15 0010XXXXX 256(4x64) K bytes SA14-SA11 0001XXXXX 256(4x64) K bytes SA10-SA8 000011XXX 000010XXX 000001XXX 192(3x64) K bytes SA7 000000111 8 K bytes SA6 000000110 8 K bytes SA5 000000101 8 K bytes SA4 000000100 8 K bytes SA3 000000011 8 K bytes SA2 000000010 8 K bytes SA1 000000001 8 K bytes SA0 000000000 8 K bytes

Publication Release Date:Dec, 22, 2008 - 25 - Revisionv A5

7.5 CFI Query Identification String

(Word Mode) DATA ADDRESS (Byte Mode) Query-unique ASCII string "QRY" 10h 11h 12h 0051h 0052h 0059h 20h 22h 24h Primary OEM Command Set 13h 14h 0002h 0000h 26h 28h Address for primary Extended Table 15h 16h 0040h 0000h 2Ah 2Ch Alternate OEM Command Set (00h = none exists) 17h 18h 0000h 0000h 2Eh 30h Address for Alternative OEM Extended table (00h = none exists) 19h 1Ah 0000h 0000h 32h 34h

7.5.1 System Interface String

(Word Mode) DATA ADDRESS (Byte Mode) VDD Min. (write/erase) D7-D4: volt , D3-D0: 100 mV 1Bh 0027h 36h VDD Max. (write/erase) D7-D4: volt , D3-D0: 100 mV 1Ch 0036h 38h VPP Min. voltage (00h=no VPP pin present) 1Dh 0000h 3Ah VPP Max. voltage (00h=no VPP pin present) 1Eh 0000h 3Ch Typical timeout per single byte/word write 2N μs 1Fh 0004h 3Eh Typical timeout for Min. size buffer write 2N μs (00h=not supported) 20h 0000h 40h Typical timeout per individual block erase 2N ms 21h 000Ah 42h Typical timeout for full chip erase 2N ms (00h=not supported) 22h 0000h 44h Max. timeout for byte/word write 2N times typical 23h 0005h 46h Max. timeout for buffer write 2N times typical 24h 0000h 48h Max. timeout per individual block erase 2N times typical 25h 0004h 4Ah Max. timeout for full chip erase 2N times typical ( 00h = not supported) 26h 0000h 4Ch

Publication Release Date:Dec, 22, 2008 - 26 - Revisionv A5

7.5.2 Device Geometry Definition

(Word Mode) DATA ADDRESS (Byte Mode) Device size =2N bytes 27h 0016h 4Eh Flash device interface description (refer to CFI publication 100) 28h 29h 0002h 0000h 50h 52h Max. number of bytes in multi-byte write=2N (00h=not supported) 2Ah 2Bh 0000h 0000h 54h 56h Number of Erase Block Regions within devices 2Ch 0002h 58h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100 ) 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h 5Ah 5Ch 5Eh 60h Erase Block Region 2 Information 31h 32h 33h 34h 003Eh 0000h 0000h 0001h 62h 64h 66h 68h Erase Block Region 3 Information 35h 36h 37h 38h 0000h 0000h 0000h 0000h 6Ah 6Ch 6Eh 70h Erase Block Region 4 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h 72h 74h 76h 78h

Publication Release Date:Dec, 22, 2008 - 27 - Revisionv A5

7.5.3 Primary Vendor-Specific Extended Query

(Word Mode) DATA ADDRESS ( Byte Mode) Query-unique ASCII string "PRI" 40h 41h 42h 0050h 0052h 0049h 80h 82h 84h Major version number, ASCII 43h 0031h 86h Minor version number, ASCII 44h 0033h 88h Silicon Revision Number 01h = 0.13 μm 45h 0001h 8Ah Erase suspend 0 = Not supported, 1= To read only; 2 = To read & write 46h 0000h 8Ch Sector protect 00 = Not supported, 01=Supported 47h 0001h 8Eh Sector Temporary Unprotect 00 = Not supported, 01=Supported 48h 0001h 90h Sector protect/unprotect scheme 49h 0004h 92h Simultaneous operation Number of Sectors (except for Bank 1) 4Ah 0038h 94h Burst mode type 00 = Not supported, 01=Supported 4Bh 0000h 96h Page mode type 00 = Not Supported, 01=4 Word Page, 02=8 Word Page 4Ch 0000h 98h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Dh 0085h 9Ah ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h 9Ch Top/Bottom Boot Sector Flag 02h=Bottom Boot Device, 03h=Top Boot Device 4Fh 000Xh 9Eh

Publication Release Date:Dec, 22, 2008 - 28 - Revisionv A5

7.5.4 Command Definitions

BUS CYCLES (note 2-5) FIRST SECOND THIRD FOURTH FIFTH SIXTH COMMAND SEQUENCE (note 1 ) CYCLE ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA Read (note 6) 1 RA RD Reset (note 7) 1 XXX F0 Word 555 2AA 555 Normal Program Byte AAA AA 555 AAA A0 PA PD Word 555 2AA 555 Unlock Bypass Byte AAA AA 555 AAA Unlock Bypass Program (note 11) 2 XXX A0 PA PD Unlock Bypass Reset (note12) 2 XXX 90 XXX 00 Word 555 2AA 555 555 2AA 555 Chip Erase Byte AAA AA 555 AAA AAA AA 555 AAA Word 555 2AA 555 555 2AA Sector Erase Byte AAA AA 555 AAA AAA AA 555

55 SA 30

Word 555 2AA 555 Manufacturer Code Byte AAA AA 555 AAA

90 X00 DA

Word 555 2AA 55 X01 Device Code Byte AAA AA 555 AAA X02 (note 16) Word 555 2AA 555 X03 Security Sector Factory Protect (Note Byte AAA AA 555 AAA X06 Word 555 2AA 555 X02 AUTOSELECT(note8) Sector/Sect or Block Protect Verify (note 10) Byte AAA AA 555 AAA X04 Word 555 2AA 555 Enter Security Sector Region Byte AAA AA 555 AAA Word 555 2AA 555 Exit Security Sector Region Byte AAA AA 555 AAA

90 XXX 00

Interface (CFI) Query (note 15) Byte AA Legend: X = Don’t Care RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first. RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in AUTOSELECT mode) or erased. Address bits A20-A12 uniquely select any sector. Notes: 1. See Bus Operations Table for details. 2. All values are in hexadecimal.

Publication Release Date:Dec, 22, 2008 - 29 - Revisionv A5 3. Except for the read cycle and the fourth cycle of the AUTOSELECT command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20-A11 are “don’t care”. 6. No unlock or command cycles requi red when bank is reading array data. 7. The Reset command is required to return to the read m ode when the device is in the AUTOSELECT mode, or if DQ5 goes high (while the device is providing status information). 8. The fourth cycle of the AUTOSELECT command sequence is a read cycle. Data bits DQ15-DQ8 are don’t care. See the AUTOSELECT Command Sequence section for more information. 9. The data is 82h for factory locked and 02h for not factory locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The Unlock Bypass command is required pr ior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 13. Command is valid when device is ready to read array data or when device is in AUTOSELECT mode. 14. See Autoselect Codes table for device ID information

7.5.5 Write Operation Status

(Note 2) DQ6 DQ5 (Note1) DQ3 DQ2 (Note 2) RY/#BY Embedded Program Algorithm #DQ7 Toggle 0 N/A No toggle 0 Standard Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to DQ5 description section for more information. 2. DQ7 and DQ2 require a valid address when reading status info rmation. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

Publication Release Date:Dec, 22, 2008 - 30 - Revisionv A5

7.6 Temporary Sector Unprotect Algorithm

#RESET = VID (Note 1) Perform Erase or Program Operations #RESET = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If #WP/ACC = VI L, outermost boot sectors will remain protected). 2. All previously protected se ctors are protected once again.

Publication Release Date:Dec, 22, 2008 - 31 - Revisionv A5

7.7 In-System Sector Protect/Unprotect Algorithms

PLSCNT=1 #RESET=VID Wait 1 μ s First Write Cycle=60h? Wait 150 μ s Verity Sector Protect:Write 40h to sector address with A6=0, A1=1,A0=0 Set up sector address Yes Sector Protect: Write 60h to sector address with A6=0,A1=1,A0=0 Read from sector address with A6=0, A1=1,A0=0 Remove V from #RESET ID Write reset command Sector Protect complete Protect another sector? Data=01h? Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT =25? No No Device failed Yes Yes No Reset PLSCNT=1 START PLSCNT=1 #RESET=VID Wait 1 μ s First Write Cycle=60h? Yes All sectors protected ? Yes Wait 15 mS Verity Sector Unprotect:Write 40h to sector address with A6=1, A1=1,A0=0 Sector Unprotect: Write 60h to any address with A6=1,A1=1,A0=0 Read from sector address with A6=1, A1=1,A0=0 Remove V from #RESET ID Write reset command Last sector verified Data=00h? No Yes No Set up first sector address Protect all sectors The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Temporary Sector Unprotect Mode No No Increment PLSCNT PLSCNT =1000? Device failed Yes Sector Unprotect complete Set up next sector address Yes Sector Protect Algorithm Sector Unprotect Algorithm No Yes No

Publication Release Date:Dec, 22, 2008 - 32 - Revisionv A5

7.8 Security Sector Protect Verify

with A6 = 0 A1 = 1, A0 = 0 Read from Security Sector address with A6 = 0 A1 = 1, A0 = 0 If data = 00h, Security Sector is unprotected. If data = 01h, Security Sector is producted. Remove V IH or V ID from #RESET Write reset command Security Sector Protect Verify complete #RESET = V IH V ID or Wait 1 μ s Enter Security Sector Exit Security Sector

7.9 Program Algorithm

Verify Data? Increment Address Yes Last Address? Yes Programming Completed Embedded Program algorithm in progress No No

Publication Release Date:Dec, 22, 2008 - 33 - Revisionv A5

7.10 Erase Algorithm

Data=FFh? Erase Completed (Note1,2) No Yes Embedded Erase algorithm in progress Notes: 1. See Command Definitions Table for erase command sequence details. 2. See DQ3 section for the sector erase timer details.

7.11 Data Polling Algorithm

Addr=VA DQ7=Data? No DQ5=1? Yes No DQ7=Data? Read DQ7-DQ0 Addr=VA FAIL PASS Yes Yes No Notes: 1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Publication Release Date:Dec, 22, 2008 - 34 - Revisionv A5

7.12 Toggle Bit Algorithm

DQ5=1? Yes No Toggle Bit Read DQ7-DQ0 Twice Yes Yes No Read DQ7-DQ0 =Toggle? =Toggle? Program/Erase Operation Not Complete,Write Reset Command Program/Erase Complete Note: The system should recheck the toggle bit even if DQ5 =”1” because the toggle bit may stop toggling as DQ5 changes to “1”. See DQ6 and DQ2 section for more information

Publication Release Date:Dec, 22, 2008 - 35 - Revisionv A5 8. ELECTRICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings

Storage Temperature Plastic Packages -65 to +150 °C Ambient Temperature with Power Applied -65 to +125 °C VDD (Note 1) -0.5 to +4.0 V A9, #OE, and #RESET (Note 2) -0.5 to +11.5 V #WP/ACC -0.5 to +10.5 V Voltage with Respect to Ground All other pins (Note 1) -0.5 to V DD +0.5 V Output Short Circuit Current (Note 3) 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. Du ring voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions, input or I/O pins may overshoot to VDD +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, #OE, #RESET, and #W P/ACC is -0.5 V. During voltage transitions, A9, #OE, #WP/ACC, and #RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +11.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on #WP/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time . Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operat ion of the device at thes e or any other conditions above those indicated in the operational sections of this data sheet is not imp lied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

8.2 Operating Ranges

Industrial Grade -40 to +85 Ambient Temperature (TA ) Extended Grade -20 to +85 VDD Supply Voltages VDD for standard voltage range 2.7 to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed.

Publication Release Date:Dec, 22, 2008 - 36 - Revisionv A5

8.3 DC Characteristics

8.4 CMOS Compatible

LIMITS PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Load Current I LI V IN =VSS to VDD, VDD = VDD (Max.) - - ±1.0 μA A9 Input Load Current I LIT V DD = VDD (Max.), A9 = VID (Max.) - - 35 μA Output Leakage Current I LO V OUT =VSS to VDD, VDD =VDD (Max.) - - ±1.0 μA

5 MHz - 10 16 mA#CE = VIL, #OE = VIH

5 MHz 10 16 mA

(Note 1, 2) ICC1 #CE = VIL, #OE = VIH Word Mode 1 MHz 2 4 mA VDD Active Write Current (Note 2, 3) ICC2 #CE = VIL, #OE = VIH, #WE = VIL - 15 30 mA VDD Standby Current (Note2,5) ICC3 #CE = VDD ±0.3V, #RESET = VDD ±0.3V - 0.2 5 μA VDD Reset Current (Note2) ICC4 #RESET = VSS ±0.3V - 0.2 5 μA Automatic Sleep Mode Current (note 2, 4,5) ICC5 VIH = VDD ±0.3V, VIL = VSS ±0.3V - 0.2 5 μA ACC Pin 5 10 mAACC Accelerated Program Current, Word or Byte IAcc #CE = VIL, #OE = VIH VDD Pin 15 30 mA Input Low Voltage V IL - -0.5 - 0.8 V Input High Voltage V IH - 0.7x V DD - V DD +0.3 V Voltage for #WP/ACC Sector Protect/ Unprotect and Program Acceleration V HH VDD =3.0V ±10% 8.5 - 9.5 V Voltage for AUTOSELECT and Temporary Sector Unprotected V ID VDD =3.0V ±10% 8.5 - 11.5 V Output Low Voltage V OL I OL = 4.0 mA, VDD = VDD (Min.) - - 0.45 V Notes: 1. The I CC current listed is typically less than 2 mA/ MHz, with #OE at VIH. 2. Maximum I CC specifications are tested with VDD = VDD max. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. Typical sleep mode current is200 nA. 6. Not 100% tested

Publication Release Date:Dec, 22, 2008 - 37 - Revisionv A5

8.5 AC Characteristics

8.6 Test Condition

Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0-3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V

8.6.1 AC Test Load and Waveforms

Publication Release Date:Dec, 22, 2008 - 38 - Revisionv A5

8.7 Read-Only Operations

PARAMETER SYM. TEST SETUP MIN. MAX. UNIT Read Cycle Time T RC 70 - ns Address to Output Delay T ACC #OE, #CE =VIL - 70 ns Chip Enable to Output Delay T CE #OE, = VIL - 70 ns Output Enable to Output Delay T OE - 30 ns Chip Enable to Output High Z T DF - 16 ns Output Enable to Output High Z T DF - 16 ns Output Hold Time From Address, #OE or #CE, Whichever Occurs First TOH 0 - ns Read 0 - ns Output Enable Hold Time Toggle and #Data polling TOEH 10 - ns Note: Not 100 % tested

8.8 Hardware Reset (#RESET)

PARAMETER SYM. MIN. MAX. UNIT #RESET PIN Low (During Embedded Algorithms) to Read Mode TReady - 20 μs #RESET Pin Low (Not During Embedded Algorithms) to Read Mode T Ready - 500 ns #RESET Pulse Width T RP 500 - ns Reset High Time Before Read T RH 50 - ns #RESET Low to Standby Mode T RPD 20 - μs RY/#BY Recovery Time T RB 0 - ns Note: Not 100 % tested

8.9 Word/Byte Configuration (#BYTE)

PARAMETER SYM. MIN. MAX. UNIT #CE to #BYTE Switching Low or High TELFL/TELFH - 5 ns #BYTE Switching Low to Output High Z TFLQZ - 16 ns #BYTE Switching High to Output Active TFHQV 70 - ns

Publication Release Date:Dec, 22, 2008 - 39 - Revisionv A5

8.10 Erase and Program Operation

PARAMETER SYM. MIN. TYP. MAX. UNIT Write Cycle Timing (Note 1) T WC 70 - - ns Address setup Time T AS 0 - - ns Address Setup Timing to #OE low during toggle bit polling TASO 15 - - ns Address Hold Time T AH 45 - - ns Address Hold Time From #CE or #OE high during toggle bit polling TAHT 0 - - ns Data Setup Time T DS 35 - - ns Data Hold Time T DH 0 - - ns Output Enable High During toggle bit polling T OEPH 20 - - ns Read Recovery Time Before Write ( #OE High to #WE Low) TGHWL 0 - - ns #CE Setup Time TCS 0 - - ns #CE HOLD Time TCH 0 - - ns Write Pulse Width T WP 30 - - ns Write Pulse Width High T WPH 30 - - ns Latency Between Read and Write Operation T SR/W 0 - - ns Byte T PB - 7 150 μs Programming Time (Note 2) Word T PW - 9 210 μs Byte Accelerated Programming Time (Noe2) Word TACCP 4 - μs Sector Erase Time (Note 2) T SE - 0.4 - sec VDD Setup Time (Note 1) T VCS 50 - - μs Write Recovery Time from RY/#BY TRB 0 - - ns Program/Erase Valid to RY/#BY Delay TBUSY 90 - - ns Notes: 1. Not 100 % tested 2. See the “Alternate #CE Controlled Erase and Progr am Operations“ section for more information

8.11 Temporary Sector Unprotect

PARAMETER SYM. MIN. MAX. UNIT VID Rise and Fall Time T VIDR 500 - ns VHH Rise and Fall Time T VHH 250 - ns #RESET Setup Time for Temporary Sector Unprotect T RSP 4 - μs #RESET Hold Time from RY/#BY High for Temporary Sector Unprotect TRRB 4 - μs Note: Not 100 % tested1

Publication Release Date:Dec, 22, 2008 - 40 - Revisionv A5

8.12 Alternate #CE Controlled Erase and Program Operations

PARAMETER SYM. Min. Typical (Note3) Max. (Note4) Unit Write Cycle Time (Note 1) T WC 70 - - ns Address Setup Time T AS 0 - - ns Address Hold Time T AH 45 - - ns Data Setup Time T DS 35 - - ns Data Hold Time T DH 0 - - ns Read Recover Time Before Write (#OE High to #WE Low) TGHEL 0 - - ns #WE Setup Time T WS 0 - - ns #WE Hold Time T WH 0 - - ns #CE Pulse Width T CP 30 - - ns #CE Pulse Width High T CPH 30 - - ns Byte T PB - 7 150 Programming Time (Note 6) Word T PW - 9 210 μs Byte Accelerated Programming Time (Note 6) Word T ACCP - 4 120 μs Sector Erase Time (Note 2) T SE - 0.4 15 sec Chip Erase Time (Note 2) T CE - 30 - sec Byte T CPB - 21 63 Chip Program Time (Note 5) Word T CPW - 14 42 sec Notes: 1. Not 100 % tested. 2. In the pre-programming step of the Embedded Erase algor ithm, all bytes are programmed to 00h before erasure. 3. Typical program and erase time assume the following conditions :25℃,3.0 V VDD, 100,000 cycles .Additionally, programming typicals assume checkerboard pattern. 4. Under worst case conditions of 90 ℃, VDD =2.7V, 100,000 cycles. 5. The typical chip programming time is considerably less t han the maximun chip programming time listed,since most bytes program faster than maximun program times listed. 6. System-level overhead is the time r equired to execute the two- or four-bus-cycle sequence for the program command. 7. The device has a minimum erase and program cycle endurance of 100,000 cycles.

Publication Release Date:Dec, 22, 2008 - 41 - Revisionv A5 9. TIMING WAVEFORMS

9.1 AC Read Waveform

#CE #OE #WE TRC TOE TACC TOH TDF High-Z Addresses Stable TRH TRH TOEH TCE #RESET RY/#BY Output Valid

9.2 Reset Waveform

Reset Timing NOT during Embedded Algorithms #RESET RY/#BY #OE,#CE TReady TRP TRB Reset Timings during Embedded Algorithms #RESET RY/#BY #OE,#CE

Publication Release Date:Dec, 22, 2008 - 42 - Revisionv A5 9.3 #BYTE Waveform for Read Operation DQ0-DQ14 DQ15/A-1 Data Output (DQ0-DQ14) DQ15 Output (DQ0-DQ7) Data Output Address Input DQ0-DQ14 DQ15 Output Address InputDQ15/A-1 Data Output (DQ0-DQ14)(DQ0-DQ7) Data Output TELFL TFLQZ TELFH TFHQV #OE #CE #BYTE #BYTE Switching from word to byte mode #BYTE Switching from byte to word mode #BYTE 9.4 #BYTE Waveform for Write Operation TSET THOLD AS(T ) (TAH ) Note: Refer to the Erase /Program Operations table for TAS and TAH Specifications. #CE #BYTE #WE The falling edge of the last #WE signal

Publication Release Date:Dec, 22, 2008 - 43 - Revisionv A5

9.5 Programming Waveform

Program Command Sequence (last two cycles) Read Status Data (last two cycles) Status DOUTPDA0h TCS TDH TWPH TBUSY TRB TVCS Data VDD RY/#BY #WE #OE #CE DST TPW Notes: 1. PA = program address, PD = program data,D OUT is the true data at the program address 2. Illustration shows device in word mode

9.6 Accelerated Programming Waveform

#WP/ACC

Publication Release Date:Dec, 22, 2008 - 44 - Revisionv A5

9.7 Chip/Sector Erase Waveform

Erase Command Sequence (last two cycles) Read Status Data 30h55h TBUSY TRB TVCS Progress In Complete 10 for Chip Erase 555h for chip erase Address Data VDD RY/#BY #WE #OE #CE Notes : 1. SA = sector address (for Sector Er ase), VA = Valid Address for reading status data (see “Write operation Status”). 2. These waveforms are for the word mode

9.8 Back-to back Read/Write Cycle Waveform

Valid PA Valid RA Valid PA Valid PA TAH Valid In Valid In TGHWL #WE Controlled Write Cycle Read Cycle #CE Controlled Write Cycle Addresses Data #WE #OE #CE

Publication Release Date:Dec, 22, 2008 - 45 - Revisionv A5 9.9 #Data Polling Waveform (During Embedded Algorithms) TRC Valid Data VA TCE TACC TOE TOEH TBUSY TOH TCH TDF Addresses DQ0-DQ6 VA VA Valid Data High Z High Z DQ7 Status Data Complement True Status Data Complement True RY/#BY #WE #OE #CE Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

9.10 Toggle Bit Waveform (During Embedded Algorithms)

DQ6/DQ2 Valid DataValid Data Valid Status Valid Status Valid Status (stop toggling) TOE TOEH TCEPH TOEPH TDH TASO TAHT TAS TAHT RY/#BY #WE #OE #CE (first read) (second read) Note: VA= Valid address;not requires for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Publication Release Date:Dec, 22, 2008 - 46 - Revisionv A5

9.11 Temporary Sector Unprotect Timing Diagram

, , TRRB TVIDR VILVSS IHVor , , VID VID Program or Erase Command Sequence #RESET #CE #WE RY/#BY

9.12 Sector/Sector Block Protect and Unprotect Timing Diagram

Valid* A1,A0 SA,A6, #RESET *For sector protect,A6=0,A1=1,A0=0.For sector unprotect ,A6=1,A1=1,A0=0 Sector/Sector Block Protect:150μs, Sector/Sector Block Unprotect:15ms 1μs Sector/sector Block Protect or Unprotect VID VIH 60h 60h Valid* Valid* 40h Verify Status #CE #WE #OE

Publication Release Date:Dec, 22, 2008 - 47 - Revisionv A5

9.13 Alternate #CE Controlled Write (Erase/Program) Operation Timing

. . DOUT#DQ7 #RESET DATA Address 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase #Data Polling PA TWC TAS TAH TWH t GHEL TCP TWS TDS TDH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase TBUSY TRH #WE #OE #CE RY/#BY TCPH TPW, TACCP, or TSE Notes: 1. Firgure indicates last two bus cycl es of a program or erase operation. 2. PA= program address, SA= sect or address, PD= program data. 3. #DQ7 is the complement of the data written to the device. Dout is the data written to the device. 4. Waveforms are for the word mode.

Publication Release Date:Dec, 22, 2008 - 48 - Revisionv A5 10. LATCHUP CHARACTERISTICS PARAMETER MIN. MAX. Input voltage with respect to VSS on all pins except I/O pins (including A9, #OE, and #RESET) -1.0V 11.5 V Input voltage with respect to VSS on all I/O pins -1.0V V DD +1.0V VDD Current -100mA +100mA Note: Includes all pins except VDD. Test conditions: VDD = 3.0 V, one pin at a time. 11. CAPACITANCE TSOP PARAMETER SYM. TEST SETUP Typical Max. UNIT Input Capacitance CIN VIN = 0 6 7.5 pF Output Capacitance COUT VOUT = 0 8.5 12 pF Control Pin Capacitance CIN2 VIN = 0 7.5 9 pF Notes: 1. Sampled, not 100 % tested. 2. Test condition TA = 25 °C, f = 1.0 MHz.

Publication Release Date:Dec, 22, 2008 - 49 - Revisionv A5 12. ORDERING INFORMATION Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

Publication Release Date:Dec, 22, 2008 - 50 - Revisionv A5 13. PACKAGE DIMENSION 13.1 48-Pin Standard Thin Small Outline Package 0.020 0.004 0.007 0.037 0.002 MIN. 0.60 Y L c 0.50 0.10 0.70 0.21 MILLIMETER A b 0.95 0.17 0.05 Sym. MIN. 1.20 0.27 1.051.00 0.22 MAX.NOM. 0.028 0.008 0.024 0.011 0.041 0.047 0.009 0.039 NOM. INCH MAX. E H D 0 5 0 5 e D 18.3 18.4 18.5 19.8 20.0 20.2 11.9 12.0 12.1 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.10 0.80 0.031 0.004 0.0200.50 θ e 1 48 b E D YA1 A L c HD θ

Publication Release Date:Dec, 22, 2008 - 51 - Revisionv A5 14. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A0 Dec,31, 2006 ALL Initial Issued ,note p21 A1 June,15,2007 ALL 1. VID was changed from 12.5 to 11.5 2. Erase time was changed form 49 Sec to 30Sec 3. Re-typesetting A2 Oct,17,2007 46 1. Update package material as Green A3 Dec.20,2007 37,40,41 1. Add note 5 and 6 2. Add max of tPB and tPW 3. Modify format and setting A4 Oct,29,2008 2,3,37,48, 1. Update order information and industrial devices ambient temperature 2. Remove BGA package type 3. Update AC Test Load A5 Dec,22,2008 Remove Erase Suspend/Resume feature Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical im plantation, atomic energy control instruments, airplane or spaceship instruments, transporta tion instruments, traffic signal instruments, combustion control instruments, or for other a pplications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.