W191 SPECTRALINEAR | Alldatasheet

Document overview

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Technical content

Features

  • Six skew controlled CMOS outputs  Output skew between any two outputs is less than 150 ps  SMBus Serial configuration interface  2.5 ns to 5 ns propagation delay  DC to 133 MHz operation (Commercial)  DC to 100 MHz operation (Industrial)  Single 3.3V supply voltage  Low power CMOS design packaged in a 16-pin SSOP (Small Shrink Outline Package) Key Specifications DDQ3 + 0.5V Block Diagram Pin Configuration[1] SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SMBusSCLOCK SDATA Device Control BUF_IN VDDQ3 SDRAM5 GND SDRAM4 VDDQ3 SDRAM3 GND SCLK SDRAM0 GND SDRAM1 BUF_IN GND SDRAM2 VDDQ3 SDATA Note: 1. Internal pull-up resistor of 250K on SDATA and SCLK.

interface with registered DIMMs. level compatible. Nominal output buffer impedance is 15:. Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. to within ±150 ps of each other. BUF_IN 4 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ). section of this data sheet. Internal 250-k: pull-up resistor. described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor. G Ground Connection: Connect all ground pins to the common system ground plane. Table 1. Byte Writing Sequence

1 Slave Address 11010010 Commands the W191 to accept the bits in Data Bytes 0-6 for internal

  1. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver). addressed slave receiver on the serial data bus. receiver on the serial data bus.

4 Data Byte 0 Refer to

functions, refer to Table 2.

5 Data Byte 1

6 Data Byte 2

7 Data Byte 3 Don’t Care

8 Data Byte 4

9 Data Byte 5

10 Data Byte 6

Table 2. Data Bytes 0–2 Serial Configuration Map[2]

  1. At power up all SDRAM outputs are enabled and active. Program Reserved bits to 0.

Rev 1.0,November 20, 2006 Page 4 of 9 Absolute Maximum Ratings[3] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description Rating Unit VDDQ3, VIN Voltage on any pin with respect to GND –0.5 to + 7.0 V TSTG Storage Temperature –65 to + 150 °C TB Ambient Temperature under Bias –55 to + 125 °C TA Operating Temperature (Commercial) 0 to + 70 °C TA Operating Temperature (Industrial) –40 to + 85 °C Parame- ter Description Test Condition Min. Typ. Max. Unit IDD 3.3V Supply Current BUF_IN = 100 MHz 173 mA IDD 3.3V Supply Current in three-state BUF_IN = 100 MHz 5 mA Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) VIL Input Low Voltage GND–0.3 0.8 V VIH Input High Voltage 2.0 V DDQ3+0.5 V IILEAK Input Leakage Current, BUF_IN –5 +5 µA IILEAK Input Leakage Current[5] –20 +5 µA Logic Outputs (SDRAM0:5) VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 65 100 160 mA IOH Output High Current V OH = 1.5V 70 110 185 mA Pin Capacitance/Inductance CIN Input Pin Capacitance (Except BUF_IN) 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H Notes: 3. Multiple supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing i s NOT required. 4. Outputs loaded by 6” 60: transmission lines with 20 pF capacitors. 5. OE, SCLOCK, and SDATA logic pins have a 250-k: internal pull-up resistor (not CMOS level).

Rev 1.0,November 20, 2006 Page 5 of 9 VDDQ3 = 3.3V ± 5% (Lump Capacitance Test Load = 30pF) Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency (Commercial) 0 133 MHz fIN Input Frequency (Industrial) 0 100 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.0 4.0 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.0 4.0 V/ns tSR Output Skew, Rising Edges 150 ps tSF Output Skew, Falling Edges 150 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 2.5 5.0 ns tPF Falling Edge Propagation Delay 2.5 5.0 ns tD Duty Cycle Measured at 1.5V 45 55 % Zo AC Output Impedance 15 :

Rev 1.0, November 20, 2006 Page 9 of 9 W191 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Package Diagrams Shrink Small Outline Package (SSOP 150 inch)