W164 SPECTRALINEAR | Alldatasheet
Document overview
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Technical content
Features
- Maximized EMI suppression using Cypress’s Spread Spectrum technology Reduces measured EMI by as much as 10 dB I 2C programmable to 153 MHz (16 selectable frequencies) Two skew-controlled copies of CPU output SEL100/66# selects CPU frequency (100 or 66.8 MHz) Seven copies of PCI output (synchronous w/CPU output) One copy of 14.31818-MHz IOAPIC output One copy of 48-MHz USB output Selectable 24-/48-MHz output is determined by resistor straps on power-up One high-drive output buffer that produces a copy of the 14.318-MHz reference Isolated core VDD pin for noise reduction Key Specifications VDDQ2 = 2.5V±5% CPU, PCI Output Edge Rate: t1 V/ns Note: Internal pull-up resistors should not be relied upon for setting I/O pins HIGH.
Table 1. Pin Selectable Frequency
Rev 1.0,November 28, 2006 Page 2 of 11 Pin ConfigurationBlock Diagram GND PCI_F PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 PCI6 VDDQ3 48MHz 24/48MHz GND REF2X/SEL48# VDDQ3 VDDQ2 IOAPIC VDDQ2 CPU0 CPU1 VDDQ3 GND SDATA SCLOCK SEL100/66# GND VDDQ3 REF2X/SEL48# VDDQ3 IOAPIC CPU0 CPU1 PCI_F XTAL PLL Ref Freq PLL 1100/66#_SEL VDDQ3 PCI1 PCI2 PCI3 PCI4 PCI5 48MHz 24/48MHz PLL2 OSC VDDQ2 PCI6 GND GND VDDQ3 GND GND I2C SCLOCK SDATA LOGIC ÷2/÷3/÷4
Rev 1.0,November 28, 2006 Page 3 of 11 Functional Description I/O Pin Operation Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of the pin is latched and the pin becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k: “strapping” resistor is connected between the l/O pin and ground or V DD. Connection to ground sets a latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W164 power-up, the first 2 ms of operation is used for input logic selection. During this period, the Reference clock output buffer is three-stated, allowing the output strapping resistor on the l/O pin to pull the pin and its associated capac- itive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is then latched. Next the output buffer is enabled which converts the l/O pin into an operating clock output. The 2-ms timer is started when V DD reaches 2.0V. The input bit can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistor has no significant effect on clock output signal integrity. The drive impedance of clock output is 25 : (nominal) which is minimally affected by the 10-k: strap to ground or V DD. As with the series termi- nation resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the inter- connecting trace short. The trace from the resistor to ground or V DD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock output is enabled following the 2-ms input period, a 14.318-MHz output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once V DD voltage has stabilized. In either Pin Definitions Pin Name Pin No. Pin Type Pin Description CPU0:1 22, 21 O CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2. PCI1:6 PCI_F 5, 6, 7, 8, 10, 11, 4 O PCI Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run synchronously to the CPU clock. Voltage swing is set by the power connection to VDDQ3. IOAPIC 24 O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by the power connection to VDDQ2. 48MHz 13 O 48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by voltage applied to VDDQ3. 24/48MHz 14 O 24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up. REF2X/SEL48# 27 I/O I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48# is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin 14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. SEL100/66# 16 I Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on page 1. SDATA 18 I/O I 2C Data Pin: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-k: pull-up resistor. SCLOCK 17 I I2C Clock Pin: The I2C data clock should be presented to this input as described in the I2C section of this data sheet. X1 1 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. X2 2 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 9, 12, 20, 26 P Power Connection: Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz, and Reference output buffers. Connect to 3.3V supply. VDDQ2 23, 25 P Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V supply. GND 3, 15, 19, 28 G Ground Connections: Connect all ground pins to the common system ground plane.
Table 3. Byte Writing Sequence
1 Slave Address 11010010 Commands the W164 to accept the bits in Data Bytes 3–6 for internal
- Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2 Command
addressed slave receiver on the serial data bus. receiver on the serial data bus. 4 Data Byte 0 Don’t Care Refer to Cypress SDRAM drivers.
5 Data Byte 1
6 Data Byte 2
functions, refer to Table 4, Data Byte Serial Configuration Map.
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
- Bits are written MSB (most significant bit) first, which is bit
- Table 4 gives the bit formats for registers located in Data
available through the serial data interface. Table 6 details the select functions for Byte 3, bits 1 and 0.
- Both Bits 0 and 1 of Byte 6 in Table 4 must be programmed as the same value.
Table 4. Data Bytes 3–6 Serial Configuration Map
01 T e s t M o d e
- CPU and PCI frequency selections are listed in Table 1 and Table 5.
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Table 6. Select Function for Data Byte 3, Bits 0:1
Rev 1.0,November 28, 2006 Page 8 of 11 Absolute Maximum Ratings[3] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description Rating Unit V DD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C ESDPROT Input ESD Protection 2 (min.) kV Parameter Description Test Cond ition Min. Typ. Max. Unit Supply Current IDDQ3 Combined 3.3V Supply Current CPU0:1 =100 MHz Outputs Loaded[4] 85 mA IDDQ3 Combined 2.5V Supply Current CPU0:1 =100 MHz Outputs Loaded[4] 30 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[5] –25 µA IIH Input High Current[5] 10 µA IIL Input Low Current (SEL100/66#) –5 µA IIH Input High Current (SEL100/66#) 5 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V VOH Output High Voltage CPU0:1/IOAPIC I OH = –1 mA 2.2 V IOL Output Low Current CPU0:1 V OL = 1.25V 50 70 100 mA PCI_F, PCI1:6 V OL = 1.5V 60 80 120 mA IOAPIC V OL = 1.25V 40 85 140 mA REF2X V OL = 1.5V 100 130 152 mA 48MHz, 24MHz V OL = 1.5V 40 50 76 mA IOH Output High Current CPU0:1 V OH = 1.25V 50 70 100 mA PCI_F, PCI1:6 V OH = 1.5V 60 70 120 mA IOAPIC V OH = 1.25V 40 87 155 mA REF2X V OH = 1.5V 100 130 150 mA 48MHz, 24MHz V OH = 1 . 5 V 4 05 09 4 m A Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section. 5. W164 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
Rev 1.0,November 28, 2006 Page 9 of 11 TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. Notes: 6. X1 input threshold voltage (typical) is V DD/2. 7. The W164 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Crystal Oscillator VTH X1 Input Threshold Voltage[6] VDDQ3 = 3.3V 1.65 V CLOAD Load Capacitance, as seen by External Crystal[7] 13 pF CIN,X1 X1 Input Capacitance[8] Pin X2 unconnected 26 pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 pF COUT Output Pin Capacitance pF LIN Input Pin Inductance 7n H Parameter Description Test Cond ition Min. Typ. Max. Unit CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 200 250 ps t SK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabili- zation from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 20 :
Rev 1.0,November 28, 2006 Page 10 of 11 PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 14 n s fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 : IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 : REF2X Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 :
Rev 1.0, November 28, 2006 Page 11 of 11 W164 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. 48-MHz and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8/100 MHz Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 24.004 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17, 57/34 t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 :
Ordering Information
Ordering Code Package Name Package Type W164 G 28-pin SOIC (300 mils) Package Diagram A A P I N1I D .530[13.462] .545[13.843] .395[10.033] .405[10.287] .090[2.286] .109[2.768] .002[0.050] .014[0.355] .007[0.177] .026[0.660] .015[0.381] .020[0.508] .019[0.482] EXTERNAL LEAD DESIGN OPTION 1 OPTION 2 DETAIL .050[1.270] SEATING PLANE DIMENSIONS IN INCHES[MM] MIN. MAX. .050[1.270] TYP. .720[18.288] .730[18.542] 0.004[0.102] 114 15 28 PART # S28.4 STANDARD PKG. SZ28.4 LEAD FREE PKG. 28-Lead Molded SOIC S28