W159B SPECTRALINEAR | Alldatasheet

Document overview

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Technical content

Features

  • Maximized EMI suppression using Cypress’s spread spectrum technology (0.5% down spread)  Seven skew-controlled copies of CPU and 16.667-MHz synchronous APIC output  Two copies of fixed-frequency 33 MHz outputs  Four copies of 66 MHz fixed-frequency outputs  Two copies of CPU/2 outputs for synchronous memory reference  One copy of 48 MHz USB output  Two copies of 14.31818 MHz reference clock  Programmable to 133 or 100 MHz operation  Power management control pins for clock stop and shut down  Available in 56-pin SSOP Key Specifications Logic inputs, except SEL133/100#, have 100-k : pull-up resistors.

Table 1. Pin Selectable Frequency

  1. Pins denoted by * have a 250-k : pull-up resistor. Design

Rev 1.0,November 21, 2006 Page 2 of 10 Overview The W159B is designed to provide the essential frequency sources to work with advanced multiprocessing Intel® archi- tecture platforms. Split voltage supply signaling provides 2.5V and 3.3V clock frequencies operating up to 133 MHz. From a low-cost 14.31818-MHz reference crystal oscillator, the W159B generates 2.5V clock outputs to support CPUs, core logic chip set, and Direct RDRAM clock generators. It also provides skew-controlled PCI and IOAPIC clocks synchronous to CPU clock, 48-MHz Universal Serial Bus (USB) clock, and replicates the 14.31818-MHz reference clock. All CPU, PCI, and IOAPIC clocks can be synchronously modulated for spread spectrum operations. Cypress employs proprietary techniques that provide the maximum EMI reduction while minimizing the clock skews that could reduce Pin Definitions Pin Name Pin No. Pin Type Pin Description CPU0:6 48, 47, 44, 43, 40, 39, 36 O CPU Clock Outputs 0 through 6: These seven CPU clocks run at a frequency set by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. For 4-way SMP systems that do not require more than 5 CPU outputs, CPU5 and CPU6 can be disabled by asserting 6W/4W# during power-up. CPUdiv2_ 0:1 32, 31 O Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing is set by the voltage applied to VDDQ2. For systems using SDRAM, CPUdiv2_0:1 output can be disabled by tying VDDQ2 on pin 30 to GND. 3V33_0:1 23, 24 O 33 MHz Fixed-Frequency Output: These are fixed-frequency outputs that can be used to drive PCI devices. REF0/ FIXAPIC#* 9I / O 14.318 MHz Reference Clock Output/APIC Speed Select: During normal opera- tions, this is a 3.3V 14.318-MHz reference output. During power-up, it is sampled to determine the operating frequency of APIC. If the sample is a “1,” APIC will be set at CPU/4. If it is a “0,” APIC will be fixed at 16.667 MHz. REF1/TEST#* 10 I/O 14.318 MHz Reference Clock Output/Test Mode: During normal operations, this is a 3.3V 14.318-MHz reference output. The input is sampled at power-up to determine if the device should initialize for normal operations or test mode. APIC0:6 4, 3, 1, 56, 55 53, 52 O Synchronous I/OAPIC Clock Outputs: APIC output frequency is determined by FIXAPIC# strapping. For 4-way SMP systems that do not require more than 5 APIC outputs, APIC5 and APIC6 can be disabled by asserting 4W/6W# during power up. 48MHz 14 O 48 MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. 3V66_0:3 16, 17, 20, 21 O 66 MHz Output 0 through 3: Fixed 66-MHz outputs. SEL133/100# 29 I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. X1 6 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. X2 7 O Crystal Connection: An output connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 6W/4W#* 26 I 4-way/6-way Output Select: This input can be changed after initialization and has an internal pull-up resistor. If left unconnected during power-up, the outputs are configured so that all CPU and APIC outputs are active. If it is pulled down during power-up, CPU5:6 and APIC5:6 will be disabled. SPREAD# 50 I Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables spread spectrum mode when held LOW. PWRDWN# 34 I Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that requests the device to enter power down mode. GND 2, 11, 13, 19, 25, 28, 33, 37, 38, 45, 46, 51 G Ground Connection VDDQ3 8, 12, 15, 18, 22, 27 P Power Connection: Power supply for 3V33, 3V66, 48MHz, and REF output buffers, core circuitry and PLL circuitry. Connect to 3.3V supply. VDDQ2 5, 30, 35, 41, 42, 49, 54 P Power Connection: Power supply for APIC and CPU, CPUdiv2 output buffers. Connect to 2.5V supply.

Table 2. Maximum Allowed Current Table 3. Clock Enable Configuration[2, 3, 4]

0 LOW LOW LOW LOW LOW LOW LOW OFF OFF

1 O N O N O NO NO N O N O N O N O N

Table 4. Power Management State Transition

  1. LOW means outputs held static LOW as per latency requirement below.
  2. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
  3. Power-up latency is when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
  4. All internal timing is referenced to the CPUCLK.
  5. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is desig ned.
  6. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is synchronized by the W159B internally.
  7. The shaded sections on the VCO and the Crystal signals indicate an active clock.
  8. Diagrams shown with respect to 133 MHz. Similar operation when CPUCLK is 100 MHz.

Rev 1.0,November 21, 2006 Page 5 of 10 Absolute Maximum Ratings [11] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C ESDPROT Input ESD Protection 2 (min.) kV Parameter Description Test Cond ition Min. Typ. Max. Unit Supply Current IDD-3.3V Combined 3.3V Supply Current CPU0:3 =133 MHz [11] 160 mA IDD-2.5 Combined 2.5V Supply Current CPU0:3 =133 MHz [11] 90 mA Logic Inputs (All referenced to VDDQ3 = 3.3V) VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[13] –25 µA IIH Input High Current[13] 10 µA IIL Input Low Current, SEL133/100#[13] –5 µA IIH Input High Current, SEL133/100#[13] 5µ A Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to V DDQ2) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 2.2 V IOL Output Low Current V OL = 1.25V 45 65 100 mA IOH Output High Current V OH = 1.25V 45 65 100 mA 48MHz, REF (Referenced to VDDQ3) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 45 65 100 mA IOH Output High Current V OH = 1.5V 45 65 100 mA 3V33, 3V66 (Referenced to VDDQ3) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 70 100 145 mA IOH Output High Current V OH = 1.5V 65 95 135 mA Notes: 11.Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 12. All clock outputs loaded with 6" 60: transmission lines with 20-pF capacitors. 13. W159B logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).

Rev 1.0,November 21, 2006 Page 6 of 10 3.3V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[17] Notes: 14. X1 input threshold voltage (typical) is VDD/2. 15. The W159B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 16. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 17. Period, jitter, offset, and skew measured on rising edge at 1.5V. 18. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz. Crystal Oscillator VTH X1 Input Threshold Voltage[14] 1.65 V CLOAD Load Capacitance, Imposed on External Crystal[15] 18 pF CIN,X1 X1 Input Capacitance[16] Pin X2 unconnected 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency Note 18 66.6 MHz t H High Time Duration of clock cycle above 2.4V 4.95 ns tL Low Time Duration of clock cycle below 0.4V 4.55 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps t SK Output Skew Measured on rising edge at 1.5V 250 ps tO CPU to 3V66 Clock Skew Covers all 3V66 outputs. Measured on rising edge at 1.5V. CPU leads 3V66 outputs. 01 . 5 n s fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 : Parameter Description Test Cond ition Min. Typ. Max. Unit

Rev 1.0,November 21, 2006 Page 7 of 10 Note: 19. 3V33 clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz. 3V33 Clock Outputs, 3V33_0:1 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V [19] 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO 3V66 to 3V33 Clock Skew Covers all 3V66 outputs. Measured on rising edge at 1.5V. 3V66 leads 3V33 output. 1.5 3.0 ns tq CPU to 3V33 Clock Skew Covers all 3V33 outputs. Measured on rising edge at 1.5V. CPU leads 3V33 output. 1.5 4.0 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for deter- mining series termination value. 15 : REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 :

Rev 1.0,November 21, 2006 Page 8 of 10 2.5V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[20] Note: 20. Period, Jitter, offset, and skew measured on rising edge at 1.25V. 48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz f D Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 : CPU Clock Outputs, CPU0:6 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 133 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 7.5 7.65 10 10.2 ns tH High Time Duration of clock cycle above 2.0V 1.87 3.0 ns tL Low Time Duration of clock cycle below 0.4V 1.67 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 200 200 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabili- zation from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 20 :

Rev 1.0,November 21, 2006 Page 9 of 10 Note: 21. APIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz. CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 133 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.3 20 20.4 ns tH High Time Duration of clock cycle above 2.0V 5.25 7.5 ns tL Low Time Duration of clock cycle below 0.4V 5.05 7.3 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps t SK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabili- zation from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 20 : APIC Clock Outputs, APIC0:2 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min Typ Max Unit f Frequency Note 21 16.67 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 :

Rev 1.0, November 21, 2006 Page 10 of 10 W159B While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.

Ordering Information

Ordering Code Package Name Package Type W159B H 56-pin SSOP (300 mils) Package Drawing and Dimensions 56-lead Shrunk Small Outline Package O56