W158 SPECTRALINEAR | Alldatasheet

Document overview

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Technical content

Features

  • Maximized EMI suppression using Cypress’s spread spectrum technology  Intel® CK98 Specif ication compliant  0.5% downspread outputs deliver up to 10 dB lower EMI  Four skew-controlled copies of CPU output  Eight copies of PCI output (synchronous w/CPU output)  Four copies of 66 MHz fixed frequency 3.3V clock  Two copies of CPU/2 outputs for synchronous memory reference  Three copies of 16.67 MHz IOAPIC clock, synchronous to CPU clock  One copy of 48 MHz USB output  Two copies of 14.31818 MHz reference clock  Programmable to 133- or 100-MHz operation  Power management control pins for clock stop and shut down  Available in 56-pin SSOP Key Specifications VDDQ2 = 2.5V±5% Logic inputs, except SEL133/100#, have 250-k : pull-up resistors

Table 1. Pin Selectable Frequency

  1. See Table 2 for complete mode selection details.

Rev 1.0,November 21, 2006 Page 2 of 12 Overview The W158 is designed to provide the essential frequency sources to work with advanced multiprocessing Intel archi- tecture platforms. Split voltage supply signaling provides 2.5V and 3.3V clock frequencies operating up to 133 MHz. From a low-cost 14.31818-MHz reference crystal oscillator, the W158 generates 2.5V clock outputs to support CPUs, core logic chip set, and Direct RDRAM clock generators. It also provides skew-controlled PCI and IOAPIC clocks synchronous to CPU clock, 48-MHz Universal Serial Bus (USB) clock, and replicates the 14.31818-MHz reference clock. All CPU, PCI, and IOAPIC clocks can be synchronously modulated for spread spectrum operations. Cypress employs proprietary techniques that provide the maximum EMI reduction while minimizing the clock skews that could reduce system timing margins. Spread Spectrum modulation is enabled by the active LOW control signal SPREAD#. The W158 also includes power management control inputs. By using these inputs, system logic can stop CPU and/or PCI clocks or power down the entire device to conserve system power. Pin Definitions Pin Name Pin No. Pin Type Pin Description CPU0:3 41, 42, 45, 46 O CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. CPUdiv2_ 0:1 49, 50 O Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing is set by the voltage applied to VDDQ2. PCI1:7 9, 11, 12, 14, 15, 17, 18 O PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously to the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs are stopped when PCI _STOP# is held LOW. PCI_F 8 O PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the state of PCI_STOP#. REF0:1 2, 3 O 14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference clock. IOAPIC0:2 53, 54, 55 O I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage swing is set by the power connection to VDDQ2. 48MHz 30 O 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. 3V66_0:3 21, 22, 25, 26 O 66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is controlled by voltage applied to VDDQ3. SEL0:1 32, 33 I Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output modes. SEL133/100# 28 I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. X1 5 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or an external reference signal. X2 6 O Crystal Connection: An output connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. SPREAD# 34 I Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables spread spectrum mode when held LOW. PWRDWN# 35 I Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that requests the device to enter power-down mode. CPU_STOP# 36 I Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input. PCI_STOP# 37 I Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all PCI outputs except PCI_F when held LOW. VDDQ3 4, 10, 16, 23, 27, 31, 39 P Power Connection: Power supply for PCI output buffers, 48-MHz USB output buffer, Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to 3.3V supply. VDDQ2 43, 47, 51, 56 P Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers. Connect to 2.5V supply. GND 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 G Ground Connection: Connect all ground pins to the common system ground plane.

The W158 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.

  1. Provided for board level “bed of nails” testing.
  2. 48-MHz PLL disabled to reduce component jitter.
  3. Normal” mode of operation.
  4. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
  5. Required for DC output impedance verification.
  6. Frequency accuracy of 48 MHz is +167 PPM to match USB default.

Table 2. Select Functions Table 3. Truth Table Table 4. Maximum Supply Current

Table 5. Clock Enable Configuration[9, 10, 11, 12, 13, 14] Table 6. Power Management State Transition

  1. LOW means outputs held static LOW as per latency requirement below.
  2. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
  3. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW.
  4. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW.
  5. An “x” indicates a “don’t care” condition.
  6. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first valid

clock comes out of the device.

  1. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
  2. All internal timing is referenced to the CPU clock.
  3. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
  4. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F.
  5. 3V66 clocks also stop/start before.
  6. PWRDWN# and PCI_STOP# are shown in a HIGH state.
  7. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.

Rev 1.0,November 21, 2006 Page 6 of 12 PCI_STOP# Timing Diagram[18, 22, 23, 24, 25, 26] PWRDWN# Timing Diagram[18, 22, 23, 27, 28] Notes: 23. All internal timing is referenced to the CPU clock. 24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output. 25. All other clocks continue to run undisturbed. 26. PWRDWN# and CPU_STOP# are shown in a HIGH state. 27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized. 28. The shaded Sections on the VCO and the Crystal signals indicate an active clock. Timing Diagrams (continued) CPU PCI PCI_STOP# PWRDWN# PCI_F (external) HI HI (internal) PCI (external) CPU_STOP# CPU PCI PWRDWN# VCO Crystal PCI CPU (internal) (internal) (external) (external)

Rev 1.0,November 21, 2006 Page 7 of 12 Absolute Maximum Ratings[29] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C ESDPROT Input ESD Protection 2 (min.) kV Parameter Description Test Cond ition Min. Typ. Max. Unit Supply Current IDD-3.3V Combined 3.3V Supply Current CPU0:3 =133 MHz [30] 160 mA IDD-2.5 Combined 2.5V Supply Current CPU0:3 =133 MHz [30] 90 mA Logic Inputs (All referenced to VDDQ3 = 3.3V) VIL Input Low Voltage GND –0.3 0.8 V VIH Input High Voltage 2.0 VDD+ 0.3 V IIL Input Low Current[31] –25 µA IIH Input High Current[31] 10 µA IIL Input Low Current, SEL133/100#[31] –5 µA IIH Input High Current, SEL133/100#[31] 5µ A Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to V DDQ2) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 2.2 V IOL Output Low Current V OL = 1.25V 45 65 100 mA IOH Output High Current V OH = 1.25V 45 65 100 mA 48MHz, REF (Referenced to VDDQ3) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 45 65 100 mA IOH Output High Current V OH = 1.5V 45 65 100 mA PCI, 3V66 (Referenced to VDDQ3) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 70 100 145 mA IOH Output High Current V OH = 1.5V 65 95 135 mA Notes: 29. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 30. All clock outputs loaded with 6" 60: transmission lines with 20-pF capacitors. 31. W158 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).

Rev 1.0,November 21, 2006 Page 8 of 12 3.3V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[35] Notes: 32. X1 input threshold voltage (typical) is VDD/2. 33. The W158 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 34. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 35. Period, jitter, offset, and skew measured on rising edge at 1.5V. 36. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz. Crystal Oscillator VTH X1 Input threshold Voltage[32] 1.65 V CLOAD Load Capacitance, Imposed on External Crystal[33] 18 pF CIN,X1 X1 Input Capacitance[34] Pin X2 unconnected 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H Parameter Description Test Cond ition Min. Typ. Max. Unit 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition /Comments Min. Typ. Max. Unit f Frequency Note 36 66.6 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 :

Rev 1.0,November 21, 2006 Page 9 of 12 Note: 37. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz. PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V [37] 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO 3V66 to PCI Clock Skew Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. 3V66 leads PCI output. 1.5 3 ns tq CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for deter- mining series termination value. 15 : REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 : 48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz f D Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 :

Rev 1.0,November 21, 2006 Page 10 of 12 2.5V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[38] Note: 38. Period, Jitter, offset, and skew measured on rising edge at 1.25V. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 133 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 7.5 7.65 10 10.2 ns tH High Time Duration of clock cycle above 2.0V 1.87 3.0 ns tL Low Time Duration of clock cycle below 0.4V 1.67 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 150 150 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabili- zation from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 20 : CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 133 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.3 20 20.4 ns tH High Time Duration of clock cycle above 2.0V 5.25 7.5 ns tL Low Time Duration of clock cycle below 0.4V 5.05 7.3 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabili- zation from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 20 :

Rev 1.0,November 21, 2006 Page 11 of 12 Note: 39. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz. IOAPIC Clock Outputs, IOAPIC0:2 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min Typ Max Unit f Frequency Note 39 16.67 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 :

Rev 1.0, November 21, 2006 Page 12 of 12 W158 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.

Ordering Information

Ordering Code Package Name Package Type W158 H 56-pin SSOP (300 mils) Package Diagram 56-lead Shrunk Small Outline Package O56